Chip heat dissipation structure
Patent Information
- Application Number
- CN202521608786.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2026-08-18
- Estimated Expiration
- 2035-07-30
AI Technical Summary
[0004]传统的N/P型半导体材料其吸热端跟散热端是一体的，这种方案下，N/P型制冷材料不能做得太薄，否则，热端和冷端之间的热传导就会太大，从而降低了制冷的效果，且传统的半导体制冷方案还需要外部电力驱动
[0019]与现有技术相比，本实用新型的有益效果是：1、本装置把散热结构的热端和冷端分开，可以减小热端和冷端的直接热传导，也能提升热电转换的效率；2、不仅不需要供电，还实现了将热量转换为电能储存，让废弃的热能转换为电能，提高了能量利用率；3、可以实现热端与芯片的合封，增加热端与芯片热传导效果；4、通过拉开热端与冷端的距离后，可以把N/P型制冷材料的厚度设计的很小，减小了焦耳热，提升了热电转换效率。
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Figure CN224653997U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of semiconductor technology, specifically relating to a chip heat dissipation structure. Background Technology
[0002] Chip heat dissipation is a crucial aspect of electronic device design. Its purpose is to control chip temperature through effective heat dissipation techniques to ensure stable device operation and extend lifespan. With increasing chip integration and power consumption, especially in high-power chips (including CPUs, SoCs, GPUs, and ASICs), heat dissipation has become a particularly prominent issue.
[0003] A semiconductor cooling technology is currently used for chip heat dissipation. When direct current passes through a thermocouple composed of two different semiconductor materials (P-type and N-type), heat absorption or release occurs at the junction, known as the Peltier effect. The P-type semiconductor (hole-type) and the N-type semiconductor (electron-type) are connected by metal electrodes to form a thermopile. When current flows from the P-type to the N-type, heat is absorbed at the junction (cold junction); when current flows from the N-type to the P-type, heat is released at the junction (hot junction). Multiple thermopiles are connected in series or parallel to form a module, dissipating heat from the hot junction, thus continuously cooling the cold junction. The traditional semiconductor cooling structure is as follows: Figure 1 As shown, P / N semiconductor elements are connected in series in terms of electrical characteristics and in parallel in terms of thermal conduction. The current is in the direction shown in the figure, with the upper end being the heat absorption end and the lower end being the heat release end.
[0004] In traditional N / P type semiconductor materials, the heat absorption end and the heat dissipation end are integrated. In this case, the N / P type cooling material cannot be made too thin, otherwise the heat conduction between the hot end and the cold end will be too large, thereby reducing the cooling effect. In addition, traditional semiconductor cooling solutions also require external power to drive them.
[0005] Therefore, we propose a heat dissipation scheme utilizing thermoelectric conversion. According to Seebeck's principle, when two different conductor (or semiconductor) materials X and Y form a closed loop with a temperature difference (ΔT = Th - Tc, Th>Tc), the charge carriers (electrons or holes) inside the materials will undergo directional movement due to the temperature gradient, ultimately generating an electromotive force (EMF) in the loop. The energy generated by this EMF is stored using an energy harvesting circuit. Finally, the heat dissipated by the chip is converted into stored electrical energy. Summary of the Invention
[0006] To address the shortcomings of existing semiconductor cooling systems used for chip heat dissipation as described in the background, a heat dissipation solution utilizing thermoelectric conversion is proposed.
[0007] To achieve the above objectives, this utility model provides the following technical solution:
[0008] A chip heat dissipation structure includes a PCB board, a chip body, a hot end, a cold end, and an energy storage device. The chip body is mounted on the PCB board. The hot end is composed of at least one first heat treatment unit, and the cold end is composed of at least one second heat treatment unit. The hot end and the chip body are encapsulated as a whole. The hot end, the cold end, and the energy storage device are connected in sequence by wires to form an electrical circuit.
[0009] Preferably, the first heat treatment unit includes an upper copper wire layer, an N-type semiconductor layer, a metal connection layer, a P-type semiconductor layer and a lower copper wire layer connected in sequence;
[0010] The second heat treatment unit includes an upper copper wire layer, an N-type semiconductor layer, an insulating layer, a P-type semiconductor layer, and a lower copper wire layer connected in sequence;
[0011] The upper copper wire layer of the first heat treatment unit is connected to the upper copper wire layer of the second heat treatment unit by a wire, and the lower copper wire layer of the first heat treatment unit is connected to the lower copper wire layer of the second heat treatment unit by a wire. The N-type semiconductor layer and the P-type semiconductor layer of the second heat treatment unit are respectively connected to the energy storage device. The first heat treatment unit, the second heat treatment unit and the energy storage device form an electrical circuit.
[0012] Preferably, a thermally conductive layer is provided between the chip body and the hot end.
[0013] Preferably, multiple first heat treatment units are stacked vertically together, and an insulating layer is provided between the first heat treatment units; and multiple second heat treatment units are stacked vertically together, and an insulating layer is provided between the second heat treatment units.
[0014] Preferably, multiple first heat treatment units are horizontally arrayed on the chip body and encapsulated together with the chip body as a whole, and multiple second heat treatment units are horizontally arrayed and encapsulated together as a whole.
[0015] Preferably, the first heat treatment unit includes an upper copper wire layer, an N-type semiconductor layer, a metal connection layer, a P-type semiconductor layer and a lower copper wire layer connected in sequence;
[0016] The second heat treatment unit includes an upper copper wire layer, an N-type semiconductor layer, a metal interconnect layer, a P-type semiconductor layer, and a lower copper wire layer connected in sequence.
[0017] Multiple first heat treatment units are stacked vertically together, and an insulating layer is provided between the first heat treatment units; multiple second heat treatment units are stacked vertically together, and an insulating layer is provided between the second heat treatment units.
[0018] Multiple first heat treatment units and second heat treatment units have copper wire layers connected alternately in sequence and connected to the energy storage device to form a series circuit.
[0019] Compared with the prior art, the beneficial effects of this utility model are: 1. This device separates the hot end and cold end of the heat dissipation structure, which can reduce the direct heat conduction between the hot end and the cold end and improve the efficiency of thermoelectric conversion; 2. Not only does it not require power supply, but it also realizes the conversion of heat into electrical energy for storage, allowing waste heat energy to be converted into electrical energy, thus improving energy utilization; 3. It can realize the sealing of the hot end and the chip, increasing the heat conduction effect between the hot end and the chip; 4. By increasing the distance between the hot end and the cold end, the thickness of the N / P type cooling material can be designed to be very small, reducing Joule heating and improving thermoelectric conversion efficiency. Attached Figure Description
[0020] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model, used together with the embodiments of this utility model to explain this utility model, and do not constitute a limitation on this utility model. In the drawings:
[0021] Figure 1 This is a schematic diagram of the principle of a conventional semiconductor cooling chip.
[0022] Figure 2 This is a general structural block diagram of the present invention;
[0023] Figure 3 This is a schematic diagram of the internal structure of the parallel mode of this utility model;
[0024] Figure 4 This is a schematic diagram of the internal structure of the serial connection mode of this utility model;
[0025] Figure 5 This is a schematic diagram of the planar structure of this utility model.
[0026] In the diagram: 1. PCB board; 2. Chip body; 21. Thermal conductive layer; 3. Hot end; 4. Cold end; 5. Energy storage device; 61. First heat treatment unit; 62. Second heat treatment unit. Detailed Implementation
[0027] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.
[0028] Please see Figure 1-2This utility model provides the following technical solution: a chip heat dissipation structure, including a PCB board 1, a chip body 2, a hot end 3, a cold end 4, and an energy storage device 5, characterized in that: the chip body 2 is mounted on the PCB board 1; the hot end 3 is composed of at least one first heat treatment unit 61; the cold end 4 is composed of at least one second heat treatment unit 62; the hot end 3 and the chip body 2 are encapsulated as a whole; the hot end 3, the cold end 4, and the energy storage device 5 are sequentially connected by wires to form an electrical circuit; the hot end 3 is encapsulated with the chip and is used to absorb heat from the chip body 2; while the cold end 4 is placed away from the hot end 3.
[0029] According to Seebeck's principle, when two different conductor or semiconductor materials X and Y form a closed loop at both ends and there is a temperature difference between the two ends (ΔT = Th - Tc, Th>Tc), the charge carriers (electrons or holes) inside the materials will move in a directional manner due to the temperature gradient, and eventually generate an electromotive force in the loop.
[0030] When the hot end 3 absorbs heat from the chip, its temperature rises, creating a temperature difference with the cold end 4, thereby generating an electromotive force. This electromotive force is stored in the energy storage device 5, and ultimately, the heat dissipated by the chip is converted into stored energy.
[0031] Example 1 (Parallel Connection)
[0032] like Figure 3 The diagram shows the internal structure. The first heat treatment unit 61 includes an upper copper wire layer, an N-type semiconductor layer, a metal connection layer, a P-type semiconductor layer, and a lower copper wire layer connected in sequence.
[0033] The second heat treatment unit 62 includes an upper copper wire layer, an N-type semiconductor layer, an insulating layer, a P-type semiconductor layer, and a lower copper wire layer connected in sequence.
[0034] Figure 3 The left side is the heat absorption end, where the chip body and the first heat treatment unit are sealed together to reduce the distance between the hot end module and the chip body, thereby improving the heat conduction effect. The heat generated by the chip body 2 is conducted to the hot end 3. The right side is the cold end. The upper copper wire layer of the first heat treatment unit 61 and the upper copper wire layer of the second heat treatment unit 62 are connected by wires, and the lower copper wire layer of the first heat treatment unit 61 and the lower copper wire layer of the second heat treatment unit 62 are connected by wires. The N-type semiconductor layer and the P-type semiconductor layer of the second heat treatment unit 62 are respectively connected to the energy storage device 5. The first heat treatment unit 61, the second heat treatment unit 62, and the energy storage device 5 form an electrical circuit.
[0035] Because of the temperature difference between the hot end 3 and the cold end 4, an electromotive force is generated in the circuit. Specifically, in the first heat treatment unit 61, current flows from the N-type semiconductor to the P-type semiconductor, and electrons (in the opposite direction to the current) move from the lower-energy P-type material to the higher-energy N-type material, absorbing heat generated by the chip in the process. In the second heat treatment unit 62, electrons move from the higher-energy N-type material to the lower-energy P-type material, releasing heat and transferring it to the outside. During this process, the current generated in the circuit can also charge the energy storage device 5. Since the hot and cold ends are separate, the N / P-type semiconductor materials can be made very thin, thereby reducing impedance and Joule heating.
[0036] A thermally conductive layer 21 is provided between the chip body 2 and the hot end 3, so that heat can be better transferred to the heat treatment unit; the small ball between the copper wire layer and the N / P type material illustrates the connection between the copper wire layer and the N / P type material.
[0037] exist Figure 3 In the schematic diagram, only two first heat treatment units 61 are shown at the hot end 3, and only two second heat treatment units 62 are shown at the cold end 4. In reality, multiple first heat treatment units 61 are stacked vertically together, and an insulating layer is provided between the first heat treatment units 61. Similarly, multiple second heat treatment units 62 are stacked vertically together, and an insulating layer is provided between the second heat treatment units 62. We need to stack multiple heat treatment units to convert enough heat into electrical energy.
[0038] Work process: such as Figure 3 As shown, due to the temperature difference between the hot end 3 and the cold end 4, the current flows from the first heat treatment unit 61 to the second heat treatment unit 62, and then flows back to the first heat treatment unit 61 through the energy storage device 5, thus forming a circuit. According to Seebeck's principle, when the junction temperatures of materials are different, the charge carriers (electrons or holes) at the high-temperature end have higher kinetic energy and will diffuse towards the low-temperature end. Specifically, electrons from the P-type semiconductor in the first heat treatment unit 61 flow to the P-type semiconductor in the second heat treatment unit 62, and electrons from the N-type semiconductor in the second heat treatment unit 62 flow to the N-type semiconductor in the first heat treatment unit 61. This diffusion causes the high-temperature end to lose charge carriers and become positively charged, while the low-temperature end accumulates charge carriers and becomes negatively charged, thus forming a potential difference across the two ends of the material.
[0039] During this process, the current generated in the circuit can also charge the energy storage device 5.
[0040] Example 2 (Series Connection)
[0041] like Figure 4 As shown, the first heat treatment unit 61 includes an upper copper wire layer, an N-type semiconductor layer, a metal connection layer, a P-type semiconductor layer and a lower copper wire layer connected in sequence.
[0042] The second heat treatment unit 62 includes an upper copper wire layer, an N-type semiconductor layer, a metal connection layer, a P-type semiconductor layer and a lower copper wire layer connected in sequence.
[0043] Multiple first heat treatment units 61 are stacked vertically together, and an insulating layer is provided between the first heat treatment units 61; multiple second heat treatment units 62 are stacked vertically together, and an insulating layer is provided between the second heat treatment units 62.
[0044] The copper wire layers of multiple first heat treatment units 61 and second heat treatment units 62 are connected alternately in sequence by wires, and are connected to the energy storage device 5 through the N-type semiconductor and P-type semiconductor of the first heat treatment unit 61 at both ends to form a series circuit, forming a situation in which multiple first and second heat treatment units are connected in series to enhance the electromotive force generated by the temperature difference.
[0045] like Figure 5 As shown, in order to improve the conversion effect, in addition to stacking multiple heat treatment units in the vertical direction, multiple treatment units can also be arranged on the horizontal plane to form multiple heat treatment arrays, which improves the efficiency of heat conversion into electrical energy.
[0046] Finally, it should be noted that the above descriptions are merely preferred embodiments of this utility model and are not intended to limit the utility model. The selection and detailed description of these embodiments in this specification are for the purpose of better explaining the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A chip heat dissipation structure, characterized in that, The device includes a PCB board (1), a chip body (2), a hot end (3), a cold end (4), and an energy storage device (5). The chip body (2) is mounted on the PCB board (1). The hot end (3) is composed of at least one first heat treatment unit (61), and the cold end (4) is composed of at least one second heat treatment unit (62). The hot end (3) and the chip body (2) are sealed together as a whole. The hot end (3), the cold end (4), and the energy storage device (5) are connected in sequence by wires to form an electrical circuit.
2. The chip heat dissipation structure according to claim 1, characterized in that, The first heat treatment unit (61) includes an upper copper wire layer, an N-type semiconductor layer, a metal connection layer, a P-type semiconductor layer and a lower copper wire layer connected in sequence; The second heat treatment unit (62) includes an upper copper wire layer, an N-type semiconductor layer, an insulating layer, a P-type semiconductor layer and a lower copper wire layer connected in sequence; The upper copper wire layer of the first heat treatment unit (61) is connected to the upper copper wire layer of the second heat treatment unit (62) by a wire, the lower copper wire layer of the first heat treatment unit (61) is connected to the lower copper wire layer of the second heat treatment unit (62) by a wire, and the N-type semiconductor layer and P-type semiconductor layer of the second heat treatment unit (62) are respectively connected to the energy storage device (5). The first heat treatment unit (61), the second heat treatment unit (62) and the energy storage device (5) form an electrical circuit.
3. The chip heat dissipation structure according to claim 1, characterized in that, A thermally conductive layer (21) is provided between the chip body (2) and the hot end (3).
4. The chip heat dissipation structure according to claim 1, characterized in that, Multiple first heat treatment units (61) are stacked vertically together, and an insulating layer is provided between the first heat treatment units (61). Multiple second heat treatment units (62) are stacked vertically together, and an insulating layer is provided between the second heat treatment units (62).
5. The chip heat dissipation structure according to claim 1, characterized in that, Multiple first heat treatment units (61) are horizontally arrayed on the chip body (2) and encapsulated together on the chip body (2) as a whole, and multiple second heat treatment units (62) are horizontally arrayed and encapsulated together as a whole.
6. The chip heat dissipation structure according to claim 1, characterized in that, The first heat treatment unit (61) includes an upper copper wire layer, an N-type semiconductor layer, a metal connection layer, a P-type semiconductor layer and a lower copper wire layer connected in sequence; The second heat treatment unit (62) includes an upper copper wire layer, an N-type semiconductor layer, a metal connection layer, a P-type semiconductor layer and a lower copper wire layer connected in sequence; Multiple first heat treatment units (61) are stacked vertically together, and an insulating layer is provided between the first heat treatment units (61); multiple second heat treatment units (62) are stacked vertically together, and an insulating layer is provided between the second heat treatment units (62). The copper wire layers of multiple first heat treatment units (61) and second heat treatment units (62) are connected alternately in sequence and connected to the energy storage device (5) to form a series circuit.