A power semiconductor module

Abstract

The utility model provides a kind of power semiconductor module, compared with traditional ceramic substrate, the present scheme realizes the significant thinning of module and the improvement of heat dissipation performance.The power semiconductor module comprises: metal substrate;Thin film dielectric layer is arranged on the surface of the metal substrate;The thickness of the thin film dielectric layer is 3-6 μm;Conductive circuit is arranged on the surface of the thin film dielectric layer, die, is installed on the conductive circuit;Encapsulation layer is wrapped in the periphery of the metal substrate, the thin film dielectric layer, the conductive circuit and the die.

Description

Technical Field

[0001] This utility model relates to the field of power semiconductor devices, and in particular to a power semiconductor module. Background Technology

[0002] Power semiconductor modules are widely used in new energy, rail transportation, and industrial frequency conversion, among other fields. One of their core components is the insulating circuit substrate (such as DCB and AMB ceramic substrates) that carries and interconnects the chips. Traditional AMB substrates use silicon nitride (Si3N4) or alumina (Al2O3) ceramic as the insulating layer. While this provides high reliability, the ceramic layer thickness is typically 0.2-0.6 mm, limiting further miniaturization and reduction of thermal resistance. Furthermore, the bonding between the ceramic and copper layers relies on active metal brazing, a process involving high temperature and pressure, resulting in high manufacturing costs and susceptibility to ceramic cracking.

[0003] In pursuit of thinner dielectric layers, some researchers have attempted to deposit aluminum nitride (AlN) or aluminum oxide thin films on metal substrates using physical vapor deposition (PVD). However, these methods generally suffer from the following problems: 1) The deposited AlN films are mostly amorphous or randomly oriented, with poor crystallinity, resulting in thermal conductivity far below theoretical values ​​(typically <100 W / m·K), failing to meet the heat dissipation requirements of high-power devices; 2) The adhesion between the film and the substrate, as well as between the film and the upper copper circuitry, is insufficient, making it prone to delamination failure under thermal cycling; 3) There is a lack of reliable integration solutions compatible with existing thick copper circuitry processes.

[0004] Therefore, there is an urgent need to develop a new dielectric layer structure that combines ultra-thin thickness, ultra-high thermal conductivity, excellent insulation strength, and high reliable bonding strength in order to break through the performance bottleneck of traditional ceramic substrates. Utility Model Content

[0005] This invention provides a power semiconductor module that, compared with traditional ceramic substrates, achieves significant thinning and improved heat dissipation performance.

[0006] This utility model provides a power semiconductor module, comprising:

[0007] metal substrate;

[0008] A thin-film dielectric layer is disposed on the surface of the metal substrate; the thickness of the thin-film dielectric layer is 3–6 μm.

[0009] Conductive lines are disposed on the surface of the thin-film dielectric layer;

[0010] The grains are mounted on the conductive lines;

[0011] An encapsulation layer is wrapped around the metal substrate, the thin film dielectric layer, the conductive lines, and the outer periphery of the die.

[0012] In one embodiment, the metal substrate is a copper-based thermally conductive carrier plate.

[0013] In one embodiment, the thermal conductivity of the thin-film dielectric layer is 170–190 W / m·K.

[0014] In one embodiment, the X-ray diffraction orientation ratio I(002) / I(100) of the thin film dielectric layer is ≥2.5, and the oxygen content is ≤2 at.%.

[0015] In one embodiment, an active solder layer is further included between the thin-film dielectric layer and the conductive line.

[0016] In one embodiment, the dielectric strength of the thin film dielectric layer is >400V / μm.

[0017] In one embodiment, a reactive bonding layer is formed at the contact surface between the active solder layer and the thin film dielectric layer.

[0018] In one embodiment, the thickness of the reactive bonding layer is 50–200 nm.

[0019] In one embodiment, the thickness of the metal substrate is 0.3–1.2 mm.

[0020] In one embodiment, the thickness of the conductive line is 0.3–0.6 mm.

[0021] As can be seen from the above technical solutions, this utility model has the following advantages:

[0022] This invention provides a power semiconductor module comprising: a metal substrate; a thin-film dielectric layer disposed on the surface of the metal substrate; the thickness of the thin-film dielectric layer being 3–6 μm; conductive lines disposed on the surface of the thin-film dielectric layer; and a die mounted on the conductive lines; and an encapsulation layer surrounding the metal substrate, the thin-film dielectric layer, the conductive lines, and the die. The power semiconductor module provided by this invention has an extremely thin thickness, significantly reducing interface thermal resistance, improving heat dissipation efficiency compared to traditional ceramic solutions, and reducing weight and production costs. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of the structure of a power semiconductor module is provided for an embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this disclosure, and to fully understand and implement the process of how this disclosure applies technical means to solve technical problems and achieve corresponding technical effects, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. The embodiments of this disclosure and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort should fall within the protection scope of this disclosure.

[0026] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.

[0027] This embodiment provides a power semiconductor module, including:

[0028] Metal substrate 100; optionally, the metal substrate 100 is a copper-based thermally conductive carrier plate; wherein the specific material of the metal substrate 100 can be selected according to the product requirements, and this utility model does not limit it in this regard.

[0029] A thin film dielectric layer 200 is disposed on the surface of the metal substrate 100; the thickness of the thin film dielectric layer 200 is 3–6 μm; optionally, the thin film dielectric layer 200 is an aluminum nitride thin film; the thermal conductivity of the thin film dielectric layer 200 is 170–190 W / m·K; the dielectric strength of the thin film dielectric layer is >400 V / μm.

[0030] A conductive line 300 is disposed on the surface of the thin-film dielectric layer 200. Optionally, the material of the conductive line 300 is copper. Optionally, the line accuracy of the conductive line 300 is ±10μm.

[0031] The 400 die is mounted on the conductive line 300;

[0032] An encapsulation layer (not shown in the figure) surrounds the metal substrate 100, the thin-film dielectric layer 200, the conductive lines 300, and the die 400. Encapsulating the metal substrate 100, the thin-film dielectric layer 200, the conductive lines 300, and the die 400 within the encapsulation layer protects the power semiconductor module. This is because the encapsulation layer isolates the module from dust, moisture, and oxidation, thus preventing performance degradation or failure of the die 40 due to mechanical damage or chemical corrosion.

[0033] In one embodiment of the present invention, optionally, the metal substrate 100 is a copper-based thermally conductive substrate; and / or, the thickness of the metal substrate 100 is 0.3–1.2 mm.

[0034] In one embodiment of the present invention, the thermal conductivity of the thin film dielectric layer 200 is optionally 170–190 W / m·K.

[0035] Optionally, in one embodiment of this utility model, the X-ray diffraction orientation ratio I(002) / I(100) of the thin film dielectric layer 200 is ≥2.5, and the oxygen content is ≤2 at.%.

[0036] (002) and (100) are Miller indices, used to identify atomic planes in different directions within a crystal. They refer to the "coordinates" of the atomic arrangement direction inside the crystal. In materials like aluminum nitride (AlN), the atoms (Al and N atoms) inside are not randomly stacked, but arranged periodically in three-dimensional space according to a very strict and regular geometric pattern, forming a "space lattice". This structure is called a crystal. We can imagine cutting this lattice with a series of parallel, equally spaced planes, which will pass through a series of atoms. These planes are called crystal planes. Due to the symmetry of the atomic arrangement, there are many crystal planes in different directions. To distinguish these crystal planes in different directions, scientists use a set of integers (h, k, l) to name them, which are called Miller indices. (100) crystal plane: usually represents the family of planes perpendicular to the a-axis. (002) crystal plane: usually represents the family of planes perpendicular to the c-axis. This is particularly important for aluminum nitride (AlN), a hexagonal wurtzite structure. AlN is anisotropic, which means that its physical properties (such as thermal conductivity and electrical conductivity) are different in different directions. Its c-axis direction (i.e., the

[001] direction, corresponding to the normal direction of the (002) crystal plane) is the direction with the highest thermal conductivity.

[0037] In X-ray diffraction (XRD) experiments, crystal planes with different orientations produce diffraction peaks at different angles. The intensity (I) of a peak reflects how many crystal grains have that crystal plane that exactly satisfies the diffraction condition. I(002) represents the contribution intensity of the (002) crystal plane (i.e., the c-axis direction) to the diffraction signal among all crystal grains. I(100) represents the contribution intensity of the (100) crystal plane (i.e., the a-axis direction) to the diffraction signal among all crystal grains. The ratio I(002) / I(100)≥2.5 means: strong orientation growth (preferred orientation): This means that in AlN thin films grown by sputtering, the vast majority of small crystals (grains) are like "neatly arranged soldiers," with their c-axis highly consistent and perpendicular to the copper substrate surface. High crystallinity: This ratio will be close to 1 for randomly oriented polycrystalline thin films (i.e., grains with random orientations). A ratio much greater than 1 indicates that the thin film not only has consistent orientation but also very good crystallinity and few defects. Direct evidence of high thermal conductivity: As mentioned earlier, heat conducts fastest along the c-axis in AlN crystals. In thin films, almost all c-axis are perpendicular to the substrate, meaning that the direction of heat flow from the upper grain 400 downwards to the copper substrate for heat dissipation is precisely the direction in which the thermal conductivity of each AlN grain is highest. This is the fundamental guarantee for achieving a high thermal conductivity of 170-190 W / m·K, close to the theoretical value. Therefore, in this patent, the characteristic of "XRD orientation ratio I(002) / I(100)≥2.5" is a quantitative and measurable key indicator.

[0038] In one embodiment of this invention, an active solder layer is further included between the thin-film dielectric layer 200 and the conductive line 300. Optionally, the active solder layer is a Ti-Cu-Ag active solder. The active solder layer serves as a solder layer to connect the thin-film dielectric layer 200 and the conductive line 300.

[0039] In one embodiment of this utility model, optionally, the Ti content in the Ti–Cu–Ag active solder is 8–12 at.%; and the total composition of Cu and Ag is 100 at.%.

[0040] In one embodiment of this invention, a reactive bonding layer is formed at the contact surface between the Ti–Cu–Ag active solder layer and the thin-film dielectric layer 200. Optionally, the reactive bonding layer is a TiN / TiAlxNy reactive layer. Optionally, the thickness of the TiN / TiAlxNy reactive layer is 50–200 nm. The reactive bonding layer enhances the bonding force between the thin-film dielectric layer 200 and the conductive line 300.

[0041] In one embodiment of this utility model, optionally, the thickness of the reaction layer is 50–200 nm.

[0042] In one embodiment of the present invention, the thickness of the metal substrate 100 is optionally 0.3–1.2 mm.

[0043] In one embodiment of the present invention, optionally, the thickness of the conductive line 300 is 0.3–0.6 mm.

[0044] In one embodiment of this invention, a soldering terminal area is further included outside the encapsulation layer. The encapsulated power semiconductor module is connected to an external cable via the soldering terminals to achieve signal transmission.

[0045] In one embodiment of this utility model, the power semiconductor module is a multi-chip module (MCM) product.

[0046] The power semiconductor module method provided by this utility model has absolute effectiveness and advantages, as detailed below:

[0047] 1. Structural advantages: The thickness of the thin film dielectric layer 200 can be controlled to only 3–6 μm, so that the overall package thickness is reduced by more than 40% compared with traditional power semiconductor devices; the interface thermal resistance is significantly reduced, and the heat dissipation path efficiency is improved compared with traditional ceramic solutions; the weight is reduced by about 30–40%.

[0048] 2. Performance advantages: The thermal conductivity of the power semiconductor module reaches 170–190 W / m·K, which is 10–20% higher than that of ceramic substrates; the dielectric strength is >400V / μm, and the withstand voltage of 6μm film is about 2.4–3.0kV; the thick copper conductor can carry a current of 300–500A (depending on the line width and heat dissipation conditions); the thermal cycle life is >5000 cycles (-40℃ to +125℃) without obvious delamination.

[0049] 3. Manufacturing advantages: The process flow is simplified by about 60%, enabling automated production; material costs are reduced by about 40-60%; the film thickness, orientation and performance uniformity are high, making it suitable for large-area production.

[0050] The power semiconductor module provided by this utility model is applicable to electric vehicle power modules (main drive inverters, DC-DC converters), industrial power conversion (frequency converters, UPS), new energy power generation (photovoltaic, wind power inverters), rail transit traction converters, and aerospace power management systems, and has broad market application prospects.

[0051] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element limited by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0052] While the embodiments disclosed herein are as described above, the foregoing content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope of this disclosure; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A power semiconductor module, characterized in that, include: metal substrate; A thin-film dielectric layer is disposed on the surface of the metal substrate; the thickness of the thin-film dielectric layer is 3–6 μm. A conductive line is disposed on the surface of the thin film dielectric layer, and an active solder layer is further included between the thin film dielectric layer and the conductive line; The grains are mounted on the conductive lines; An encapsulation layer is wrapped around the metal substrate, the thin film dielectric layer, the conductive lines, and the outer periphery of the die.

2. The power semiconductor module according to claim 1, characterized in that, The thickness of the metal substrate is 0.3–1.2 mm.

3. The power semiconductor module according to claim 1, characterized in that, The thermal conductivity of the thin film dielectric layer is 170–190 W / m·K.

4. The power semiconductor module according to claim 1, characterized in that, The X-ray diffraction orientation ratio of the thin film dielectric layer is I(002) / I(100)≥2.

5.

5. The power semiconductor module according to claim 1, characterized in that, The dielectric strength of the thin film dielectric layer is >400 V / μm.

6. The power semiconductor module according to claim 1, characterized in that, The thickness of the conductive line is 0.3–0.6 mm.

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