A backside interconnect leadless piezoresistive pressure sensor package structure

Abstract

The utility model relates to a back interconnection leadless piezoresistive pressure sensor packaging structure. The utility model discloses a chip body, it includes silicon wafer, top layer ion implantation isolation oxide layer, bottom etching stop oxide layer, light doped P type piezoresistor and heavy doped P+ structure, top layer ion implantation isolation oxide layer sets up in the top surface of silicon wafer, back interconnection structure, it includes TSV through -hole, insulating layer and PAD electric connection metal block structure, leadless flip -chip connection structure, it includes PCB substrate and micro tin ball, and micro tin ball sets up between back pad part and PCB substrate, is used for making chip body and PCB substrate form leadless flip -chip electric connection. The utility model overcomes the problem of the prior art piezoresistive pressure sensor front pad and gold wire bonding structure occupies sensitive surface area, is easy to corrosion, is easy to break line and the problem that parasitic parameter is higher.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging structure technology, and in particular to a back-interconnected leadless piezoresistive pressure sensor packaging structure. Background Technology

[0002] Piezoresistive pressure sensors, with their advantages of simple structure, high sensitivity, fast response speed, and controllable cost, are widely used in industrial fluid detection, medical equipment, intelligent sensing, miniature precision pneumatic systems, and hydraulic systems. With the development of interventional medical catheters, miniature precision pipelines, and miniature pressure monitoring devices, sensor chips need further miniaturization and must maintain stable electrical connections under corrosive media, high-pressure impacts, and high-frequency vibration environments.

[0003] Existing piezoresistive pressure sensor chips typically employ a structure with a piezoresistive resistor arranged on the front, metal wiring leading out from the front, and pads on the front. While this structure facilitates conventional electrical connections, the metal wiring and pads occupy the sensitive surface area of ​​the chip, compressing the layout space of the piezoresistive diaphragm and the effective pressure-sensing area. As chip size further shrinks, the space conflict between the pads, wiring, and pressure-sensing diaphragm becomes even more pronounced, limiting the development of sensors towards ultra-miniaturization.

[0004] Meanwhile, the front-side metal wiring and pads of traditional chips are easily exposed to the external environment. When sensors are used in bodily fluids, acidic or alkaline liquids, high-salt spray environments, or other corrosive fluids, the exposed metal structure is prone to oxidation corrosion, electrochemical corrosion, or interface contamination, which can lead to problems such as changes in contact resistance, signal drift, and open-circuit failure. Covering the front-side metal structure with an additional protective layer may alter the pressure transmission path and increase film stress and the risk of interlayer failure.

[0005] Furthermore, most existing miniature piezoresistive pressure sensors use gold wire bonding to achieve electrical connection between the chip and external circuitry. While gold wire bonding has certain applicability in conventionally sized devices, it is prone to fatigue, loosening, or breakage under conditions such as ultra-small chips, high-pressure shocks, high-frequency vibrations, or bending. Additionally, the gold wire and bonding points can introduce parasitic parameters, adversely affecting the stable transmission of weak pressure signals. Utility Model Content

[0006] Therefore, the technical problem to be solved by this utility model is to overcome the problems of the front pad and gold wire bonding structure of the piezoresistive pressure sensor occupying sensitive surface area, being prone to corrosion, being prone to wire breakage, and having high parasitic parameters in the prior art.

[0007] To solve the above technical problems, this utility model provides a back-side interconnected leadless piezoresistive pressure sensor packaging structure, comprising: The chip body includes a silicon wafer, a top ion-implanted isolation oxide layer, a bottom etch-barrier oxide layer, a lightly doped P-type varistor, and a heavily doped P+ structure. The top ion-implanted isolation oxide layer is disposed on the top surface of the silicon wafer, the bottom etch-barrier oxide layer is disposed on the back surface of the silicon wafer, and the lightly doped P-type varistor and the heavily doped P+ structure are disposed on the upper part of the silicon wafer and are in contact with each other. The back-side interconnect structure includes a TSV via, an insulating layer, and a PAD electrical connection metal block structure. The TSV via extends from the back side of the bottom etch-block oxide layer to the back side of the heavily doped P+ structure. The insulating layer is disposed on the back side of the bottom etch-block oxide layer and extends to the inner wall of the TSV via. The PAD electrical connection metal block structure fills the TSV via and contacts the heavily doped P+ structure. The back side of the PAD electrical connection metal block structure extends to form a back-side pad portion. A leadless flip-chip connection structure includes a PCB substrate and micro solder balls, wherein the micro solder balls are disposed between the back pad portion and the PCB substrate to enable the chip body to form a leadless flip-chip electrical connection with the PCB substrate.

[0008] In one embodiment of this utility model, the aspect ratio of the TSV through hole is not less than 1:3.

[0009] In one embodiment of this utility model, the diameter of the TSV through hole is 10μm~200μm.

[0010] In one embodiment of this utility model, the insulating layer is made of SiO2.

[0011] In one embodiment of this utility model, the thickness of the insulating layer is 0.5μm~1μm.

[0012] In one embodiment of this utility model, the PAD electrical connection metal block structure is a SnAg alloy metal block structure, and the PAD electrical connection metal block structure includes a filling portion located in the TSV through hole and a back pad portion.

[0013] In one embodiment of this utility model, the width of the back pad portion is greater than the orifice width of the TSV via.

[0014] In one embodiment of this utility model, the shape of the TSV via includes an inverted cone shape near the back pad portion and a column shape connecting the end of the inverted cone shape.

[0015] The above-mentioned technical solution of this utility model has the following advantages compared with the prior art: This invention discloses a back-interconnected leadless piezoresistive pressure sensor packaging structure. The back-interconnect structure is formed through TSV vias, a SiO2 insulating layer, and a PAD electrical connection metal block structure. This allows the electrical signal from the lightly doped P-type piezoresistor to be led out from the back of the chip via a heavily doped P+ structure, reducing metal wiring and pad occupation on the sensitive surface of the chip and facilitating chip miniaturization. The electrical connection structure is located on the back of the chip, reducing the risk of the front metal being exposed to corrosive media and improving corrosion resistance and reliability. The flip-chip connection between the micro-solder balls and the PCB substrate eliminates the need for gold wire bonding, reducing the risk of gold wire breakage, loosening, and parasitic parameters. The PAD electrical connection metal block structure fills the TSV vias and forms the back-interconnect pads, providing both electrical connection and local support functions, improving the mechanical stability of the packaging structure under high-pressure shock and vibration environments. Attached Figure Description

[0016] To make the content of this utility model easier to understand, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0017] Figure 1 This is a schematic diagram of the back-interconnected leadless piezoresistive pressure sensor packaging structure according to an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the packaging structure of a leadless piezoresistive pressure sensor with a top cover pressure-bearing structure and a back-interconnected structure according to an embodiment of the present invention.

[0019] Explanation of reference numerals in the instruction manual: 1. Silicon wafer; 2. Top layer ion implantation isolation oxide layer; 3. Bottom layer etched barrier oxide layer; 4. Lightly doped P-type varistor; 5. Heavily doped P+ structure; 6. TSV via; 7. Insulating layer; 8. PAD electrical connection metal block structure; 9. Top cover pressure-bearing structure; 10. Back groove structure; 11. Micro solder balls; 12. PCB substrate. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments are not intended to limit the present invention.

[0021] In this utility model, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this utility model, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model.

[0022] In this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc. are understood to exclude the stated number; "above," "below," "within," etc. are understood to include the stated number. In the description of this utility model, if "first" or "second" is used, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the order of the indicated technical features.

[0023] In this utility model, unless otherwise explicitly defined, terms such as "set," "install," and "connect" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model based on the specific content of the technical solution.

[0024] Reference Figure 1 As shown, the present invention discloses a back-interconnected leadless piezoresistive pressure sensor packaging structure, comprising: The chip body includes a silicon wafer 1, a top ion-implanted isolation oxide layer 2, a bottom etch-barrier oxide layer 3, a lightly doped P-type varistor 4, and a heavily doped P+ structure 5. The top ion-implanted isolation oxide layer 2 is disposed on the top surface of the silicon wafer 1, the bottom etch-barrier oxide layer 3 is disposed on the back surface of the silicon wafer 1, the lightly doped P-type varistor 4 and the heavily doped P+ structure 5 are disposed on the upper part of the silicon wafer 1, and the heavily doped P+ structure 5 is in contact with the lightly doped P-type varistor 4. The top ion-implanted isolation oxide layer 2 is used to form electrical isolation of the varistor detection area, and the bottom etch-barrier oxide layer 3 is used to define the back via structure area. The back-side interconnect structure includes a TSV via 6, an insulating layer 7, and a PAD electrical connection metal block structure 8. The TSV via 6 extends from the back side of the bottom etch barrier oxide layer 3 to the back side of the heavily doped P+ structure 5. The insulating layer 7 is disposed on the back side of the bottom etch barrier oxide layer 3 and extends to the inner wall of the TSV via 6. The PAD electrical connection metal block structure 8 fills the TSV via 6 and contacts the heavily doped P+ structure 5. The back side of the PAD electrical connection metal block structure 8 extends to form a back-side pad portion. The leadless flip-chip connection structure includes a PCB substrate 12 and micro solder balls 11. The micro solder balls 11 are disposed between the back pad portion and the PCB substrate 12 to enable the chip body and the PCB substrate 12 to form a leadless flip-chip electrical connection.

[0025] Understandably, the lightly doped P-type varistor 4 is disposed on the upper part of the silicon wafer 1 to generate a resistance change under pressure. Multiple lightly doped P-type varistors 4 can form a Wheatstone bridge varistor layer. The heavily doped P+ structure 5 is in contact with the lightly doped P-type varistor 4 and is disposed at the end of the lightly doped P-type varistor 4, serving as an internal interconnect region between the lightly doped P-type varistor 4 and the back interconnect structure.

[0026] In one embodiment, boron ions are implanted into the silicon wafer 1 to form the lightly doped P-type varistor 4, forming a Wheatstone bridge used as the varistor layer to output feedback of the pressure signal magnitude. The boron ion implantation energy is 50 keV to 130 keV, and the implantation dose is 0.5 × 10⁻⁶. 14 cm -2 ~1.8×10 14 cm -2 ; Boron ions are implanted into the silicon wafer 1 on which the lightly doped P-type varistors 4 are formed to form heavily doped P+ structures 5 with internal interconnects. The implantation energy of the boron ions is 30 keV to 80 keV, and the implantation dose is 3 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 .

[0027] In one embodiment, the aspect ratio of the TSV through-hole 6 is not less than 1:3, and the diameter of the TSV through-hole 6 is 10μm~200μm.

[0028] In one embodiment, the insulating layer 7 is made of SiO2, and its thickness is 0.5 μm to 1 μm. The insulating layer 7 is used to isolate the PAD electrical connection metal block structure 8 from the sidewall of the TSV via 6, preventing leakage current from the via sidewall and improving the reliability of vertical interconnection.

[0029] In one embodiment, the PAD electrical connection metal block structure 8 is a SnAg alloy metal block structure, and the PAD electrical connection metal block structure 8 includes a filling portion located in the TSV through-hole 6 and the back pad portion.

[0030] In one embodiment, the width of the back pad portion is greater than the orifice width of the TSV via 6. Exemplarily, the shape of the TSV via 6 includes an inverted cone shape near the back pad portion and a cylindrical end connecting to the inverted cone shape. Thus, the back pad portion can serve as the connection surface for the micro solder balls 11, while simultaneously forming a localized pressure-bearing support platform on the back of the silicon wafer 1, improving the mechanical stability of the via area and the soldering area.

[0031] Specifically, the leadless flip-chip connection structure includes a PCB substrate 12 and micro solder balls 11. The micro solder balls 11 are disposed between the back pad portion and the PCB substrate 12 to form a leadless flip-chip electrical connection between the chip body and the PCB substrate 12. Multiple micro solder balls 11 can be provided, and each of the multiple micro solder balls 11 is connected to a corresponding multiple PAD electrical connection metal block structures 8.

[0032] In use, the pressure detection signal generated by the lightly doped P-type varistor 4 is transmitted to the PAD electrical connection metal block structure 8 through the heavily doped P+ structure 5, and then transmitted to the PCB substrate 12 through the micro solder balls 11. Since the electrical connection structure is mainly located on the back of the chip, the exposed metal wiring and pads on the sensitive side of the chip are reduced or avoided, which can reduce the corrosion of the metal interconnect structure by corrosive media.

[0033] Compared to gold wire bonding structures, this embodiment uses micro-solder balls 11 flip-chip connections, which can eliminate gold wires and bonding points, reduce the space occupied by gold wires in ultra-small chips, reduce the risk of gold wire fatigue fracture under high-frequency vibration, high-pressure impact or bending environments, and reduce the parasitic parameters introduced by gold wires, so that weak pressure electrical signals can be transmitted more stably.

[0034] Reference Figure 2 As shown, this embodiment may also include a top cover pressure-bearing structure 9. The top cover pressure-bearing structure 9 is bonded to the top surface (top ion implantation isolation oxide layer 2) of the chip body. The top cover pressure-bearing structure 9 is provided with a back groove structure 10, which forms an absolute pressure cavity and a pressure conduction position with the chip body.

[0035] In summary, this embodiment achieves back-side electrical signal output and leadless packaging of the piezoresistive pressure sensor by combining the TSV back-side interconnect structure and the micro-solder ball 11 flip-chip structure. This reduces the exposure of metal on the sensitive surface while improving the corrosion resistance, electrical connection reliability, and packaging mechanical stability of the ultra-small sensor.

[0036] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solution of this utility model and not to limit it. Although this utility model has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solution of this utility model without departing from the spirit and scope of the technical solution of this utility model, and all such modifications and substitutions should be covered within the scope of the claims of this utility model.

Claims

1. A back-side interconnect leadless piezoresistive pressure sensor packaging structure, characterized in that, include: The chip body includes a silicon wafer (1), a top ion implanted isolation oxide layer (2), a bottom etch barrier oxide layer (3), a lightly doped P-type varistor (4), and a heavily doped P+ structure (5). The top ion implanted isolation oxide layer (2) is disposed on the top surface of the silicon wafer (1), the bottom etch barrier oxide layer (3) is disposed on the back surface of the silicon wafer (1), and the lightly doped P-type varistor (4) and the heavily doped P+ structure (5) are disposed on the upper part of the silicon wafer (1) and are in contact with each other. The back-side interconnect structure includes a TSV via (6), an insulating layer (7), and a PAD electrical connection metal block structure (8). The TSV via (6) extends from the back side of the bottom etch barrier oxide layer (3) to the back side of the heavily doped P+ structure (5). The insulating layer (7) is disposed on the back side of the bottom etch barrier oxide layer (3) and extends to the inner wall of the TSV via (6). The PAD electrical connection metal block structure (8) fills the TSV via (6) and contacts the heavily doped P+ structure (5). The back side of the PAD electrical connection metal block structure (8) extends to form a back-side pad. The leadless flip-chip connection structure includes a PCB substrate (12) and micro solder balls (11). The micro solder balls (11) are disposed between the back pad portion and the PCB substrate (12) to enable the chip body and the PCB substrate (12) to form a leadless flip-chip electrical connection.

2. The back-side interconnected leadless piezoresistive pressure sensor packaging structure according to claim 1, characterized in that, The aspect ratio of the TSV through hole (6) is not less than 1:

3.

3. A back-interconnected leadless piezoresistive pressure sensor packaging structure according to claim 1 or 2, characterized in that, The diameter of the TSV through hole (6) is 10μm~200μm.

4. The back-side interconnected leadless piezoresistive pressure sensor packaging structure according to claim 1, characterized in that, The insulating layer (7) is made of SiO2.

5. A back-interconnected leadless piezoresistive pressure sensor packaging structure according to claim 1 or 4, characterized in that, The thickness of the insulating layer (7) is 0.5μm~1μm.

6. The back-side interconnected leadless piezoresistive pressure sensor packaging structure according to claim 1, characterized in that, The PAD electrical connection metal block structure (8) is a SnAg alloy metal block structure, and the PAD electrical connection metal block structure (8) includes a filling portion located in the TSV through hole (6) and the back pad portion.

7. The back-side interconnected leadless piezoresistive pressure sensor packaging structure according to claim 1, characterized in that, The width of the back pad portion is greater than the opening width of the TSV via (6).

8. The back-side interconnect leadless piezoresistive pressure sensor packaging structure according to claim 1, characterized in that, The shape of the TSV via (6) includes an inverted cone shape near the back pad portion and a column shape connecting the end of the inverted cone shape.

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