A function test circuit and test device of a PCIE interface

Abstract

The application provides a PCIE interface function test circuit and a test device, and relates to the technical field of circuit testing.The circuit comprises a to-be-tested intelligent module, a switch module and an Ethernet controller chip.A plurality of groups of signal transmission pins in a first PCIE interface of the to-be-tested intelligent module are respectively connected to a plurality of groups of first signal transmission pins of the switch module.Second signal transmission pins of the switch module are further connected to target signal transmission pins in a second PCIE interface of the Ethernet controller chip.A function control pin of the first PCIE interface is connected to a function control pin of the second PCIE interface.A selection enable pin of the first PCIE interface is connected to a selection pin of the switch module, so as to control any first signal transmission pin in the plurality of groups of first signal transmission pins and the second signal transmission pin to be conducted.The application can completely test the PCIE interface of the to-be-tested intelligent module, and meet the diversified test requirements of the PCIE interface.

Description

Technical Field

[0001] This application relates to the field of circuit testing technology, and more specifically, to a functional test circuit and test device for a PCIe interface. Background Technology

[0002] In the design of smart devices, functional testing of the PCIe (Peripheral Component Interconnect Express) interface of the smart module is crucial, as its accuracy directly affects the performance and stability of the device.

[0003] Currently, functional testing of the PCIe interface of smart modules mainly uses Ethernet interface circuits with PCIe interfaces, and network testing is conducted via network cables. However, most Ethernet controller chips on the market use 1-lane PCIe interfaces. For smart modules with 2-lane PCIe interfaces, it is impossible to comprehensively and completely test all their functions, resulting in incomplete test coverage and failing to meet the diverse testing needs of smart module PCIe interfaces. Utility Model Content

[0004] This application addresses the shortcomings of the prior art by providing a functional test circuit and test device for a PCIe interface, thereby resolving the problems existing in the prior art.

[0005] The technical solution adopted in the embodiments of this application is as follows: In a first aspect, embodiments of this application provide a functional test circuit for a PCIe interface, the functional test circuit comprising: a smart module under test, a switch module, and an Ethernet controller chip; The first PCIe interface of the smart module under test has multiple sets of signal transmission pins that are respectively connected to multiple sets of first signal transmission pins of the switch module, and the second signal transmission pin of the switch module is also connected to the target signal transmission pin in the second PCIe interface of the Ethernet controller chip. The function control pin of the first PCIe interface is connected to the function control pin of the second PCIe interface, and the selection enable pin of the first PCIe interface is connected to the selection pin of the switch module to control any one of the first signal transmission pins in the multiple sets of first signal transmission pins to be turned on with the second signal transmission pin.

[0006] In one embodiment, the plurality of signal transmission pins includes two sets of signal transmission pins, and the plurality of the first signal transmission pins includes two sets of first signal transmission pins; The switching module includes: a first switching unit, a second switching unit, a first inverter, and a second inverter; The first end of the first switch unit and the first end of the second switch unit are respectively two sets of the first signal transmission pins, which are used to connect to the two sets of signal transmission pins in the first PCIe interface; the second end of the first switch unit and the second end of the second switch unit serve as the second signal transmission pins. The input terminal of the first inverter is the selection pin of the switching module, the output terminal of the first inverter is connected to the control terminal of the first switching unit, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the control terminal of the second switching unit.

[0007] In one embodiment, the function control pin includes: a reference clock pin; The reference clock pin of the first PCIe interface is connected to the reference clock pin of the second PCIe interface.

[0008] In one embodiment, the function control pin further includes a clock request pin; The clock request pin of the first PCIe interface is connected to the clock request pin of the second PCIe interface.

[0009] In one embodiment, the function control pin further includes a reset pin; The reset pin of the first PCIe interface is connected to the reset pin of the second PCIe interface.

[0010] In one embodiment, the function control pin further includes a wake-up pin; The wake-up pin of the first PCIe interface is connected to the wake-up pin of the second PCIe interface.

[0011] In one embodiment, multiple sets of signal transmission pins in the first PCIe interface are respectively connected to multiple sets of first signal transmission pins of the switching module through multiple first signal lines; The second signal transmission pin of the switch module is connected to the target signal transmission pin in the second PCIE interface of the Ethernet controller chip via a second signal line. The function control pin of the first PCIe interface is connected to the function control pin of the second PCIe interface via a third signal line; the selection enable pin of the first PCIe interface is connected to the selection pin of the switch module via a fourth signal line.

[0012] Secondly, embodiments of this application also provide a testing apparatus, including: a test board, and a functional testing circuit for the PCIE interface described in any of the above embodiments disposed on the test board.

[0013] In one embodiment, the test board is provided with a first test fixture, a second test fixture, and a third test fixture; The first test fixture, the second test fixture, and the third test fixture are respectively used to fix the smart module under test, the switch module, and the Ethernet controller chip in the functional test circuit on the test board.

[0014] The beneficial effects of this application are as follows: This application provides a functional test circuit for a PCIe interface. The functional test circuit includes a smart module under test, a switch module, and an Ethernet controller chip. Multiple sets of signal transmission pins in the first PCIe interface of the smart module under test are respectively connected to multiple sets of first signal transmission pins of the switch module. The second signal transmission pin of the switch module is also connected to the target signal transmission pin in the second PCIe interface of the Ethernet controller chip. The functional control pin of the first PCIe interface is connected to the functional control pin of the second PCIe interface. The selection enable pin of the first PCIe interface is connected to the selection pin of the switch module to control any one of the multiple sets of first signal transmission pins to be turned on with the second signal transmission pin.

[0015] The multiple sets of first signal transmission pins of the switching module can be used to switch and test multiple sets of signal transmission pins in the first PCIE interface of the smart module under test, thereby realizing the complete test of the PCIE interface of the smart module under test, meeting the diverse test requirements of the PCIE interface, and using only one Ethernet controller chip, resulting in a simple circuit and reduced test costs. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the structural schematic diagrams of a functional test circuit for a PCIe interface provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the switch module provided in an embodiment of this application; Figure 3 A second schematic diagram of the functional test circuit for the PCIE interface provided in this application embodiment; Figure 4 The third schematic diagram of the functional test circuit of the PCIE interface provided in the embodiments of this application.

[0018] Explanation of reference numerals in the attached diagram: K1, first switch; K2, second switch; K3, third switch; K4, fourth switch; K5, fifth switch; K6, sixth switch; K7, seventh switch; K8, eighth switch. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0022] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can be a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] In modern computers and electronic devices, the PCIe (Peripheral Component Interconnect Express) interface, as a high-speed serial computer expansion bus standard, plays a crucial role in data transmission and functional interaction between devices. To ensure the proper functioning of the PCIe interface in intelligent modules, an Ethernet interface circuit with a PCIe interface is required for network testing via a network cable. However, most Ethernet controller chips currently on the market use a 1-lane PCIe interface, which cannot fully test intelligent modules with a 2-lane PCIe interface, resulting in incomplete test coverage.

[0025] Therefore, this application provides a functional test circuit for a PCIe interface that can simultaneously meet the testing requirements of 1-lane PCIe and 2-lane PCIe interfaces. It should be noted that, unless otherwise specified, the features in the embodiments of this application can be combined with each other. The following, in conjunction with the accompanying drawings, provides specific examples illustrating the functional test circuit for the PCIe interface provided by this application.

[0026] Figure 1 This is one of the structural schematic diagrams of the functional test circuit for the PCIe interface provided in the embodiments of this application, such as... Figure 1 As shown, the circuit includes the smart module under test, a switch module, and an Ethernet controller chip. They work together to complete the functional testing of the 1-lane PCIe interface and the 2-lane PCIe interface.

[0027] The smart module under test is the core test object of the entire test circuit. It integrates various complex functional modules and processing units. The first PCIe interface is the hardware interface for the smart module under test to interact with external devices and perform functional collaboration, including but not limited to: multiple sets of signal transmission pins, function control pins, and selection enable pins.

[0028] The switch module plays a crucial role in signal routing and switching in the test circuit. Its multiple sets of first signal transmission pins are connected one-to-one with the multiple sets of signal transmission pins of the first PCIe interface of the smart module under test, establishing a signal transmission path between the smart module and the switch module. The second signal transmission pin of the switch module is connected to the target signal transmission pin in the second PCIe interface of the Ethernet controller chip, establishing a signal transmission path between the switch module and the Ethernet controller chip.

[0029] As a crucial component of the test circuit, the Ethernet controller chip's second PCIe interface is used to receive signals from or send signals to the smart module under test. The Ethernet controller chip plays a dual role during testing: firstly, it acts as a signal receiver, converting signals received from the smart module under test via the second PCIe interface into a recognizable network data format; secondly, it also acts as a signal feedback source, feeding back the processing results and relevant status information to the smart module under test through the second PCIe interface after signal processing.

[0030] In the functional test circuit of the PCIe interface provided in this application, the connection relationship of each module is as follows: multiple sets of signal transmission pins in the first PCIe interface are respectively connected to multiple sets of first signal transmission pins of the switch module through multiple first signal lines; the second signal transmission pin of the switch module is connected to the target signal transmission pin in the second PCIe interface of the Ethernet controller chip through a second signal line; the functional control pin of the first PCIe interface is connected to the functional control pin of the second PCIe interface through a third signal line; and the selection enable pin of the first PCIe interface is connected to the selection pin SEL of the switch module through a fourth signal line to control any one of the multiple sets of first signal transmission pins to be turned on with the second signal transmission pin.

[0031] The functional test circuit also includes an Ethernet interface. The network interface of the Ethernet controller chip is also connected to the Ethernet interface, enabling the Ethernet controller chip to achieve bidirectional connection between the smart module under test and the Ethernet network through the Ethernet interface. For example, when the smart module under test needs to send data, the Ethernet controller chip converts the digital signals in the smart module under test into electrical or optical signals suitable for transmission over Ethernet and sends them out through the Ethernet interface. When receiving data, the Ethernet controller chip converts the signals received by the Ethernet interface into digital signals that the smart module under test can understand and transmits them to the smart module under test for processing.

[0032] The following is in conjunction with the appendix Figure 2 and attached Figure 3 Taking the multiple signal transmission pins in the first PCIE interface of the smart module under test as two groups (e.g., including 1-lane PCIE interface and 2-lane PCIE interface), and the multiple first signal transmission pins of the switch module as two groups, the functional test circuit of the PCIE interface provided in this application is further explained.

[0033] Figure 2 This is a schematic diagram of the structure of the switch module provided in the embodiments of this application, as shown below. Figure 2As shown, the switching module includes a first switching unit, a second switching unit, a first inverter INV1, and a second inverter INV2. The first switching unit includes a first switch K1, a second switch K2, a third switch K3, and a fourth switch K4. The second switching unit includes a fifth switch K5, a sixth switch K6, a seventh switch K7, and an eighth switch K8. In the two sets of signal transmission pins of the first PCIe interface, the 1-lane PCIe interface includes a positive transmit pin PCIE_TX0_P and a negative transmit pin PCIE_TX0_N. "0" indicates that this is channel 0 in the PCIe transmit channel. When the smart module sends data to the Ethernet controller chip via the PCIe bus, PCIE_TX0_P and PCIE_TX0_N are used to transmit the data from the smart module under test to the Ethernet controller chip in the form of differential signals in channel 0. The 1-lane PCIe interface also includes a positive receive pin PCIE_RX0_P and a negative receive pin PCIE_RX0_N. When the smart module receives data sent by the Ethernet controller chip via the PCIe bus, PCIE_RX0_P and PCIE_RX0_N are used to receive the data sent by the Ethernet controller chip in the form of differential signals in channel 0.

[0034] The 2-lane PCIe interface includes a positive transmit pin PCIE_TX1_P and a negative transmit pin PCIE_TX1_N. "1" indicates that this is the first channel in the PCIe transmit channel. When the smart module sends data to the Ethernet controller chip via the PCIe bus, PCIE_TX1_P and PCIE_TX1_N are used to transmit the data from the smart module under test to the Ethernet controller chip in differential signal form in the first channel. The 2-lane PCIe interface also includes a positive receive pin PCIE_RX1_P and a negative receive pin PCIE_RX1_N. When the smart module receives data sent by the Ethernet controller chip via the PCIe bus, PCIE_RX1_P and PCIE_RX1_N are used to receive the data sent by the Ethernet controller chip in differential signal form in the first channel.

[0035] Figure 3 This is a second schematic diagram of the structure of the functional test circuit for the PCIe interface provided in the embodiments of this application, as shown below. Figure 3 As shown, the first terminal of the first switching unit (that is, the first terminals of switches K1, K2, K3, and K4) respectively correspond to Figure 2 The first terminals of the second switch unit (i.e., the first terminals of switches K5, K6, K7, and K8) correspond to B0+, B0-, B1+, and B1- respectively. Figure 2C0+, C0-, C1+, and C1- in the diagram represent two sets of first signal transmission pins, which are used to connect to the two sets of signal transmission pins in the first PCIe interface. Specifically, the first end B0+ of K1 is used to connect to the positive transmit pin PCIE_TX0_P of the 1-lane PCIe interface, the first end B0- of K2 is used to connect to the negative transmit pin PCIE_TX0_N of the 1-lane PCIe interface, the first end B1+ of K3 is used to connect to the positive receive pin PCIE_RX0_P of the 1-lane PCIe interface, and the first end B1- of K4 is used to connect to the negative receive pin PCIE_RX0_N of the 1-lane PCIe interface.

[0036] The first terminal C0+ of K5 is used to connect to the positive transmit pin PCIE_TX1_P of the 2-lane PCIE interface; the first terminal C0- of K6 is used to connect to the negative transmit pin PCIE_TX1_N of the 2-lane PCIE interface; the first terminal C1+ of K7 is used to connect to the positive receive pin PCIE_RX1_P of the 2-lane PCIE interface; and the first terminal C1- of K8 is used to connect to the negative receive pin PCIE_RX1_N of the 2-lane PCIE interface.

[0037] The second terminal of the first switching unit and the second terminal of the second switching unit serve as the second signal transmission pins (corresponding to...). Figure 2 The input of the second inverter INV2 is the selection pin SEL of the switch module. The output of the second inverter INV2 is connected to the control terminal of the first switch unit (K1, K2, K3, K4). The output of the second inverter INV2 is also connected to the input of the first inverter INV1. The output of the first inverter INV1 is connected to the control terminal of the second switch unit (K5, K6, K7, K8).

[0038] A0+, A0-, A1+, and A1- are connected to PCIE_RXP, PCIE_RXN, PCIE_TXP, and PCIE_TXN of the Ethernet controller chip, respectively. PCIE_RXP is the positive receive pin of the Ethernet controller chip, and PCIE_RXN is the negative receive pin. The Ethernet controller chip receives data sent by the smart module under test through PCIE_RXP and PCIE_RXN. PCIE_TXP is the positive transmit pin of the Ethernet controller chip, and PCIE_TXN is the negative transmit pin. The Ethernet controller chip sends data to the smart module under test through PCIE_TXP and PCIE_TXN.

[0039] The first PCIe interface selection enable pin could be, for example, the SEL_EN pin, which is connected to the selection pin SEL of the switching module via the fourth signal line.

[0040] When the PCIE interface functional test for the smart module under test is started, the smart module under test pulls the SEL pin of the switch module high through the SEL_EN pin. At this time, the signal path of the switch module is B0+>A0+, B0->A0-, B1+>A1+, B1->A1-. That is, B0+ is connected to A0+, B0- is connected to A0-, B1+ is connected to A1+, and B1- is connected to A1-. In the 1-lane PCIE interface of the smart module under test, PCIE_TX0_P is connected to the PCIE_RXP of the Ethernet controller chip, PCIE_TX0_N is connected to the PCIE_RXN of the Ethernet controller chip, PCIE_RX0_P is connected to the PCIE_TXP of the Ethernet controller chip, and PCIE_RX0_N is connected to the PCIE_TXN of the Ethernet controller chip. The 1-lane PCIE interface (TX0, RX0 signals) of the smart module under test can communicate with the Ethernet controller chip. When the smart module under test completes Ethernet communication and can ping the fixed IP address, the 1-lane PCIE interface test is considered successful; otherwise, the test is considered abnormal.

[0041] After the smart module under test completes the test of the 1-lane PCIE interface, the SEL_EN of the smart module under test pulls the SEL pin of the switch module S1 low. At this time, the signal path of the switch module is C0+>A0+, C0->A0-, C1+>A1+, C1->A1-. That is, C0+ is connected to A0+, C0- is connected to A0-, C1+ is connected to A1+, and C1- is connected to A1-. In the 2-lane PCIE interface of the smart module under test, PCIE_TX1_P is connected to the PCIE_RXP of the Ethernet controller chip, PCIE_TX1_N is connected to the PCIE_RXN of the Ethernet controller chip, PCIE_RX1_P is connected to the PCIE_TXP of the Ethernet controller chip, and PCIE_RX1_N is connected to the PCIE_TXN of the Ethernet controller chip. The 2-lane PCIe interface (TX1, RX1 signals) of the smart module under test can communicate with the Ethernet controller chip. When the smart module under test completes Ethernet communication and can ping the fixed IP address, the 2-lane PCIe interface test is considered successful; otherwise, the test is considered abnormal.

[0042] In one embodiment, Figure 4 The third schematic diagram of the functional test circuit for the PCIe interface provided in the embodiments of this application is shown below. Figure 4As shown, in the first PCIe interface of the smart module under test, the function control pins include a reference clock pin. The reference clock pin is connected to the reference clock pin in the second PCIe interface on the Ethernet controller chip. Based on this connection, the smart module under test can obtain a clock differential signal from the Ethernet controller chip.

[0043] For example, the reference clock pins in the first PCIe interface may include a positive reference clock pin PCIE_RFE_CLK_P and a negative reference clock pin PCIE_RFE_CLK_N. The positive reference clock pin PCIE_RFE_CLK_P in the first PCIe interface is connected to the positive reference clock pin PCIE_RFE_CLK_P in the second PCIe interface on the Ethernet controller chip, and the PCIE_RFE_CLK_P signal is provided to the Ethernet controller chip by the smart module under test; the negative reference clock pin PCIE_RFE_CLK_N in the first PCIe interface is connected to the negative reference clock pin PCIE_RFE_CLK_N in the second PCIe interface on the Ethernet controller chip, and the PCIE_RFE_CLK_N signal is provided to the Ethernet controller chip by the smart module under test.

[0044] Continue to refer to Figure 4 In the first PCIe interface of the smart module under test, the function control pins also include a clock request pin, and the clock request pin of the first PCIe interface is connected to the clock request pin of the second PCIe interface.

[0045] For example, the clock request pin in the first PCIe interface could be PCIe_CLK_REQ. This pin is connected to the clock request pin PCIe_CLK_REQ in the second PCIe interface on the Ethernet controller chip. When the smart module under test enters a low-power state and needs to be reactivated, it will request the recovery of the clock signal through the PCIe_CLK_REQ pin. At this time, the Ethernet controller chip sends the clock differential signal to the positive reference clock pin PCIe_RFE_CLK_P and the negative reference clock pin PCIe_RFE_CLK_N in the first PCIe interface of the smart module under test through the positive reference clock pin PCIe_RFE_CLK_P and the negative reference clock pin PCIe_RFE_CLK_N in its second PCIe interface.

[0046] Continue to refer to Figure 4 In the first PCIe interface of the smart module under test, the function control pins also include a reset pin, and the reset pin of the first PCIe interface is connected to the reset pin of the second PCIe interface.

[0047] For example, the reset pin in the first PCIe interface can be PCIe_RESET_N. This pin is connected to the reset pin PCIe_RESET_N in the second PCIe interface on the Ethernet controller chip. When the smart module under test encounters an abnormal situation, such as a data transmission error, link failure, or device hang, triggering the PCIe_RESET_N signal can restore the smart module under test from the abnormal state. The smart module under test will re-initialize and retrain the link, and attempt to re-establish a normal communication link, thereby enabling the smart module under test to continue to operate stably.

[0048] Continue to refer to Figure 4 In the first PCIe interface of the smart module under test, the function control pins also include a wake-up pin, and the wake-up pin of the first PCIe interface is connected to the wake-up pin of the second PCIe interface.

[0049] For example, the wake-up pin in the first PCIe interface can be PCIe_WAKE_N. This pin is connected to the wake-up pin PCIe_WAKE_N in the second PCIe interface on the Ethernet controller chip. When the smart module under test enters a sleep state and the main power supply Vcc stops supplying power, a wake-up request can be submitted to the Ethernet controller chip through the PCIe_WAKE_N pin to wake up the smart module under test.

[0050] Optionally, when the test fixture space is insufficient or the test conditions do not include Ethernet, the Ethernet interface can be omitted, and the smart module under test and the Ethernet controller chip can be connected via software to determine whether the PCIe interface is normal.

[0051] Optionally, since the PCIe interface speed of the smart module under test is usually relatively high, the channel bandwidth of the switching module is set to be greater than 1GHz to provide sufficient signal transmission capability, enabling the smart module under test and the Ethernet controller chip to interact with each other at high speed, avoiding data congestion due to bandwidth limitations, thereby improving the performance and efficiency of the entire system.

[0052] Based on the PCIE interface functional test circuit provided in the above embodiments, this application also provides a test device, including a test board and the PCIE interface functional test circuit described in any of the above embodiments disposed on the test board.

[0053] The test board is also equipped with a first test fixture, a second test fixture, and a third test fixture. The first test fixture is used to fix the smart module under test in the functional test circuit onto the test board, the second test fixture is used to fix the switch module onto the test board, and the third test fixture is used to fix the Ethernet controller chip onto the test board. That is, the smart module under test, the switch module, and the Ethernet controller chip are all integrated on the test board.

[0054] Optionally, since the PCIe interface traces have impedance requirements, when completing the above circuit design on the test board, the differential impedance needs to be 85 Ohm~100 Ohm.

[0055] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A functional test circuit for a PCIe interface, characterized in that, The functional test circuit includes: the smart module under test, the switch module, and the Ethernet controller chip; The first PCIe interface of the smart module under test has multiple sets of signal transmission pins that are respectively connected to multiple sets of first signal transmission pins of the switch module, and the second signal transmission pin of the switch module is also connected to the target signal transmission pin in the second PCIe interface of the Ethernet controller chip. The function control pin of the first PCIe interface is connected to the function control pin of the second PCIe interface, and the selection enable pin of the first PCIe interface is connected to the selection pin of the switch module to control any one of the first signal transmission pins in the multiple sets of first signal transmission pins to be turned on with the second signal transmission pin.

2. The circuit according to claim 1, characterized in that, The multiple sets of signal transmission pins include: two sets of signal transmission pins, and the multiple sets of the first signal transmission pins include: two sets of first signal transmission pins; The switching module includes: a first switching unit, a second switching unit, a first inverter, and a second inverter; The first end of the first switch unit and the first end of the second switch unit are respectively two sets of the first signal transmission pins, which are used to connect to the two sets of signal transmission pins in the first PCIe interface; the second end of the first switch unit and the second end of the second switch unit serve as the second signal transmission pins. The input terminal of the first inverter is the selection pin of the switching module, the output terminal of the first inverter is connected to the control terminal of the first switching unit, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the control terminal of the second switching unit.

3. The circuit according to claim 1, characterized in that, The function control pins include: a reference clock pin; The reference clock pin of the first PCIe interface is connected to the reference clock pin of the second PCIe interface.

4. The circuit according to claim 1, characterized in that, The function control pin also includes: a clock request pin; The clock request pin of the first PCIe interface is connected to the clock request pin of the second PCIe interface.

5. The circuit according to claim 1, characterized in that, The function control pin also includes: a reset pin; The reset pin of the first PCIe interface is connected to the reset pin of the second PCIe interface.

6. The circuit according to claim 1, characterized in that, The function control pin also includes: a wake-up pin; The wake-up pin of the first PCIe interface is connected to the wake-up pin of the second PCIe interface.

7. The circuit according to claim 1, characterized in that, In the first PCIe interface, multiple sets of signal transmission pins are respectively connected to multiple sets of first signal transmission pins of the switching module through multiple first signal lines; The second signal transmission pin of the switch module is connected to the target signal transmission pin in the second PCIE interface of the Ethernet controller chip via a second signal line. The function control pin of the first PCIe interface is connected to the function control pin of the second PCIe interface via a third signal line; the selection enable pin of the first PCIe interface is connected to the selection pin of the switch module via a fourth signal line.

8. The circuit according to claim 1, characterized in that, The functional test circuit also includes an Ethernet interface, and the network interface of the Ethernet controller chip is also connected to the Ethernet interface.

9. A testing device, characterized in that, include: The test board, and the functional test circuit of the PCIE interface as described in any one of claims 1-8 disposed on the test board.

10. The apparatus according to claim 9, characterized in that, The test board is equipped with: a first test fixture, a second test fixture, and a third test fixture; The first test fixture, the second test fixture, and the third test fixture are respectively used to fix the smart module under test, the switch module, and the Ethernet controller chip in the functional test circuit on the test board.

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