Semiconductor photonic device

Abstract

Various embodiments of the present utility model relate to a semiconductor photonic device. The semiconductor photonic device includes a light modulator structure, the light modulator structure is thermally coupled to a heater structure, and the heater structure is used for heating the waveguide structure of the light modulator structure to modulate the input optical signal through thermo-optic modulation. The heater structure includes a semiconductor heater component, the semiconductor heater component is electrically coupled to a first electrode (for example, a Vπ electrode) through one or more first contacts and is electrically coupled to a second electrode (for example, a ground electrode) through a plurality of second contacts. The one or more first contacts and the plurality of second contacts enable an electrical input to be applied to the semiconductor heater component across a plurality of parallel contact points, thereby enabling a lower phase shift voltage to be used to achieve sufficient power to heat the waveguide structure of the light modulator structure.

Description

Technical Field

[0001] This utility model relates to a semiconductor photonic device. Background Technology

[0002] Semiconductor devices can be configured to use optical signals for high-speed and secure data transmission between integrated circuits and / or semiconductor dies within the semiconductor device. Optical signals can be transmitted via waveguides within the semiconductor device. Waveguides confine the optical signal, reducing optical loss and improving propagation efficiency. Data can be encoded into optical signals by modulating the light into optical pulses using an optical modulator. These optical pulses are then transmitted to the waveguides to propagate to other areas of the semiconductor device. Utility Model Content

[0003] This invention provides a semiconductor photonic device. The semiconductor photonic device includes a semiconductor waveguide and a semiconductor heater structure. The semiconductor heater structure is parallel to the semiconductor waveguide and coupled to it through a semiconductor connection region. The semiconductor heater structure includes a doped semiconductor region, a first contact structure, a second contact structure, and a third contact structure. The first contact structure is located at a first end of the doped semiconductor region. The second contact structure is located at a second end of the doped semiconductor region opposite to the first end. The third contact structure is located on the doped semiconductor region, wherein the third contact structure is located between the first contact structure and the second contact structure.

[0004] Another aspect of this invention provides a method for forming a semiconductor photonic device. The method includes forming an optical modulator structure and a modulator heater structure in a semiconductor layer above a first dielectric layer of the semiconductor photonic device. The modulator heater structure is laterally adjacent to the optical modulator structure, wherein the optical modulator structure and the modulator heater structure are physically coupled in the semiconductor layer and arranged along a first direction in the semiconductor photonic device. The method further includes forming a second dielectric layer above the first dielectric layer, above the optical modulator structure, and above the modulator heater structure. The method further includes forming a plurality of recesses in the second dielectric layer above the modulator heater structure. The method further includes forming a first contact structure, a second contact structure, and a third contact structure in the plurality of recesses. The first contact structure is located at a first end of the modulator heater structure, the second contact structure is located at a second end of the modulator heater structure opposite to the first end, and the third contact structure is laterally located between the first contact structure and the second contact structure in a second direction substantially perpendicular to the first direction.

[0005] Another aspect of this utility model provides a semiconductor photonic device. The semiconductor photonic device includes an optical modulator structure in a semiconductor layer. The semiconductor photonic device also includes a modulator heater structure coupled to the optical modulator structure through one or more semiconductor interconnect regions in the semiconductor layer. The modulator heater structure includes a first contact structure, a second contact structure, a third contact structure, a first semiconductor heater section, and a second semiconductor heater section. The third contact structure is located between the first contact structure and the second contact structure. The first semiconductor heater section is located between the first contact structure and the third contact structure. The second semiconductor heater section is located between the second contact structure and the third contact structure.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figures 1A to 1E This is a diagram of the example semiconductor photonic device described in this article.

[0008] Figure 2A and Figure 2B This is a diagram illustrating an example implementation of heating the waveguide of the optical modulator structure described herein.

[0009] Figures 3A to 3O This is a diagram illustrating an exemplary embodiment of the formation of a semiconductor photonic device (or part thereof) as described herein.

[0010] Figures 4A to 4C This is a diagram of the example semiconductor photonic device described in this article.

[0011] Figure 5A and Figure 5B This is a diagram of the example semiconductor photonic device described in this article.

[0012] Figure 6A and Figure 6B This is a diagram of the example semiconductor photonic device described in this article.

[0013] Figure 7 This is a flowchart of an example process related to the formation of a semiconductor photonic device as described herein. Detailed Implementation

[0014] This utility model provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the utility model. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby potentially preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one component or feature and another shown in the figures. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0016] Photonic integrated circuits in semiconductor photonic devices may include optical modulator structures. Some optical modulator structures modulate input optical signals via electro-optic modulation. An electrical input (e.g., current, voltage) is applied to the terminals of the optical modulator structure, and the electrical input generates an electric field within the optical modulator structure. The electric field alters the resonant frequency of the optical modulator structure, thereby modulating the phase of the input optical signal.

[0017] Another type of optical modulator structure includes a thermo-optical modulator that modulates the phase of the input optical signal via a thermo-optical effect. A thermal phase shifter (TPS) structure (or thermo-optical phase shift heater) is thermally coupled to the waveguide of the optical modulator structure. An electrical input is applied to the terminals of the TPS structure, and the resistance of the TPS structure dissipates the electrical input as heat. This heat is supplied to the waveguide, changing its temperature (and thus its refractive index), thereby allowing the phase of the input optical signal to be altered.

[0018] The TPS structure of a thermo-optical modulator can include one or more types of materials. In some cases, the TPS structure includes one or more metallic materials. Metallic materials typically have low resistivity and enable the TPS structure to operate at a relatively low phase shift voltage (V). πTo generate sufficient power, TPS structures in other cases incorporate one or more semiconductor materials, such as silicon (Si). Semiconductor materials typically have higher thermal conductivity than metallic materials, allowing TPS structures to reach higher temperatures more efficiently than those made of metal. However, semiconductor materials also have higher resistivity, requiring significantly higher phase-shift voltages to achieve sufficient power generation compared to metal-based TPS structures. Higher phase-shift voltages can increase the power dissipation of the TPS structure, thus reducing its operating efficiency.

[0019] In some embodiments described herein, the semiconductor photonic device includes an optical modulator structure thermally coupled to a heater structure (e.g., a TPS structure or a thermo-optical phase-shifting heater), a waveguide structure for heating the optical modulator structure to modulate an input optical signal via thermo-optical modulation. The heater structure includes a semiconductor heater assembly electrically coupled to a first electrode (e.g., V0) via one or more first contacts. π The first electrode is electrically coupled to a second electrode (e.g., a ground electrode) via multiple second contacts. One or more first contacts and multiple second contacts enable an electrical input to be applied to the semiconductor heater assembly through multiple parallel contact points, thereby allowing a lower phase-shift voltage to be used to achieve power sufficient to heat the waveguide structure of the optical modulator structure. Specifically, one or more first contacts and multiple second contacts effectively divide the semiconductor heater assembly into multiple segments, and each segment is coupled to a contact pair comprising one of the one or more first contacts and one of the multiple second contacts. The contact pairs are configured to locally power a segment, rather than powering the entire area of ​​the semiconductor heater assembly, thereby achieving lower resistance and enabling the use of a lower phase-shift voltage.

[0020] Therefore, by using one or more first contacts and multiple second contacts to divide the semiconductor heater assembly into multiple sections, the heater structure can operate more effectively at lower voltages. Furthermore, because the heater structure can operate at lower voltages, it integrates with other complementary metal-oxide-semiconductor (CMOS) components in the semiconductor photonic device.

[0021] It is compatible with metal-oxide-semiconductor (CMOS) integrated circuit devices and can be formed using CMOS manufacturing processes similar to those used for CMOS integrated circuit devices.

[0022] Figures 1A to 1E This is a diagram of the example semiconductor photonic device 100 described herein. Figure 1A A top view of the semiconductor photonic device 100 is shown. Figure 1AAs shown, the semiconductor photonic device 100 includes a photonic integrated circuit 102 configured for optical communication between the semiconductor photonic device 100 and / or between the semiconductor photonic device 100 and another device outside the semiconductor photonic device 100. The photonic integrated circuit 102 includes a waveguide structure 104 optically and / or physically coupled to an optical modulator structure 106. The photonic integrated circuit 102 may also include another waveguide structure 108, wherein the waveguide structures 104 and 108 are coupled to the optical modulator structure 106 at opposite ends.

[0023] The photonic integrated circuit 102 may include a Mach-Zender modulator (MZM) structure or another type of optical modulator integrated circuit, wherein an optical signal (e.g., an input optical signal, a modulated optical signal) is coupled between one or more waveguides (e.g., waveguide structure 104 and / or waveguide structure 108) and the optical modulator structure 106. Waveguide structure 104 may correspond to an input waveguide for providing the optical signal to the optical modulator structure 106, while waveguide structure 108 may correspond to an output waveguide for receiving the modulated optical signal from the optical modulator structure 106. Therefore, the optical signal can primarily travel along... Figure 1A The x-direction propagation shown is through the photonic integrated circuit 102.

[0024] Waveguide structures 104 and 108 may each comprise an approximately linear structure of silicon (Si), germanium (Ge), and / or other waveguide materials through which optical signals can propagate. Waveguide structures 104 and 108 may each extend along the x-direction. Alternatively, waveguide structures 104 and / or 108 may be curved or have other top-view shapes or profiles.

[0025] The optical modulator structure 106 may include silicon (Si) or another type of semiconductor material, and may include in Figure 1A The diagram shows multiple optical modulator segments 110a and 110b spaced apart from each other along the y-direction. The ends of optical modulator segments 110a and 110b are coupled to waveguide structure 104, and optical signals received from waveguide structure 104 are shunt between optical modulator segments 110a and 110b. This allows optical signals propagating through optical modulator segments 110a and 110b to be modulated in different ways (e.g., modulated at different frequencies or phases), or allows optical signals propagating through one of optical modulator segments 110a or 110b to be modulated while optical signals propagating through the other of optical modulator segments 110a or 110b are not modulated.

[0026] Figure 1AA detailed view of a portion of the optical modulator section 110a is provided for further illustration. The optical modulator section 110b may have a similar configuration to that shown in the partial detailed view of the optical modulator section 110a, or it may have a different configuration.

[0027] like Figure 1A As shown in the detailed view, the optical modulator structure 106 includes multiple pad regions 112a and 112b, which are coupled to corresponding connection regions 114a and 114b, respectively. Furthermore, the pad regions 112a and 112b are coupled to the waveguide structure 116 of the optical modulator structure 106 via the connection regions 114a and 114b, respectively. The pad regions 112a and 112b are laterally adjacent in the y-direction.

[0028] Opposite sides of waveguide structure 116. Pad regions 112a and 112b, connection regions 114a and 114b, and waveguide structure 116 are arranged along the y-direction and extend along the x-direction. Furthermore, pad regions 112a and 112b, connection regions 114a and 114b, and waveguide structure 116 may all be formed from the same semiconductor layer of semiconductor photonic device 100, such that pad regions 112a and 112b, connection regions 114a and 114b, and waveguide structure 116 are all physically coupled through the same semiconductor layer. The semiconductor layer (therefore, pad regions 112a and 112b, connection regions 114a and 114b, and waveguide structure 116) may include silicon (Si), silicon doped with one or more dopants (e.g., n-type dopants, p-type dopants), silicon-germanium (SiGe), germanium (Ge), and / or other semiconductor materials.

[0029] like Figure 1A As further shown in the detailed view, the optical modulator segment 110a includes a transition segment 118, wherein the lateral (y-direction) width of the connecting regions 114a and 114b decreases between the main segment of the optical modulator segment 110a and the modulation segment 120 of the optical modulator segment 110a. A heater structure 122 is included in the modulation segment 120. The heater structure 122 is configured to generate heat, which is injected into the waveguide structure 116 through the connecting region 114a to change the temperature of the waveguide structure 116 in the modulation segment 120. Therefore, the heater structure 122 may be referred to as a modulator heater structure. The temperature change of the waveguide structure 116 in the modulation segment 120 alters the refractive index of the waveguide structure 116, allowing the optical signal propagating through the waveguide structure 116 to be modulated via thermo-optic modulation. Therefore, heater structure 122 can be referred to as TPS structure or thermo-optic phase shifter heater.

[0030] like Figure 1A As shown in the detailed view, heater structure 122 includes a semiconductor heater region 124, which includes a doped semiconductor region in the pad region 112a of the optical modulator structure 106. Therefore, heater structure 122 can be referred to as a semiconductor heater structure. The semiconductor heater region 124 of heater structure 122 extends along waveguide structure 116 in modulation section 120 and is thermally coupled to waveguide structure 116 via connection region 114a. Heat generated in semiconductor heater region 124 can propagate to waveguide structure 116 through connection region 114a.

[0031] The semiconductor heater region 124 includes a semiconductor material doped with one or more dopants (e.g., silicon (Si), silicon-germanium (SiGe), germanium (Ge)). For example, among other examples, the semiconductor heater region 124 may include silicon doped with one or more n-type dopants (e.g., phosphorus (P) and / or arsenic (As)). As another example, among other examples, the semiconductor heater region 124 may include silicon doped with one or more p-type dopants (e.g., boron (B) and / or gallium (Ga)).

[0032] like Figure 1A As further shown in the detailed view, the heater structure 122 includes a plurality of contact structures electrically coupled to the semiconductor heater region 124. The plurality of contact structures include a plurality of contact structures 126a and 126b, and a contact structure 128. Contact structures 126a and 126b are located at opposite ends of the semiconductor heater region 124, and contact structure 128 is located between contact structures 126a and 126b. Contact structures 126a, 126b, and 128 are located on the semiconductor heater region 124 and arranged along the semiconductor heater region 124 in the x-direction.

[0033] Contact structures 126a and 126b can be electrically coupled in parallel to an electrical ground in the semiconductor photonic device 100, and contact structure 128 can be electrically coupled to a voltage source in the semiconductor photonic device 100. This allows the phase-shifted voltage input to be distributed in parallel to sections 130a and 130b (e.g., semiconductor heater sections) of the semiconductor heater region 124. For example, a phase-shifted voltage can be applied between contact structures 126a and 128 to apply the phase-shifted voltage to section 130a, and a phase-shifted voltage can be applied between contact structures 126b and 128 to apply the phase-shifted voltage to section 130b. Compared to applying a larger phase-shifted voltage over the entire length of the semiconductor heater region 124, this allows a lower phase-shifted voltage to be used to achieve sufficient power to generate heat in sections 130a and 130b.

[0034] Compared to the overall length of the entire semiconductor heater region 124, the shorter lengths of each segment 130a and 130b result in each segment 130a and 130b having a lower resistance than the entire length of the semiconductor heater region 124. This is because the resistance of each segment 130a and 130b is based in part on the length of each segment 130a and 130b, while the resistance of the entire semiconductor heater region 124 is based in part on its overall length. For the same cross-sectional area, dividing the semiconductor heater region 124 into approximately equal-length segments 130a and 130b results in each segment 130a and 130b having the following resistances:

[0035]

[0036] Where R S The resistance R corresponds to the section (e.g., section 130a, section 130b) of the semiconductor heater region 124. H The resistance corresponds to the overall resistance of the semiconductor heater region 124, and n corresponds to the number of segments. Therefore, for two segments of approximately equal length, the resistance of each segment is approximately 1 / 4 of the resistance of the overall semiconductor heater region 124. Increasing the number of segments exponentially decreases the resistance of each segment.

[0037] For the same power level used to generate heat in semiconductor heater region 124, the reduced resistance of each segment of semiconductor heater region 124 allows the phase shift voltage applied to each segment to be reduced inversely proportional to the number of segments:

[0038]

[0039] Therefore, for two segments of approximately equal length, a segment phase shift voltage V can be applied to each segment to achieve a specific power level. πS Approximately the phase shift voltage V required to achieve the same power level when applied across the entire length of the semiconductor heater region 124. πH Half of it. Therefore, the contact structures 126a, 126b and 128 are arranged along the semiconductor heater region 124, thereby enabling a lower segment phase shift voltage V to be applied to each segment 130a and 130b. πS Instead of applying a large phase shift voltage V over the entire length of the semiconductor heater region 124 πH This allows the semiconductor heater region 124 to generate the same amount of heat more efficiently at lower voltages.

[0040] Although the above example is described with segments 130a and 130b having approximately equal lengths, the semiconductor heater region 124 can be distinguished by contact structures 126a, 126b, and 128, resulting in segments 130a and 130b (and / or additional segments) having different lengths in the x-direction. In some embodiments, the x-direction length of the segments (e.g., segments 130a and 130b) can range from about 5 micrometers to about 25 micrometers. If the x-direction length of a segment of the semiconductor heater region 124 is less than about 5 micrometers, the density of contact structures above the semiconductor heater region 124 may increase to the extent that the parasitic resistance of the contact structures increases power consumption and reduces thermal efficiency. If the x-direction length of a segment of the semiconductor heater region 124 is greater than about 25 micrometers, a segment phase shift voltage V can be applied to each segment to achieve a specific power level. πS This could lead to increased power consumption in heater structure 122, thereby reducing its operating efficiency. If the length of the segment of semiconductor heater region 124 in the x-direction is in the range of approximately 5 micrometers to approximately 25 micrometers, low parasitic resistance can be achieved for the contact structure, and a low power level can be achieved for heater structure 122. However, other values ​​and ranges beyond approximately 5 micrometers to approximately 25 micrometers are also within the scope of this disclosure.

[0041] Figure 1B The semiconductor photonic device 100 is shown along Figure 1A A cross-sectional view of the centerline AA. Therefore, Figure 1B The cross-sectional view shown is of the modulation segment 120 of the optical modulator structure 106 of the semiconductor photonic device 100, spanning in the y-direction. Specifically, Figure 1B The cross-sectional view shown is the portion of the modulation section 120 that includes the contact structure 126a.

[0042] like Figure 1B As shown, the semiconductor heater region 124 of the light modulator structure 106 and the associated heater structure 122 may be formed in and / or included in a semiconductor layer located above the semiconductor substrate 132 of the semiconductor photonic device 100. The semiconductor substrate 132 may include a silicon (Si) material layer, a germanium (Ge) material layer, and / or other semiconductor material layers. The semiconductor substrate 132 may include the same semiconductor material as the semiconductor layer in which the light modulator structure 106 and the semiconductor heater region 124 are formed, or it may include a different semiconductor material.

[0043] like Figure 1BAs further shown, the semiconductor heater region 124 is included in a portion of the pad region 112a of the optical modulator structure 106. The semiconductor heater region 124 (and therefore the pad region 112a) is located laterally adjacent to the waveguide structure 116 of the optical modulator structure 106 and is physically and thermally coupled to the waveguide structure 116 via the connection region 114a. The pad region 112b is physically and thermally coupled to the waveguide structure 116 via the connection region 114b.

[0044] The optical modulator structure 106 and the semiconductor heater region 124 can be encapsulated in a dielectric layer 134. The dielectric layer 134 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y The dielectric layer 134 may contain silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), silicon fluoride glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. The portion of dielectric layer 134 below the optical modulator structure 106 and the semiconductor heater region 124 may correspond to a buried oxide (BOX) layer on the silicon on insulator (SOI) substrate in which the semiconductor photonic device 100 is formed. Another portion of dielectric layer 134 laterally surrounding the optical modulator structure 106 and the semiconductor heater region 124 and located above them may correspond to a shallow trench isolation (STI) portion of dielectric layer 134.

[0045] A silicide layer 136 may be included on the semiconductor heater region 124 of the heater structure 122. The silicide layer 136 may include a metal silicide layer, such as titanium silicide (TiSi), ruthenium silicide (RuSi), cobalt silicide (CoSi), and / or other types of metal silicide materials. Including the silicide layer 136 can achieve a sufficiently low contact resistance between the semiconductor heater region 124 and the contact structures 126a, 126b, and 128 of the heater structure 122.

[0046] Additional dielectric layers are included above the optical modulator structure 106, above the semiconductor heater region 124 of the heater structure, and above the dielectric layer 134. The additional dielectric layers may include an etch stop layer (ESL) 138 above the dielectric layer 134, an interlayer dielectric (ILD) layer 140 above the ESL 138, another ESL 142 above the ILD layer 140, and / or another ILD layer 144 above the ESL 142, etc. In some embodiments, the ILD layers and ESLs may be arranged alternately along the z-direction in the semiconductor photonic device 100.

[0047] ESL 138, ILD layer 140, ESL 142, and ILD layer 144 may each include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y The dielectric materials used include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), silicon fluoride glass (FSG), undoped silicon glass (USG), carbon-doped silicon oxide, and / or other dielectric materials. In some embodiments, ESL 138 and 142 comprise a first dielectric material (or a first dielectric material composition), while ILD layers 140 and 144 comprise a second dielectric material (or a second dielectric material composition) different from the first dielectric material. This allows ESL 138 and 142, as well as ILD layers 140 and 144, to be etched using different types of etchants.

[0048] like Figure 1B As further shown, the contact structure 126a of the heater structure 122 extends along the z-direction through the ESL 138 and the ILD layer 140. The contact structure 126a may rest on the silicide layer 136, such that the contact structure 126a is located on and electrically coupled to the semiconductor heater region 124 of the heater structure 122 through the silicide layer 136. The contact structure 126a may include vias, contact plugs, conductive pillars, and / or other types of conductive structures. The contact structure 126a may include conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au). In some embodiments, one or more layers (e.g., barrier layers, adhesive layers) are included between the contact structure 126a and the surrounding dielectric layer. The one or more layers may include silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner materials.

[0049] like Figure 1BAs further shown, the contact structure 126a is electrically and / or physically coupled to the metallization layer 146 above it. The metallization layer 146 may be included in the ESL 142 and ILD layer 144 above the contact structure 126a. The metallization layer 146 may correspond to the electrode of the heater structure 122 (e.g., a ground electrode), and the metallization layer 146 may electrically couple the contact structure 126a to an electrical ground.

[0050] The metallization layer 146 may include one or more conductive structures, including one or more vias, one or more trenches, one or more contact plugs, one or more conductive traces, and / or other types of conductive structures. The metallization layer 146 may include one or more conductive metals, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au). In some embodiments, the metallization layer 146 includes one or more substrates (e.g., barrier substrates, adhesion substrates) between itself and the surrounding dielectric layer. One or more substrates may include silicon oxide (SiO₂). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner materials.

[0051] Figure 1C The semiconductor photonic device 100 is shown along Figure 1A Another sectional view of the center line BB. Therefore, Figure 1C The cross-sectional view shown is the modulation section 120 of the optical modulator structure 106 of the semiconductor photonic device 100, spanning in the y-direction. Specifically, Figure 1C The sectional view shown spans the portion of the modulation section 120 that includes the contact structure 128.

[0052] like Figure 1CAs shown, the contact structure 128 of the heater structure 122 extends through the ESL 138 and the ILD layer 140 in the z-direction. The contact structure 128 may rest on the silicide layer 136, such that the contact structure 128 is located on and electrically coupled to the semiconductor heater region 124 of the heater structure 122 through the silicide layer 136. The contact structure 128 may include vias, contact plugs, conductive pillars, and / or other types of conductive structures. The contact structure 128 may include conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au). In some embodiments, contact structures 126a and 128 comprise the same material (or the same material composition). In some embodiments, contact structures 126a and 128 comprise different materials (or different material compositions). In some embodiments, one or more layers (e.g., barrier layers, adhesive layers) are included between the contact structure 128 and the surrounding dielectric layer. The one or more layers may include silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner materials.

[0053] like Figure 1C As further shown, the contact structure 128 is electrically and / or physically coupled to the metallization layer 148 above it. The metallization layer 148 may be included in the ESL 142 and ILD layer 144 above the contact structure 128. The metallization layer 148 may correspond to the electrode (e.g., Vπ electrode) of the heater structure 122, and the metallization layer 148 may electrically couple the contact structure 128 to a voltage source (e.g., a phase-shift voltage source) of the semiconductor photonic device 100.

[0054] The metallization layer 148 may include one or more conductive structures, including one or more vias, one or more trenches, one or more contact plugs, one or more conductive traces, and / or other types of conductive structures. The metallization layer 148 may include one or more conductive metals, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au). In some embodiments, the metallization layer 148 includes one or more substrates (e.g., barrier substrates, adhesion substrates) between itself and the surrounding dielectric layer. One or more substrates may include silicon oxide (SiO₂). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner materials.

[0055] Figure 1D The semiconductor photonic device 100 is shown along Figure 1A Another sectional view of the center line CC. Therefore, Figure 1D The cross-sectional view shown is the semiconductor heater region 124 of the heater structure 122 in the modulation section 120 of the light modulator structure 106 along the x-direction.

[0056] like Figure 1D As shown, contact structures 126a, 126b, and 128 of heater structure 122 are located on semiconductor heater region 124 and arranged along semiconductor heater region 124 in the x-direction. Contact structure 126a is located at the first end of semiconductor heater region 124 of heater structure 122, contact structure 126b is located at the second end of semiconductor heater region 124 of heater structure 122 opposite to the first end, and contact structure 128 is located between contact structures 126a and 126b in the x-direction. Segment 130a of semiconductor heater region 124 is located between contact structures 126a and 128, and segment 130b of semiconductor heater region 124 is located between contact structures 126b and 128. Metallization layer 146 is located above and electrically coupled to contact structures 126a and 126b, and metallization layer 148 is located above and electrically coupled to contact structure 128.

[0057] Contact structure 126b may rest on silicide layer 136, such that contact structure 126b is located on and electrically coupled to semiconductor heater region 124 of heater structure 122 through silicide layer 136. Contact structure 126b may include vias, contact plugs, conductive pillars, and / or other types of conductive structures. Contact structure 126b may include conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au). In some embodiments, contact structure 126a and contact structure 126b comprise the same material (or the same material composition). In some embodiments, contact structure 126a and contact structure 126b comprise different materials (or different material compositions). In some embodiments, contact structure 126b includes one or more layers (e.g., barrier layers, adhesive layers) between contact structure 126b and the surrounding dielectric layer. One or more layers may include silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner materials.

[0058] Figure 1E A top view is shown of a portion of the light modulator structure 106, including the heater structure 122. Figure 1E Additional details of metallization layers 146 and 148 are shown. (See attached image.) Figure 1EAs shown, the metallization layer 146 is electrically coupled and / or physically coupled to the contact structures 126a and 126b, such that the contact structures 126a and 126b are electrically coupled in parallel, and that the contact structures 126a and 126b are electrically coupled in parallel to the ground 150.

[0059] The metallization layer 148 is electrically and / or physically coupled to the contact structure 128, thereby electrically coupling the contact structure 128 to the voltage source 152. The parallel connection of the contact structures 126a and 126b to the electrical ground 150, and the connection of the contact structure 128 to the voltage source 152, allow a phase-shift voltage to be applied in parallel to the section 130a from the contact structure 126a to the contact structure 128, and allow a phase-shift voltage to be applied to the section 130b from the contact structure 126b to the contact structure 128.

[0060] As mentioned above, providing Figures 1A to 1E As an example. Other examples can be found in relation to... Figures 1A to 1E The descriptions are different.

[0061] Figure 2A and Figure 2B This is a figure of an example embodiment 200 in which the waveguide structure 116 of the optical modulator structure 106 described herein is heated. Figure 2A and Figure 2B As shown, the heater structure 122 associated with the optical modulator structure 106 can be operated by applying a phase-shift voltage to the semiconductor heater region 124. Specifically, referring to... Figure 2A A phase-shift voltage can be applied to section 130a by applying a phase-shift voltage between contact structure 126a and contact structure 128, and a phase-shift voltage can be applied to section 130b by applying a phase-shift voltage between contact structure 126b and contact structure 128.

[0062] The phase-shift voltage between contact structures 126a and 128 causes current to flow through section 130a of the semiconductor heater region 124, resulting in Joule heating in the semiconductor heater region 124. Specifically, the resistance of the material in section 130a consumes part of the current, causing the electrical energy of the current to be converted into heat energy. Similarly, the phase-shift voltage between contact structures 126b and 128 causes current to flow through section 130b of the semiconductor heater region 124, resulting in Joule heating in the semiconductor heater region 124. In this way, a heating region 202 is generated in the semiconductor heater region 124.

[0063] like Figure 2BAs shown, the heating zone 202 extends through the connection zone 114a and into the waveguide structure 116 of the optical modulator structure 106. In this way, the heat generated by the heater structure 122 in the heating zone 202 is provided to the waveguide structure 116 through the connection zone 114a, which enables the waveguide structure 116 to be heated.

[0064] As mentioned above, providing Figure 2A and Figure 2B As an example. Other examples can be found in relation to... Figure 2A and Figure 2B The descriptions are different.

[0065] Figures 3A to 3O This is a diagram of an exemplary embodiment 300 of forming a semiconductor photonic device 100 (or a portion thereof) as described herein. In particular, exemplary embodiment 300 may include an example of an optical modulator structure 106 and associated heater structure 122 for forming the semiconductor photonic device 100. In some embodiments, another semiconductor photonic device as described herein may be formed by combining one or more semiconductor processing operations described in conjunction with exemplary embodiment 300, for example, combining... Figures 4A to 4C The semiconductor photonic device 400 described and illustrated, combined with Figure 5A and Figure 5B The semiconductor photonic device 500 described and illustrated, combined with Figure 6A and Figure 6B The semiconductor photonic device 600 and / or other semiconductor photonic devices described and illustrated. In some embodiments, one or more semiconductor processing operations described in conjunction with Example Embodiment 300 may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, and / or wafer / die transfer tools, etc.

[0066] like Figure 3A As shown, a substrate 302 may be provided. The substrate 302 may include an SOI substrate, which includes a semiconductor substrate 132 (e.g., a silicon (Si) substrate and / or other types of semiconductor substrates), a dielectric layer 134 (e.g., a BOX layer and / or other types of insulating layer) on and / or on the semiconductor substrate 132, and a semiconductor layer 304 (e.g., a silicon (Si) layer and / or other types of semiconductor layer) on and / or on the dielectric layer 134.

[0067] Alternatively, a semiconductor substrate 132 can be provided as a semiconductor wafer, and a dielectric layer 134 can be formed on and / or on the semiconductor substrate 132 using deposition tools. A semiconductor layer 304 can also be formed or provided on and / or on the dielectric layer 134. The dielectric layer 134 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), oxidation techniques (e.g., thermal oxidation), and / or other types of deposition techniques. The semiconductor layer 304 can be formed using epitaxial techniques and / or other types of deposition techniques. Alternatively, a bonding tool can be used to bond the semiconductor layer 304 to the dielectric layer 134. For example, the semiconductor layer 304 can be provided as another semiconductor wafer, and a bonding dielectric layer can be formed on the semiconductor wafer using deposition tools. A bonding tool can then be used to bond the bonding dielectric layer to the dielectric layer 134 to bond the semiconductor layer 304 to the dielectric layer 134.

[0068] like Figure 3B As shown, a portion of semiconductor layer 304 is removed to form a semiconductor heater region 124 for the optical modulator structure 106 and the heater structure 122 within semiconductor layer 304. Specifically, the optical modulator structure 106 and the semiconductor heater region 124 are formed within semiconductor layer 304 such that the optical modulator structure 106 and the semiconductor heater region 124 are physically connected within semiconductor layer 304. The waveguide structure 116 of the optical modulator structure 106 and the semiconductor heater region 124 of the heater structure 122 are coupled through a connection region 114a of the optical modulator structure 106.

[0069] In some embodiments, a pattern in a hard mask layer is used to etch the semiconductor layer 304 to form the light modulator structure 106 and the semiconductor heater region 124. A hard mask layer can be formed on the semiconductor layer 304 using deposition tools (e.g., using CVD, PVD, atomic layer deposition (ALD), oxidation, and / or other types of deposition techniques), and a photoresist layer can be formed on the hard mask layer (e.g., using spin coating and / or other types of deposition techniques). An exposure tool can be used to expose the photoresist layer to a radiation source to form a pattern in the photoresist layer. A developing tool can develop and remove portions of the photoresist layer to expose the pattern.

[0070] An etching tool can be used to etch the hard mask layer to transfer a pattern from the photoresist layer to the hard mask layer. The etching tool can be used to etch the semiconductor layer 304 based on the pattern in the hard mask layer, forming the light modulator structure 106 and the semiconductor heater region 124 by removing portions of the semiconductor layer 304 according to the pattern. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal tool is used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a planarization tool is used to remove the remaining portions of the hard mask layer using chemical mechanical planarization (CMP) and / or other types of planarization techniques.

[0071] like Figure 3C As shown, additional material can be deposited around the optical modulator structure 106 and the semiconductor heater region 124 to form the dielectric layer 134. This additional material may correspond to the STI portion of the dielectric layer 134. The additional material of the dielectric layer 134 can be deposited using deposition tools via CVD, PVD, oxidation techniques (e.g., thermal oxidation) and / or other types of deposition techniques. In some embodiments, an STI liner is first deposited onto the dielectric layer 134, and then the additional material of the dielectric layer 134 is deposited on the STI liner.

[0072] A planarization tool can be used to perform CMP operations and / or other types of planarization operations to planarize the dielectric layer 134. This makes the top surface of the dielectric layer 134 approximately coplanar with the top surfaces of the optical modulator structure 106 and the semiconductor heater region 124.

[0073] like Figure 3D As shown, a portion of the pad region 112a in the modulation segment 120 of the optical modulator structure 106 can be doped using one or more types of dopants to dope the semiconductor heater region 124 of the heater structure 122. A portion of the pad region 112a can be doped using an ion implantation tool by implanting ions into the semiconductor material of the pad region 112a. Dopants may include n-type dopants, p-type dopants, and / or other dopant types. Other portions of the optical modulator structure 106 may remain undoped, or portions other than the semiconductor heater region 124 may be doped. In some embodiments, the pad region 112a may be selectively doped using an implantation mask. Alternatively, the semiconductor layer 304 may be doped (e.g., using an implantation mask) before etching the semiconductor layer 304 to form the pad region 112a.

[0074] like Figure 3EAs shown, additional material can be deposited over the optical modulator structure 106 and the semiconductor heater region 124 to form the dielectric layer 134. The additional material for the dielectric layer 134 can be deposited using deposition tools via CVD techniques (e.g., remote plasma oxide (RPO) CVD) and / or other types of deposition techniques.

[0075] An opening may be formed in the dielectric layer 134 above the semiconductor heater region 124, and a silicide layer 136 may be formed on the semiconductor heater region 124. Forming the silicide layer 136 may include depositing (e.g., using a deposition tool) a metal layer on the semiconductor heater region 124, and performing an annealing operation on the metal layer using an annealing tool. The annealing operation causes the metal layer to react with the semiconductor material of the semiconductor heater region 124, thereby forming the silicide layer 136.

[0076] like Figure 3F As shown, an ESL 138 can be formed over the optical modulator structure 106, the semiconductor heater region 124, and the dielectric layer 134. An ILD layer 140 can be formed over the ESL 138. The ESL 138 and / or ILD layer 140 can be deposited using deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, a planarization operation (e.g., CMP operation) can be performed using a planarization tool after depositing the ESL 138 and / or ILD layer 140 to planarize the ESL 138 and / or ILD layer 140.

[0077] like Figures 3G to 3I As shown, multiple recesses are formed on the silicide layer 136 above the semiconductor heater region 124 via ESL 138 and ILD layer 140. The multiple recesses may include recesses 306, 308, and 310, etc. Alternatively, recesses 306, 308, and / or 310 may be formed before the formation of the silicide layer 136, and the silicide layer 136 may be formed on the heating region 124 via recesses 306, 308, and / or 310. Recess 306 may be formed at a first end of the semiconductor heater region 124. Recess 310 may be formed at a second end of the semiconductor heater region 124, the second end being opposite to the first end in the x-direction. Recess 308 may be formed between recesses 306 and 310 in the x-direction.

[0078] In some embodiments, the ESL 138 and / or ILD layer 140 are etched using a pattern in the photoresist layer to form recesses 306-310. In these embodiments, a deposition tool can be used to form the photoresist layer on the ILD layer 140. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the ESL 138 and / or ILD layer 140 based on the pattern to form recesses 306-310. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative to pattern-based etching of ESL 138 and / or ILD layer 140.

[0079] like Figures 3J to 3L As shown, contact structures 126a, 126b, and 128 are formed such that each contact structure 126a, 126b, and 128 falls on the semiconductor heater region 124. Specifically, contact structures 126a, 126b, and 128 may fall on the silicide layer 136 on the semiconductor heater region 124. Contact structure 126a may be formed in recess 306 such that contact structure 126a is located on a first side of the semiconductor heater region 124. Contact structure 126b may be formed in recess 310 such that contact structure 126b is located on a second side of the semiconductor heater region 124. Contact structure 128 may be formed in recess 308 such that contact structure 128 is formed in the x-direction between contact structures 126a and 126b.

[0080] In some embodiments, contact structures 126a, 126b, and 128 are formed in the same deposition operation or in the same sequence of operations. In some embodiments, two or more of contact structures 126a, 126b, and 128 are formed in different deposition operations. Contact structures 126a, 126b, and / or 128 can be deposited using deposition tools employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. Contact structures 126a, 126b, and / or 128 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and contact structures 126a, 126b, and / or 128 are deposited on the seed layer. In some embodiments, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize contact structures 126a, 126b, and / or 128 after deposition.

[0081] like Figures 3M to 3O As shown, ESL 142 and ILD layer 144 are formed over ILD layer 140. ESL 142 may be formed over ILD layer 144, and ILD layer 144 may be formed over ESL 142. ESL 142 and / or ILD layer 144 can be deposited using deposition tools employing PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, planarization operations (e.g., CMP operations) can be performed using planarization tools to planarize ESL 142 and / or ILD layer 144 after deposition.

[0082] like Figures 3M to 3O As further shown, metallization layers 146 and 148 are formed in ESL 142 and / or ILD layer 144. Metallization layer 146 may be formed such that metallization layer 146 falls on contact structures 126a and 126b. Metallization layer 148 may be formed such that metallization layer 148 falls on contact structure 128.

[0083] To form metallization layers 146 and 148, recesses may be formed in ESL 142 and ILD layers 144. In some embodiments, a pattern in a photoresist layer is used to etch ESL 142 and / or ILD layers 144 to form the recesses. Recesses may be formed over contact structures 126a and 126b, exposing contact structures 126a and 126b through the recesses. Another recess may be formed over contact structure 128, exposing contact structure 128 through the recess.

[0084] In these embodiments, a photoresist layer can be formed on the ILD layer 144 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the ESL 142 and / or the ILD layer 144 based on the pattern to form a recess. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative to pattern-based etching of the ESL 142 and / or the ILD layer 144.

[0085] Metallization layers 146 and / or 148 can be deposited using deposition tools employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. Metallization layers 146 and / or 148 may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then metallization layers 146 and / or 148 are deposited on the seed layer. In some embodiments, a planarization operation (e.g., CMP operation) is performed using planarization tools to planarize metallization layers 146 and / or 148 after deposition.

[0086] As mentioned above, providing Figures 3A to 3O As an example. Other examples can be found in relation to... Figures 3A to 3O The descriptions are different.

[0087] Figures 4A to 4C This is a diagram of the example semiconductor photonic device 400 described herein. The semiconductor photonic device 400 can be used in conjunction with... Figures 3A to 3O It is formed using similar technologies and processes.

[0088] Figure 4A A top view of a semiconductor photonic device 400 is shown. Figure 4A As shown, the semiconductor photonic device 400 includes a combination of Figures 1A to 1EThe photonic integrated circuit 102 shown and described in the semiconductor photonic device 100 is similar to the photonic integrated circuit 102. For example, the photonic integrated circuit 102 in the semiconductor photonic device 400 includes a waveguide structure 104 optically and / or physically coupled to an optical modulator structure 106, and another waveguide structure 108, wherein the waveguide structure 104 and the waveguide structure 108 are coupled to the optical modulator structure 106 at opposite ends of the optical modulator structure 106. Furthermore, the optical modulator structure 106 in the photonic integrated circuit 102 of the semiconductor photonic device 400 includes a heater structure 122, which includes a semiconductor heater region 124 divided into multiple segments (e.g., multiple semiconductor heater segments) by multiple contacts, similar to the heater structure 122 in the photonic integrated circuit 102 of the semiconductor photonic device 100.

[0089] However, as Figure 4A As shown, the heater structure 122 in the photonic integrated circuit 102 of the semiconductor photonic device 400 includes multiple contact structures 128a and 128b to further distinguish the semiconductor heater region 124 into additional segments 130c. Therefore, the semiconductor heater region 124 in the semiconductor photonic device 400 includes segments 130a-130c, wherein segment 130a is located between (and defined by) contact structures 126a and 128a, segment 130b is located between (and defined by) contact structures 126b and 128a, and segment 130c is located between (and defined by) contact structures 126b and 128b. This allows for a further reduction in the phase-shift voltage required to achieve a specific power level for the heater structure 122, as the phase-shift voltage is applied in parallel to a greater number of segments of the semiconductor heater region 124.

[0090] like Figure 4A As shown, contact structure 126a is located at the first end of semiconductor heater region 124, and contact structure 128b is located at the second end of semiconductor heater region 124 opposite to the first end. Contact structure 126b is located between contact structure 126a and contact structure 128b, more specifically between contact structure 128a and contact structure 128b. Contact structure 128a is located between contact structure 126a and contact structure 128b, more specifically between contact structure 126a and contact structure 126b.

[0091] Figure 4B Show along Figure 4A A sectional view of the center line CC. (e.g.) Figure 4BAs shown, contact structures 126a, 126b, 128a, and 128b may be located on the semiconductor heater region 124 and may be arranged along the semiconductor heater region 124 in the x-direction. Contact structures 126a and 126b may be electrically coupled and / or physically coupled to the metallization layer 146, and contact structures 128a and 128b may be electrically coupled and / or physically coupled to the metallization layer 148.

[0092] Figure 4C A top view of a portion of the light modulator structure 106, including the heater structure 122, is shown. Figure 4C Additional details are provided regarding the metallization layers 146 and 148 in the semiconductor photonic device 400. (For example...) Figure 4C As shown, the metallization layer 146 is electrically coupled and / or physically coupled to the contact structures 126a and 126b, such that the contact structures 126a and 126b are electrically coupled in parallel, and that the contact structures 126a and 126b are electrically coupled in parallel to the electrical ground 150.

[0093] The metallization layer 148 is electrically and / or physically coupled to contact structures 128a and 128b, such that contact structures 128a and 128b are electrically coupled in parallel, and that contact structures 128a and 128b are electrically coupled in parallel to voltage source 152. The parallel connection of contact structures 126a and 126b to ground 150 and the parallel connection of contact structures 128a and 128b to voltage source 152 allow a phase-shift voltage to be applied in parallel to section 130a between contact structures 126a and 128a, to section 130b between contact structures 126b and 128a, and to section 130c between contact structures 126b and 128b.

[0094] As mentioned above, providing Figures 4A to 4C As an example. Other examples can be found in relation to... Figures 4A to 4C The differences described herein are not identical. For example, additional contact structures may be included on the semiconductor heater region 124 to further divide the semiconductor heater region 124 into additional segments. The number of segments other than those described herein is also included within the scope of this disclosure.

[0095] Figure 5A and Figure 5B This is a diagram of the example semiconductor photonic device 500 described in this article. Figure 5A A top view of the semiconductor photonic device 500 is shown.

[0096] The photonic integrated circuit 502 may include a bus optical waveguide structure 504 and an optical modulator structure 506. The bus optical waveguide structure 504 has an input terminal 508a and an output terminal 508b. The optical modulator structure 506 and the bus optical waveguide structure 504 may be adjacent and / or side-by-side in the y-direction within the semiconductor photonic device 500, so that optical signals can be coupled between the optical modulator structure 506 and the bus optical waveguide structure 504 in the coupling region 510. The unmodulated input optical signal may be received by the bus optical waveguide structure 504 at the input terminal 508a, while the modulated output optical signal in the optical modulator structure 506 may be provided from the output terminal 508b of the bus optical waveguide structure 504.

[0097] A bus optical waveguide structure 504 may extend along the x-direction to one side of the optical modulator structure 506. The bus optical waveguide structure 504 confines the optical signal, which reduces optical loss and improves the propagation efficiency of the optical signal. The bus optical waveguide structure 504 may include an extended waveguide, including a planar waveguide, a ribbed waveguide, and / or other types of waveguide structures. An input optical signal may enter the bus optical waveguide structure 504 at a first end, while an output optical signal (e.g., a modulated optical signal) may be provided by the bus optical waveguide structure 504 at a second (opposite) end. The optical signal may be coupled between the bus optical waveguide structure 504 and the optical modulator structure 506 in a laterally adjacent coupling region.

[0098] Optical modulator structure 506 includes a micro-ring modulator (MRM) or another dead-loop modulator structure, comprising a pad region 512, multiple connection regions 514a and 514b, and a dead-loop optical waveguide structure 516. The dead-loop optical waveguide structure 516 is a continuous waveguide structure that is self-connected and has no endpoints. The structure of optical modulator structure 506 differs from that of optical modulator structure 106 in that optical modulator structure 106 (e.g., MZM) has endpoints coupled to waveguide structures 104 and 108. Optical signals are not coupled into and out of optical modulator structure 106 through propagation via waveguide structures 104 and 108, but rather through evanescent coupling in coupling region 510 between the bus optical waveguide structure 504 and the dead-loop optical waveguide structure 516 of optical modulator structure 506. When the evanescent field of the optical signal propagating in the bus optical waveguide structure 504 extends into the portion of the dead-loop optical waveguide structure 516 in the coupling region 510 adjacent to the bus optical waveguide structure 504, evanescent coupling occurs from the bus optical waveguide structure 504 to the dead-loop optical waveguide structure 516. Similarly, when the evanescent field of the optical signal propagating in the dead-loop optical waveguide structure 516 extends into the portion of the bus optical waveguide structure 504 in the coupling region 510, evanescent coupling occurs from the dead-loop optical waveguide structure 516 to the bus optical waveguide structure 504.

[0099] The bus optical waveguide structure 504, pad region 512, connection regions 514a and 514b, and dead-loop optical waveguide structure 516 may be formed in a semiconductor layer and may include silicon (Si), silicon doped with one or more types of dopants, germanium (Ge), silicon-germanium (SiGe), and / or other semiconductor materials.

[0100] like Figure 5A As further shown, the optical modulator structure 506 includes a resonant section 518 and a modulation section 520. The resonant section 518 comprises the main length of the optical modulator structure 506 around the dead-loop top view shape. The modulation section 520 may be included in the coupling region 510 and may include a heater structure 522 configured for modulating an optical signal, which then propagates around the optical modulator structure 506 in the resonant section 518. The heater structure 522 may be included in a pad section laterally adjacent to the bus optical waveguide structure 504 and may be configured to generate heat that will be injected through the bus optical waveguide structure 504 and the connection region 514a into the dead-loop optical waveguide structure 516 to change the temperature of the dead-loop optical waveguide structure 516 in the modulation section 520. Therefore, the heater structure 522 may be referred to as a modulator heater structure. The temperature change of the dead-loop optical waveguide structure 516 in the modulation section 520 alters the refractive index of the dead-loop optical waveguide structure 516, allowing the optical signal propagating through the dead-loop optical waveguide structure 516 to be modulated via thermo-optic modulation. Therefore, the heater structure 522 can be referred to as a TPS structure or a thermo-optic phase shifter heater.

[0101] The heater structure 522 includes a semiconductor heater region 524, which comprises a doped semiconductor region in a pad section laterally adjacent to the bus optical waveguide structure 504 in the y-direction. Therefore, the heater structure 522 may be referred to as a semiconductor heater structure. The semiconductor heater region 524 of the heater structure 522 extends along the bus optical waveguide structure 504 in the modulation section 520 and is thermally coupled to the dead-loop optical waveguide structure 516 via the bus optical waveguide structure 504 and connection regions 514a and 514c. Heat generated in the semiconductor heater region 524 can propagate through the bus optical waveguide structure 504 and through connection regions 514a and 514c to the dead-loop optical waveguide structure 516.

[0102] Semiconductor heater region 524 includes a semiconductor material doped with one or more types of dopants (e.g., silicon (Si), silicon-germanium (SiGe), germanium (Ge)). For example, among other examples, semiconductor heater region 524 may include silicon doped with one or more n-type dopants (e.g., phosphorus (P) and / or arsenic (As)). As another example, semiconductor heater region 124 may include silicon doped with one or more p-type dopants (e.g., boron (B) and / or gallium (Ga)), and so on.

[0103] The heater structure 522 includes a plurality of contact structures electrically coupled to the semiconductor heater region 524. The plurality of contact structures include a plurality of contact structures 526a and 526b, and a contact structure 528. Contact structures 526a and 526b are located at opposite ends of the semiconductor heater region 524, and contact structure 528 is located between contact structures 526a and 526b. Contact structures 526a, 526b, and 528 are located on the semiconductor heater region 524 and are arranged along the semiconductor heater region 524 in the x-direction.

[0104] Contact structures 526a and 526b can be electrically coupled in parallel to an electrical ground in the semiconductor photonic device 500, and contact structure 528 can be electrically coupled to a voltage source in the semiconductor photonic device 500. This allows a phase-shifted voltage input to be distributed in parallel to sections 530a and 530b (e.g., semiconductor heater sections) of the semiconductor heater region 524. For example, a phase-shifted voltage can be applied between contact structures 526a and 528 to apply the phase-shifted voltage to section 530a, and a phase-shifted voltage can be applied between contact structures 526b and 528 to apply the phase-shifted voltage to section 530b. Compared to applying a larger phase-shifted voltage over the entire length of the semiconductor heater region 524, this allows a lower phase-shifted voltage to be used to achieve sufficient power to generate heat in sections 530a and 530b.

[0105] Figure 5B A top view of the coupling region 510, including the bus optical waveguide structure 504, the optical modulator structure 506, and the heater structure 522, is shown. Figure 5B As shown, similar to metallization layers 146 and 148, metallization layers 532 and 534 are included in the semiconductor photonic device 500. Metallization layer 532 is electrically coupled and / or physically coupled to contact structures 526a and 526b, such that contact structures 526a and 526b are electrically coupled in parallel, and that contact structures 526a and 526b are electrically coupled in parallel to electrical ground 536.

[0106] The metallization layer 534 is electrically and / or physically coupled to the contact structure 528, such that the contact structure 528 is electrically coupled to the voltage source 538. The parallel connection of the contact structures 526a and 526b to the electrical ground 536, and the connection of the contact structure 528 to the voltage source 538, allows a phase-shift voltage to be applied in parallel to the segment 530a between the contact structures 526a and 528, and also allows a phase-shift voltage to be applied in parallel to the segment 530b between the contact structures 526b and 528.

[0107] Semiconductor photonic device 500 can be used and combined Figures 3A to 3O Similar technologies and processes are used to form the device. For example, a semiconductor photonic device 500 can be formed on a substrate 302 (e.g., an SOI substrate), which includes a semiconductor substrate 132, a dielectric layer (e.g., a BOX layer) 134, and a semiconductor layer 304. A bus optical waveguide structure 504, an optical modulator structure 506, and a semiconductor heater region 524 can be used in conjunction with these technologies. Figure 3B A similar method is used to form the semiconductor layer 304. Additional material for the dielectric layer 134 can be used in conjunction with bonding... Figure 3C A similar arrangement is formed around the bus optical waveguide structure 504, the optical modulator structure 506, and the semiconductor heater region 524, and the semiconductor heater region 524 can be used in conjunction with... Figure 3D Doping is performed in a similar manner. The silicide layer 136 can be used with bonding... Figure 3E A similar manner is formed on the semiconductor heater region 524. ESL 138 and ILD layer 140 can be used in conjunction with... Figure 3F Formed in a similar manner. Contact structures 526a, 526b, and 528 can be used in conjunction with... Figures 3G to 3L A similar manner is formed on the semiconductor heater region 524 of the heater structure 522. Metallization layers 532 and 534 can be used with bonding... Figures 3M to 3O It is formed in a similar manner.

[0108] As described above, it provides Figure 5A and Figure 5B As an example. Other examples can be found in relation to... Figure 5A and Figure 5B The descriptions are different.

[0109] Figure 6A and 6B This is a diagram of the example semiconductor photonic device 600 described herein. The semiconductor photonic device 600 can be used in conjunction with... Figures 3A to 3O Similar technologies and processes have been developed.

[0110] Figure 6A A top view of a semiconductor photonic device 600 is shown. Figure 6AAs shown, the semiconductor photonic device 600 includes a combination of Figure 5A and Figure 5B The photonic integrated circuit 502 described and illustrated in the semiconductor photonic device 500 is similar to the photonic integrated circuit 502 described in the semiconductor photonic device 600. For example, the photonic integrated circuit 502 in the semiconductor photonic device 600 includes a bus optical waveguide structure 504 optically and / or physically coupled to an optical modulator structure 506, wherein the optical modulator structure 506 and the bus optical waveguide structure 504 are laterally adjacent to each other so that an optical signal can be coupled between the optical modulator structure 506 and the bus optical waveguide structure 504 in a coupling region 510. Furthermore, a heater structure 522 is configured to modulate the optical signal subsequently propagating around the optical modulator structure 506. The heater structure 522 is configured to generate heat, which is injected through the bus optical waveguide structure 504 and the connection region 514a into the dead-loop optical waveguide structure 516 of the optical modulator structure 506 to change the temperature of the dead-loop optical waveguide structure 516 in the modulation section 520.

[0111] However, as Figure 6A As shown, the heater structure 522 in the photonic integrated circuit 502 of the semiconductor photonic device 600 includes multiple contact structures 528a and 528b to further divide the semiconductor heater region 524 into additional segments 530c. Therefore, the semiconductor heater region 524 in the semiconductor photonic device 600 includes segments 530a-530c, wherein segment 530a is located between (and defined by) contact structures 526a and 528a, segment 530b is located between (and defined by) contact structures 526b and 528a, and segment 530c is located between (and defined by) contact structures 526b and 528b. This allows the phase-shift voltage used to achieve a specific power level in the heater structure 522 to be further reduced, as the phase-shift voltage is applied in parallel across a greater number of segments of the semiconductor heater region 524.

[0112] like Figure 6A As shown, contact structure 526a is located at the first end of semiconductor heater region 524, and contact structure 528b is located at the second end of semiconductor heater region 524 opposite to the first end. Contact structure 526b is located between contact structure 526a and contact structure 528b, more specifically between contact structure 528a and contact structure 528b. Contact structure 528a is located between contact structure 526a and contact structure 528b, more specifically between contact structure 526a and contact structure 526b.

[0113] Figure 6BAnother top view of the coupling region 510 of the photonic integrated circuit 502 is shown, including a portion of the bus optical waveguide structure 504, a portion of the optical modulator structure 506, and the heater structure 522. Figure 6B Additional details are provided regarding the metallization layers 532 and 534 in the semiconductor photonic device 600. For example... Figure 6B As shown, the metallization layer 532 is electrically coupled and / or physically coupled to the contact structures 526a and 526b, such that the contact structures 526a and 526b are electrically coupled in parallel, and that the contact structures 526a and 526b are electrically coupled in parallel to the electrical ground 536.

[0114] The metallization layer 534 is electrically and / or physically coupled to contact structures 528a and 528b, such that contact structures 528a and 528b are electrically coupled in parallel, and that contact structures 528a and 528b are electrically coupled in parallel to voltage source 538. The parallel connection of contact structures 526a and 526b to ground 536 and the parallel connection of contact structures 528a and 528b to voltage source 538 allows a phase-shift voltage to be applied in parallel to segment 530a between contact structures 526a and 528a, a phase-shift voltage to be applied in parallel to segment 530b between contact structures 526b and 528a, and a phase-shift voltage to be applied in parallel to segment 530c between contact structures 526b and 528b.

[0115] As mentioned above, providing Figure 6A and Figure 6B As an example. Other examples can be found in relation to... Figure 6A and Figure 6B The differences described herein are not identical. For example, additional contact structures may be included on the semiconductor heater region 524 to further divide the semiconductor heater region 524 into additional segments. The number of segments other than those described herein is also included within the scope of this disclosure.

[0116] Figure 7 This is a flowchart of an example process 700 related to the formation of a semiconductor photonic device as described herein. In some embodiments, one or more semiconductor processing tools are used for execution. Figure 7 One or more process blocks, semiconductor processing tools such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or other types of semiconductor processing tools.

[0117] like Figure 7As shown, process 700 may include forming an optical modulator structure and a modulator heater structure laterally adjacent to the optical modulator structure in a semiconductor layer above a first dielectric layer of the semiconductor photonic device (block 710). For example, one or more semiconductor processing tools may be used to form an optical modulator structure (e.g., optical modulator structure 106, optical modulator structure 506) and a modulator heater structure (e.g., heater structure 122, heater structure 522) laterally adjacent to the optical modulator structure in a semiconductor layer (e.g., semiconductor layer 304) above a first dielectric layer (e.g., dielectric layer 134) of the semiconductor photonic device (e.g., semiconductor photonic device 100, semiconductor photonic device 400, semiconductor photonic device 500, semiconductor photonic device 600), as described herein. In some embodiments, the optical modulator structure and the modulator heater structure are physically coupled in the semiconductor layer and arranged in the semiconductor photonic device along a first direction (e.g., the y-direction).

[0118] like Figure 7 As further illustrated, process 700 may include forming a second dielectric layer over the first dielectric layer, over the optical modulator structure, and over the modulator heater structure (box 720). For example, the second dielectric layer (e.g., ESL 138, ILD layer 140) may be formed over the first dielectric layer, over the optical modulator structure, and over the modulator heater structure using one or more semiconductor processing tools, as described herein.

[0119] like Figure 7 As further shown, process 700 may include forming a plurality of recesses in a second dielectric layer above the modulator heater structure (box 730). For example, one or more semiconductor processing tools may be used to form a plurality of recesses (e.g., recess 306, recess 308, recess 310) in the second dielectric layer above the modulator heater structure, as described herein.

[0120] like Figure 7As further illustrated, process 700 may include forming a first contact structure at a first end of the modulator heater structure, a second contact structure at a second end of the modulator heater structure opposite to the first end, and a third contact structure laterally located between the first and second contact structures in a second direction substantially perpendicular to the first direction (block 740). For example, one or more semiconductor processing tools may be used to form the first contact structure (e.g., contact structures 126a and / or 526a) at the first end of the modulator heater structure, the second contact structure (e.g., contact structures 126b, 128b, 526b and / or 528b) at the second end of the modulator heater structure opposite to the first end, and the third contact structure (e.g., contact structures 128, 128a, 526b, 528 and / or 528a) laterally located between the first and second contact structures in a second direction substantially perpendicular to the first direction (e.g., the x-direction), as described herein.

[0121] Process 700 may include additional implementations, such as any single implementation or any combination of implementations described below and / or combined with one or more other processes described elsewhere herein.

[0122] In a first embodiment, process 700 includes forming a third dielectric layer (e.g., ESL 142, ILD layer 144) over the second dielectric layer, over the first contact structure, over the second contact structure, and over the third contact structure; forming a first metallization layer (e.g., metallization layer 146, metallization layer 532) coupled to the first contact structure and the second contact structure in the third dielectric layer, wherein the first metallization layer couples the first contact structure and the second contact structure together; and forming a second metallization layer (e.g., metallization layer 148, metallization layer 534) coupled to the third contact structure in the third dielectric layer.

[0123] In a second embodiment, process 700 includes doping the modulator heater structure with one or more types of dopants before forming the second dielectric layer.

[0124] In a third embodiment, process 700 includes forming a fourth contact structure (e.g., contact structures 126b, 128, 128a, 526b, 528 and / or 528a) laterally located in a second direction between the first contact structure and the second contact structure in a plurality of recesses.

[0125] In the fourth embodiment, process 700 includes forming a third dielectric layer (e.g., ESL 142, ILD layer 144) above the second dielectric layer, above the first contact structure, above the second contact structure, and above the third contact structure; forming a first metallization layer (e.g., metallization layer 146, metallization layer 532) coupled to the first contact structure and the third contact structure in the third dielectric layer, wherein the first metallization layer couples the first contact structure and the third contact structure together; and forming a second metallization layer (e.g., metallization layer 148, metallization layer 534) coupled to the second contact structure and the fourth contact structure in the third dielectric layer, wherein the second metallization layer couples the second contact structure and the fourth contact structure together.

[0126] In the fifth embodiment, forming the first contact structure and the third contact structure includes forming the first contact structure and the third contact structure such that the spacing between the first contact structure and the third contact structure is in the range of about 5 micrometers to about 25 micrometers.

[0127] although Figure 7 Several example blocks of process 700 are shown, but in some embodiments, process 700 includes... Figure 7 The blocks shown can be compared to more blocks, fewer blocks, different blocks, or blocks with different arrangements. Additionally, or as an alternative, two or more blocks of process 700 can be executed in parallel.

[0128] In this manner, the semiconductor photonic device includes an optical modulator structure thermally coupled to a heater structure, for heating a waveguide structure of the optical modulator structure to modulate the input optical signal via thermo-optical modulation. The heater structure includes a semiconductor heater assembly electrically coupled to a first electrode (e.g., V) via one or more first contacts. π The first electrode is electrically coupled to a second electrode (e.g., a ground electrode) via multiple second contacts. One or more first contacts and multiple second contacts enable an electrical input to be applied to the semiconductor heater assembly via multiple parallel contact points, thereby allowing a lower phase-shift voltage to be used to achieve power sufficient to heat the waveguide structure of the optical modulator structure.

[0129] As described in more detail above, some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device includes a semiconductor waveguide. The semiconductor photonic device includes a semiconductor heater structure located alongside the semiconductor waveguide and coupled to the semiconductor waveguide via a semiconductor connection region. The semiconductor heater structure includes a doped semiconductor region, a first contact structure located at a first end of the doped semiconductor region, a second contact structure located at a second end of the doped semiconductor region opposite to the first end, and a third contact structure located on the doped semiconductor region. The third contact structure is located between the first contact structure and the second contact structure.

[0130] In some embodiments, the semiconductor photonic device further includes a first metallization layer electrically coupled to the first contact structure and the second contact structure; and a second metallization layer electrically coupled to the third contact structure. In some embodiments, the second metallization layer is electrically coupled to a voltage source, and the first metallization layer is electrically coupled to ground. In some embodiments, the semiconductor photonic device further includes a first metallization layer electrically coupled to the first contact structure; and a second metallization layer electrically coupled to the second contact structure and the third contact structure, wherein the second metallization layer electrically couples the second contact structure and the third contact structure in parallel to the voltage source. In some embodiments, the semiconductor heater structure further includes a fourth contact structure located on a doped semiconductor region, wherein the fourth contact structure is located between the second contact structure and the third contact structure. In some embodiments, the semiconductor photonic device further includes a first metallization layer electrically coupled to the first contact structure and the third contact structure; and a second metallization layer electrically coupled to the second contact structure and the fourth contact structure. In some embodiments, the second contact structure and the fourth contact structure are electrically coupled to the voltage source in parallel through the second metallization layer, and the first contact structure and the third contact structure are electrically coupled to ground in parallel through the first metallization layer.

[0131] As described in more detail above, some embodiments described herein provide a method. The method includes forming an optical modulator structure and a modulator heater structure laterally adjacent to the optical modulator structure in a semiconductor layer above a first dielectric layer of a semiconductor photonic device. The optical modulator structure and the modulator heater structure are physically coupled in the semiconductor layer and are arranged along a first direction in the semiconductor photonic device. The method includes forming a second dielectric layer above the first dielectric layer, above the optical modulator structure, and above the modulator heater structure. The method includes forming a plurality of recesses in the second dielectric layer above the modulator heater structure. The method includes forming a first contact structure at a first end of the modulator heater structure, a second contact structure at a second end of the modulator heater structure opposite to the first end, and a third contact structure laterally located between the first and second contact structures in a second direction substantially perpendicular to the first direction in the plurality of recesses.

[0132] In some embodiments, the method further includes: forming a third dielectric layer over the second dielectric layer, over the first contact structure, over the second contact structure, and over the third contact structure; forming a first metallization layer coupled to the first contact structure and the second contact structure in the third dielectric layer, wherein the first metallization layer couples the first contact structure and the second contact structure together; and forming a second metallization layer coupled to the third contact structure in the third dielectric layer. In some embodiments, the method further includes doping the modulator heater structure with one or more types of dopants before forming the second dielectric layer. In some embodiments, the method further includes forming a fourth contact structure in a plurality of recesses, the fourth contact structure being laterally located between the first contact structure and the second contact structure in a second direction. In some embodiments, the method further includes: forming a third dielectric layer over the second dielectric layer, over the first contact structure, over the second contact structure, and over the third contact structure; forming a first metallization layer coupled to the first contact structure and the third contact structure in the third dielectric layer, wherein the first metallization layer couples the first contact structure and the third contact structure together; and forming a second metallization layer coupled to the second contact structure and the fourth contact structure in the third dielectric layer, wherein the second metallization layer couples the second contact structure and the fourth contact structure together. In some embodiments, forming the first contact structure and the third contact structure includes forming the first contact structure and the third contact structure such that the spacing between the first contact structure and the third contact structure is in the range of about 5 micrometers to about 25 micrometers.

[0133] As described in more detail above, some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device includes an optical modulator structure in a semiconductor layer. The semiconductor photonic device includes a modulator heater structure coupled to the optical modulator structure via one or more semiconductor interconnect regions in the semiconductor layer. The modulator heater structure includes a first contact structure, a second contact structure, a third contact structure located between the first and second contact structures, a first semiconductor heater section located between the first and third contact structures, and a second semiconductor heater section located between the second and third contact structures.

[0134] In some embodiments, the optical modulator structure includes a Mach-Zehnder modulator (MZM); wherein a first semiconductor heater section and a second semiconductor heater section are located in the pad region of the MZM; and wherein the pad region is coupled to the waveguide region of the MZM through one or more semiconductor connection regions. In some embodiments, the optical modulator structure includes a microring modulator (MRM); wherein a bus optical waveguide in the semiconductor layer is located between the MRM and the modulator heater structure; and wherein the first semiconductor heater section and the second semiconductor heater section are coupled to the waveguide structure of the MRM through the bus optical waveguide and multiple semiconductor connection regions. In some embodiments, the modulator heater structure further includes a fourth contact structure, wherein the fourth contact structure is located between the second contact structure and the third contact structure. In some embodiments, the modulator heater structure further includes a third semiconductor heater section located between the third contact structure and the fourth contact structure. In some embodiments, the second contact structure and the fourth contact structure are electrically coupled in parallel to a voltage source; and the first contact structure and the third contact structure are electrically coupled in parallel to ground. In some embodiments, the second contact structure and the fourth contact structure are electrically coupled in parallel to the first metallization layer in the semiconductor photonic device; and the first contact structure and the third contact structure are electrically coupled in parallel to the second metallization layer in the semiconductor photonic device.

[0135] The terms “approximately” and “substantially” can indicate that a given quantity varies within a range of 5% of its value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not limiting. It should be understood that the terms “approximately” and “substantially” can refer to a given quantity as a percentage of the content disclosed herein.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor photonic device, characterized in that, include: Semiconductor waveguide; as well as A semiconductor heater structure, located alongside the semiconductor waveguide and coupled to the semiconductor waveguide via a semiconductor connection region, includes: Doped semiconductor region; The first contact structure is located at the first end of the doped semiconductor region; The second contact structure is located at the second end of the doped semiconductor region opposite to the first end; and The third contact structure is located on the doped semiconductor region. The third contact structure is located between the first contact structure and the second contact structure.

2. The semiconductor photonic device according to claim 1, characterized in that, Also includes: A first metallization layer is electrically coupled to the first contact structure and the second contact structure; as well as The second metallization layer is electrically coupled to the third contact structure.

3. The semiconductor photonic device according to claim 2, characterized in that, The second metallization layer is electrically coupled to a voltage source; and The first metallization layer is electrically coupled to the ground.

4. A semiconductor photonic device, characterized in that, include: The optical modulator structure is located within the semiconductor layer. as well as A modulator heater structure, coupled to the optical modulator structure through one or more semiconductor connection regions in the semiconductor layer, includes: First contact structure; Second contact structure; The third contact structure is located between the first contact structure and the second contact structure; A first semiconductor heater section is located between the first contact structure and the third contact structure; and The second semiconductor heater section is located between the second contact structure and the third contact structure.

5. The semiconductor photonic device according to claim 4, characterized in that, The optical modulator structure mentioned above includes a Mach-Zehnder modulator. The first semiconductor heater section and the second semiconductor heater section are located in the pad area of ​​the Mach-Zehnder modulator; and The pad region is coupled to the waveguide region of the Mach-Zehnder modulator through one or more semiconductor connection regions.

6. The semiconductor photonic device according to claim 4, characterized in that, The optical modulator structure mentioned above includes a micro-ring modulator. The bus optical waveguide in the semiconductor layer is located between the micro-ring modulator and the modulator heater structure; and The first semiconductor heater section and the second semiconductor heater section are coupled to the waveguide structure of the micro-ring modulator through the bus optical waveguide and multiple semiconductor connection regions.

7. The semiconductor photonic device according to claim 4, characterized in that, The modulator heater structure also includes: Fourth contact structure, The fourth contact structure is located between the second contact structure and the third contact structure.

8. The semiconductor photonic device according to claim 7, characterized in that, The modulator heater structure also includes: The third semiconductor heater section is located between the third contact structure and the fourth contact structure.

9. The semiconductor photonic device according to claim 7, characterized in that, The second contact structure and the fourth contact structure are electrically coupled in parallel to a voltage source; and The first contact structure and the third contact structure are electrically coupled in parallel to the ground.

10. The semiconductor photonic device according to claim 7, characterized in that, The second contact structure and the fourth contact structure are electrically coupled in parallel to the first metallization layer in the semiconductor photonic device; and The first contact structure and the third contact structure are electrically coupled in parallel to the second metallization layer in the semiconductor photonic device.

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