Touch screen driving chip based on dynamic energy efficiency adjustment

Abstract

The utility model discloses a kind of touch screen drive chip based on dynamic energy efficiency regulation, it is related to the technical field of semiconductor including circuit, solve the deficiency of traditional touch screen drive chip in touch precision, display effect, power consumption control and system including degree;The chip is through multimodule collaborative architecture and dynamic energy efficiency regulation, realized the integration design of high sensitivity touch control detection and low power consumption display drive;The utility model is through distributed module collaborative architecture, dynamic power management and high-precision signal processing, significantly improve the touch screen touch sensitivity, display definition and energy efficiency ratio, applicable to high resolution, low power consumption mobile terminal and intelligent display equipment.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, including circuit technology, and more specifically to a touch screen driver chip based on dynamic energy efficiency regulation. Background Technology

[0002] With the widespread application of touchscreens in consumer electronics, industrial control, and smart terminals, the market's performance requirements for touchscreen driver chips are becoming increasingly stringent. On the one hand, consumer electronics seek higher touch sensitivity and display resolution; for example, high-end smartphones and tablets need to support ten-point or higher precise touch, coupled with 2K or 4K high-resolution screens, to achieve delicate display and smooth interaction. In industrial scenarios, touchscreens need to work stably in complex environments, posing challenges to the chip's environmental adaptability and anti-interference capabilities.

[0003] On the other hand, energy efficiency has become a key pain point. Traditional touch screen driver chips have architectural flaws: power management is mostly simple hierarchical power supply, which cannot dynamically adjust voltage and current according to real-time load, resulting in high power consumption even when idle or under light load, and poor battery life; the coordination between touch and display driver modules is insufficient, the signal processing link is redundant, and the timing control is lagging, which not only reduces touch response speed and display refresh rate, but also wastes energy due to redundant calculations.

[0004] In terms of technical implementation, traditional chips have simple capacitive sensing array designs, low detection accuracy, and limited scanning frequency, making it impossible to accurately capture fast touch actions; the signal conditioning circuit has weak noise suppression capabilities, and weak touch signals are easily interfered with, affecting subsequent analog-to-digital conversion and positioning accuracy; the row / column driving circuit layout of the display driving module is unreasonable, resulting in signal crosstalk and insufficient voltage swing, leading to poor display uniformity and image distortion at high refresh rates; dynamic power management lacks real-time load sensing and intelligent adjustment, making it difficult to balance performance and power consumption.

[0005] In summary, existing touchscreen driver chips have shortcomings in touch accuracy, display effect, energy efficiency optimization, and environmental adaptability, and cannot meet the market's demand for high-performance, low-power, and high-reliability touchscreen applications. There is an urgent need to innovate architectures and technologies, break through key technologies such as dynamic energy efficiency adjustment, multi-module collaborative optimization, and adaptation to complex scenarios, and develop integrated driver chips with high touch sensitivity, high display resolution, and intelligent power consumption control. Utility Model Content

[0006] The purpose of this invention is to achieve a balance between high performance and low power consumption in touchscreen driver chips through a multi-module collaborative architecture.

[0007] To achieve the above-mentioned technical effects, the present invention adopts the following technical solution: A touchscreen driver chip based on dynamic energy efficiency regulation includes a touch sensing module, a dynamic power management module, a display driver module, a signal processing module, a communication interface module, and a control core unit; the control core unit is disposed within the chip. The display driving module includes a row scanning driving circuit, a column data driving circuit, a pixel compensation circuit, and a timing control circuit. The row scanning driving circuit uses a layered metal interconnect layer for wiring and is distributed laterally along the bottom edge of the chip. The column data driving circuit adopts a dual-sided symmetrical distribution architecture and is respectively located in the output areas on the left and right sides of the chip. The pixel compensation circuit is located on the data path of the row scanning driving circuit and the column data driving circuit. The timing control circuit is located in the control area inside the display driving module. The touch sensing module includes a capacitive sensing array, a signal conditioning circuit, an analog-to-digital converter circuit, and a touch positioning unit; the capacitive sensing array is disposed in the detection area surrounding the chip; the signal conditioning circuit is disposed at the signal output terminal of the capacitive sensing array; the analog-to-digital converter circuit is disposed between the output terminal of the signal conditioning circuit and the input terminal of the control core unit; the touch positioning unit is disposed inside the control core unit. The dynamic power management module includes an adaptive voltage regulation circuit, a load sensing circuit, and a power optimization controller; the load sensing circuit is located on the power path of each functional module of the chip; the adaptive voltage regulation circuit is connected between the power input area of ​​the chip and each functional module; the power optimization controller is included inside the control core unit.

[0008] The signal processing module is located near the data input area of ​​the chip, adjacent to the output end of the touch sensing module; the communication interface module is located on the edge of the chip, and the data transmission port of the communication interface module is close to the pin position of the chip package.

[0009] As a further description of the above technical solution, the touch sensing module includes a capacitive sensing array, a signal conditioning circuit, an analog-to-digital converter circuit, and a touch positioning unit; the capacitive sensing array adopts a multi-channel array layout, with TX(1)-TX(n) as the excitation channel and RX(1)-RX(m) and DM-RX(1)-DM-RX(m) as differential detection channels; the signal conditioning circuit is connected to the signal output terminal of the capacitive sensing array, and the signal conditioning circuit adopts an operational amplifier link of AD698 and subsequent AD8615, connected to the output terminal of the front-end capacitive sensing array, with a gain adjustment range of ≥40dB based on the circuit configuration, and a signal bandwidth of ≥5MHz based on the operational amplifier and filtering characteristics, to accurately condition and amplify the input signal; the analog-to-digital converter circuit is set between the output terminal of the signal conditioning circuit and the input terminal of the control core unit, adopts Σ-Δ modulation, has a resolution of ≥16 bits, and a sampling rate of ≥1MHz; the touch positioning unit is included inside the control core unit, supports ten-point touch recognition, has a positioning accuracy of ≤0.5mm, and is adaptable to glove touch and wet hand operation.

[0010] As a further description of the above technical solution, the signal processing module is located adjacent to the output end of the touch sensing module and includes a signal preprocessing unit, a multi-channel digital filter, an adaptive noise suppression circuit, and a feature extraction engine. The signal preprocessing unit adopts a programmable gain amplifier (PGA) with a gain adjustment range ≥40dB, an input impedance ≥10MΩ, and supports ±10kV ESD protection. The multi-channel digital filter is based on an FIR / IIR hybrid architecture, with each channel configured with an independent coefficient memory, supporting dynamic adjustment of the cutoff frequency, and a stopband attenuation ≥60dB. The adaptive noise suppression circuit has a convergence speed ≤1ms and automatically identifies and suppresses 50 / 60Hz power frequency interference and RF radiated noise. The feature extraction engine includes a touch event detector, a gesture recognition accelerator, and a pressure estimation unit, with a processing delay ≤200μs.

[0011] As a further description of the above technical solution, the display driving module includes a row scanning driving circuit, a column data driving circuit, a pixel compensation circuit, and a timing control circuit. The row scanning driving circuit is equipped with a multi-level output buffer, which is supported by a high-voltage driving unit. The output voltage swing is 0-20V, and it is equipped with an output buffer and voltage conversion circuit with a driving capability of ≥8mA, supporting a refresh rate of up to 60Hz. The three-layer metal interconnect layer includes a power layer, a signal layer, and a ground layer. The column data driving circuit is equipped with a high-precision digital-to-analog converter and a programmable current source, with an output current range of 1-15mA, a settling time of <2μs, and supports intelligent switching between HDR display mode and low-power Eco mode. The pixel compensation circuit includes a gamma correction circuit with a measurement accuracy of 0.01%, a timing jitter compensation unit, a temperature compensation circuit, and a self-calibration module with a built-in reference voltage source for periodically calibrating the driving circuit. The timing control circuit adopts a programmable logic array, supports multi-channel data synchronization, has a clock control unit with a phase adjustment accuracy of ≤50ps, and is adapted to a temperature range of -20℃ to 100℃ by a temperature-compensated crystal oscillator.

[0012] As a further description of the above technical solution, the dynamic power management module includes an adaptive voltage regulation circuit, a load sensing circuit, and a power consumption optimization controller. The load sensing circuit monitors the dynamic current changes of the touch sensing module and the display driving module in real time through a current mirror sampling and analog-to-digital conversion unit, with a response time of <100μs. The adaptive voltage regulation circuit is connected to an external power supply and equipped with a dynamic voltage frequency adjustment (DVFS) unit, with a voltage regulation accuracy of ±20mV and a frequency switching stabilization time of <50μs. The power consumption optimization controller coordinates the power distribution under different operating modes through a preset energy efficiency strategy table, supports custom power consumption thresholds through the I²C interface, and adapts to the energy efficiency requirements of different application scenarios.

[0013] As a further description of the above technical solution, the control core unit adopts a heterogeneous multi-core architecture, including a main processor, a memory management unit, and a hardware acceleration engine. The main processor connects the memory management unit and the hardware acceleration engine simultaneously via a 64-bit AXI bus, forming a closed loop for data processing. The main processor uses an ARM Cortex-M7 core with a clock speed of ≥400MHz, including a double-precision FPU and DSP extensions, supports the SIMD instruction set, and achieves parallel processing of touch and display data through a hardware thread scheduler. The memory management unit is configured with a 32KB instruction cache and a 32KB data cache, adopts a multi-stage pipeline design to achieve ≥64-bit data bandwidth, and has a built-in dynamic memory partition controller to allocate touch and display data buffers as needed. The hardware acceleration engine uses a dedicated image processing unit, implements 2D graphics acceleration based on a tile-based rendering architecture, supports 1080p@120Hz video scaling and format conversion, and has a built-in JPEG / PNG compression engine.

[0014] As a further description of the above technical solution, the communication interface module includes a high-speed data interface and a low-speed control interface; the high-speed data interface adopts the MIPIDSI / CSI protocol, with a data transmission rate ≥4Gbps and supports 4-channel data transmission; the low-speed control interface supports multiple protocols such as SPI / I2C / UART, with a communication rate ≥10Mbps, and has a built-in ESD protection circuit, supporting ±10kV contact discharge protection.

[0015] Positive and beneficial effects: This invention provides a touchscreen driver chip based on dynamic energy efficiency adjustment. Through an innovative architecture design, it achieves multi-module collaborative operation: the touch sensing module employs a high-precision capacitor array and intelligent positioning to accurately capture complex scenarios involving subtle touch movements; the display driver module enhances the clarity and refresh rate of high-resolution images through layered wiring and pixel compensation technology; and the dynamic power management module constructs a closed loop of "load sensing - voltage regulation - power consumption optimization" to intelligently balance performance and energy efficiency. The modules are compactly and rationally arranged, with the control core unit centrally located and signal processing and communication interfaces close to functional areas, shortening transmission paths and reducing latency. This chip not only achieves breakthroughs in key indicators such as touch accuracy, display effect, and standby power consumption, but also improves system reliability and environmental adaptability through integrated design. It provides a low-power, high-response, and highly compatible touch display solution for high-end smart terminals, significantly promoting the upgrade of human-computer interaction experience. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is an overall flowchart of the present invention; Figure 2 This is a circuit diagram of the signal conditioning circuit of this utility model; Figure 3 This is a circuit diagram of the capacitive sensing array of this utility model; Figure 4 This is a structural diagram of the present invention; In the diagram: 1. Touch sensing module; 2. Dynamic power management module; 3. Display driver module; 4. Signal processing module; 5. Communication interface module; 6. Control core unit; 7. Chip; 8. Row scan driver circuit; 9. Column data driver circuit; 10. Pixel compensation circuit; 11. Timing control circuit; 12. Capacitive sensing array; 13. Signal conditioning circuit; 14. Analog-to-digital conversion circuit; 15. Touch positioning unit; 16. Adaptive voltage regulation circuit; 27. Load sensing circuit; 28. Power consumption optimization controller; 29. ​​Signal preprocessing unit; 40. Multi-channel digital filter; 41. Adaptive noise suppression circuit; 42. Feature extraction engine; 33. Main processor; 64. Memory management unit; 65. Hardware acceleration engine; 66. High-speed data interface; 57. Low-speed control interface. Detailed Implementation

[0017] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0018] according to Figures 1-4 A touch screen driver chip based on dynamic energy efficiency regulation includes a touch sensing module 1, a dynamic power management module 2, a display driver module 3, a signal processing module 4, a communication interface module 5, and a control core unit 6; the control core unit 6 is disposed within the chip 7. The display driving module 3 includes a row scanning driving circuit 31, a column data driving circuit 32, a pixel compensation circuit 33, and a timing control circuit 34. The row scanning driving circuit 31 uses a three-layer metal interconnect layer wiring, which is distributed laterally along the bottom edge of the chip. The column data driving circuit 32 adopts a dual-sided symmetrical distribution architecture and is respectively set in the output areas on the left and right sides of the chip. The pixel compensation circuit 33 is set on the data path of the row scanning driving circuit 31 and the column data driving circuit 32. The timing control circuit 34 is set in the control area inside the display driving module. The touch sensing module 1 includes a capacitive sensing array 11, a signal conditioning circuit 12, an analog-to-digital converter 13, and a touch positioning unit 14; the capacitive sensing array 11 is disposed in the detection area surrounding the chip; the signal conditioning circuit 12 is disposed at the signal output terminal of the capacitive sensing array 11; the analog-to-digital converter 13 is disposed between the output terminal of the signal conditioning circuit 12 and the input terminal of the control core unit 6; and the touch positioning unit 14 is disposed inside the control core unit 6. The dynamic power management module 2 includes an adaptive voltage regulation circuit 21, a load sensing circuit 22, and a power optimization controller 23; the load sensing circuit 22 is disposed on the power path of each functional module of the chip; the adaptive voltage regulation circuit 21 is connected between the power input area of ​​the chip and each functional module; the power optimization controller 23 is included inside the control core unit 6.

[0019] The signal processing module 4 is located near the data input area of ​​the chip 7, adjacent to the output end of the touch sensing module 1; the communication interface module 5 is located in the edge area of ​​the chip 7, and the data transmission port of the communication interface module 5 is close to the pin position of the chip package.

[0020] Further, the touch sensing module 1 includes a capacitive sensing array 11, a signal conditioning circuit 12, an analog-to-digital converter circuit 13, and a touch positioning unit 14; the capacitive sensing array 11 adopts a multi-channel array layout, with TX(1)-TX(n) as the excitation channel and RX(1)-RX(m) and DM-RX(1)-DM-RX(m) as differential detection channels; the signal conditioning circuit 12 is connected to the signal output terminal of the capacitive sensing array 11, and the signal conditioning circuit 12 adopts an operational amplifier link of AD698 and subsequent AD8615, connected to... The output of the front-end capacitive sensing array 11 has a gain adjustment range of ≥40dB based on the circuit configuration, and a signal bandwidth of ≥5MHz based on the operational amplifier and filtering characteristics, which accurately conditions and amplifies the input signal; the analog-to-digital conversion circuit 13 is located between the output of the signal conditioning circuit 12 and the input of the control core unit 6, and adopts Σ-Δ modulation, with a resolution of ≥16 bits and a sampling rate of ≥1MHz; the touch positioning unit 14 is included inside the control core unit 6, supports ten-point touch recognition, has a positioning accuracy of ≤0.5mm, and is adaptable to glove touch and wet hand operation.

[0021] In a specific embodiment, the touch sensing module 1 achieves high-precision touch detection through a multi-channel collaborative architecture. The spatially distributed detection of the capacitive sensing array 11, the low-noise amplification of the signal conditioning circuit 12, the high-precision quantization of the analog-to-digital conversion circuit 13, and the touch positioning unit 14 are organically combined. First, the capacitive sensing array 11 sends excitation signals through the TX(1)-TX(n) channels, and the differential channels RX(1)-RX(m) and DM-RX(1)-DM-RX(m) receive the capacitance change signals caused by touch, forming a spatial two-dimensional detection matrix. Then, the signal conditioning circuit 12 uses AD698 to complete the initial signal conditioning, and AD8615 operational amplifier links further amplify the signal. Through ≥40dB gain adjustment and ≥5MHz bandwidth control, environmental noise is effectively suppressed and weak signal strength is improved. Next, the analog-to-digital conversion circuit 13 uses Σ-Δ modulation technology to digitize the analog signal with ≥16-bit resolution and ≥1MHz sampling rate. Finally, the touch positioning unit 14, based on the hardware resources of the control core unit 6, analyzes the multi-point touch signal to extract features, distinguishes between real touch and interference, and achieves accurate positioning of ten-point touch. Through differential detection architecture and high-precision signal chain design, the anti-interference capability is significantly improved, maintaining stable detection even in complex electromagnetic environments; the multi-channel parallel scanning mechanism, combined with high-speed analog-to-digital conversion, enables a scanning frequency of ≥60Hz, effectively capturing fast touch actions; intelligent touch positioning reduces the false touch rate, and combined with hardware acceleration processing, the touch response latency is ≤20ms, providing a guarantee for highly dynamic interactive scenarios; the overall module power consumption is ≤50mW, extending battery life in battery-powered devices, achieving a dual breakthrough in touch performance and energy efficiency.

[0022] Furthermore, the signal processing module 4 is located adjacent to the output of the touch sensing module 1 and includes a signal preprocessing unit 41, a multi-channel digital filter 42, an adaptive noise suppression circuit 43, and a feature extraction engine 44. The signal preprocessing unit 41 uses a programmable gain amplifier (PGA) with a gain adjustment range ≥40dB, an input impedance ≥10MΩ, and supports ±10kV ESD protection. The multi-channel digital filter 42 is based on an FIR / IIR hybrid architecture, with each channel configured with an independent coefficient memory, supporting dynamic adjustment of the cutoff frequency, and a stopband attenuation ≥60dB. The adaptive noise suppression circuit 43 has a convergence speed ≤1ms and automatically identifies and suppresses 50 / 60Hz power frequency interference and RF radiated noise. The feature extraction engine 44 includes a touch event detector, a gesture recognition accelerator, and a pressure estimation unit, with a processing delay ≤200μs.

[0023] In a specific embodiment, the signal processing module 4 implements real-time processing and feature extraction of touch signals through a four-stage pipeline architecture. Analog signal conditioning, digital filtering, adaptive noise suppression, and intelligent feature extraction are organically combined to form a complete signal processing chain. First, the signal preprocessing unit 41 receives the weak signal output from the touch sensing module 1. The programmable gain amplifier (PGA) dynamically adjusts the gain to ≥40dB based on the input signal strength, ensuring a high input impedance ≥10MΩ, reducing signal attenuation by ±10kV ESD, and protecting the circuit from external electrostatic discharge damage to the chip. Subsequently, the multi-channel digital filter 42, based on an FIR / IIR hybrid architecture, performs frequency domain shaping on the preprocessed signal. Each channel has an independently configured coefficient memory, and the cutoff frequency of 10Hz-1MHz is dynamically adjusted according to the touch scenario to achieve a stopband attenuation of ≥60dB. The system effectively filters out high-frequency switching noise and low-frequency mechanical vibration interference. Next, the adaptive noise suppression circuit 43 tracks and eliminates 50 / 60Hz power frequency interference and RF radiated noise in real time with a convergence speed of ≤1ms. A closed-loop suppression system is formed by adjusting the reference signal and feedback. Finally, the feature extraction engine 44 processes the filtered signal in parallel. The touch event detector identifies the touch occurrence time by threshold comparison. The gesture recognition accelerator distinguishes between sliding and clicking actions based on the template. The pressure estimation unit estimates the pressure intensity by the relationship between the touch area and the signal strength. The end-to-end processing delay is ≤200μs. Through dynamic gain control and multi-level filtering, the signal-to-noise ratio is improved by ≥20dB, enabling the chip to detect minute capacitance changes of 0.05pF. The adaptive noise suppression circuit effectively solves the problem of electromagnetic interference in industrial environments, reducing the false touch rate by more than 90%. The hardware acceleration design of the feature extraction engine enables complex gesture recognition accuracy to reach 98.5%, and pressure detection resolution ≤5g, providing a guarantee for precise touch operation. The overall module power consumption is ≤30mW, only 60% of that of traditional solutions, achieving high-performance signal processing while meeting low-power design requirements.

[0024] Furthermore, the display driving module 3 includes a row scanning driving circuit 31, a column data driving circuit 32, a pixel compensation circuit 33, and a timing control circuit 34; the row scanning driving circuit 31 is equipped with a multi-stage output buffer, which is supported by a high-voltage driving unit, with an output voltage swing of 0-20V, and is equipped with an output buffer and voltage conversion circuit with a driving capability of ≥8mA, supporting a refresh rate of up to 60Hz; the three-layer metal interconnect layer includes a power layer, a signal layer, and a ground layer; the column data driving circuit 32 internally includes a high-precision digital-to-analog converter and a programmable current source. The output current range is 1-15mA, the settling time is <2μs, and it supports intelligent switching between HDR display mode and low-power Eco mode. The pixel compensation circuit 33 includes a gamma correction circuit with a measurement accuracy of 0.01%, a timing jitter compensation unit, a temperature compensation circuit, and a self-calibration module with a built-in reference voltage source for periodically calibrating the drive circuit. The timing control circuit 34 adopts a programmable logic array, supports multi-channel data synchronization, has a clock control unit with a phase adjustment accuracy of ≤50ps, and is adapted to a temperature range of -20℃ to 100℃ by a temperature-compensated crystal oscillator.

[0025] In a specific embodiment, the display driver module 3 achieves high-precision display control through a layered collaborative architecture. It organically combines high-voltage driving, precise digital-to-analog conversion, multi-dimensional pixel compensation, and precise timing synchronization to form a complete display driver chain. First, the multi-level output buffer of the row scanning driver circuit 31, under the action of a high-voltage driver unit supporting a voltage swing of 0-20V, generates a row selection signal through a voltage conversion circuit. A driving capability greater than 8mA ensures rapid signal transmission to the edge of the display array. The three metal interconnect layers are the power layer, signal layer, and ground layer, respectively. Layered wiring reduces signal crosstalk and supports a 60Hz automotive refresh rate. Next, the high-precision digital-to-analog converter of the column data driver circuit 32 converts digital grayscale values ​​into analog current. The programmable current source dynamically adjusts the output current from 1-15mA, and the less than 2μs setup time meets the requirements of high frame rate data updates. Intelligent switching of H... DR and Eco modes enhance contrast in high-brightness scenes and reduce power consumption under low load. Subsequently, the pixel compensation circuit 33 initiates multi-dimensional calibration: the gamma correction circuit adjusts the brightness curve with an accuracy of 0.01%, the timing jitter compensation unit eliminates signal transmission delay, the temperature compensation circuit corrects threshold voltage drift caused by changes in ambient temperature in real time, and the self-calibration module periodically refreshes the driving parameters using the built-in reference voltage source. Finally, the programmable logic array of the timing control circuit 34 generates a synchronous clock, the clock control unit with a phase adjustment accuracy of ≤50ps ensures strict alignment of row / column driving signals, and the temperature-compensated crystal oscillator maintains frequency stability over a wide temperature range. Through high-voltage drive and low-impedance wiring, 1080p@60Hz ultra-high-definition display is achieved with a dynamic contrast ratio of 1000:1; intelligent power management improves energy efficiency by 40% in HDR mode and reduces standby power consumption to 5mW in Eco mode; multi-dimensional compensation technology improves pixel brightness uniformity to over 98% and color deviation ΔE < 1, effectively eliminating image ghosting and flicker; the entire module maintains stable operation within a temperature range of -20℃ to 100℃, and the mean time between failures (MTBF) is extended to 100,000 hours, meeting the demanding environmental application requirements of automotive and industrial applications.

[0026] Furthermore, the dynamic power management module 2 includes an adaptive voltage regulation circuit 21, a load sensing circuit 22, and a power consumption optimization controller 23. The load sensing circuit 22 monitors the dynamic current changes of the touch sensing module 1 and the display driving module 3 in real time through a current mirror sampling and analog-to-digital conversion unit, with a response time of <100μs. The adaptive voltage regulation circuit 21 is connected to an external power supply and equipped with a dynamic voltage frequency adjustment (DVFS) unit, with a voltage regulation accuracy of ±20mV and a frequency switching stabilization time of <50μs. The power consumption optimization controller 23 coordinates the power distribution under different working modes through a preset energy efficiency strategy table, supports custom power consumption thresholds through the I²C interface, and adapts to the energy efficiency requirements of different application scenarios.

[0027] In a specific embodiment, the dynamic power management module 2 achieves full-chip energy efficiency optimization through a real-time sensing-dynamic adjustment-intelligent decision-making architecture. It deeply couples current monitoring, DVFS control, and strategic power allocation to form a closed-loop energy efficiency management system. First, the current mirror sampling unit of the load sensing circuit 22 is connected in parallel to the power paths of each module, collecting current data at 10μs intervals. A 12-bit analog-to-digital converter quantizes the analog signal into a digital value, and digital filtering eliminates ripple interference, achieving a load change response of <100μs. Second, the DVFS unit of the adaptive voltage regulation circuit 21 dynamically adjusts the Buck output voltage of the buck converter based on the load data through a digital PID controller. The voltage regulation range is 0.8V-3.3V, with an accuracy of ±20mV, while simultaneously using a PLL phase-locked loop. The clock frequency is adjusted from 10MHz to 400MHz, and the frequency switching adopts pre-charge technology to ensure a stabilization time of <50μs. Finally, the power optimization controller 23 has a predefined strategy table that includes 63 operating modes such as touch-intensive, display refresh, and standby, which are automatically switched according to the load status: when touch is active, the touch module voltage is increased to 2.5V and the clock frequency is 300MHz; when the display refresh rate is high, 3.0V voltage is allocated to the display driver; when idle, a sleep mechanism is triggered, non-critical modules are shut down and a low-power oscillator with a frequency ≤1MHz is enabled. Real-time load sensing reduces power adjustment latency by 85%, dynamic voltage regulation saves 42% of power consumption compared to fixed voltage power supply, and the intelligent sleep mechanism reduces standby power consumption to 5mW; the DVFS unit achieves an energy efficiency ratio of 0.35mW / MHz under 40nm process, which is 35% higher than traditional solutions; the power consumption threshold for each mode can be customized through the I²C interface, so that the chip can achieve optimal energy efficiency in different scenarios such as industrial control and consumer electronics; the entire module area accounts for only 3.2% of the total chip area, achieving a balance between high energy efficiency and small area.

[0028] Furthermore, the control core unit 6 adopts a heterogeneous multi-core architecture, including a main processor 61, a memory management unit 62, and a hardware acceleration engine 63. The main processor 61 is connected to both the memory management unit 62 and the hardware acceleration engine 63 via a 64-bit AXI bus, forming a closed loop for data processing. The main processor 61 uses an ARM Cortex-M7 core with a clock speed of ≥400MHz, includes a double-precision FPU and DSP extensions, supports the SIMD instruction set, and achieves parallel processing of touch and display data through a hardware thread scheduler. The memory management unit 62 is configured with a 32KB instruction cache and a 32KB data cache, adopts a multi-stage pipeline design to achieve ≥64-bit data bandwidth, and has a built-in dynamic memory partition controller to allocate touch and display data buffers as needed. The hardware acceleration engine 63 uses a dedicated image processing unit, implements 2D graphics acceleration based on a tile-based rendering architecture, supports 1080p@60Hz video scaling and format conversion, and has a built-in JPEG / PNG compression engine.

[0029] In a specific embodiment, the control core unit 6 achieves efficient processing of touch and display data through a heterogeneous multi-core architecture. It deeply integrates the flexible control of the main processor, the high-speed data scheduling of the memory management unit, and the dedicated computing power of the hardware acceleration engine to form a three-level processing acceleration chain. First, the main processor 61 separates touch and display tasks through a hardware thread scheduler: touch data is transmitted to the dedicated buffer of the memory management unit 62 via a 64-bit AXI bus, while display data is directly directed to the hardware acceleration engine 63; a double-precision FPU and DSP extension work in conjunction with the SIMD instruction set. Next, the multi-stage pipeline architecture of the memory management unit 62 processes data in parallel with ≥64-bit bandwidth: a 32KB instruction cache prefetches touch and display processing code, and a 32KB data cache uses a ping-pong structure to store real-time sampling points; a dynamic memory partition controller dynamically allocates a 40% touch buffer and a 60% display buffer according to task priority, ensuring that critical data is not overwritten. Finally, the hardware acceleration engine 63, based on a tile-based rendering architecture, divides the 1080p display area into 16×16 pixel sub-blocks and performs 2D graphics transformations in parallel. The video scaling unit enables dynamic resolution adjustment at a 60Hz refresh rate, and the JPEG / PNG compression engine improves the display data compression rate to 50%, reducing memory bandwidth requirements. The heterogeneous architecture reduces touch response latency to 15ms and display frame rate fluctuation to <2%, achieving "zero-perception" interaction. Memory bandwidth utilization is increased to 85%, and data transmission latency is reduced by 60%. The hardware acceleration engine improves graphics rendering efficiency to 8 times that of traditional solutions, and the 1080p video decoding power consumption is only 45mW. Dynamic memory partitioning shortens multi-task switching time to 3μs, supporting simultaneous processing of 10 touch data streams and 2 display outputs. The overall operand / mJ energy efficiency ratio is 3.2 times higher than that of a single-core architecture, achieving low-power operation of 0.35mW / MHz under 40nm process technology, providing a high-performance, low-power core control solution for high-resolution touchscreens.

[0030] Furthermore, the communication interface module 5 includes a high-speed data interface 51 and a low-speed control interface 52; the high-speed data interface 51 adopts the MIPIDSI / CSI protocol, with a data transmission rate ≥4Gbps and supports 4-channel data transmission; the low-speed control interface 52 supports multiple protocols such as SPI / I2C / UART, with a communication rate ≥10Mbps, and has a built-in ESD protection circuit, supporting ±10kV contact discharge protection.

[0031] In a specific embodiment, the communication interface module 5 achieves high-speed data transmission and reliable control command interaction through a layered protocol architecture. It organically combines high-speed differential signal transmission with low-speed serial protocol control to form a communication link with bandwidth matching and strong anti-interference capabilities. First, the high-speed data interface 51 adopts the MIPIDSI / CSI protocol, configuring 4-channel differential signal pairs at the physical layer, with each channel having a data transmission rate ≥1Gbps. Embedded clock recovery technology eliminates transmission jitter. The data link layer implements 8b / 10b encoding to improve signal transmission reliability and supports switching between burst mode and continuous mode, adapting to the needs of low-bandwidth mode for static images and automatic switching to high-bandwidth display content transmission during video playback. Second, the low-speed control interface 52 adopts a protocol multiplexing design, dynamically configuring SPI, I2C, or UART mode through a mode selection register, with a communication rate ≥10Mbps, meeting the interface compatibility requirements of different master control devices. Frame header verification and CRC cyclic redundancy check are implemented at the protocol layer to improve the accuracy of control command transmission. Finally, a multi-level ESD protection circuit is integrated into the interface physical layer: TVS diodes are configured on the input and output pins for primary protection, and internal current-limiting resistors and clamping circuits provide secondary protection, supporting ±10kV contact discharge protection. The high-speed data interface enables uncompressed real-time transmission of 1080p@120Hz display data with an image latency of <1ms, representing a 3-fold increase in bandwidth compared to traditional single-channel interfaces. The low-speed control interface supports 10ms-level control command response and protocol switching time <5μs, meeting the rapid configuration requirements of multi-protocol compatible devices. The ESD protection circuit elevates the chip's anti-static capability in industrial environments to Level 4 of the international standard IEC61000-4-2, reducing the field failure rate by 92%. The overall module power consumption is ≤25mW, accounting for only 8% of the chip's total power consumption, achieving a balance between high-speed communication and low power consumption. Through protocol layering design, the chip can seamlessly interface with mainstream application processors, improving system integration flexibility and market adaptability.

[0032] While specific embodiments of this utility model have been described above, those skilled in the art should understand that these specific embodiments are merely illustrative. Those skilled in the art can make various omissions, substitutions, and changes to the details of the above methods and systems without departing from the principles and essence of this utility model. For example, combining the above method steps to perform substantially the same function and achieve substantially the same result according to substantially the same method falls within the scope of this utility model. Therefore, the scope of this utility model is defined only by the appended claims.

Claims

1. A touchscreen driver chip based on dynamic energy efficiency regulation, characterized in that, It includes a touch sensing module (1), a dynamic power management module (2), a display driver module (3), a signal processing module (4), a communication interface module (5), and a control core unit (6); the control core unit (6) is located within the chip (7); The display driver module (3) includes a row scanning driver circuit (31), a column data driver circuit (32), a pixel compensation circuit (33), and a timing control circuit (34). The row scanning driver circuit (31) uses a 3-layer metal interconnect layer wiring and is distributed horizontally along the bottom edge of the chip. The column data driver circuit (32) adopts a dual-sided symmetrical distribution architecture and is respectively set in the output areas on the left and right sides of the chip. The pixel compensation circuit (33) is set on the data path of the row scanning driver circuit (31) and the column data driver circuit (32). The timing control circuit (34) is set in the control area inside the display driver module. The touch sensing module (1) includes a capacitive sensing array (11), a signal conditioning circuit (12), an analog-to-digital converter (13), and a touch positioning unit (14); the capacitive sensing array (11) is disposed in the detection area surrounding the chip; the signal conditioning circuit (12) is disposed at the signal output terminal of the capacitive sensing array (11); the analog-to-digital converter (13) is disposed between the output terminal of the signal conditioning circuit (12) and the input terminal of the control core unit (6); the touch positioning unit (14) is disposed inside the control core unit (6); The dynamic power management module (2) includes an adaptive voltage regulation circuit (21), a load sensing circuit (22), and a power optimization controller (23); the load sensing circuit (22) is located on the power path of each functional module of the chip; the adaptive voltage regulation circuit (21) is connected between the power input area of ​​the chip and each functional module; the power optimization controller (23) is included inside the control core unit (6); The signal processing module (4) is located near the data input area of ​​the chip (7) and adjacent to the output end of the touch sensing module (1); the communication interface module (5) is located in the edge area of ​​the chip (7) and the data transmission port of the communication interface module (5) is close to the pin position of the chip package.

2. The touchscreen driver chip based on dynamic energy efficiency adjustment according to claim 1, characterized in that, The touch sensing module (1) includes a capacitive sensing array (11), a signal conditioning circuit (12), an analog-to-digital conversion circuit (13), and a touch positioning unit (14). The capacitive sensing array (11) adopts a multi-channel array layout, with TX(1)-TX(n) as the excitation channel, and RX(1)-RX(m) and DM-RX(1)-DM-RX(m) as differential detection channels. The signal conditioning circuit (12) is connected to the signal output terminal of the capacitive sensing array (11). The signal conditioning circuit (12) adopts an operational amplifier link of AD698 and subsequent AD8615, and is connected to the output terminal of the front-end capacitive sensing array (11). The gain adjustment range is ≥40dB based on the circuit configuration, and the signal bandwidth is ≥5MHz based on the operational amplifier and filtering characteristics, so as to accurately condition and amplify the input signal. The analog-to-digital conversion circuit (13) is located between the output of the signal conditioning circuit (12) and the input of the control core unit (6), and adopts Σ-Δ modulation with a resolution of ≥16 bits and a sampling rate of ≥1MHz. The touch positioning unit (14) is included inside the control core unit (6), supports ten-point touch recognition, has a positioning accuracy of ≤0.5mm, and is adaptable to glove touch and wet hand operation.

3. The touchscreen driver chip based on dynamic energy efficiency adjustment according to claim 1, characterized in that, The signal processing module (4) is located adjacent to the output of the touch sensing module (1) and includes a signal preprocessing unit (41), a multi-channel digital filter (42), an adaptive noise suppression circuit (43), and a feature extraction engine (44). The signal preprocessing unit (41) adopts a programmable gain amplifier (PGA), with a gain adjustment range of ≥40dB, an input impedance of ≥10MΩ, and supports ±10kV ESD protection. The multi-channel digital filter (42) is based on a hybrid FIR / IIR architecture, with each channel configured with an independent coefficient memory, supporting dynamic adjustment of the cutoff frequency, and a stopband attenuation of ≥60dB. The adaptive noise suppression circuit (43) has a convergence speed of ≤1ms and automatically identifies and suppresses 50 / 60Hz power frequency interference and RF radiated noise. The feature extraction engine (44) includes a touch event detector, a gesture recognition accelerator, and a pressure estimation unit, with a processing delay of ≤200μs.

4. The touchscreen driver chip based on dynamic energy efficiency adjustment according to claim 1, characterized in that, The display driving module (3) includes a row scanning driving circuit (31), a column data driving circuit (32), a pixel compensation circuit (33), and a timing control circuit (34). The row scanning driving circuit (31) is equipped with a multi-level output buffer, which is supported by a high-voltage driving unit. The output voltage swing is 0-20V. It is equipped with an output buffer and voltage conversion circuit with a driving capability of ≥8mA, and supports a refresh rate of up to 240Hz. The three-layer metal interconnect layer includes a power layer, a signal layer, and a ground layer. The column data driving circuit (32) is equipped with a high-precision digital-to-analog converter and a programmable... The current source has an output current range of 1-15mA and a settling time of <2μs. It supports intelligent switching between HDR display mode and low-power Eco mode. The pixel compensation circuit (33) includes a gamma correction circuit with a measurement accuracy of 0.01%, a timing jitter compensation unit, a temperature compensation circuit, and a self-calibration module with a built-in reference voltage source for periodically calibrating the drive circuit. The timing control circuit (34) adopts a programmable logic array, supports multi-channel data synchronization, has a clock control unit with a phase adjustment accuracy of ≤50ps, and is adapted to a working temperature range of -20℃ to 70℃ by a temperature-compensated crystal oscillator.

5. The touchscreen driver chip based on dynamic energy efficiency adjustment according to claim 1, characterized in that, The dynamic power management module (2) includes an adaptive voltage regulation circuit (21), a load sensing circuit (22), and a power optimization controller (23). The load sensing circuit (22) monitors the dynamic current changes of the touch sensing module (1) and the display driving module (3) in real time through a current mirror sampling and analog-to-digital conversion unit, with a response time of <100μs. The adaptive voltage regulation circuit (21) is connected to an external power supply and equipped with a dynamic voltage frequency adjustment (DVFS) unit, with a voltage regulation accuracy of ±20mV and a frequency switching stabilization time of <50μs. The power optimization controller (23) coordinates the power distribution under different working modes through a preset energy efficiency strategy table, supports custom power consumption thresholds through the I²C interface, and adapts to the energy efficiency requirements of different application scenarios.

6. The touchscreen driver chip based on dynamic energy efficiency regulation according to claim 1, characterized in that: The control core unit (6) adopts a heterogeneous multi-core architecture, including a main processor (61), a memory management unit (62), and a hardware acceleration engine (63). The main processor (61) is connected to the memory management unit (62) and the hardware acceleration engine (63) through a 64-bit AXI bus to form a data processing closed loop. The main processor (61) adopts an ARM Cortex-M7 core with a main frequency of ≥400MHz, including a double-precision FPU and DSP extension, supports the SIMD instruction set, and realizes parallel processing of touch and display data through a hardware thread scheduler. The memory management unit (62) is configured with a 32KB instruction cache and a 32KB data cache, adopts a multi-stage pipeline design to achieve ≥64-bit data bandwidth, and has a built-in dynamic memory partition controller to allocate touch and display data buffers as needed. The hardware acceleration engine (63) adopts a dedicated image processing unit, realizes 2D graphics acceleration based on a Tile-based rendering architecture, supports 1080p@120Hz video scaling and format conversion, and has a built-in JPEG / PNG compression engine.

7. The touchscreen driver chip based on dynamic energy efficiency adjustment according to claim 1, characterized in that, The communication interface module (5) includes a high-speed data interface (51) and a low-speed control interface (52); the high-speed data interface (51) adopts the MIPIDSI / CSI protocol, with a data transmission rate ≥4Gbps and supports 4-channel data transmission; the low-speed control interface (52) supports multiple protocols such as SPI / I2C / UART, with a communication rate ≥10Mbps, built-in ESD protection circuit, and supports ±10kV contact discharge protection.

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