A 6U CPCI-compliant main control board based on a high-performance multi-core processor

Abstract

The 6U CPCI specification main control board of the high-performance multi-core processor comprises a CPCI interface, a PMC interface A, a PMC interface B, a SATA interface A, a SATA interface B, an XMC interface A, an XMC interface B, a PCIe bridge A, a PCIe bridge B, a high-performance multi-core processor, an I2C device, an Ethernet module, a DDR3L module, a Flash module, a complex programmable logic device, a multi-protocol transceiver and a connector.

Description

Technical Field

[0001] This utility model belongs to the field of embedded industrial control and communication equipment technology. Specifically, it designs a high-performance multi-core processor 6U main control board that conforms to the CPCI standard. It is especially suitable for scenarios with stringent requirements for computing power and reliability, such as military electronics, rail transit control, and high-precision data acquisition. Background Technology

[0002] The CPCI bus, with its high reliability, hot-swappability, and modularity, is widely used in embedded systems operating in harsh environments. Traditional CPCI controllers typically use 4-8 core processors, but today's demands require processors with higher performance and more cores. However, current CPCI controllers face the following limitations: 1. Insufficient computing power: Multi-channel high-speed data acquisition requires parallel processing, and the existing main control board is unable to meet the real-time processing requirements; 2. Limited scalability: The number of PCIe lanes is relatively small, making it difficult to connect multiple functional cards simultaneously; 3. Low bus efficiency: The single PCI bus mode leads to rigid system topology.

[0003] Therefore, there is a need to develop CPCI main control boards with higher speeds, more channels, and higher bus efficiency. The development of a 6U CPCI main control board using a high-performance multi-core processor is of great significance.

[0004] Therefore, there is a need to develop CPCI main control boards with higher speeds, more channels, and higher bus efficiency. The development of a 12-core 6UCPCI main control board is of great significance. Summary of the Invention

[0005] To address the current requirements for CPCI main controller computing power, channel count, and bus efficiency in relevant fields, and to meet future development needs, this invention provides a 6U CPCI-specification main controller board employing a high-performance multi-core processor. This main controller board uses a high-performance multi-core processor with a maximum clock speed of 1.8GHz; the CPCI interface supports a 64-bit PCI bus with configurable master-slave mode; it has two expansion slots, one XMC supporting 4x PCIe 3.0 and one XMC supporting 4x PCIe 2.0; the PMC supports a 64-bit PCI bus, which can provide three different operating frequencies: 33MHz, 66MHz, and 133MHz; two onboard SATA II interfaces, supporting up to four Gigabit Ethernet interfaces; and the CPLD provides 16 programmable GPIOs.

[0006] The 6U CPCI-compliant main control board based on a high-performance multi-core processor includes: CPCI interface, PMC interface A, PMC interface B, SATA interface A, SATA interface B, XMC interface A, XMC interface B, PCIe bridge A, PCIe bridge B, high-performance multi-core processor, I2C device, Ethernet module, DDR3L module, Flash module, complex programmable logic device, multi-protocol transceiver, and connectors; The CPCI interface connects to PCIe bridge B, PMC interface A, Ethernet module, PMC interface B, SATA interface B, high-performance multi-core processor, complex programmable logic device, and multi-protocol transceiver. The CPCI interface contains five connectors: J1, J2, J3, J4, and J5, which enable signal input and output. PMC interface A connects to CPCI interface, PMC interface B, and PCIe bridge chip A to enable PCI signal transmission and reception. PMC interface B connects to CPCI interface, PMC interface A, and PCIe bridge chip A to enable PCI signal transmission and reception. SATA interface A connects to high-performance multi-core processors and supports large-capacity hard drives; SATA interface B connects to CPCI interface, high-performance multi-core processors, and supports large-capacity hard drives; XMC interface A connects to a high-performance multi-core processor to enable PCIe signal transmission and reception; XMC interface B connects to a high-performance multi-core processor to enable PCIe signal transmission and reception; PCIe bridge A connects PMC interface A, PMC interface B, and a high-performance multi-core processor to achieve the conversion between PCIe and PCI signals; PCIe bridge chip B connects to the CPCI interface and high-performance multi-core processors, enabling the conversion between PCIe and PCI signals; High-performance multi-core processors connect to CPCI interfaces, SATA interface A, SATA interface B, XMC interface A, XMC interface B, PCIe bridge A, PCIe bridge B, I2C devices, Ethernet modules, DDR3L modules, Flash modules, complex programmable logic devices, and multi-protocol transceivers; I2C devices connect to high-performance multi-core processors; Ethernet module connects to CPCI interface, high-performance multi-core processor, and connectors; The DDR3L module connects to a high-performance multi-core processor to enable storage functionality; Flash modules connect to high-performance multi-core processors and complex programmable logic devices to achieve storage functions; Complex programmable logic devices connect to CPCI interfaces, Flash modules, and high-performance multi-core processors to achieve control functions; Multi-protocol transceiver connects to CPCI interface, high-performance multi-core processor, and connectors; The connector connects to the Ethernet module and the multi-protocol transceiver, providing an external connector for the main control board.

[0007] The beneficial effects of this utility model are as follows: The 6U CPCI-specification main control board with a high-performance multi-core processor is designed as a 6U CPCI specification. This main control board uses a high-performance multi-core processor as the core processing device to achieve high computing power, high speed, and high precision data acquisition. It uses a PCIe bridge chip to realize the conversion between PCIe and PCI. The Flash module and DDR3L module realize data storage. The multi-protocol transceiver realizes multi-protocol communication. The Ethernet module realizes Ethernet communication. The complex programmable logic device realizes overall control and GPIO functions. It is suitable for scenarios with stringent requirements for computing power and reliability, such as military electronics, rail transit control, and high-precision data acquisition.

[0008] The technical solution of this utility model will be further described in detail below with reference to the accompanying drawings and examples. Attached Figure Description

[0009] Figure 1 The structural block diagram of the 6U CPCI specification main control board with a high-performance multi-core processor provided by this utility model. Detailed Implementation

[0010] like Figure 1 The diagram shown is a structural block diagram of the 6U CPCI specification main control board with a high-performance multi-core processor provided by this utility model.

[0011] The 6U CPCI-compliant main control board of the high-performance multi-core processor includes: CPCI interface 1, PMC interface A2, PMC interface B3, SATA interface A4, SATA interface B5, XMC interface A6, XMC interface B7, PCIe bridge A8, PCIe bridge B9, high-performance multi-core processor 10, I2C device 11, Ethernet module 12, DDR3L module 13, Flash module 14, complex programmable logic device 15, multi-protocol transceiver 16, and connector 17. The CPCI interface 1 connects to the PCIe bridge chip B9, PMC interface A2, Ethernet module 12, PMC interface B3, SATA interface B5, high-performance multi-core processor 10, complex programmable logic device 15, and multi-protocol transceiver 16. The CPCI interface 1 contains 5 connectors: J1, J2, J3, J4, and J5, which realize signal input and output. PMC interface A2 connects to CPCI interface 1, PMC interface B3, and PCIe bridge chip A8 to enable PCI signal transmission and reception. PMC interface B3 connects to CPCI interface 1, PMC interface A2, and PCIe bridge chip A8 to realize PCI signal transmission and reception; The SATA interface A4 connects to a high-performance multi-core processor 10 and supports large-capacity hard drives; SATA interface B5 connects to CPCI interface 1, high-performance multi-core processor 10, and supports large-capacity hard drives; XMC interface A6 connects to a high-performance multi-core processor 10 to enable PCIe signal transmission and reception; XMC interface B7 connects to a high-performance multi-core processor 10 to enable PCIe signal transmission and reception; PCIe bridge chip A8 connects to PMC interface A2, PMC interface B3, and high-performance multi-core processor 10 to realize the conversion between PCIe and PCI signals; PCIe bridge chip B9 connects to CPCI interface 1 and high-performance multi-core processor 10, realizing the conversion between PCIe and PCI signals; The high-performance multi-core processor 10 is connected to CPCI interface 1, SATA interface A4, SATA interface B5, XMC interface A6, XMC interface B7, PCIe bridge A8, PCIe bridge B9, I2C device 11, Ethernet module 12, DDR3L module 13, Flash module 14, complex programmable logic device 15, and multi-protocol transceiver 16. The high-performance multi-core processor 10 used in this solution is model T4240, which is equipped with 12 dual-thread e6500 cores. I2C device 11 connects to high-performance multi-core processor 10; Ethernet module 12 connects to CPCI interface 1, high-performance multi-core processor 10, and connector 17; The DDR3L module 13 is connected to the high-performance multi-core processor 10 to realize the storage function; Flash module 14 connects to high-performance multi-core processor 10 and complex programmable logic device 15 to realize storage function; The complex programmable logic device 15 connects to the CPCI interface 1, the Flash module 14, and the high-performance multi-core processor 10 to realize control functions. Multi-protocol transceiver 16 connects to CPCI interface 1, high-performance multi-core processor 10, and connector 17; Connector 17 connects to Ethernet module 12 and multi-protocol transceiver 16, providing an external connector for the main control board.

[0012] The beneficial effects of this utility model are as follows: The 6U CPCI-specification main control board with a high-performance multi-core processor is designed as a 6U CPCI specification. This main control board uses a high-performance multi-core processor as the core processing device to achieve high computing power, high speed, and high precision data acquisition. It uses a PCIe bridge chip to realize signal conversion between the PCIe bus and PCI. The Flash module and DDR3L module realize data storage. The multi-protocol transceiver realizes multi-protocol communication. The Ethernet module realizes Ethernet communication. The complex programmable logic device realizes overall control and GPIO interface. It is suitable for scenarios with stringent requirements for computing power and reliability, such as military electronics, rail transit control, and high-precision data acquisition.

[0013] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and not to limit it. Although the utility model has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solution of this utility model, and these modifications or equivalent substitutions cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of this utility model.

Claims

1. A 6U CPCI-compliant main control board based on a high-performance multi-core processor, characterized in that: The 6U CPCI-compliant main control board of the high-performance multi-core processor includes: CPCI interface, PMC interface A, PMC interface B, SATA interface A, SATA interface B, XMC interface A, XMC interface B, PCIe bridge A, PCIe bridge B, high-performance multi-core processor, I2C device, Ethernet module, DDR3L module, Flash module, complex programmable logic device, multi-protocol transceiver, and connectors; Among them, the CPCI interface connects to PCIe bridge chip B, PMC interface A, Ethernet module, PMC interface B, SATA interface B, high-performance multi-core processor, complex programmable logic device, and multi-protocol transceiver. PMC interface A connects to CPCI interface, PMC interface B, and PCIe bridge chip A to enable PCI signal transmission and reception. PMC interface B connects to CPCI interface, PMC interface A, and PCIe bridge chip A to enable PCI signal transmission and reception. SATA interface A connects to high-performance multi-core processors and supports large-capacity hard drives; SATA interface B connects to CPCI interface, high-performance multi-core processors, and supports large-capacity hard drives; XMC interface A connects to a high-performance multi-core processor to enable PCIe signal transmission and reception; XMC interface B connects to a high-performance multi-core processor to enable PCIe signal transmission and reception; PCIe bridge A connects PMC interface A, PMC interface B, and a high-performance multi-core processor to achieve the conversion between PCIe and PCI signals; PCIe bridge chip B connects to the CPCI interface and high-performance multi-core processors, enabling the conversion between PCIe and PCI signals; High-performance multi-core processors connect to CPCI interfaces, SATA interface A, SATA interface B, XMC interface A, XMC interface B, PCIe bridge A, PCIe bridge B, I2C devices, Ethernet modules, DDR3L modules, Flash modules, complex programmable logic devices, and multi-protocol transceivers; I2C devices connect to high-performance multi-core processors; Ethernet module connects to CPCI interface, high-performance multi-core processor, and connectors; The DDR3L module connects to a high-performance multi-core processor to enable storage functionality; Flash modules connect to high-performance multi-core processors and complex programmable logic devices to achieve storage functions; Complex programmable logic devices connect to CPCI interfaces, Flash modules, and high-performance multi-core processors to achieve control functions; Multi-protocol transceiver connects to CPCI interface, high-performance multi-core processor, and connectors; The connector connects to the Ethernet module and the multi-protocol transceiver, providing an external connector for the main control board.

2. The 6U CPCI specification main control board based on a high-performance multi-core processor according to claim 1, characterized in that: The CPCI interface includes five connectors: J1, J2, J3, J4, and J5, which enable signal input and output.

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