Gate driver

Abstract

The gate driver includes a plurality of stages. Each of the stages includes a control circuit and a first gate output circuit to an M-1th gate output circuit, and each of the stages respectively receives a first clock signal to an Mth clock signal, where M is a positive integer greater than or equal to 3. The control circuit receives an input signal in response to one of the first clock signal to the Mth clock signal, and controls a voltage of a control node and a voltage of an inverted control node based on the input signal. The first gate output circuit to the M-1th gate output circuit sequentially outputs, in response to the voltage of the control node and the voltage of the inverted control node, a clock signal different from the one of the first clock signal to the Mth clock signal received by the control circuit among the first clock signal to the Mth clock signal as a first gate signal to an M-1th gate signal.

Description

Technical Field

[0001] Embodiments of this invention relate to a gate driver. More specifically, this invention relates to a gate driver for reducing dead time and power consumption. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel may include gate lines, data lines, emitter lines, and pixels. The display panel driver may include a gate driver for providing gate signals to the gate lines, a data driver for providing data voltages to the data lines, an emitter driver for providing emitter signals to the emitter lines, and a drive controller for controlling the gate driver, data driver, and emitter driver. Utility Model Content

[0003] In display devices where the gate driver is integrated into the display panel, the number of transistors and signal lines in the gate driver can affect the dead time and power consumption of the display device. For example, when the number of transistors and signal lines in the gate driver is large, there is a problem of increased dead time and power consumption in the display device.

[0004] The present invention provides a gate driver for reducing dead time and power consumption.

[0005] In an embodiment of the gate driver according to the present invention, the gate driver includes multiple stages. In such an embodiment, each stage includes a control circuit and a first gate output circuit to a (M-1)th gate output circuit, and each stage receives a first clock signal to an Mth clock signal, where M is a positive integer greater than or equal to 3. In such an embodiment, the control circuit receives an input signal in response to one of the first to Mth clock signals and controls the voltage of the control node and the voltage of the inverting control node based on the input signal. In such an embodiment, the first to M-1th gate output circuits, in response to the voltage of the control node and the voltage of the inverting control node, sequentially output a clock signal from the first to Mth clock signals that is different from one of the first to Mth clock signals received by the control circuit as the first to M-1th gate signals.

[0006] In an implementation, one of the first clock signal to the Mth clock signal may be the Mth clock signal, and the control circuit may include: a first transistor, including a gate electrode for receiving the Mth clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node; a second transistor, including a gate electrode connected to an inverting control node, a first electrode for receiving a high gate voltage, and a second electrode; and a third transistor, including a gate electrode for receiving a control clock signal, a first electrode connected to a control node, and a second electrode connected to the second electrode of the second transistor.

[0007] In an implementation, the control clock signal can be one of the first clock signal to the (M-1)th clock signal.

[0008] In an implementation, the control circuit may further include a fourth transistor, which includes a gate electrode connected to the control node, a first electrode for receiving the Mth clock signal, and a second electrode connected to the inverting control node.

[0009] In an implementation, the control circuit may further include a fifth transistor, which includes a gate electrode for receiving an Mth clock signal, a first electrode for receiving a low gate voltage, and a second electrode connected to an inverting control node.

[0010] In an implementation, the control circuit may further include a fourth transistor, which includes a gate electrode for receiving an input signal, a first electrode for receiving an M-1th gate signal, and a second electrode connected to an inverting control node.

[0011] In an implementation, the control circuit may further include a fifth transistor, which includes a gate electrode for receiving a (M-1)th gate signal, a first electrode for receiving a low gate voltage, and a second electrode connected to an inverting control node.

[0012] In one embodiment, the first gate output circuit may include: a sixth transistor, including a gate electrode connected to an inverting control node, a first electrode receiving a high gate voltage, and a second electrode connected to the first gate output node, wherein a first gate signal is output from the first gate output node; a seventh transistor, including a gate electrode connected to a control node, a first electrode receiving a first clock signal, and a second electrode connected to the first gate output node; a first capacitor, including a first electrode receiving a high gate voltage and a second electrode connected to the inverting control node; and a second capacitor, including a first electrode connected to the control node and a second electrode connected to the first gate output node. In another embodiment, the second gate output circuit may include: a ninth transistor, including a gate electrode connected to an inverting control node, a first electrode receiving a high gate voltage, and a second electrode connected to the second gate output node, wherein a second gate signal is output from the second gate output node; a tenth transistor, including a gate electrode connected to the control node, a first electrode receiving a second clock signal, and a second electrode connected to the second gate output node; and a fourth capacitor, including a first electrode connected to the control node and a second electrode connected to the second gate output node.

[0013] In one implementation, the control node may include a first control node, a second control node, and a third control node. In such an implementation, the first gate output circuit may further include an eighth transistor, which includes a gate electrode receiving a low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

[0014] In an implementation, the second gate output circuit may further include an eleventh transistor, which includes a gate electrode receiving a low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the third control node.

[0015] In an implementation, one of the first clock signal to the Mth clock signal may be the Mth clock signal, and the control circuit may include: a first transistor, including a gate electrode for receiving the Mth clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node; a second transistor, including a gate electrode connected to a control node, a first electrode for receiving a high gate voltage, and a second electrode connected to an inverting control node; and a third transistor, including a gate electrode connected to a control node, a first electrode for receiving a low gate voltage, and a second electrode connected to an inverting control node.

[0016] In one embodiment, the first gate output circuit may include: a fourth transistor, including a gate electrode connected to an inverting control node, a first electrode receiving a high gate voltage, and a second electrode connected to the first gate output node, wherein a first gate signal is output from the first gate output node; a fifth transistor, including a gate electrode connected to a control node, a first electrode receiving a first clock signal, and a second electrode connected to the first gate output node; a first capacitor, including a first electrode receiving a high gate voltage and a second electrode connected to the inverting control node; and a second capacitor, including a first electrode connected to the control node and a second electrode connected to the first gate output node. In another embodiment, the second gate output circuit may include: a seventh transistor, including a gate electrode connected to an inverting control node, a first electrode receiving a high gate voltage, and a second electrode connected to the second gate output node, wherein a second gate signal is output from the second gate output node; an eighth transistor, including a gate electrode connected to the control node, a first electrode receiving a second clock signal, and a second electrode connected to the second gate output node; and a fourth capacitor, including a first electrode connected to the control node and a second electrode connected to the second gate output node.

[0017] According to the implementation of the gate driver, since the gate output circuit shares the control circuit, the number of transistors and signal lines in each stage can be reduced, and the dead zone and power consumption of the display device can be reduced. Attached Figure Description

[0018] The above and other features of the present invention will become more apparent from the detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention;

[0020] Figure 2 It is shown Figure 1 A circuit diagram illustrating the implementation method of the pixels;

[0021] Figure 3 This is a block diagram illustrating a gate driver according to an embodiment of the present invention;

[0022] Figure 4 It is shown Figure 3 Timing diagram of an implementation of the gate driver operation;

[0023] Figure 5 It is shown Figure 3 A block diagram of the gate driver stage;

[0024] Figure 6 It is shown Figure 3A circuit diagram illustrating an implementation of the gate driver stage;

[0025] Figure 7 It is shown Figure 3 A circuit diagram of another embodiment of the gate driver stage;

[0026] Figure 8 It is shown Figure 3 A circuit diagram of another embodiment of the gate driver stage;

[0027] Figure 9 This is a block diagram illustrating an embodiment of the electronic device; and

[0028] Figure 10 It shows that Figure 9 The diagram illustrates an implementation of an electronic device as a smartphone. Detailed Implementation

[0029] The present invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Similar reference numerals consistently denote similar elements.

[0030] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being "directly" on another element, there is no intermediary element.

[0031] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, reference to “a” element in a claim followed by “the” element includes one element and multiple elements. For example, “a single element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” or “including” and / or “comprising” specify the presence of the described features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0033] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to encompass different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “below” the other element will subsequently be oriented “above” the other element. Thus, depending on the specific orientation of the drawing, the term “below” can encompass both “below” and “above” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other element will subsequently be oriented “above” the other element. Thus, the term “below” or “under” can encompass both “above” and “below” orientations.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0035] Embodiments are described herein with reference to illustrations that serve as schematic representations of preferred embodiments. Therefore, variations in the illustrated shapes should be anticipated, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments disclosed herein should not be construed as being limited to a specific shape of the regions as shown herein, but should include deviations in shape, for example, due to manufacturing processes. For instance, regions shown or described as flat may typically have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0036] The present invention will be described in more detail below with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram illustrating a display device 100 according to an embodiment of the present invention.

[0038] refer to Figure 1 An embodiment of the display device 100 may include a display panel 110 and a display panel driver. The display panel driver may include a drive controller 120, a gate driver 130, a gamma reference voltage generator 140, a data driver 150, and a transmit driver 160.

[0039] The display panel 110 may include a display area for displaying images and a peripheral area adjacent to the display area.

[0040] The display panel 110 may include a gate line GL, a data line DL, an emitter line EML, and a pixel P electrically connected to the gate line GL, the data line DL, and the emitter line EML, respectively. The gate line GL may extend in a first direction, the data line DL may extend in a second direction intersecting the first direction, and the emitter line EML may extend in the first direction.

[0041] The drive controller 120 can receive input image data IMG and input control signal CONT from an external device. In some embodiments, the input image data IMG may include, for example, red image data, green image data, and blue image data. The input image data IMG may also include white image data. In some embodiments, the input image data IMG may include, for example, magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0042] The drive controller 120 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0043] The drive controller 120 can generate a first control signal CONT1 for controlling the operation of the gate driver 130 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 130. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0044] The drive controller 120 can generate a second control signal CONT2 for controlling the operation of the data driver 150 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 150. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0045] The drive controller 120 can generate a data signal DATA based on the input image data IMG. The drive controller 120 can output the data signal DATA to the data driver 150.

[0046] The drive controller 120 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 140, and output the third control signal CONT3 to the gamma reference voltage generator 140.

[0047] The drive controller 120 can generate a fourth control signal CONT4 for controlling the operation of the transmitter driver 160 based on the input control signal CONT, and output the fourth control signal CONT4 to the transmitter driver 160.

[0048] The gate driver 130 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 120. The gate driver 130 can output the gate signal to the gate line GL.

[0049] Gamma reference voltage generator 140 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from drive controller 120. Gamma reference voltage generator 140 can provide the gamma reference voltage VGREF to data driver 150. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0050] In some implementations, for example, the gamma reference voltage generator 140 may be located in the drive controller 120 or in the data driver 150.

[0051] Data driver 150 can receive a second control signal CONT2 and a data signal DATA from drive controller 120, and a gamma reference voltage VGREF from gamma reference voltage generator 140. Data driver 150 can use the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. Data driver 150 can output the data voltage to data line DL.

[0052] The transmit driver 160 can generate a transmit signal for driving the transmit line EML in response to a fourth control signal CONT4 received from the drive controller 120. The transmit driver 160 can output the transmit signal to the transmit line EML.

[0053] In the implementation method, such as Figure 1 As shown, the gate driver 130 may be disposed on a first side of the display panel 110, and the emitter driver 160 may be disposed on a second side of the display panel 110. Although shown, the present invention is not limited thereto. In another embodiment, for example, both the gate driver 130 and the emitter driver 160 may be disposed on the first side of the display panel 110. In another embodiment, for example, both the gate driver 130 and the emitter driver 160 may be disposed on two opposite sides of the display panel 110. In another embodiment, for example, the gate driver 130 and the emitter driver 160 may be integrally formed as a single chip.

[0054] Figure 2 It is shown Figure 1 A circuit diagram illustrating the implementation of pixel P.

[0055] refer to Figure 1 and Figure 2 The implementation of pixel P may include first pixel transistors PT1 to seventh pixel transistors PT7, storage capacitor CST, and light-emitting element EL.

[0056] The first pixel transistor PT1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first pixel transistor PT1 may generate a drive current based on the difference between the voltage of the first node N1 and the voltage of the second node N2.

[0057] The second pixel transistor PT2 may include a gate electrode for receiving a data write gate signal GW[N], a first electrode for receiving a data voltage VDATA, and a second electrode connected to the second node N2. Here, N is a positive integer greater than or equal to 1. In such an implementation, pixel P may be a pixel in the Nth row. The second pixel transistor PT2 may provide the data voltage VDATA to the second node N2 in response to the data write gate signal GW[N].

[0058] The third pixel transistor PT3 may include a gate electrode for receiving a compensation gate signal GC[N], a first electrode connected to a third node N3, and a second electrode connected to a first node N1. The third pixel transistor PT3 may be diode-connected to the first pixel transistor PT1 (or diode-connected to the first pixel transistor PT1) in response to the compensation gate signal GC[N].

[0059] The fourth pixel transistor PT4 may include a gate electrode for receiving an initialization gate signal GI[N], a first electrode for receiving an initialization voltage VINT, and a second electrode connected to the first node N1. The fourth pixel transistor PT4 may provide an initialization voltage VINT to the first node N1 in response to the initialization gate signal GI[N].

[0060] The fifth pixel transistor PT5 may include a gate electrode for receiving the emission signal EM[N], a first electrode for receiving the first power supply voltage ELVDD, and a second electrode connected to the second node N2. The sixth pixel transistor PT6 may include a gate electrode for receiving the emission signal EM[N], a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The fifth pixel transistor PT5 and the sixth pixel transistor PT6 can control the emission time of the light-emitting element EL in response to the emission signal EM[N].

[0061] The seventh pixel transistor PT7 may include a gate electrode that receives an anode initialization gate signal GB[N], a first electrode that receives an anode initialization voltage VAINT, and a second electrode connected to the fourth node N4. The seventh pixel transistor PT7 may provide an anode initialization voltage VAINT to the fourth node N4 in response to the anode initialization gate signal GB[N].

[0062] The storage capacitor CST may include a first electrode that receives a first power supply voltage ELVDD and a second electrode connected to a first node N1. The storage capacitor CST may store a data voltage VDATA.

[0063] The light-emitting element EL may include an anode connected to the fourth node N4 and a cathode receiving a second power supply voltage ELVSS. The light-emitting element EL may emit light based on a drive current. Since the intensity of the drive current is determined based on the level of the data voltage VDATA, the emission intensity of the light-emitting element EL may be determined based on the level of the data voltage VDATA.

[0064] In one embodiment, the first pixel transistor PT1, the second pixel transistor PT2, and the fifth pixel transistors PT5 through the seventh pixel transistors PT7 can be P-type transistors, and the third pixel transistor PT3 and the fourth pixel transistor PT4 can be N-type transistors. In another embodiment, for example, the P-type transistor can be a P-type metal-oxide-semiconductor (PMOS) transistor. In yet another embodiment, for example, the N-type transistor can be an N-type metal-oxide-semiconductor (NMOS) transistor. However, the present invention is not limited thereto. The first pixel transistors PT1 through the seventh pixel transistors PT7 can be P-type transistors. Optionally, the first pixel transistors PT1 through the seventh pixel transistors PT7 can be N-type transistors. Furthermore, although... Figure 2 The embodiment of pixel P shown includes seven transistors PT1 to PT7 and a capacitor CST, but the present invention is not limited thereto. In the embodiment, pixel P may include at least two or more pixel switching elements or at least one or more capacitors.

[0065] Figure 3 This is a block diagram illustrating a gate driver 200 according to an embodiment of the present invention. Figure 4 It is a display Figure 3 Timing diagram of an implementation of the operation of the gate driver 200.

[0066] refer to Figures 1 to 4 According to an embodiment of the present invention, the gate driver 200 may include multiple stages ST[1], ST[2], ST[3], ST[4]... Each of the stages ST[1], ST[2], ST[3], ST[4]... may receive a gate start signal FLM and clock signals CLK1 to CLK4. The clock signals CLK1 to CLK4 may have different phases from each other. The first stage ST[1] may receive the gate start signal FLM as an input signal, and subsequent stages ST[2], ST[3], ST[4]... may receive previous gate signals GS[3], GS[6], GS[9]... as input signals.

[0067] The stages ST[1], ST[2], ST[3], ST[4]... can sequentially generate gate signals GS[1], GS[2], GS[3], GS[4], GS[5], GS[6], GS[7], GS[8], GS[9], GS

[10] , GS

[11] , GS

[12] ...

[0068] In an implementation, for example, the first stage ST[1] may receive the gate start signal FLM in response to the fourth clock signal CLK4. The first stage ST[1] may generate a first clock signal CLK1 as a first gate signal GS[1] based on the gate start signal FLM. The first stage ST[1] may generate a second clock signal CLK2 as a second gate signal GS[2] based on the gate start signal FLM. The first stage ST[1] may generate a third clock signal CLK3 as a third gate signal GS[3] based on the gate start signal FLM.

[0069] In an implementation, for example, the second-stage ST[2] may receive the third gate signal GS[3] in response to the third clock signal CLK3. The second-stage ST[2] may generate a fourth clock signal CLK4 as the fourth gate signal GS[4] based on the third gate signal GS[3]. The second-stage ST[2] may generate a first clock signal CLK1 as the fifth gate signal GS[5] based on the third gate signal GS[3]. The second-stage ST[2] may generate a second clock signal CLK2 as the sixth gate signal GS[6] based on the third gate signal GS[3].

[0070] In an implementation, for example, the third-stage ST[3] may receive the sixth gate signal GS[6] in response to the second clock signal CLK2. The third-stage ST[3] may generate a third clock signal CLK3 as the seventh gate signal GS[7] based on the sixth gate signal GS[6]. The third-stage ST[3] may generate a fourth clock signal CLK4 as the eighth gate signal GS[8] based on the sixth gate signal GS[6]. The third-stage ST[3] may generate a first clock signal CLK1 as the ninth gate signal GS[9] based on the sixth gate signal GS[6].

[0071] In an implementation, for example, the fourth stage ST[4] may receive the ninth gate signal GS[9] in response to the first clock signal CLK1. The fourth stage ST[4] may generate a second clock signal CLK2 as the tenth gate signal GS

[10] based on the ninth gate signal GS[9]. The fourth stage ST[4] may generate a third clock signal CLK3 as the eleventh gate signal GS

[11] based on the ninth gate signal GS[9]. The fourth stage ST[4] may generate a fourth clock signal CLK4 as the twelfth gate signal GS

[12] based on the ninth gate signal GS[9].

[0072] Figure 5 It is shown Figure 3 Block diagram of stage 300 of gate driver 200.

[0073] refer to Figures 1 to 5 Each stage 300 of the gate driver 200 according to an embodiment of the present invention may include a control circuit and a first gate output circuit to a (M-1)th gate output circuit. Here, M is a positive integer greater than or equal to 3. Each stage 300 of the gate driver 200 may receive a first clock signal to an Mth clock signal. In an embodiment, for example, the control circuit may receive one of the first clock signal to the Mth clock signal, and the first gate output circuit to the (M-1)th gate output circuit may respectively receive a clock signal from the first clock signal to the Mth clock signal that is different from the clock signal received by the control circuit. For ease of description, the embodiment where M is 4 will be described primarily as an example below, but it is not limited thereto. In another embodiment, for example, M may be 3.

[0074] Each stage 300 of the gate driver 200 according to an embodiment of the present invention may include a control circuit 310 and gate output circuits 320, 330, and 340. Here, stage 300 may be the Nth stage. Here, N is a positive integer greater than or equal to 1.

[0075] The control circuit 310 can receive the input signal IN[N] in response to the fourth clock signal CLK4. The input signal IN[N] can be the gate start signal FLM or the previous gate signal GS[3N-3]. The control circuit 310 can control the voltage VNQ of the control node and the voltage VNQB of the inverting control node based on the input signal IN[N].

[0076] Gate output circuits 320, 330, and 340 can receive clock signals CLK1, CLK2, and CLK3 in response to the voltage VNQ of the control node and the voltage VNQB of the inverting control node. Gate output circuits 320, 330, and 340 can sequentially generate and output clock signals CLK1, CLK2, and CLK3 as gate signals GS[3N-2], GS[3N-1], and GS[3N]. In this embodiment, the gate signal GS[3N] can also be referred to as the (M-1)th gate signal. Here, the clock signals CLK1, CLK2, and CLK3 received by gate output circuits 320, 330, and 340 may be different from the clock signal CLK4 received by control circuit 310.

[0077] In an embodiment, for example, gate output circuits 320, 330, and 340 may include a first gate output circuit 320, a second gate output circuit 330, and a third gate output circuit 340. The first gate output circuit 320 may generate a first clock signal CLK1 as a first gate signal GS[3N-2] in response to the voltage VNQ of the control node and the voltage VNQB of the inverting control node. The second gate output circuit 330 may generate a second clock signal CLK2 as a second gate signal GS[3N-1] in response to the voltage VNQ of the control node and the voltage VNQB of the inverting control node. The third gate output circuit 340 may generate a third clock signal CLK3 as a third gate signal GS[3N] in response to the voltage VNQ of the control node and the voltage VNQB of the inverting control node.

[0078] In this implementation, since the gate output circuits 320, 330, and 340 share the control circuit 310, the number of transistors and signal lines in each stage 300 can be reduced, and the dead zone and power consumption of the display device 100 can be reduced.

[0079] Figure 6 It is shown Figure 3 Circuit diagram of implementation 300A of gate driver 200 stage 300.

[0080] refer to Figures 1 to 6 Each stage 300A implementation may include a control circuit 310A and gate output circuits 320A, 330A, and 340A. The control circuit 310A may receive a fourth clock signal CLK4. The gate output circuits 320A, 330A, and 340A may receive clock signals CLK1, CLK2, and CLK3, which are different from the fourth clock signal CLK4.

[0081] The control circuit 310A can receive the input signal IN[N] in response to the fourth clock signal CLK4, and can control the voltage VNQ of control nodes NQ1, NQ2, NQ3, and NQ4 and the voltage VNQB of the inverting control node NQB based on the input signal IN[N]. The input signal IN[N] can be the gate start signal FLM or the previous gate signal GS[3N-3].

[0082] The control circuit 310A may include a first transistor T1, a second transistor T2, and a third transistor T3. The control circuit 310A may also include a fourth transistor T4. The control circuit 310A may also include a fifth transistor T5.

[0083] The first transistor T1 may include a gate electrode that receives the fourth clock signal CLK4, a first electrode that receives the input signal IN[N], and a second electrode that is connected to control nodes NQ1, NQ2, NQ3, and NQ4.

[0084] The second transistor T2 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode.

[0085] The third transistor T3 may include a gate electrode for receiving the control clock signal CCLK, a first electrode connected to control nodes NQ1, NQ2, NQ3, and NQ4, and a second electrode connected to the second electrode of the second transistor T2. In an embodiment, the control clock signal CCLK may be different from the fourth clock signal CLK4, and may be one of the clock signals CLK1, CLK2, and CLK3 received by the gate output circuits 320A, 330A, and 340A.

[0086] The fourth transistor T4 may include a gate electrode connected to control nodes NQ1, NQ2, NQ3, and NQ4, a first electrode receiving the fourth clock signal CLK4, and a second electrode connected to the inverting control node NQB.

[0087] The fifth transistor T5 may include a gate electrode that receives the fourth clock signal CLK4, a first electrode that receives a low gate voltage VGL, and a second electrode that is connected to the inverting control node NQB.

[0088] In response to the voltage VNQ of control nodes NQ1, NQ2, NQ3, and NQ4 and the voltage VNQB of the inverting control node NQB, gate output circuits 320A, 330A, and 340A can receive clock signals CLK1, CLK2, and CLK3. Gate output circuits 320A, 330A, and 340A can sequentially generate clock signals CLK1, CLK2, and CLK3 as gate signals GS[3N-2], GS[3N-1], and GS[3N]. In some embodiments, for example, gate output circuits 320A, 330A, and 340A may include a first gate output circuit 320A, a second gate output circuit 330A, and a third gate output circuit 340A. In some embodiments, for example, control nodes NQ1, NQ2, NQ3, and NQ4 may include a first control node NQ1, a second control node NQ2, a third control node NQ3, and a fourth control node NQ4.

[0089] The first gate output circuit 320A may include a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2. The first gate output circuit 320A may also include an eighth transistor T8.

[0090] The sixth transistor T6 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the first gate output node NGS1. The first gate signal GS[3N-2] may be output from the first gate output node NGS1.

[0091] The seventh transistor T7 may include a gate electrode connected to the second control node NQ2, a first electrode receiving the first clock signal CLK1, and a second electrode connected to the first gate output node NGS1.

[0092] The first capacitor C1 may include a first electrode that receives a high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0093] The second capacitor C2 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the first gate output node NGS1.

[0094] The eighth transistor T8 may include a gate electrode that receives a low gate voltage VGL, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2. Since the eighth transistor T8 turns on in response to the low gate voltage VGL, the eighth transistor T8 may be an normally-on transistor (AOT).

[0095] The second gate output circuit 330A may include a ninth transistor T9, a tenth transistor T10, and a fourth capacitor C4. The second gate output circuit 330A may also include a third capacitor C3. The second gate output circuit 330A may also include an eleventh transistor T11.

[0096] The ninth transistor T9 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the second gate output node NGS2. The second gate signal GS[3N-1] may be output from the second gate output node NGS2.

[0097] The tenth transistor T10 may include a gate electrode connected to the third control node NQ3, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the second gate output node NGS2.

[0098] The third capacitor C3 may include a first electrode that receives a high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0099] The fourth capacitor C4 may include a first electrode connected to the third control node NQ3 and a second electrode connected to the second gate output node NGS2.

[0100] The eleventh transistor T11 may include a gate electrode that receives a low gate voltage VGL, a first electrode connected to the first control node NQ1, and a second electrode connected to the third control node NQ3. Since the eleventh transistor T11 turns on in response to the low gate voltage VGL, the eleventh transistor T11 may be a normally-on transistor.

[0101] The third gate output circuit 340A may include a twelfth transistor T12, a thirteenth transistor T13, and a sixth capacitor C6. The third gate output circuit 340A may also include a fifth capacitor C5. The third gate output circuit 340A may also include a fourteenth transistor T14.

[0102] The twelfth transistor T12 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the third gate output node NGS3. The third gate signal GS[3N] can be output from the third gate output node NGS3.

[0103] The thirteenth transistor T13 may include a gate electrode connected to the fourth control node NQ4, a first electrode receiving the third clock signal CLK3, and a second electrode connected to the third gate output node NGS3.

[0104] The fifth capacitor C5 may include a first electrode that receives a high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0105] The sixth capacitor C6 may include a first electrode connected to the fourth control node NQ4 and a second electrode connected to the third gate output node NGS3.

[0106] The fourteenth transistor T14 may include a gate electrode that receives a low gate voltage VGL, a first electrode connected to the first control node NQ1, and a second electrode connected to the fourth control node NQ4. Since the fourteenth transistor T14 turns on in response to the low gate voltage VGL, the fourteenth transistor T14 may be a normally-on transistor.

[0107] In one embodiment, the first transistor T1 through the fourteenth transistor T14 can be P-type transistors. For example, in another embodiment, the P-type transistor can be a PMOS transistor.

[0108] Figure 7 It is shown Figure 3 A circuit diagram of another embodiment 300B of the gate driver 200 stage 300.

[0109] refer to Figures 1 to 7 , Figure 7 Class 300B and Figure 6The stage 300A is essentially the same, except that the gate electrode of the fourth transistor T4 receives the input signal IN[N], the first electrode of the fourth transistor T4 receives the third gate signal GS[3N], and the gate electrode of the fifth transistor T5 receives the third gate signal GS[3N]. Therefore, the same reference numerals are used for the same or similar components, and any repeated detailed descriptions thereof will be omitted.

[0110] In the implementation of level 300B, such as Figure 7 As shown, the fourth transistor T4 may include a gate electrode that receives the input signal IN[N], a first electrode that receives the third gate signal GS[3N], and a second electrode connected to the inverting control node NQB.

[0111] The fifth transistor T5 may include a gate electrode that receives the third gate signal GS[3N], a first electrode that receives the low gate voltage VGL, and a second electrode that is connected to the inverting control node NQB.

[0112] Figure 8 It is shown Figure 3 A circuit diagram of another embodiment 300C of the gate driver 200 stage 300.

[0113] refer to Figures 1 to 5 and Figure 8 Each stage 300C may include a control circuit 310C and gate output circuits 320C, 330C, and 340C. The control circuit 310C may receive a fourth clock signal CLK4. The gate output circuits 320C, 330C, and 340C may receive clock signals CLK1, CLK2, and CLK3, which are different from the fourth clock signal CLK4.

[0114] The control circuit 310C can receive the input signal IN[N] in response to the fourth clock signal CLK4, and can control the voltage VNQ of control nodes NQ1, NQ2, NQ3, and NQ4 and the voltage VNQB of the inverting control node NQB based on the input signal IN[N]. The input signal IN[N] can be the gate start signal FLM or the previous gate signal GS[3N-3].

[0115] The control circuit 310C may include a first transistor T1, a second transistor T2, and a third transistor T3.

[0116] The first transistor T1 may include a gate electrode that receives the fourth clock signal CLK4, a first electrode that receives the input signal IN[N], and a second electrode that is connected to control nodes NQ1, NQ2, NQ3, and NQ4.

[0117] The second transistor T2 may include a gate electrode connected to control nodes NQ1, NQ2, NQ3, and NQ4, a first electrode receiving a high gate voltage VGH, and a second electrode.

[0118] The third transistor T3 may include a gate electrode connected to control nodes NQ1, NQ2, NQ3, and NQ4, a first electrode receiving a low gate voltage VGL, and a second electrode connected to the second electrode of the second transistor T2.

[0119] Gate output circuits 320C, 330C, and 340C can receive clock signals CLK1, CLK2, and CLK3 in response to the voltages VNQ of control nodes NQ1, NQ2, NQ3, and NQ4 and the voltage VNQB of the inverting control node NQB. Gate output circuits 320A, 330A, and 340A can sequentially generate clock signals CLK1, CLK2, and CLK3 as gate signals GS[3N-2], GS[3N-1], and GS[3N]. In an embodiment, for example, gate output circuits 320C, 330C, and 340C may include a first gate output circuit 320C, a second gate output circuit 330C, and a third gate output circuit 340C. In an embodiment, for example, control nodes NQ1, NQ2, NQ3, and NQ4 may include a first control node NQ1, a second control node NQ2, a third control node NQ3, and a fourth control node NQ4.

[0120] The first gate output circuit 320C may include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. The first gate output circuit 320C may also include a sixth transistor T6.

[0121] The fourth transistor T4 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the first gate output node NGS1. The first gate signal GS[3N-2] may be output from the first gate output node NGS1.

[0122] The fifth transistor T5 may include a gate electrode connected to the second control node NQ2, a first electrode receiving the first clock signal CLK1, and a second electrode connected to the first gate output node NGS1.

[0123] The first capacitor C1 may include a first electrode that receives a high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0124] The second capacitor C2 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the first gate output node NGS1.

[0125] The sixth transistor T6 may include a gate electrode that receives a low gate voltage VGL, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2. Since the sixth transistor T6 turns on in response to the low gate voltage VGL, the sixth transistor T6 may be a normally-on transistor.

[0126] The second gate output circuit 330C may include a seventh transistor T7, an eighth transistor T8, and a fourth capacitor C4. The second gate output circuit 330C may also include a third capacitor C3. The second gate output circuit 330C may also include a ninth transistor T9.

[0127] The seventh transistor T7 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the second gate output node NGS2. The second gate signal GS[3N-1] may be output from the second gate output node NGS2.

[0128] The eighth transistor T8 may include a gate electrode connected to the third control node NQ3, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the second gate output node NGS2.

[0129] The third capacitor C3 may include a first electrode that receives a high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0130] The fourth capacitor C4 may include a first electrode connected to the third control node NQ3 and a second electrode connected to the second gate output node NGS2.

[0131] The ninth transistor T9 may include a gate electrode that receives a low gate voltage VGL, a first electrode connected to the second control node NQ2, and a second electrode connected to the third control node NQ3. Since the ninth transistor T9 turns on in response to the low gate voltage VGL, the ninth transistor T9 may be a normally-on transistor.

[0132] The third gate output circuit 340C may include a tenth transistor T10, an eleventh transistor T11, and a sixth capacitor C6. The third gate output circuit 340C may also include a fifth capacitor C5. The third gate output circuit 340C may also include a twelfth transistor T12.

[0133] The tenth transistor T10 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the third gate output node NGS3. The third gate signal GS[3N] may be output from the third gate output node NGS3.

[0134] The eleventh transistor T11 may include a gate electrode connected to the fourth control node NQ4, a first electrode receiving the third clock signal CLK3, and a second electrode connected to the third gate output node NGS3.

[0135] The fifth capacitor C5 may include a first electrode that receives a high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0136] The sixth capacitor C6 may include a first electrode connected to the fourth control node NQ4 and a second electrode connected to the third gate output node NGS3.

[0137] The twelfth transistor T12 may include a gate electrode that receives a low gate voltage VGL, a first electrode connected to the third control node NQ3, and a second electrode connected to the fourth control node NQ4. Since the twelfth transistor T12 turns on in response to the low gate voltage VGL, the twelfth transistor T12 may be a normally-on transistor.

[0138] In one embodiment, the first transistor T1, the second transistor T2, and the fourth transistors T4 through T12 can be P-type transistors, and the third transistor T3 can be an N-type transistor. In another embodiment, for example, the P-type transistor can be a PMOS transistor. In yet another embodiment, for example, the N-type transistor can be an NMOS transistor.

[0139] Figure 9 This is a block diagram illustrating an embodiment of the electronic device 1000. Figure 10 It shows that Figure 9 The diagram illustrates an implementation of the electronic device 1000 as a smartphone.

[0140] refer to Figure 9 and Figure 10 Implementations of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 100. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0141] In the implementation method, such as Figure 10As shown, the electronic device 1000 can be implemented as a smartphone. However, the electronic device 1000 is not limited to this. In embodiments, for example, the electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet computer, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device, etc.

[0142] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0143] The memory device 1020 can store data for the operation of the electronic device 1000. In embodiments, for example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile (DRAM) device, and the like.

[0144] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, CD-ROM devices, etc.

[0145] I / O device 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, touchscreen, etc., and output devices such as a printer, speaker, etc. In some embodiments, I / O device 1040 may include display device 1060.

[0146] The power supply 1050 can provide power for the operation of the electronic device 1000.

[0147] The display device 1060 can be connected to other components via a bus or other communication link.

[0148] The embodiments of this utility model can be applied to any display device and any electronic device including the display device, such as mobile phones, smartphones, tablet computers, digital televisions (TV), 3D televisions, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0149] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0150] Although the present invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made in the embodiments without departing from the spirit or scope of the present invention as defined by the appended claims.

Claims

1. A gate driver comprising multiple stages, characterized in that, Each of the stages includes a control circuit and gate output circuits from the first to the (M-1)th gate output circuits, wherein each of the stages receives a first clock signal, a second clock signal to the (M-1)th clock signal, and the Mth clock signal, respectively, where M is a positive integer greater than or equal to 3. The control circuit receives an input signal in response to one of the first to the Mth clock signals, and controls the voltage of the control node and the voltage of the inverting control node based on the input signal. The first gate output circuit to the (M-1)th gate output circuit, in response to the voltage of the control node and the voltage of the inverting control node, sequentially outputs the first clock signal to the (M)th clock signal, which is different from the first clock signal to the (M)th clock signal received by the control circuit, as the first gate signal, the second gate signal to the (M-1)th gate signal.

2. The gate driver according to claim 1, characterized in that, The first clock signal to the Mth clock signal is the Mth clock signal, and The control circuit includes: The first transistor includes a gate electrode for receiving the Mth clock signal, a first electrode for receiving the input signal, and a second electrode connected to the control node; The second transistor includes a gate electrode connected to the inverting control node, a first electrode receiving a high gate voltage, and a second electrode; and The third transistor includes a gate electrode for receiving a control clock signal, a first electrode connected to the control node, and a second electrode connected to the second electrode of the second transistor.

3. The gate driver according to claim 2, characterized in that, The control clock signal is one of the first clock signal to the (M-1)th clock signal.

4. The gate driver according to claim 2, characterized in that, The control circuit also includes: The fourth transistor includes a gate electrode connected to the control node, a first electrode that receives the Mth clock signal, and a second electrode connected to the inverting control node.

5. The gate driver according to claim 4, characterized in that, The control circuit also includes: The fifth transistor includes a gate electrode for receiving the Mth clock signal, a first electrode for receiving a low gate voltage, and a second electrode connected to the inverting control node.

6. The gate driver according to claim 2, characterized in that, The control circuit also includes: The fourth transistor includes a gate electrode for receiving the input signal, a first electrode for receiving the (M-1)th gate signal, and a second electrode connected to the inverting control node.

7. The gate driver according to claim 6, characterized in that, The control circuit also includes: The fifth transistor includes a gate electrode for receiving the (M-1)th gate signal, a first electrode for receiving a low gate voltage, and a second electrode connected to the inverting control node.

8. The gate driver according to claim 2, characterized in that, The first gate output circuit includes: The sixth transistor includes a gate electrode connected to the inverting control node, a first electrode receiving the high gate voltage, and a second electrode connected to the first gate output node, wherein the first gate signal is output from the first gate output node; The seventh transistor includes a gate electrode connected to the control node, a first electrode receiving the first clock signal, and a second electrode connected to the first gate output node; A first capacitor includes a first electrode receiving the high gate voltage and a second electrode connected to the inverting control node; and The second capacitor includes a first electrode connected to the control node and a second electrode connected to the first gate output node, and The second gate output circuit in the first gate output circuit to the (M-1)th gate output circuit includes: The ninth transistor includes a gate electrode connected to the inverting control node, a first electrode receiving the high gate voltage, and a second electrode connected to the second gate output node, wherein the second gate signal is output from the second gate output node; The tenth transistor includes a gate electrode connected to the control node, a first electrode receiving the second clock signal, and a second electrode connected to the second gate output node; and The fourth capacitor includes a first electrode connected to the control node and a second electrode connected to the second gate output node.

9. The gate driver according to claim 8, characterized in that, The control nodes include a first control node, a second control node, and a third control node, and The first gate output circuit further includes: The eighth transistor includes a gate electrode that receives a low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

10. The gate driver according to claim 9, characterized in that, The second gate output circuit also includes: The eleventh transistor includes a gate electrode that receives the low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the third control node.

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