Display panel and electronic device comprising the same

Abstract

The present application provides a display panel and an electronic device including the same. The display panel includes a pixel including a pixel circuit and a light emitting diode, a data line configured to provide a data signal to the pixel, a gate line configured to provide a gate signal to the pixel, and a power supply line configured to provide a power supply signal to the pixel. The pixel circuit includes a driving transistor, a switching transistor, a compensation transistor, and a sub-compensation transistor. The sub-compensation transistor is configured to transfer a compensation signal to a sub-control electrode of the driving transistor, and is configured to be controlled by the same signal as the compensation transistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0104872, filed on August 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a display panel and an electronic device including the display panel, and more specifically, to a display panel and an electronic device including the display panel designed to improve image quality at low gray levels by changing the threshold voltage of the driving transistor. Background Technology

[0004] Display devices typically include a display panel, signal control circuitry, gate drive circuitry, data drive circuitry, and transmission control circuitry. The display panel typically includes multiple gate lines, multiple data lines, and multiple pixels connected to the gate lines and data lines.

[0005] Each of the plurality of pixels may include pixel circuitry and a light-emitting diode (LED). The pixel circuitry may include a drive transistor that controls the current flowing through the LED. The brightness of the light emitted from the LED corresponds to the current flowing through the LED.

[0006] The threshold voltage of the driving transistor may vary depending on temperature. When the threshold voltage changes, the current flowing through the LED and the brightness of the light emitted from the LED may also change. Utility Model Content

[0007] Embodiments of this disclosure provide a display panel configured to improve image quality at low gray levels by changing the threshold voltage of a driving transistor, and an electronic device including the display panel.

[0008] A display panel according to embodiments of the present disclosure may include pixels, data lines, gate lines, and power lines. Each pixel may include pixel circuitry and a light-emitting diode (LED). Data lines may be configured to provide data signals to the pixel. Gate lines may be configured to provide gate signals to the pixel. Power lines may be configured to provide power signals to the pixel. Pixel circuitry may include a driving transistor, a switching transistor, a compensation transistor, and a sub-compensation transistor. The driving transistor may be electrically connected to the LED. The driving transistor may include an input electrode, an output electrode, a control electrode, and a sub-control electrode. The switching transistor may be configured to be controlled by a gate signal and may be disposed between the data line and the driving transistor. The compensation transistor may be disposed between the output electrode and the control electrode of the driving transistor. The sub-compensation transistor may be configured to transmit a compensation signal to the sub-control electrode of the driving transistor. The sub-compensation transistor may be configured to be controlled by the same signal as the compensation transistor.

[0009] In embodiments of this disclosure, the voltage value of the compensation signal can be greater than the voltage value of the power supply signal. In embodiments of this disclosure, the voltage value of the compensation signal can decrease when the ambient temperature decreases.

[0010] The display panel according to embodiments of this disclosure may further include an emission control line. The pixel circuit may further include a first emission transistor, a second emission transistor, and an emission compensation transistor. The emission control line may be configured to provide an emission control signal to the pixel. The first emission transistor may be configured to be controlled by the emission control signal and may be disposed between the power supply line and the driving transistor. The second emission transistor may be configured to be controlled by the emission control signal and may be disposed between the driving transistor and the light-emitting diode. The emission compensation transistor may be configured to be controlled by the emission control signal and may be disposed between the power supply line and the secondary control electrode of the driving transistor.

[0011] In embodiments of this disclosure, the pixel circuit may further include a capacitor. The capacitor may be disposed between the power supply line and the compensation transistor.

[0012] The display panel according to embodiments of this disclosure may further include a first initialization line. The pixel circuit may further include a first initialization transistor. The first initialization line may be configured to provide a first initialization signal to the pixel. The first initialization transistor may be disposed between the first initialization line and the control electrode of the driving transistor. The first initialization transistor may be configured to conduct simultaneously with a compensation transistor for a predetermined time period.

[0013] The display panel according to embodiments of this disclosure may further include a second initialization line. The pixel circuitry may further include a second initialization transistor. The second initialization line may be configured to provide a second initialization signal to the pixel. The second initialization transistor may be disposed between the second initialization line and a light-emitting diode (LED). The second initialization transistor may be configured to transmit the second initialization signal to the LED.

[0014] The display panel according to embodiments of this disclosure may further include bias signal lines. The pixel circuitry may further include bias transistors. The bias signal lines may be configured to provide bias signals to the pixels. The bias transistors may be disposed between the bias signal lines and the driving transistors. The bias transistors may be configured to be controlled by the same signal as the second initialization transistor.

[0015] A display panel according to embodiments of the present disclosure may include pixels, data lines, gate lines, power lines, and emission control lines. Each pixel may include pixel circuitry and a light-emitting diode (LED). Data lines may be configured to provide data signals to the pixel. Gate lines may be configured to provide gate signals to the pixel. Power lines may be configured to provide power signals to the pixel. Emission control lines may be configured to provide emission control signals to the pixel. Pixel circuitry may include a driving transistor, a switching transistor, a first emitting transistor, a second emitting transistor, and an emission compensation transistor. The driving transistor may be electrically connected to the LED. The driving transistor may include an input electrode, an output electrode, a control electrode, and a sub-control electrode. The switching transistor may be configured to be controlled by a gate signal and may be disposed between the data line and the driving transistor. The first emitting transistor may be configured to be controlled by an emission control signal and may be disposed between the power line and the driving transistor. The second emitting transistor may be configured to be controlled by an emission control signal and may be disposed between the driving transistor and the LED. The emission compensation transistor may be configured to be controlled by an emission control signal and may be disposed between the power line and the sub-control electrode of the driving transistor.

[0016] In embodiments of this disclosure, the pixel circuit may further include a compensation transistor and a sub-compensation transistor. The compensation transistor may be disposed between the output electrode and the control electrode of the driving transistor. The sub-compensation transistor may be configured to transmit a compensation signal to the sub-control electrode of the driving transistor. The sub-compensation transistor may be configured to be controlled by the same signal as the compensation transistor.

[0017] In embodiments of this disclosure, the voltage value of the compensation signal can be greater than the voltage value of the power supply signal. In embodiments of this disclosure, the voltage value of the compensation signal can decrease when the ambient temperature decreases. In embodiments of this disclosure, the pixel circuit may further include a capacitor, which can be disposed between the power supply line and the compensation transistor.

[0018] The display panel according to embodiments of this disclosure may further include a first initialization line. The pixel circuit may further include a first initialization transistor. The first initialization line may be configured to provide a first initialization signal to the pixel. The first initialization transistor may be disposed between the first initialization line and the control electrode of the driving transistor. The first initialization transistor may be configured to conduct simultaneously with a compensation transistor for a predetermined time period.

[0019] The display panel according to embodiments of this disclosure may further include a second initialization line. The pixel circuitry may further include a second initialization transistor. The second initialization line may be configured to provide a second initialization signal to the pixel. The second initialization transistor may be disposed between the second initialization line and the light-emitting diode (LED). The second initialization transistor may be configured to transmit the second initialization signal to the LED.

[0020] The display panel according to embodiments of this disclosure may further include bias signal lines. The pixel circuitry may further include bias transistors. The bias signal lines may be configured to provide bias signals to the pixels. The bias transistors may be disposed between the bias signal lines and the driving transistors. The bias transistors may be configured to be controlled by the same signal as the second initialization transistor.

[0021] In embodiments of this disclosure, the voltage value of the data signal can be in the range of about 0.5V to about 6.8V. The voltage value of the bias signal can be in the range of about 5.0V to about 6.0V. The voltage value of the power supply signal can be in the range of about 4.1V to about 5.1V. The voltage value of the first initialization signal can be in the range of about -3.0V to about -2.0V. The voltage value of the second initialization signal can be in the range of about -1.9V to about -0.5V.

[0022] The display panel according to embodiments of this disclosure may include a metal pattern, a first semiconductor pattern, a first conductive pattern, a second conductive pattern, a second semiconductor pattern, and a third conductive pattern. The metal pattern may include a first lower sub-electrode portion. The first semiconductor pattern may be disposed on the metal pattern and may include a first lower semiconductor portion, a second lower semiconductor portion, a third lower semiconductor portion, and a fourth lower semiconductor portion. The first lower semiconductor portion may overlap with the first lower sub-electrode portion. The second lower semiconductor portion may extend from one end of the first lower semiconductor portion, and the third lower semiconductor portion may extend from the other end of the first lower semiconductor portion. The fourth lower semiconductor portion may be spaced apart from the second lower semiconductor portion. The first conductive pattern may be disposed on the first semiconductor pattern and may include a first lower electrode portion, a second lower electrode portion, a third lower electrode portion, and a fourth lower electrode portion. The first lower electrode portion may overlap with the first lower semiconductor portion, and the second lower electrode portion may be spaced apart from the first lower electrode portion. The second lower electrode portion may overlap with the second lower semiconductor portion. The third lower electrode portion may extend from one end of the second lower electrode portion and overlap with the third lower semiconductor portion. The fourth lower electrode portion may extend from the other end of the second lower electrode portion and overlap with the fourth lower semiconductor portion.

[0023] A second conductive pattern may be disposed on the first conductive pattern and may include a first upper sub-electrode portion. The first upper sub-electrode portion may overlap with a first lower electrode portion. A second semiconductor pattern may be disposed on the second conductive pattern and may include a first upper semiconductor portion and a second upper semiconductor portion. The second upper semiconductor portion may be spaced apart from the first upper semiconductor portion. A third conductive pattern may be disposed on the second semiconductor pattern and may include a first upper electrode portion and a second upper electrode portion. The first upper electrode portion may overlap with the first upper semiconductor portion, and the second upper electrode portion may overlap with the second upper semiconductor portion. The second upper electrode portion may extend from one end of the first upper electrode portion.

[0024] The display panel according to embodiments of this disclosure may further include a connection electrode pattern. The connection electrode pattern may be disposed on a third conductive pattern. The connection electrode pattern may include a first connection electrode, a second connection electrode, and a third connection electrode. The first connection electrode may contact a first lower electrode portion through a first contact hole and a second upper semiconductor portion through a second contact hole. The second connection electrode may contact a fourth lower semiconductor portion through a third contact hole and a first lower sub-electrode portion through a fourth contact hole. The third connection electrode may contact the first upper semiconductor portion through a fifth contact hole and a first lower sub-electrode portion through a sixth contact hole.

[0025] In embodiments of this disclosure, the metal pattern may further include a second lower sub-electrode portion and a third lower sub-electrode portion. The connecting electrode pattern may further include a fourth connecting electrode and a fifth connecting electrode. The fourth connecting electrode may contact the first upper semiconductor portion through a seventh contact hole and contact the third lower sub-electrode portion through an eighth contact hole. The fifth connecting electrode may contact the second lower sub-electrode portion through a ninth contact hole and contact the fourth lower semiconductor portion through a tenth contact hole.

[0026] According to embodiments of this disclosure, an electronic device includes: a processor; a memory storing applications executed by the processor; a display device; and a user interface. The display device may include the display panel described above. The user interface may be configured to sense user input via touch or cursor selection of icons presented on the display panel. Upon receiving user input, the processor may be prompted to execute one or more of the stored applications.

[0027] In embodiments of this disclosure, the stored applications may include one or more of camera applications, streaming applications, and telephone applications.

[0028] In embodiments of this disclosure, the user interface may be a touchscreen embedded in a display panel, wherein the touchscreen may include a touch sensor for sensing touches or taps made by the user.

[0029] According to embodiments of this disclosure, by changing the threshold voltage of the driving transistor, a display panel capable of improving image quality at low grayscale levels and an electronic device including the display panel can be provided. Attached Figure Description

[0030] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0032] Figure 2A This is an exemplary equivalent circuit diagram of pixels according to an embodiment of the present disclosure;

[0033] Figure 2B The diagram shows the part from... Figure 2A An exemplary equivalent circuit diagram of pixels with emission compensation transistors omitted in the diagram is shown.

[0034] Figure 2C The diagram shows the part from... Figure 2A An exemplary equivalent circuit diagram of pixels in the diagram, omitting the sub-compensation transistor;

[0035] Figure 2D This is a waveform diagram illustrating the signal provided to a display device according to an embodiment of the present disclosure;

[0036] Figure 3 This is a plan view illustrating the layout of a pixel circuit according to an embodiment of the present disclosure;

[0037] Figures 4A to 4G It is a plan view of any one of the multiple patterns;

[0038] Figures 5A to 5F The diagram shows the components stacked sequentially according to the manufacturing process. Figures 4A to 4G An exemplary diagram of the shapes of at least some of the patterns in the diagram;

[0039] Figure 6A This is an exemplary equivalent circuit diagram of pixels according to an embodiment of the present disclosure;

[0040] Figure 6B This is a waveform diagram illustrating the signal provided to a pixel of a display device according to an embodiment of the present disclosure; and

[0041] Figure 7 This is a diagram illustrating an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0042] Embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. Throughout the accompanying drawings, the same reference numerals may refer to the same elements.

[0043] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and these elements are not limited by these terms. Thus, an “first” element in one embodiment may be described as a “second” element in another embodiment.

[0044] It should be understood that the descriptions of features or aspects within the various embodiments should generally be considered applicable to other similar features or aspects in other embodiments, unless the context clearly indicates otherwise.

[0045] As used herein, the singular forms “a” and “the (said)” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0046] For ease of explanation, spatial relative terms such as “below,” “under,” “down,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation, other than those depicted in the figures. For example, if the device in the figures is flipped, the element described as “below,” “under,” or “below” other elements or features will then be oriented “above” other elements or features. Therefore, the example terms “below” and “below” can encompass both above and below orientations.

[0047] It will be understood that when a component is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, it can be directly on, directly connected to, directly coupled to, or directly adjacent to that other component, or there can be intermediary components. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between those two components, or there can be one or more intermediary components. It will also be understood that when a component is referred to as "covering" another component, it can be the only component covering that other component, or one or more intermediary components can also cover that other component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0048] In this document, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it should be understood that these elements or values ​​are the same, equal to each other within measurement error, or, if not equal in a measurable degree, sufficiently close in value to be functionally equal, as understood by one of ordinary skill in the art. For example, taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the term “about” as used herein includes the stated value and means within an acceptable deviation of a particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations as understood by one of ordinary skill in the art, such as within ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, it should be understood that while a parameter may be described herein as having a “about” specific value, according to embodiments, the parameter may precisely have that specific value or approximately have that specific value within measurement error, as understood by one of ordinary skill in the art. Other uses of these terms and similar terms to describe relationships between components should be interpreted in a similar manner.

[0049] Expressions such as “comprising” or “including” are intended to specify a characteristic, quantity, step, operation, element, part, or combination thereof, and should not be construed as excluding any possibility of the presence or addition of one or more other characteristics, quantities, steps, operations, elements, parts, or combinations thereof.

[0050] When something is described as “outputting” to a component, it should be interpreted as outputting directly to that component, but it can also be interpreted as outputting via another component. On the other hand, if something is described as “directly outputting” to a component, it should be interpreted as the output not being made via another component. Furthermore, when a component is described as being “on” a component, it should be understood that the component is located above or below the component, and not necessarily above the component in the direction of gravity.

[0051] Embodiments of this disclosure relate to a display device capable of improving image quality at low grayscale levels by compensating for threshold voltage variations in the driving transistor. These threshold voltage variations, which may be caused by fluctuations in ambient temperature, can lead to unexpected changes in the current flowing through the light-emitting diode, resulting in inconsistent brightness and degraded display performance. To address this problem, the display device according to the embodiments can utilize a compensation mechanism that dynamically adjusts the voltage at the secondary control electrode of the driving transistor, which can stabilize its operating characteristics and prevent or reduce unwanted brightness fluctuations.

[0052] Embodiments of this application may utilize compensation transistors, including a sub-compensation transistor and an emitter compensation transistor, which can work together to calibrate the threshold voltage of the driving transistor. The compensation signal can be adjusted based on temperature changes to counteract deviations in the electrical properties of the driving transistor and to provide a consistent drive current to the light-emitting diode. Furthermore, a temperature sensor can detect changes in ambient temperature in real time, enabling precise compensation adjustments. This method effectively mitigates the effects of leakage current and improves the black level performance of the display device, thereby reducing unintended emissions in dark image areas.

[0053] By implementing the above compensation techniques, embodiments of this disclosure can provide stable image quality under varying environmental conditions, such as at low gray levels where brightness inconsistencies are most pronounced.

[0054] Figure 1 This is a block diagram of a display device DD according to an embodiment of the present disclosure. Figure 2A This is an exemplary equivalent circuit diagram of a pixel PX according to an embodiment of the present disclosure. Figure 2B The diagram shows the part from... Figure 2A An exemplary equivalent circuit diagram of pixel PX-1, in which the emitter compensation transistor TRL is omitted, is shown in the pixel PX diagram. Figure 2C The diagram shows the part from... Figure 2A An exemplary equivalent circuit diagram of pixel PX-2, in which the sub-compensation transistor TRS is omitted, is shown in pixel PX.

[0055] refer to Figure 1 The display device DD according to the embodiments of the present disclosure may include a display panel DP, a signal control circuit SCC, a gate drive circuit GDC, a data drive circuit DDC, and an emission control circuit ECC.

[0056] refer to Figure 2A , Figure 2B and Figure 2C The display panel DP may include a data line DL, a power line PL, a first gate line GL1, a second gate line GL2, a third gate line GL3, a first initialization line INL1, a second initialization line INL2, a compensation signal line GCL, an emission control line ECL, a bias signal line BL, and pixels PX, PX-1, or PX-2. Figure 2A , Figure 2B and Figure 2C The pixels PX, PX-1 or PX-2 and each line shown in the figure can be provided as multiple (strips).

[0057] The data line DL can be configured to provide the data signal DS to the pixel PX. The power line PL can be configured to provide the first power signal ELVDD to the pixel PX. The first gate line GL1 can be configured to provide the first gate signal GW to the pixel PX. The second gate line GL2 can be configured to provide the second gate signal GI to the pixel PX. The third gate line GL3 can be configured to provide the third gate signal GB to the pixel PX.

[0058] The first initialization line INL1 can be configured to provide the first initialization signal VINT to pixel PX. The second initialization line INL2 can be configured to provide the second initialization signal AINT to pixel PX. The compensation signal line GCL can be configured to provide the compensation control signal GC to pixel PX. The transmit control line ECL can be configured to provide the transmit control signal EM to pixel PX. The bias signal line BL can be configured to provide the bias signal BS to pixel PX.

[0059] The display panel DP according to embodiments of this disclosure can be a light-emitting display panel. For example, the display panel DP can be any one of an organic light-emitting display panel, a quantum dot light-emitting display panel, a micro-LED display panel, a liquid crystal display panel, an electrophoretic display panel, and an electrowetting display panel. The emitting layer of an organic light-emitting display panel can include an organic light-emitting material. Inorganic light-emitting display panels can include quantum dot light-emitting display panels and micro-LED display panels based on inorganic materials. Hereinafter, the display panel DP will be described based on an organic light-emitting display panel. However, embodiments of this disclosure are not limited thereto.

[0060] The signal control circuit SCC (e.g., a timing controller) can be configured to control the gate drive circuit GDC, the data drive circuit DDC, and the transmit control circuit ECC. The signal control circuit SCC can be configured to receive image data and control signals from an external graphics control unit. Control signals may include, for example, a vertical synchronization signal that distinguishes frame intervals, a horizontal synchronization signal that distinguishes line intervals (e.g., a line identification signal), a data enable signal that is high only during segments of output data to indicate segments in which data is received, and a clock signal. The gate drive circuit GDC can be configured to receive control signals from the signal control circuit SCC and provide the gate control signal GS to the pixel PX via multiple gate lines.

[0061] In embodiments of this disclosure, the gate drive circuit (GDC) can be formed simultaneously with the pixel (PX) using a thin-film process. For example, the gate drive circuit (GDC) can be mounted in the form of an oxide semiconductor TFT gate driver circuit (OSG) or an amorphous silicon TFT gate driver circuit (ASG).

[0062] The data drive circuit DDC can be configured to receive control signals from the signal control circuit SCC and provide the data signal DS to the pixel PX via the data line DL. The transmit control circuit ECC can be configured to receive control signals from the signal control circuit SCC and provide the transmit control signal EM to the pixel PX via the transmit control line ECL. In embodiments of this disclosure, the gate drive circuit GDC and the transmit control circuit ECC can be integrated into a single circuit instead of being separated.

[0063] Figure 2A This is an equivalent circuit diagram of pixel PX according to an embodiment of the present disclosure.

[0064] refer to Figure 2A In embodiments of this disclosure, at least one of the second gate line GL2, the first initialization line INL1, the second initialization line INL2, the compensation signal line GCL, the third gate line GL3, and the bias signal line BL may be omitted.

[0065] In embodiments of this disclosure, the voltage value of the data signal DS can be between about 0.5V and about 6.8V.

[0066] The voltage value of the first power signal ELVDD can be between approximately 4.1V and approximately 5.1V. For example, the voltage value of the first power signal ELVDD can be approximately 4.6V. However, the voltage value of the first power signal ELVDD is not limited to the description herein and can be adjusted according to embodiments of this disclosure.

[0067] The voltage value of the first initialization signal VINT can be between approximately -3.0V and approximately -2.0V. For example, the voltage value of the first initialization signal VINT can be approximately -2.5V. However, the voltage value of the first initialization signal VINT is not limited to this and can be adjusted according to embodiments of the present disclosure.

[0068] In embodiments of this disclosure, the voltage value of the second initialization signal AINT can be between approximately -1.9V and approximately -0.5V. For example, the voltage value of the second initialization signal AINT can be approximately -1.4V. However, the voltage value of the second initialization signal AINT is not limited to this and can be adjusted according to embodiments of this disclosure.

[0069] The voltage value of the third gate signal GB can be between approximately -8.0V and approximately 6.5V. The voltage value of the bias signal BS can be between approximately 5.0V and approximately 6.0V. For example, the voltage value of the bias signal BS can be approximately 5.5V. However, the voltage value of the bias signal BS is not limited to this and can be adjusted according to embodiments of the present disclosure.

[0070] A pixel PX may include a pixel circuit PC and a light-emitting diode (LD). The structure of a pixel PX according to embodiments of this disclosure is not limited to... Figure 2A The structure shown is illustrated. For example, in embodiments of this disclosure, the pixel PX can be implemented in various forms by emitting light from a light-emitting diode (LD).

[0071] The pixel circuit PC can be configured to control the current flowing through the light-emitting diode LD in response to the data signal DS. The pixel circuit PC may include a driving transistor TRD, a switching transistor TRW, a compensation transistor TRC, a secondary compensation transistor TRS, a first emitter transistor TRE1, a second emitter transistor TRE2, an emitter compensation transistor TRL, a capacitor CST, a first initialization transistor TRI1, a second initialization transistor TRI2, and a bias transistor TRB.

[0072] In the pixel circuit PC according to an embodiment of the present disclosure, at least one of the sub-compensation transistor TRS, the first emitter transistor TRE1, the second emitter transistor TRE2, the emitter compensation transistor TRL, the capacitor CST, the first initialization transistor TRI1, the second initialization transistor TRI2, and the bias transistor TRB may be omitted.

[0073] In embodiments of this disclosure, the pixel PX can be a hybrid oxide polysilicon (HOP) pixel suitable for low-frequency driving. That is, the compensation transistor TRC, the sub-compensation transistor TRS, and the first initialization transistor TRI1 can each be an oxide thin-film transistor. Furthermore, the driving transistor TRD, the switching transistor TRW, the first emitter transistor TRE1, the second emitter transistor TRE2, the emitter compensation transistor TRL, the second initialization transistor TRI2, and the bias transistor TRB can each be a low-temperature polysilicon (LTPS) thin-film transistor.

[0074] In embodiments of this disclosure, the driving transistor TRD, the switching transistor TRW, the first emitter transistor TRE1, the second emitter transistor TRE2, the emitter compensation transistor TRL, the second initialization transistor TRI2, and the bias transistor TRB can each be an NMOS transistor or a PMOS transistor. The compensation transistor TRC, the sub-compensation transistor TRS, and the first initialization transistor TRI1 can each be other types of transistors (e.g., if the first set of transistors is NMOS, then the second set of transistors is PMOS, and vice versa). However, this disclosure is not limited thereto. For example, according to embodiments of this disclosure, the pixel PX can be configured with various combinations of NMOS transistors and PMOS transistors.

[0075] A driving transistor TRD can be configured to control the current flowing through a light-emitting diode (LED) LD in response to a voltage applied to a control electrode. The driving transistor TRD can be electrically connected to the LED LD. The driving transistor TRD may include an input electrode, an output electrode, a control electrode, and a secondary control electrode. The input electrode can be one of a source electrode and a drain electrode, and the output electrode can be the other of a source electrode and a drain electrode. The control electrode can be a gate electrode. The secondary control electrode can be a back gate electrode. When a predetermined signal is applied to the secondary control electrode, the threshold voltage of the driving transistor TRD can be changed.

[0076] The switching transistor TRW can be configured to be controlled by a first gate signal GW. The switching transistor TRW can be positioned between the data line DL and the driving transistor TRD. The switching transistor TRW can be configured to be turned on by the first gate signal GW to transmit at least a portion of the data signal DS to the input electrode of the driving transistor TRD.

[0077] The compensation transistor TRC can be positioned between the output electrode and the control electrode of the driving transistor TRD. The compensation transistor TRC can be configured to be controlled by the compensation control signal GC. When the compensation transistor TRC is turned on by the compensation control signal GC, the driving transistor TRD can be connected by a diode, thereby allowing its threshold voltage to be compensated.

[0078] The secondary compensation transistor TRS can be configured to transmit the compensation signal VCP to the secondary control electrode of the driving transistor TRD. The secondary compensation transistor TRS can be configured to be controlled by the same signal as the compensation transistor TRC. That is, the secondary compensation transistor TRS and the compensation transistor TRC are controlled by the same signal. The secondary compensation transistor TRS can be configured to be turned on by the compensation control signal GC to transmit the compensation signal VCP to the secondary control electrode of the driving transistor TRD. When the compensation signal VCP is applied to the secondary control electrode of the driving transistor TRD, the threshold voltage of the driving transistor TRD can be changed.

[0079] The threshold voltage of the driving transistor TRD can vary depending on the ambient temperature. That is, depending on the ambient temperature, the current flowing through the light-emitting diode (LD) may be more or less than expected, thus affecting brightness. For example, in the case where the driving transistor TRD is a PMOS transistor, an increase in ambient temperature typically reduces the absolute value of its threshold voltage, leading to an increase in the current flowing through the LD. As a result, the image quality of the display panel may degrade at low grayscale levels due to unexpected brightness changes.

[0080] In embodiments of this disclosure, the voltage value of the compensation signal VCP can decrease when the ambient temperature decreases. In embodiments of this disclosure, the voltage value of the compensation signal VCP can increase when the ambient temperature increases. By changing the voltage value of the compensation signal VCP according to the ambient temperature, the change in the threshold voltage of the driving transistor TRD according to the ambient temperature can be offset or reduced. Accordingly, the image quality of the display panel can be prevented from deteriorating at low gray levels. In embodiments of this disclosure, the ambient temperature can be detected by a temperature sensor installed in the display device DD. The temperature sensor can be disposed adjacent to the display panel DP to accurately detect temperature changes of the display panel DP.

[0081] For example, in embodiments of this disclosure, the compensation signal VCP is dynamically adjusted in response to changes in ambient temperature, which can mitigate the effects of threshold voltage variations in the driving transistor TRD. For instance, when the ambient temperature decreases, the voltage value of the compensation signal VCP can also decrease, thereby offsetting the increase in the absolute value of the threshold voltage of the driving transistor TRD. Conversely, when the ambient temperature increases, the voltage value of the compensation signal VCP can increase, thereby offsetting the decrease in the absolute value of the threshold voltage of the driving transistor TRD. By continuously adjusting the compensation signal VCP according to temperature fluctuations, the system can stabilize the operating characteristics of the driving transistor TRD, which can prevent or reduce unexpected changes in the current supplied to the light-emitting diode LD. As a result, brightness inconsistencies—for example, those that may degrade image quality at low gray levels—can be effectively minimized or reduced. In embodiments, the ambient temperature can be detected in real time by a temperature sensor disposed adjacent to the display panel DP. This temperature sensor enables accurate detection of temperature changes within the display environment, allowing the compensation mechanism to respond proactively and accurately maintain display performance.

[0082] In embodiments of this disclosure, the voltage value of the compensation signal VCP can be higher than the voltage value of the first power supply signal ELVDD. When the driving transistor TRD is a PMOS transistor, if the voltage value of the compensation signal VCP is higher than the voltage value of the first power supply signal ELVDD, the threshold voltage of the driving transistor TRD may experience a negative offset. That is, the compensation signal VCP can help to offset or reduce changes in the threshold voltage of the driving transistor TRD based on ambient temperature. For example, when the voltage value of the first power supply signal ELVDD is approximately 4.6V, the voltage value of the compensation signal VCP can be greater than approximately 4.6V. However, the voltage value of the compensation signal VCP is not limited to this.

[0083] The first emitter transistor TRE1 can be configured to be controlled by the emitter control signal EM. The first emitter transistor TRE1 can be located between the power supply line PL and the drive transistor TRD. The first emitter transistor TRE1 can be configured to be turned on by the emitter control signal EM to transmit the first power supply signal ELVDD to the input electrode of the drive transistor TRD.

[0084] The second emitting transistor TRE2 can be configured to be controlled by the emitter control signal EM. The second emitting transistor TRE2 can be positioned between the driving transistor TRD and the light-emitting diode LD. The second emitting transistor TRE2 can be configured to be turned on by the emitter control signal EM to electrically connect the output electrode of the driving transistor TRD to the light-emitting diode LD.

[0085] The emitter compensation transistor TRL can be configured to be controlled by the emitter control signal EM. The emitter compensation transistor TRL can be positioned between the power supply line PL and the secondary control electrode of the driving transistor TRD. The emitter compensation transistor TRL can be configured to turn on in response to the emitter control signal EM and transmit a first power supply signal ELVDD to the secondary control electrode of the driving transistor TRD. When the first power supply signal ELVDD is provided to the secondary control electrode of the driving transistor TRD, the threshold voltage of the driving transistor TRD can be changed. That is, the first power supply signal ELVDD can help offset or reduce changes in the threshold voltage of the driving transistor TRD based on ambient temperature.

[0086] For example, in embodiments of this disclosure, the emitter compensation transistor TRL can be configured to calibrate the threshold voltage of the driving transistor TRD by selectively supplying a stable voltage signal to the secondary control electrode of the driving transistor TRD. For example, the emitter compensation transistor TRL can be controlled by an emitter control signal EM and located between the power line PL and the secondary control electrode of the driving transistor TRD. When the emitter compensation transistor TRL is turned on by the emitter control signal EM, it can transmit a first power supply signal ELVDD to the secondary control electrode of the driving transistor TRD, thereby affecting the operating characteristics of the driving transistor TRD. By applying the first power supply signal ELVDD to this secondary control electrode of the driving transistor TRD, the threshold voltage of the driving transistor TRD can be dynamically adjusted to compensate for fluctuations that would otherwise occur due to changes in ambient temperature. As a result, this mechanism can help stabilize the current flowing through the driving transistor TRD, which can prevent unexpected changes in brightness (e.g., preventing unexpected changes in brightness in low grayscale image areas). This compensation technique can allow image quality to remain consistent even when the display device DD operates under varying temperature conditions.

[0087] A capacitor CST can be placed between the power line PL and the compensation transistor TRC. The capacitor CST can be configured to store a charge corresponding to the data signal DS. Based on the amount of charge stored in the capacitor CST, the current flowing through the drive transistor TRD when the first emitter transistor TRE1 and the second emitter transistor TRE2 are turned on can be determined.

[0088] The first initialization transistor TRI1 can be disposed between the first initialization line INL1 and the control electrode of the driving transistor TRD. The first initialization transistor TRI1 can be configured to be controlled by the second gate signal GI. The first initialization transistor TRI1 can be configured to turn on in response to the second gate signal GI and transmit at least a portion of the first initialization signal VINT to the control electrode of the driving transistor TRD.

[0089] The second initialization transistor TRI2 can be disposed between the second initialization line INL2 and the light-emitting diode LD. The second initialization transistor TRI2 can be configured to be controlled by a third gate signal GB. The second initialization transistor TRI2 can be configured to transmit a second initialization signal AINT to the light-emitting diode LD. That is, the second initialization transistor TRI2 can be configured to turn on in response to the third gate signal GB and transmit at least a portion of the second initialization signal AINT to the light-emitting diode LD.

[0090] The second initialization transistor TRI2 can be used to improve the black level performance of pixel PX. When the second initialization transistor TRI2 is turned on, the parasitic capacitance of the light-emitting diode LD can be discharged, thereby reducing the leakage current generated by the driving transistor TRD. As a result, when achieving black brightness, the emission of the light-emitting diode LD due to leakage current can be prevented or reduced, thereby improving the black level performance.

[0091] A bias transistor TRB can be positioned between the bias signal line BL and the drive transistor TRD. The bias transistor TRB can be configured to be controlled by the same signal (i.e., the third gate signal GB) as the second initialization transistor TRI2. That is, the bias transistor TRB can be configured to turn on in response to the third gate signal GB and transmit the bias signal BS to the input electrode of the drive transistor TRD. The bias signal BS helps to keep the drive transistor TRD on for a predetermined time period.

[0092] A light-emitting diode (LD) can be configured to emit light at a predetermined brightness in response to a current supplied by a pixel circuit PC. To achieve this, the voltage value of a first power supply signal ELVDD can be set higher than the voltage value of a second power supply signal ELVSS. One end of the LD can be electrically connected to a second emitting transistor TRE2, and the second power supply signal ELVSS can be applied to the other end of the LD. In embodiments of this disclosure, the voltage value of the second power supply signal ELVSS can be in the range of about -0.9V to about -1.9V. For example, the voltage value of the second power supply signal ELVSS can be about -1.4V. However, the voltage value of the second power supply signal ELVSS is not limited to this. For example, according to embodiments of this disclosure, the LD can be, but is not limited to, an organic light-emitting diode (OLED).

[0093] Figure 2B It is from Figure 2A An exemplary equivalent circuit diagram of pixel PX-1, in which the emitter compensation transistor TRL is omitted, is shown in the pixel PX diagram.

[0094] refer to Figure 2BIn embodiments of this disclosure, at least one of the second gate line GL2, the first initialization line INL1, the second initialization line INL2, the compensation signal line GCL, the third gate line GL3, the transmit control line ECL, and the bias signal line BL may be omitted.

[0095] Pixel PX-1 may include pixel circuit PC-1 and light-emitting diode LD. Pixel circuit PC-1 may include driving transistor TRD, switching transistor TRW, compensation transistor TRC, sub-compensation transistor TRS, first emitter transistor TRE1, second emitter transistor TRE2, capacitor CST, first initialization transistor TRI1, second initialization transistor TRI2, and bias transistor TRB.

[0096] In the pixel circuit PC-1 according to an embodiment of the present disclosure, at least one of the first emitter transistor TRE1, the second emitter transistor TRE2, the capacitor CST, the first initialization transistor TRI1, the second initialization transistor TRI2, and the bias transistor TRB can be omitted. For ease of explanation, references to previous documents have been omitted. Figure 1 and Figure 2A Further description of the components and technologies described.

[0097] Figure 2C It is from Figure 2A An exemplary equivalent circuit diagram of pixel PX-2, in which the sub-compensation transistor TRS is omitted, is shown in pixel PX.

[0098] refer to Figure 2C In embodiments of this disclosure, at least one of the second gate line GL2, the first initialization line INL1, the second initialization line INL2, the compensation signal line GCL, the third gate line GL3, and the bias signal line BL may be omitted.

[0099] Pixel PX-2 may include pixel circuit PC-2 and light-emitting diode LD. Pixel circuit PC-2 may include driving transistor TRD, switching transistor TRW, compensation transistor TRC, first emitter transistor TRE1, second emitter transistor TRE2, emitter compensation transistor TRL, capacitor CST, first initialization transistor TRI1, second initialization transistor TRI2, and bias transistor TRB.

[0100] In the pixel circuit PC-2 according to an embodiment of the present disclosure, at least one of the compensation transistor TRC, capacitor CST, first initialization transistor TRI1, second initialization transistor TRI2, and bias transistor TRB may be omitted. For ease of explanation, references to previous documents have been omitted. Figure 1 and Figure 2A Further description of the components and technologies described.

[0101] Figure 2D This is a waveform diagram illustrating the signals provided to pixels PX, PX-1, and PX-2 according to an embodiment of the present disclosure.

[0102] refer to Figure 2D According to embodiments of the present disclosure, the first initialization transistor TRI1 of pixels PX, PX-1, and PX-2 can be configured to be turned on simultaneously with the compensation transistor TRC during a predetermined time period PR.

[0103] Figure 3 This is a plan view illustrating the layout of the pixel circuit PC-3 according to an embodiment of the present disclosure. The layout of the pixel circuit PC-3 may have multiple superimposed patterns. Figures 4A to 4G Each of the multiple patterns is a plan view. Figures 5A to 5F The diagram shows the components stacked sequentially according to the manufacturing process. Figures 4A to 4G An exemplary diagram of the shapes of at least some of the patterns in the diagram.

[0104] refer to Figures 3 to 4G According to embodiments of the present disclosure, the pixel circuit PC-3 of the display panel DP may include a metal pattern BML, a first semiconductor pattern ACT, a first conductive pattern GAT1, a second conductive pattern GAT2, a second semiconductor pattern OACT, a third conductive pattern GAT3, and a connecting electrode pattern SD.

[0105] Figure 4A This is a flat design of a metal pattern in BML. (Reference) Figure 4A The metal pattern BML may include a first lower sub-electrode portion LSE1, a second lower sub-electrode portion LSE2, and a third lower sub-electrode portion LSE3. In embodiments of this disclosure, at least one of the second lower sub-electrode portion LSE2 and the third lower sub-electrode portion LSE3 may be omitted.

[0106] The second lower sub-electrode portion LSE2 can be electrically connected to the power supply line PL. The third lower sub-electrode portion LSE3 can be electrically connected to the compensation signal line GCL. The second lower sub-electrode portion LSE2 can be configured to provide a first power supply signal ELVDD. The third lower sub-electrode portion LSE3 can be configured to provide a compensation signal VCP. In embodiments of this disclosure, the power supply line PL and the compensation signal line GCL can each be electrically connected to any one of the first conductive pattern GAT1, the second conductive pattern GAT2, and the third conductive pattern GAT3.

[0107] Figure 4B This is a plan view of the first semiconductor pattern ACT. (Reference) Figure 3 and Figure 4BThe first semiconductor pattern ACT may include a first lower semiconductor portion LSC1, a second lower semiconductor portion LSC2, a third lower semiconductor portion LSC3, a fourth lower semiconductor portion LSC4, a fifth lower semiconductor portion LSC5, and a sixth lower semiconductor portion LSC6.

[0108] The first lower semiconductor portion LSC1, the second lower semiconductor portion LSC2, the third lower semiconductor portion LSC3, and the fourth lower semiconductor portion LSC4 can be components constituting the driving transistor TRD, the first emitter transistor TRE1, the second emitter transistor TRE2, and the emitter compensation transistor TRL, respectively. The second lower semiconductor portion LSC2 can extend from one end of the first lower semiconductor portion LSC1. The third lower semiconductor portion LSC3 can extend from the other end of the first lower semiconductor portion LSC1. The fourth lower semiconductor portion LSC4 can be spaced apart from the second lower semiconductor portion LSC2. The fifth lower semiconductor portion LSC5 can extend from the second lower semiconductor portion LSC2. The sixth lower semiconductor portion LSC6 can be spaced apart from the fifth lower semiconductor portion LSC5.

[0109] In embodiments of this disclosure, each of the first lower semiconductor portions LSC1 to the sixth lower semiconductor portions LSC6 may include a silicon semiconductor. The silicon semiconductor may include at least one of amorphous silicon and polycrystalline silicon. For example, each of the first lower semiconductor portions LSC1 to the sixth lower semiconductor portions LSC6 may include low-temperature polycrystalline silicon (LTPS). However, the materials included in the first lower semiconductor portions LSC1 to the sixth lower semiconductor portions LSC6 are not limited thereto.

[0110] Figure 5A The diagram shows... Figure 4A and Figure 4B The superimposed shapes.

[0111] refer to Figure 3 and Figure 5A The first semiconductor pattern ACT can be disposed on the metal pattern BML. The first lower semiconductor portion LSC1 can overlap with the first lower sub-electrode portion LSE1. The portion of the first lower sub-electrode portion LSE1 that overlaps with the first lower semiconductor portion LSC1 can be an element constituting the sub-control electrode of the driving transistor TRD.

[0112] The second lower semiconductor section LSC2 can overlap with the first lower sub-electrode section LSE1. The third lower semiconductor section LSC3 can overlap with the second lower sub-electrode section LSE2. The fifth lower semiconductor section LSC5 can overlap with the third lower sub-electrode section LSE3.

[0113] Figure 4C This is a plan view of the first conductive pattern GAT1.

[0114] refer to Figure 4C The first conductive pattern GAT1 may include a first lower electrode portion LEL1, a second lower electrode portion LEL2, a third lower electrode portion LEL3, a fourth lower electrode portion LEL4, a fifth lower electrode portion LEL5, and a sixth lower electrode portion LEL6. The second lower electrode portion LEL2 may be spaced apart from the first lower electrode portion LEL1. The third lower electrode portion LEL3 may extend from one end of the second lower electrode portion LEL2, and the fourth lower electrode portion LEL4 may extend from the other end of the second lower electrode portion LEL2. The fifth lower electrode portion LEL5 may be spaced apart from the first lower electrode portion LEL1, the second lower electrode portion LEL2, the third lower electrode portion LEL3, and the fourth lower electrode portion LEL4. The sixth lower electrode portion LEL6 may extend from one end of the fifth lower electrode portion LEL5.

[0115] Figure 5B The diagram shows... Figures 4A to 4C The superimposed shapes.

[0116] refer to Figure 3 and Figure 5B A first conductive pattern GAT1 can be disposed on a first semiconductor pattern ACT. A first lower electrode portion LEL1 can overlap with a first lower semiconductor portion LSC1. The portion of the first lower electrode portion LEL1 that overlaps with the first lower semiconductor portion LSC1 can be an element constituting the control electrode of a driving transistor TRD. A second lower electrode portion LEL2 can overlap with a second lower semiconductor portion LSC2. The portion of the second lower electrode portion LEL2 that overlaps with the second lower semiconductor portion LSC2 can be an element constituting the control electrode of a first emitter transistor TRE1. A third lower electrode portion LEL3 can overlap with a third lower semiconductor portion LSC3. The portion of the third lower electrode portion LEL3 that overlaps with the third lower semiconductor portion LSC3 can be an element constituting the control electrode of a second emitter transistor TRE2. A fourth lower electrode portion LEL4 can overlap with a fourth lower semiconductor portion LSC4. The portion of the fourth lower electrode portion LEL4 that overlaps with the fourth lower semiconductor portion LSC4 can be an element constituting the control electrode of an emitter compensation transistor TRL. A fifth lower electrode portion LEL5 can overlap with a fifth lower semiconductor portion LSC5. The portion of the fifth lower electrode portion LEL5 that overlaps with the fifth lower semiconductor portion LSC5 can be an element constituting the control electrode of the switching transistor TRW. The sixth lower electrode portion LEL6 can overlap with the sixth lower semiconductor portion LSC6. The portion of the sixth lower electrode portion LEL6 that overlaps with the sixth lower semiconductor portion LSC6 can be the control electrode of the second initialization transistor TRI2.

[0117] Figure 4D This is a plan view of the second conductive pattern GAT2.

[0118] refer to Figure 4D The second conductive pattern GAT2 may include a first upper sub-electrode portion HSE1, a second upper sub-electrode portion HSE2, a third upper sub-electrode portion HSE3, a fourth upper sub-electrode portion HSE4, and a fifth upper sub-electrode portion HSE5. The second upper sub-electrode portion HSE2 may be spaced apart from the first upper sub-electrode portion HSE1. The second upper sub-electrode portion HSE2 may be an element constituting the sub-control electrode of the sub-compensation transistor TRS. In embodiments of this disclosure, the second upper sub-electrode portion HSE2 may be omitted. The third upper sub-electrode portion HSE3 may extend from the second upper sub-electrode portion HSE2. The third upper sub-electrode portion HSE3 may be an element constituting the sub-control electrode of the compensation transistor TRC. In embodiments of this disclosure, the third upper sub-electrode portion HSE3 may be omitted. The fourth upper sub-electrode portion HSE4 may be spaced apart from the first upper sub-electrode portion HSE1, the second upper sub-electrode portion HSE2, and the third upper sub-electrode portion HSE3. The fourth upper sub-electrode portion HSE4 may be an element constituting the sub-control electrode of the first initialization transistor TRI1. In embodiments of this disclosure, the fourth upper sub-electrode portion HSE4 may be omitted. The fifth upper sub-electrode portion HSE5 may be spaced apart from the first upper sub-electrode portion HSE1, the second upper sub-electrode portion HSE2, the third upper sub-electrode portion HSE3, and the fourth upper sub-electrode portion HSE4. The fifth upper sub-electrode portion HSE5 may be electrically connected to the first initialization line INL1.

[0119] Figure 5C The diagram shows... Figures 4A to 4D The superimposed shapes.

[0120] refer to Figure 5C The second conductive pattern GAT2 can be disposed on the first conductive pattern GAT1. The first upper sub-electrode portion HSE1 can overlap with the first lower electrode portion LEL1. The capacitor CST is defined in the area where the first upper sub-electrode portion HSE1 and the first lower electrode portion LEL1 overlap.

[0121] Figure 4E This is a plan view of the second semiconductor pattern OACT.

[0122] refer to Figure 3 and Figure 4EThe second semiconductor pattern OACT may include a first upper semiconductor portion HSC1, a second upper semiconductor portion HSC2, and a third upper semiconductor portion HSC3. In embodiments of this disclosure, the third upper semiconductor portion HSC3 may be omitted. The second upper semiconductor portion HSC2 may be spaced apart from the first upper semiconductor portion HSC1. The third upper semiconductor portion HSC3 may extend from the second upper semiconductor portion HSC2. The first upper semiconductor portion HSC1, the second upper semiconductor portion HSC2, and the third upper semiconductor portion HSC3 may each be an element constituting a sub-compensation transistor TRS, a compensation transistor TRC, and a first initialization transistor TRI1, respectively. In embodiments of this disclosure, the first upper semiconductor portion HSC1, the second upper semiconductor portion HSC2, and the third upper semiconductor portion HSC3 may each include at least one of metal oxide, crystalline oxide semiconductor, and amorphous oxide semiconductor. For example, the oxide semiconductor may include at least one of indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide, zinc indium oxide, indium oxide, titanium oxide, indium zinc tin oxide (IZTO), and zinc tin oxide (ZTO).

[0123] Figure 5D The diagram shows... Figures 4A to 4E The superimposed shapes.

[0124] refer to Figure 5D The second semiconductor pattern OACT can be set on the second conductive pattern GAT2.

[0125] Figure 4F This is a plan view of the third conductive pattern, GAT3.

[0126] refer to Figure 4F A third conductive pattern GAT3 may be disposed on the second semiconductor pattern OACT. The third conductive pattern GAT3 may include a first upper electrode portion HEL1, a second upper electrode portion HEL2, and a third upper electrode portion HEL3. In embodiments of this disclosure, the third upper electrode portion HEL3 may be omitted. The second upper electrode portion HEL2 may extend from one end of the first upper electrode portion HEL1. The third upper electrode portion HEL3 may be spaced apart from the first upper electrode portion HEL1 and the second upper electrode portion HEL2.

[0127] Figure 5E The diagram shows... Figures 4A to 4E The superimposed shapes.

[0128] refer to Figure 3 and Figure 5EThe first upper electrode portion HEL1 may overlap with the first upper semiconductor portion HSC1. The portion of the first upper electrode portion HEL1 that overlaps with the first upper semiconductor portion HSC1 may be an element constituting the control electrode of the sub-compensation transistor TRS. The second upper electrode portion HEL2 may overlap with the second upper semiconductor portion HSC2. The portion of the second upper electrode portion HEL2 that overlaps with the second upper semiconductor portion HSC2 may be an element constituting the control electrode of the compensation transistor TRC. The third upper electrode portion HEL3 may overlap with the third upper semiconductor portion HSC3. The portion of the third upper electrode portion HEL3 that overlaps with the third upper semiconductor portion HSC3 may be an element constituting the control electrode of the first initialization transistor TRI1.

[0129] Figure 4G It is a planar diagram of the connected electrode pattern SD.

[0130] refer to Figure 4G The connecting electrode pattern SD may include a first connecting electrode CNT1, a second connecting electrode CNT2, a third connecting electrode CNT3, a fourth connecting electrode CNT4, a fifth connecting electrode CNT5, a sixth connecting electrode CNT6, a seventh connecting electrode CNT7, an eighth connecting electrode CNT8, a ninth connecting electrode CNT9, a tenth connecting electrode CNT10, and an eleventh connecting electrode CNT11. The first to eleventh connecting electrodes CNT1 to CNT11 may each contact at least one of the other patterns located in the underlying layer through a contact hole. Specific examples in this regard are described in detail below, but this disclosure should not be limited to these examples.

[0131] Figure 5F The diagram shows... Figures 4A to 4G The superimposed shapes.

[0132] refer to Figure 5F The connecting electrode pattern SD can be set on the third conductive pattern GAT3.

[0133] The first connection electrode CNT1 can contact the first lower electrode portion LEL1 through the first contact hole H1. Furthermore, the first connection electrode CNT1 can contact the second upper semiconductor portion HSC2 through the second contact hole H2. The first lower electrode portion LEL1 can be an element constituting the control electrode of the driving transistor TRD. The first connection electrode CNT1 can be an element constituting the input electrode of the compensation transistor TRC. In other words, the first connection electrode CNT1 can electrically connect the control electrode of the driving transistor TRD to the input electrode of the compensation transistor TRC through the first contact hole H1 and the second contact hole H2.

[0134] The second connection electrode CNT2 can contact the fourth lower semiconductor portion LSC4 through the third contact hole H3. Furthermore, the second connection electrode CNT2 can contact the first lower sub-electrode portion LSE1 through the fourth contact hole H4. The second connection electrode CNT2 can be a component constituting the output electrode of the emitter compensation transistor TRL. The first lower sub-electrode portion LSE1 can be a component constituting the sub-control electrode of the driving transistor TRD. In other words, the second connection electrode CNT2 can electrically connect the output electrode of the emitter compensation transistor TRL to the sub-control electrode of the driving transistor TRD through the third contact hole H3 and the fourth contact hole H4.

[0135] The third connection electrode CNT3 can contact the first upper semiconductor portion HSC1 through the fifth contact hole H5. Furthermore, the third connection electrode CNT3 can contact the first lower sub-electrode portion LSE1 through the sixth contact hole H6. The third connection electrode CNT3 can be a component constituting the input electrode of the sub-compensation transistor TRS. The first lower sub-electrode portion LSE1 can be a component constituting the sub-control electrode of the driving transistor TRD. In other words, the third connection electrode CNT3 can electrically connect the input electrode of the sub-compensation transistor TRS to the sub-control electrode of the driving transistor TRD through the fifth contact hole H5 and the sixth contact hole H6.

[0136] The fourth connection electrode CNT4 can contact the first upper semiconductor portion HSC1 through the seventh contact hole H7. Furthermore, the fourth connection electrode CNT4 can contact the third lower sub-electrode portion LSE3 through the eighth contact hole H8. The fourth connection electrode CNT4 can be a component constituting the output electrode of the sub-compensation transistor TRS. The third lower sub-electrode portion LSE3 can be electrically connected to the compensation signal line GCL. In other words, the fourth connection electrode CNT4 can electrically connect the output electrode of the sub-compensation transistor TRS to the compensation signal line GCL through the seventh contact hole H7 and the eighth contact hole H8.

[0137] The fifth connection electrode CNT5 can contact the second lower sub-electrode portion LSE2 through the ninth contact hole H9. Furthermore, the fifth connection electrode CNT5 can contact the fourth lower semiconductor portion LSC4 through the tenth contact hole H10. The second lower sub-electrode portion LSE2 can be electrically connected to the power line PL. The fifth connection electrode CNT5 can be a component constituting the input electrode of the emitter compensation transistor TRL. In other words, the fifth connection electrode CNT5 can electrically connect the input electrode of the emitter compensation transistor TRL to the power line PL through the ninth contact hole H9 and the tenth contact hole H10.

[0138] The sixth connecting electrode CNT6 can contact the second lower semiconductor portion LSC2 through the eleventh contact hole H11. The sixth connecting electrode CNT6 can electrically connect the second lower semiconductor portion LSC2 to at least one component of the first semiconductor pattern ACT. The seventh connecting electrode CNT7 can contact the third lower semiconductor portion LSC3 through the thirteenth contact hole H13.

[0139] The eighth connection electrode CNT8 can contact at least one of the first lower semiconductor portion LSC1 and the third lower semiconductor portion LSC3 through the fourteenth contact hole H14. Furthermore, the eighth connection electrode CNT8 can contact the second upper semiconductor portion HSC2 through the fifteenth contact hole H15. In other words, the eighth connection electrode CNT8 can electrically connect the compensation transistor TRC to at least one of the driving transistor TRD and the second emitter transistor TRE2 through the fourteenth contact hole H14 and the fifteenth contact hole H15.

[0140] The ninth connecting electrode CNT9 can contact the sixth lower semiconductor section LSC6 through the sixteenth contact hole H16. The ninth connecting electrode CNT9 can be electrically connected to the second initialization line INL2. The tenth connecting electrode CNT10 can contact the fifth lower semiconductor section LSC5 through the seventeenth contact hole H17.

[0141] The eleventh connection electrode CNT11 can contact the third upper semiconductor portion HSC3 through the eighteenth contact hole H18. Furthermore, the eleventh connection electrode CNT11 can contact the fifth upper sub-electrode portion HSE5 through the nineteenth contact hole H19. The fifth upper sub-electrode portion HSE5 can be electrically connected to the first initialization line INL1. In other words, the eleventh connection electrode CNT11 can electrically connect the input electrode of the first initialization transistor TRI1 to the first initialization line INL1 through the eighteenth and nineteenth contact holes H18 and H19.

[0142] Figure 6A This is an exemplary equivalent circuit diagram illustrating a pixel PX-3 according to an embodiment of the present disclosure. Figure 6B This is a waveform diagram illustrating the signal provided to pixel PX-3 according to an embodiment of the present disclosure.

[0143] refer to Figure 6A According to embodiments of the present disclosure, the display panel DP may include a data line DL, a power line PL, a first gate line GL1, a second gate line GL2, a first initialization line INL1, a third gate line GL3, an emission control line ECL, and a pixel PX-3. In embodiments of the present disclosure, at least one of the second gate line GL2, the first initialization line INL1, the third gate line GL3, and the emission control line ECL may be omitted.

[0144] The data line DL can be configured to provide the data signal DS to pixel PX-3. The power line PL can be configured to provide the first power signal ELVDD to pixel PX-3. The first gate line GL1 can be configured to provide the first gate signal GW to pixel PX-3. The second gate line GL2 can be configured to provide the second gate signal GI to pixel PX-3. The first initialization line INL1 can be configured to provide the first initialization signal VINT to pixel PX-3. The third gate line GL3 can be configured to provide the third gate signal GB to pixel PX-3. The transmit control line ECL can be configured to provide the transmit control signal EM to pixel PX-3. Pixel PX-3 may include pixel circuitry PC-4 and a light-emitting diode LD.

[0145] The pixel circuit PC-4 may include a driving transistor TRD, a switching transistor TRW, a compensation transistor TRC, a secondary compensation transistor TRS, a first emitter transistor TRE1, a second emitter transistor TRE2, an emitter compensation transistor TRL, a capacitor CST, a first initialization transistor TRI1, and a second initialization transistor TRI2. In embodiments of this disclosure, at least one of the secondary compensation transistor TRS, the first emitter transistor TRE1, the second emitter transistor TRE2, the emitter compensation transistor TRL, the capacitor CST, the first initialization transistor TRI1, and the second initialization transistor TRI2 may be omitted in the pixel circuit PC-4.

[0146] In embodiments of this disclosure, pixel PX-3 may be a low-temperature polycrystalline silicon (LTPS) pixel. That is, the driving transistor TRD, the switching transistor TRW, the compensation transistor TRC, the sub-compensation transistor TRS, the first emitter transistor TRE1, the second emitter transistor TRE2, the emitter compensation transistor TRL, the first initialization transistor TRI1, and the second initialization transistor TRI2 may each be an LTPS thin-film transistor.

[0147] In embodiments of this disclosure, the driving transistor TRD, the switching transistor TRW, the compensation transistor TRC, the secondary compensation transistor TRS, the first emitter transistor TRE1, the second emitter transistor TRE2, the emitter compensation transistor TRL, the first initialization transistor TRI1, and the second initialization transistor TRI2 can each be a PMOS transistor. In embodiments of this disclosure, the driving transistor TRD, the switching transistor TRW, the compensation transistor TRC, the secondary compensation transistor TRS, the first emitter transistor TRE1, the second emitter transistor TRE2, the emitter compensation transistor TRL, the first initialization transistor TRI1, and the second initialization transistor TRI2 can each be an NMOS transistor. However, this disclosure is not limited to these configurations, and the pixel PX-3 can be configured with various combinations of NMOS and PMOS transistors.

[0148] A driving transistor (TRD) can be electrically connected to a light-emitting diode (LD). A driving transistor (TRD) may include an input electrode, an output electrode, a control electrode, and a secondary control electrode.

[0149] The switching transistor TRW can be configured to be controlled by the first gate signal GW. The switching transistor TRW can be positioned between the data line DL and the drive transistor TRD.

[0150] A compensation transistor TRC can be disposed between the output electrode of the driving transistor TRD and the control electrode of the driving transistor TRD. The compensation transistor TRC can be configured to be controlled by a first gate signal GW. That is, in the display panel DP according to an embodiment of this disclosure, in... Figures 2A to 2C In this configuration, the compensation transistor TRC is configured to be controlled by the compensation control signal GC, while... Figure 6A In this configuration, the compensation transistor TRC can be configured to be controlled by the first gate signal GW.

[0151] The secondary compensation transistor TRS can be configured to transmit the compensation signal VCP to the secondary control electrode of the driving transistor TRD. The secondary compensation transistor TRS can be configured to be controlled by the same signal (i.e., the first gate signal GW) as the compensation transistor TRC. In embodiments of this disclosure, the voltage value of the compensation signal VCP can be greater than the voltage value of the first power supply signal ELVDD. In embodiments of this disclosure, the voltage value of the compensation signal VCP can decrease when the ambient temperature decreases.

[0152] The first emitter transistor TRE1 can be configured to be controlled by the emitter control signal EM. The first emitter transistor TRE1 can be located between the power supply line PL and the drive transistor TRD.

[0153] The second emitting transistor TRE2 can be configured to be controlled by the emitter control signal EM. The second emitting transistor TRE2 can be positioned between the driver transistor TRD and the light-emitting diode LD.

[0154] The emitter compensation transistor TRL can be configured to be controlled by the emitter control signal EM. The emitter compensation transistor TRL can be positioned between the power supply line PL and the secondary control electrode of the drive transistor TRD.

[0155] The capacitor CST can be placed between the power line PL and the compensation transistor TRC.

[0156] The first initialization transistor TRI1 can be disposed between the first initialization line INL1 and the control electrode of the driving transistor TRD. The first initialization transistor TRI1 can be configured to be controlled by the second gate signal GI. The first initialization transistor TRI1 can be configured to turn on in response to the second gate signal GI and transmit at least a portion of the first initialization signal VINT to the control electrode of the driving transistor TRD.

[0157] The second initialization transistor TRI2 can be positioned between the first initialization line INL1 and the light-emitting diode LD. The input electrode of the second initialization transistor TRI2 can be electrically connected to the first initialization transistor TRI1 and the first initialization line INL1. The output electrode of the second initialization transistor TRI2 can be electrically connected to the second emitting transistor TRE2 and the light-emitting diode LD.

[0158] The second initialization transistor TRI2 can be configured to be controlled by a third gate signal GB. The second initialization transistor TRI2 can be configured to turn on in response to the third gate signal GB and transmit at least a portion of the first initialization signal VINT to the light-emitting diode LD.

[0159] One end of the light-emitting diode (LED) LD can be electrically connected to the second emitting transistor TRE2, and the other end of the LED LD can be supplied with a second power supply signal ELVSS. In embodiments of this disclosure, the voltage value of the second power supply signal ELVSS can be in the range of about -0.9V to about -1.9V. For example, the voltage value of the second power supply signal ELVSS can be about -1.4V. However, the voltage value of the second power supply signal ELVSS is not limited to this.

[0160] Figure 7 This is a diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure.

[0161] refer to Figure 7 According to embodiments of this disclosure, the electronic device 1000 can output various information (e.g., images, text, music, etc.) through the display module 1140, which may correspond, for example, to the display device DD described above. When the processor 1110 executes the application program 1123 stored in the memory 1120, the display module 1140 can provide information related to the application program 1123 to the user through the display panel 1141. The display panel 1141 may correspond to the display panel DP described above.

[0162] In some embodiments, the electronic device 1000 may be configured as, for example, a smartphone, camera, smart TV, monitor, smartwatch, tablet computer, automotive display, or AR / VR head-mounted display. For example, the electronic device 1000 may be a smartphone including a touch-sensitive display area DA for interaction and a non-display area NDA containing sensors and circuitry for enhanced functionality. For example, the electronic device 1000 may be a television or monitor including a large display area DA for high-resolution video playback and a non-display area NDA incorporating drive circuitry or connection modules for external input. For example, the electronic device 1000 may be a smartwatch including a display area DA optimized for compact and high-definition visual effects and a non-display area NDA integrating biometric sensors for health monitoring. In some cases, the electronic device 1000 is an AR / VR head-mounted display.

[0163] In some embodiments, memory 1120 may store information such as software code for running application 1123. Application 1123 may include software designed to perform specific tasks or provide functionality to a user. Application 1123 may run under the control of processor 1110 and utilize data stored in memory 1120 to deliver a wide range of functions, such as productivity tools, multimedia streaming and playback, file or mail delivery services, or communication services. Application 1123 interacts seamlessly with user interface 1161 or touchscreen 1142, allowing a user to initiate, manipulate, and use the program via user input, such as touch, tap, gesture, or voice interaction.

[0164] When a user selects an application via touchscreen 1142 or user interface 1161, processor 1110 can execute application program 1123 corresponding to the selected application, retrieved from memory 1120, to perform the application's functions. For example, when a user selects a camera application by tapping an icon (or camera application icon) displayed on display panel 1141, processor 1110 activates the camera module. Processor 1110 can then send image data corresponding to a captured image obtained by the camera module to display module 1140. Display module 1140 can then display the image corresponding to the captured image via display panel 1141.

[0165] In one embodiment, when a user wishes to make a call, the user taps a phone icon displayed on the display panel 1141, and the processor 1110 can execute a phone application stored in the memory 1120. A phone keypad can be displayed on the display panel 1141 for the user to enter the phone number to call.

[0166] In this embodiment, the display module 1140 may be integrated into an electronic device 1000, such as a laptop computer, smart TV, or tablet computer. A user wishing to access a multimedia streaming application (e.g., watch music videos or movies) can do so by tapping the corresponding icon. This action activates the application, allowing the user to watch streaming content.

[0167] Processor 1110 may include a main processor 1111 and an auxiliary processor or coprocessor 1112. The main processor 1111 may include a central processing unit (CPU). The main processor 1111 may further include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0168] The coprocessor 1112 may include a controller 1112-1. The controller 1112-1 may include an interface conversion circuit and a timing control circuit (which may correspond to the signal control circuit SCC described above). The controller 1112-1 can receive image signals from the main processor 1111, convert the data format of the image signals to match the interface specification of the display module 1140, and output the image data. The controller 1112-1 can output various control signals to drive the display module 1140. For example, the controller 1112-1 can drive the display module 1140 to display icons on the display screen (or display panel 1141) suitable for user selection to execute the application 1123.

[0169] Memory 1120 may store one or more applications 1123, as well as various data used by at least one component of electronic device 1000 (e.g., processor 1110 or user interface 1161), and input or output data for commands related to application 1123. For example, camera applications, GPS applications, augmented reality and virtual reality applications, and other applications may be executed by processor 1110 after the user selects a corresponding icon presented on the display screen (or display panel 1141) via touchscreen 1142 or user interface 1161. Furthermore, various setting data corresponding to user settings may be stored in memory 1120. Memory 1120 may include volatile memory 1121 and non-volatile memory 1122.

[0170] Display module 1140 can output visual information (images) to a user. Display module 1140 may include a display panel 1141, a gate driver (which may correspond to the gate drive circuit GDC and / or transmit control circuit ECC described above), a source driver (which may correspond to the data drive circuit DDC described above), a voltage generation circuit, and a touch screen 1142. Display module 1140 may further include a window, a chassis, and a bracket to protect display panel 1141. Display module 1140 may include at least a portion of the configuration of the display device DD described above.

[0171] User interface 1161 serves as an interaction medium between the user and electronic device 1000. User interface 1161 can detect input made by a part of the user's body (e.g., a finger) or by a pen or mouse, and generate an electrical signal or data value corresponding to the input. User interface 1161 includes a fingerprint sensor 1162, an input sensor 1163, and a digitizer 1164.

[0172] The fingerprint sensor 1162 can sense fingerprints for biometric identification of a user, and can also measure one or more biometric signals related to biometric information such as blood pressure, water content, or weight.

[0173] Input sensor 1163 can sense user interactions including, for example, touch, tap, gesture, motion, voice commands, and eye movements. Input sensor 1163 includes optical sensors for image capture, eye tracking, or motion and gesture detection. The optical sensors can be infrared or semiconductor photodetectors. Input sensor 1163 includes audio and acoustic sensors, which can be MEMS microphones for voice recognition or voice-based interaction. The audio and acoustic sensors can be mounted as part of user interface 1161 or embedded in display panel 1141.

[0174] The digitizer 1164 can generate data values ​​corresponding to the coordinate information of input via a pen or mouse to control the movement of the screen cursor. The digitizer 1164 can generate electromagnetic changes caused by the input as data values. The digitizer 1164 can detect input via a passive pen, or send and receive data using an active pen or remote control.

[0175] At least one of the fingerprint sensor 1162, the input sensor 1163, and the digitizer 1164 can be implemented as a sensor layer formed on the top layer of the display panel 1141 by a process that is continuous with the process of forming the various elements (e.g., light-emitting elements and transistors) included in the display panel 1141.

[0176] Furthermore, the user interface 1161 may further include, for example, a gesture sensor, a gyroscope sensor for sensing rotational motion, an accelerometer sensor for tracking translational motion, a grip sensor, a pressure sensor, a proximity sensor, a color sensor, an infrared (IR) emitter and camera sensor for tracking gaze direction and eye movement, a temperature sensor, or a light sensor. For example, the gyroscope sensor, accelerometer sensor, infrared emitter, and camera sensor may be particularly suitable for AR / VR head-mounted display functions.

[0177] Touchscreen 1142 includes a touch sensor embedded in display panel 1141 to sense pressure applied to the top layer (screen) of display panel 1141. The touch sensor can be capacitive or resistive. Touchscreen 1142 can serve as a primary interface for users to select and manipulate applications, control electronic device 1000, and interact with electronic device 1000.

[0178] The display panel 1141 (or display) may include, for example, a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel. However, the type of display panel 1141 is not particularly limited. The display panel 1141 may be a rigid type or a flexible type that can be rolled or folded. The display module 1140 may further include supports, brackets, and heat dissipation components for supporting the display panel 1141. The display module 1140 may include the display device DD described above.

[0179] Power module 1150 can supply power to components of electronic device 1000. Power module 1150 may include a battery charged with a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 1150 may include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the components described above, including display module 1140.

[0180] In accordance with the conventions of the art, this disclosure describes various embodiments in terms of functional blocks, units, and / or modules, and illustrates them in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or similar devices, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing certain functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions.

[0181] Although this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the claims.

Claims

1. A display panel, comprising: A pixel includes pixel circuitry and a light-emitting diode (LED). The data line is configured to provide data signals to the pixel; The gate line is configured to provide a gate signal to the pixel; as well as The power line is configured to provide a power signal to the pixel. The pixel circuit includes: A driving transistor is electrically connected to the light-emitting diode and includes an input electrode, an output electrode, a control electrode, and a secondary control electrode; A switching transistor, configured to be controlled by the gate signal, is disposed between the data line and the driving transistor; A compensation transistor is disposed between the output electrode and the control electrode of the driving transistor; and A secondary compensation transistor is configured to transmit a compensation signal to the secondary control electrode of the driving transistor and is configured to be controlled by the same signal as the compensation transistor.

2. The display panel according to claim 1, wherein, The voltage value of the compensation signal is greater than the voltage value of the power supply signal.

3. The display panel according to claim 1, wherein, The voltage value of the compensation signal decreases as the ambient temperature decreases.

4. The display panel according to claim 1, further comprising: A transmit control line is configured to provide a transmit control signal to the pixel. The pixel circuit further includes: A first transmitting transistor is configured to be controlled by the transmitting control signal and is disposed between the power line and the driving transistor; A second emitting transistor, configured to be controlled by the emission control signal, is disposed between the driving transistor and the light-emitting diode; and An emitter compensation transistor is configured to be controlled by the emitter control signal and is disposed between the power supply line and the secondary control electrode of the drive transistor.

5. The display panel according to claim 1, wherein, The pixel circuit further includes: A capacitor is disposed between the power line and the compensation transistor.

6. The display panel according to claim 1, further comprising: A first initialization line is configured to provide a first initialization signal to the pixel. The pixel circuit further includes: A first initialization transistor is disposed between the first initialization line and the control electrode of the driving transistor, and is configured to be turned on simultaneously with the compensation transistor for a predetermined time period.

7. The display panel according to claim 1, further comprising: The second initialization line is configured to provide a second initialization signal to the pixel. The pixel circuit further includes: A second initialization transistor is disposed between the second initialization line and the light-emitting diode, and is configured to transmit the second initialization signal to the light-emitting diode.

8. The display panel according to claim 7, further comprising: A bias signal line is configured to provide a bias signal to the pixel. The pixel circuit further includes: A bias transistor is disposed between the bias signal line and the drive transistor, and is configured to be controlled by the same signal as the second initialization transistor.

9. An electronic device comprising: processor; Memory, storing applications executed by the processor; The display device includes a display panel according to any one of claims 1 to 8; as well as The user interface is configured to sense user input via touch or cursor selection of an icon presented on the display panel, wherein upon receiving the user input, the processor is prompted to execute one or more of the stored applications.

10. The electronic device according to claim 9, wherein, The stored applications include one or more of camera applications, streaming applications, and phone applications.

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