A multi-protected dc power supply input circuit

Abstract

The utility model provides a kind of multi-protection DC power supply input circuit, it is related to technical field, solve the existing power supply input circuit, maintenance cost is high, loss is more, the problem of performance significantly reduces.The utility model includes overcurrent protection circuit, anti-reverse connection protection circuit, overvoltage protection circuit, power switch protection circuit and intelligent shutdown circuit;The overcurrent protection circuit includes fast recovery fuse and TVS surge protection device;The anti-reverse connection protection circuit includes first PMOS field effect tube;The overvoltage protection circuit includes overvoltage protection chip, first resistance and second resistance;The power switch protection circuit includes second PMOS field effect tube and power switch KEY;The intelligent shutdown circuit includes third PMOS field effect tube, NPN triode.The utility model has the beneficial effect that: overvoltage protection is fast, avoids damage to rear stage circuit;Shutdown response is timely, reduces the energy consumption and security risk when equipment is shut down;Circuit is stable and reliable, improves power supply circuit anti-interference ability and service life.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit protection technology, specifically to a multi-protection DC power input circuit. Background Technology

[0002] With the widespread application of electronic devices, DC power supply systems face more complex operating environments. For example, in scenarios such as portable computers, home appliances, and data centers, DC power supply systems need to cope with issues such as sudden changes in high-power loads and line interference. Traditional power supply systems, due to problems such as harmonic interference, can no longer meet high reliability requirements, making DC technology a research hotspot. DC input protection circuits are safety protection devices designed for DC power supply systems, primarily used to prevent damage to equipment caused by abnormal conditions such as overvoltage, overcurrent, and reverse connection. Their core design concept is based on power electronics technology, achieving multi-dimensional protection through the integration of multiple protection mechanisms.

[0003] The existing power input circuit is a combination of TVS, fuse, and diode to form an overvoltage, overcurrent, and reverse connection protection circuit. However, the one-time fuse cannot be recovered after a failure, resulting in high maintenance costs. The diode reverse connection protection circuit has a voltage drop loss of more than 0.7V, and the power consumed by the diode increases with the increase of the load circuit current. The increase of ambient temperature will significantly reduce the clamping performance of the TVS tube, making it unable to cope with complex fault scenarios. Utility Model Content

[0004] The purpose of this invention is to solve the problems of existing power input circuits, which use one-time fuses that cannot be recovered after failure, have high maintenance costs, high losses, significantly reduced performance, and cannot cope with complex fault scenarios.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A multi-protection DC power input circuit, characterized in that it includes an overcurrent protection circuit, a reverse connection protection circuit, an overvoltage protection circuit, a power switch protection circuit, and an intelligent shutdown circuit connected in sequence.

[0007] The overcurrent protection circuit includes a fast reset fuse and a TVS surge protection device. The first terminal of the fast reset fuse is electrically connected to the input terminal of the DC power supply, the second terminal of the fast reset fuse is electrically connected to the first terminal of the TVS surge protection device, and the second terminal of the TVS surge protection device is grounded.

[0008] The reverse connection protection circuit includes a first PMOS field-effect transistor, the drain of which is connected to the second end of a fast recovery fuse.

[0009] The overvoltage protection circuit includes an overvoltage protection chip, a first resistor, and a second resistor. The input terminal of the overvoltage protection chip is electrically connected to the source of a first PMOS field-effect transistor and the first terminal of the first resistor, respectively. The second terminal of the first resistor is electrically connected to the first terminal of the second resistor and the overvoltage lockout terminal of the overvoltage protection chip, respectively. The ground terminal of the overvoltage protection chip and the second terminal of the second resistor are grounded.

[0010] The power switch protection circuit includes a second PMOS field-effect transistor, a fifth resistor, a sixth resistor, and a power switch. The drain of the second PMOS field-effect transistor is electrically connected to the output terminal of the overvoltage protection chip and the first terminal of the fifth resistor. The second terminal of the fifth resistor is electrically connected to the gate of the second PMOS field-effect transistor and the first terminal of the sixth resistor. The second terminal of the sixth resistor is electrically connected to the first terminal of the power switch, and the second terminal of the power switch is grounded.

[0011] The intelligent shutdown circuit includes a third PMOS field-effect transistor, an NPN transistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor. The source of the third PMOS field-effect transistor is electrically connected to the drain of the second PMOS field-effect transistor, the first terminal of the seventh resistor, and the input terminal of the monitoring circuit of the control board. The drain of the third PMOS field-effect transistor is electrically connected to the output terminal of the DC power supply. The gate of the third PMOS field-effect transistor is electrically connected to the first terminal of the tenth resistor. The second terminal of the tenth resistor is electrically connected to the collector of the NPN transistor. The base of the NPN transistor is electrically connected to the second terminal of the seventh resistor, the second terminal of the eighth resistor, and the first terminal of the ninth resistor. The first terminal of the eighth resistor is electrically connected to the power enable control pin of the control board. The second terminal of the ninth resistor is electrically connected to the emitter of the NPN transistor. The emitter of the NPN transistor is grounded.

[0012] A further improvement is that the reverse connection protection circuit also includes a third resistor and a fourth resistor. The first end of the third resistor is electrically connected to the source of the first PMOS field-effect transistor, the second end of the third resistor is electrically connected to the gate of the first PMOS field-effect transistor and the first end of the fourth resistor, and the second end of the fourth resistor is grounded.

[0013] A further improvement is that the reverse connection protection circuit also includes a first capacitor and a second capacitor. The first terminal of the first capacitor is electrically connected to the source of the first PMOS field-effect transistor and the first terminal of the first resistor, respectively. The second terminal of the first capacitor is grounded. The first terminal of the second capacitor is electrically connected to the second terminal of the first resistor and the overvoltage lockout terminal of the overvoltage protection chip, respectively. The second terminal of the second capacitor is electrically connected to the second terminal of the second resistor.

[0014] A further improvement is that the power switch protection circuit also includes a third capacitor, the first end of which is electrically connected to the first end of the fifth resistor and the drain of the second PMOS field-effect transistor, and the second end of which is electrically connected to the second end of the fifth resistor and the gate of the second PMOS field-effect transistor.

[0015] A further improvement is made to the intelligent shutdown circuit, which further includes an eleventh resistor and a fourth capacitor. The first end of the eleventh resistor is electrically connected to the source of the third PMOS field-effect transistor and the drain of the second PMOS field-effect transistor. The second end of the eleventh resistor is electrically connected to the gate of the third PMOS field-effect transistor and the first end of the tenth resistor. The first end of the fourth capacitor is electrically connected to the first end of the eleventh resistor and the source of the third PMOS field-effect transistor. The second end of the fourth capacitor is electrically connected to the second end of the eleventh resistor and the gate of the third PMOS field-effect transistor.

[0016] Compared with existing technologies, the above technical solution has the following advantages:

[0017] Overvoltage protection is fast. Through the overvoltage protection chip and voltage divider resistor, the active protection IC overcomes the limitations of TVS through intelligent control, monitors the input voltage in real time, and triggers the overvoltage protection signal when the input voltage exceeds the preset threshold, achieving millisecond-level overvoltage response and avoiding damage to downstream circuits.

[0018] The shutdown response is timely, the MOSFET anti-reverse connection circuit is in place, the power consumption is low (<0.1V voltage drop), the response is faster than mechanical fuse, the shutdown delay is shortened, and the energy consumption and safety hazards when the equipment is shut down are reduced.

[0019] The circuit is stable and reliable, with input / output filtering, ESD protection, and back-end feedback protection designs to improve the power supply circuit's anti-interference capability and lifespan. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the circuit structure of this utility model;

[0022] Figure 2 This is a schematic diagram of the overcurrent protection circuit in this utility model.

[0023] Figure 3This is a schematic diagram of the reverse connection protection circuit in this utility model.

[0024] Figure 4 This is a schematic diagram of the overvoltage protection circuit in this utility model.

[0025] Figure 5 This is a schematic diagram of the circuit structure of the power switch protection circuit in this utility model;

[0026] Figure 6 This is a schematic diagram of the circuit structure of the intelligent shutdown circuit in this utility model.

[0027] Explanation of reference numerals in the attached diagram: Fast recovery fuse F1, TVS surge protector D1, first PMOS field-effect transistor Q1, second PMOS field-effect transistor Q2, third PMOS field-effect transistor Q3, NPN transistor Q4, overvoltage protection chip U1, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, ninth resistor R9, tenth resistor R10, eleventh resistor R11, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, power switch KEY. Detailed Implementation

[0028] For ease of description, in this embodiment, the upper or left end in the accompanying drawings is defined as the first end, and the lower or right end as the second end; in the drawings, the gate (G) of the PMOS field-effect transistor is the gate, the source (S) is the source, and the drain (D) is the gate; see also Figures 1-6 As shown, the technical solution adopted in this specific embodiment is:

[0029] A multi-protection DC power input circuit includes an overcurrent protection circuit, a reverse connection protection circuit, an overvoltage protection circuit, a power switch protection circuit, and an intelligent shutdown circuit connected in sequence.

[0030] The overcurrent protection circuit includes a fast reset fuse F1 and a TVS surge protector D1. The first terminal of the fast reset fuse F1 is electrically connected to the input terminal of the DC 12V power supply, the second terminal of the fast reset fuse F1 is electrically connected to the first terminal of the TVS surge protector D1, and the second terminal of the TVS surge protector D1 is grounded.

[0031] The reverse connection protection circuit includes a first PMOS field-effect transistor Q1, and the drain of the first PMOS field-effect transistor Q1 is connected to the second end of a fast recovery fuse F1.

[0032] The overvoltage protection circuit includes an overvoltage protection chip U1, a first resistor R1, and a second resistor R2. The input terminal of the overvoltage protection chip U1 is electrically connected to the source of the first PMOS field-effect transistor Q1 and the first terminal of the first resistor R1. The second terminal of the first resistor R1 is electrically connected to the first terminal of the second resistor R2 and the overvoltage lockout terminal (OVLO) of the overvoltage protection chip U1. The ground terminal of the overvoltage protection chip U1 and the second terminal of the second resistor R2 are grounded.

[0033] The power switch protection circuit includes a second PMOS field-effect transistor Q2, a fifth resistor R5, a sixth resistor R6, and a power switch KEY. The drain of the second PMOS field-effect transistor Q2 is electrically connected to the output terminal of the overvoltage protection chip U1 and the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is electrically connected to the gate of the second PMOS field-effect transistor Q2 and the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is electrically connected to the first terminal of the power switch KEY. The second terminal of the power switch KEY is grounded.

[0034] The intelligent shutdown circuit includes a third PMOS field-effect transistor Q3, an NPN transistor Q4, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10. The source of the third PMOS field-effect transistor Q3 is electrically connected to the drain of the second PMOS field-effect transistor Q2, the first terminal of the seventh resistor R7, and the input terminal (12V0_ON_MCU) of the monitoring circuit of the control board. The drain of the third PMOS field-effect transistor Q3 is electrically connected to the output terminal (12V0_OUT) of the DC 12V power supply. The gate of the field-effect transistor Q3 is electrically connected to the first end of the tenth resistor R10. The second end of the tenth resistor R10 is electrically connected to the collector of the NPN transistor Q4. The base of the NPN transistor Q4 is electrically connected to the second end of the seventh resistor R7, the second end of the eighth resistor R8, and the first end of the ninth resistor R9. The first end of the eighth resistor R8 is electrically connected to the power enable control pin (MCU_POWER_EN) of the control board. The second end of the ninth resistor R9 is electrically connected to the emitter of the NPN transistor Q4. The emitter of the NPN transistor Q4 is grounded.

[0035] The reverse connection protection circuit further includes a third resistor R3 and a fourth resistor R4. The first end of the third resistor R3 is electrically connected to the source of the first PMOS field-effect transistor Q1, the second end of the third resistor R3 is electrically connected to the gate of the first PMOS field-effect transistor Q1 and the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded.

[0036] The reverse connection protection circuit further includes a first capacitor C1 and a second capacitor C2. The first terminal of the first capacitor C1 is electrically connected to the source of the first PMOS field-effect transistor Q1 and the first terminal of the first resistor R1, respectively. The second terminal of the first capacitor C1 is grounded. The first terminal of the second capacitor C2 is electrically connected to the second terminal of the first resistor R1 and the overvoltage lockout terminal (OVLO) of the overvoltage protection chip U1, respectively. The second terminal of the second capacitor C2 is electrically connected to the second terminal of the second resistor R2.

[0037] The power switch protection circuit further includes a third capacitor C3. The first end of the third capacitor C3 is electrically connected to the first end of the fifth resistor R5 and the drain of the second PMOS field-effect transistor Q2, respectively. The second end of the third capacitor C3 is electrically connected to the second end of the fifth resistor R5 and the gate of the second PMOS field-effect transistor Q2, respectively.

[0038] The intelligent shutdown circuit further includes an eleventh resistor R11 and a fourth capacitor C4. The first end of the eleventh resistor R11 is electrically connected to the source of the third PMOS field-effect transistor Q3 and the drain of the second PMOS field-effect transistor Q2. The second end of the eleventh resistor R11 is electrically connected to the gate of the third PMOS field-effect transistor Q3 and the first end of the tenth resistor R10. The first end of the fourth capacitor C4 is electrically connected to the first end of the eleventh resistor R11 and the source of the third PMOS field-effect transistor Q3. The second end of the fourth capacitor C4 is electrically connected to the second end of the eleventh resistor R11 and the gate of the third PMOS field-effect transistor Q3.

[0039] Wherein, each capacitor is a surface-mount capacitor, and each resistor is a surface-mount resistor.

[0040] The calculation formula for the overvoltage lockout terminal is: VOVLO=1.2x(1+R1 / R2). When passing through the overvoltage protection chip U1, the matching resistors R1\R2 of the protection threshold are calculated using the configuration function of the IC to realize the input overvoltage protection function.

[0041] The working principle of this utility model is as follows: The DC 12V input power supply is protected against overcurrent by the fast recovery fuse F1 and TVS surge protection device D1 in the overcurrent protection circuit; it is also protected against reverse connection by the first PMOS field-effect transistor Q1 in the reverse connection protection circuit; when passing through the overvoltage protection chip U1 in the overvoltage protection circuit, the IC's configuration function is used to calculate the matching resistors R1 and R2 for the protection threshold, thus achieving input overvoltage protection; when passing through the power switch protection circuit, the fast switching function of the second PMOS field-effect transistor Q2 is used to control the rapid trigger shutdown signal at the gate, realizing the power on / off switch of the device and shortening the shutdown delay; when passing through the intelligent shutdown circuit, the output DC power supply powers the monitoring circuit of the control board. When abnormalities are detected in the operating voltage, circuit, or temperature of the control board, the power shutdown signal MCU_POWER_EN is output at a low level according to the preset threshold, and NPN transistor Q4 is turned off, while Q3 is turned off, cutting off the downstream power supply of the DC 12V power supply. This achieves monitoring and feedback protection of the operating status of the control board and the input power supply, providing dual protection for both the front and rear power supplies.

[0042] The reverse connection protection works as follows: When the power supply polarity is correct, the current initially flows through the Zener diode of the MOSFET, causing the source (S) voltage to be close to 0V. After the voltage is divided by the two resistors, a voltage is provided to the gate (G), causing the MOSFET to conduct. Because its on-resistance is very small, it replaces the internal diode of the MOSFET. When the power supply is reversed, the internal diode of the MOSFET does not conduct until it reaches its breakdown voltage. The voltage divider resistors have no current flowing through them and cannot provide a voltage to the gate, so they also do not conduct, thus providing protection.

[0043] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions provided are merely illustrative of the principles of this utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of protection of this utility model as defined by the appended claims and their equivalents. Any aspects of this utility model not detailed herein are well-known to those skilled in the art.

Claims

1. A multi-protection DC power input circuit, characterized in that: It includes an overcurrent protection circuit, a reverse connection protection circuit, an overvoltage protection circuit, a power switch protection circuit, and an intelligent shutdown circuit, which are connected in sequence. The overcurrent protection circuit includes a fast reset fuse and a TVS surge protection device. The first terminal of the fast reset fuse is electrically connected to the input terminal of the DC power supply, the second terminal of the fast reset fuse is electrically connected to the first terminal of the TVS surge protection device, and the second terminal of the TVS surge protection device is grounded. The reverse connection protection circuit includes a first PMOS field-effect transistor, the drain of which is connected to the second end of a fast recovery fuse. The overvoltage protection circuit includes an overvoltage protection chip, a first resistor, and a second resistor. The input terminal of the overvoltage protection chip is electrically connected to the source of a first PMOS field-effect transistor and the first terminal of the first resistor, respectively. The second terminal of the first resistor is electrically connected to the first terminal of the second resistor and the overvoltage lockout terminal of the overvoltage protection chip, respectively. The ground terminal of the overvoltage protection chip and the second terminal of the second resistor are grounded. The power switch protection circuit includes a second PMOS field-effect transistor, a fifth resistor, a sixth resistor, and a power switch. The drain of the second PMOS field-effect transistor is electrically connected to the output terminal of the overvoltage protection chip and the first terminal of the fifth resistor. The second terminal of the fifth resistor is electrically connected to the gate of the second PMOS field-effect transistor and the first terminal of the sixth resistor. The second terminal of the sixth resistor is electrically connected to the first terminal of the power switch, and the second terminal of the power switch is grounded. The intelligent shutdown circuit includes a third PMOS field-effect transistor, an NPN transistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor. The source of the third PMOS field-effect transistor is electrically connected to the drain of the second PMOS field-effect transistor, the first terminal of the seventh resistor, and the input terminal of the monitoring circuit of the control board. The drain of the third PMOS field-effect transistor is electrically connected to the output terminal of the DC power supply. The gate of the third PMOS field-effect transistor is electrically connected to the first terminal of the tenth resistor. The second terminal of the tenth resistor is electrically connected to the collector of the NPN transistor. The base of the NPN transistor is electrically connected to the second terminal of the seventh resistor, the second terminal of the eighth resistor, and the first terminal of the ninth resistor. The first terminal of the eighth resistor is electrically connected to the power enable control pin of the control board. The second terminal of the ninth resistor is electrically connected to the emitter of the NPN transistor. The emitter of the NPN transistor is grounded.

2. The multi-protection DC power input circuit according to claim 1, characterized in that: The reverse connection protection circuit further includes a third resistor and a fourth resistor. The first end of the third resistor is electrically connected to the source of the first PMOS field-effect transistor, the second end of the third resistor is electrically connected to the gate of the first PMOS field-effect transistor and the first end of the fourth resistor, and the second end of the fourth resistor is grounded.

3. The multi-protection DC power input circuit according to claim 1, characterized in that: The reverse connection protection circuit further includes a first capacitor and a second capacitor. The first terminal of the first capacitor is electrically connected to the source of the first PMOS field-effect transistor and the first terminal of the first resistor, respectively. The second terminal of the first capacitor is grounded. The first terminal of the second capacitor is electrically connected to the second terminal of the first resistor and the overvoltage lockout terminal of the overvoltage protection chip, respectively. The second terminal of the second capacitor is electrically connected to the second terminal of the second resistor.

4. The multi-protection DC power input circuit according to claim 1, characterized in that: The power switch protection circuit also includes a third capacitor. The first end of the third capacitor is electrically connected to the first end of the fifth resistor and the drain of the second PMOS field-effect transistor, respectively. The second end of the third capacitor is electrically connected to the second end of the fifth resistor and the gate of the second PMOS field-effect transistor, respectively.

5. A multi-protection DC power input circuit according to claim 1, characterized in that: The intelligent shutdown circuit also includes an eleventh resistor and a fourth capacitor. The first end of the eleventh resistor is electrically connected to the source of the third PMOS field-effect transistor and the drain of the second PMOS field-effect transistor. The second end of the eleventh resistor is electrically connected to the gate of the third PMOS field-effect transistor and the first end of the tenth resistor. The first end of the fourth capacitor is electrically connected to the first end of the eleventh resistor and the source of the third PMOS field-effect transistor. The second end of the fourth capacitor is electrically connected to the second end of the eleventh resistor and the gate of the third PMOS field-effect transistor.

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