Weak light type energy management circuit structure

Abstract

The utility model discloses a weak light type energy management circuit structure belongs to solar cell technical field, including solar panel assembly, capacitor power module, battery power module, circuit management module and load end. The weak light type energy management circuit structure, through battery power module and capacitor power module cooperation circuit management module, realize capacitor power module to load power supply when strong light, capacitor power module to load power supply when short -term weak light, battery power module to load power supply when long -term weak light no light, through PMOS pipe, energy storage capacitor and voltage detection chip, through voltage detection chip detection energy storage capacitor voltage, cooperation PMOS pipe realizes energy storage capacitor full charge automatic opening solar panel assembly, compared with prior art device, avoided the problem that low -power solar circuit could not normally work under weak light environment, improved practicality.

Description

Technical Field

[0001] This utility model belongs to the field of solar energy technology, and in particular relates to a low-light energy management circuit structure. Background Technology

[0002] Currently, solar power is widely used in low-power power supply scenarios due to its advantages such as simple circuit structure, convenient use and maintenance, and environmental friendliness. In recent years, the use of solar cells in the Internet of Things (IoT) field has been increasing.

[0003] Existing solar power generation modules often fail to provide sufficient voltage to meet load demands during periods of low light, leading to power outages and potential disconnections at the load end. While some existing technologies utilize boost converters to increase voltage and meet load requirements, these are expensive and energy-intensive, making them unsuitable for low-power circuits.

[0004] To address this issue, we propose a low-light energy management circuit structure. Utility Model Content

[0005] The purpose of this invention is to solve the problem that low-light solar circuits are difficult to operate normally in the prior art, and to propose a low-light energy management circuit structure.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A low-light energy management circuit structure includes a solar panel assembly, a capacitor power supply module, a battery power supply module, a circuit management module, and a load terminal. The circuit management module includes a PMOS transistor, a voltage detection chip, a Zener diode, a first resistor, and a second resistor. The first and second resistors are connected in series. One end of the first resistor is connected to the positive terminal of the solar panel assembly, and the other end of the second resistor is grounded. The gate of the PMOS transistor is connected to the voltage divider point between the first and second resistors. The source of the PMOS transistor is connected to the positive terminal of the solar panel assembly, and the drain of the PMOS transistor is connected to the capacitor power supply module. The detection terminal of the voltage detection chip is connected to the drain of the PMOS transistor, and the output terminal of the voltage detection chip is connected to the gate of the PMOS transistor via the Zener diode. The capacitor power supply module includes an energy storage capacitor. The positive terminal of the energy storage capacitor is connected to the load terminal, and the negative terminal of the energy storage capacitor is grounded. The drain of the PMOS transistor is connected to the positive terminal of the energy storage capacitor. The battery power supply module includes a battery. The positive terminal of the battery is connected to the load terminal via a third diode, and the negative terminal of the battery is grounded.

[0008] Preferably, a first diode is connected in series between the positive terminal of the energy storage capacitor and the load terminal.

[0009] Preferably, a second diode is connected in series between the drain of the PMOS transistor and the positive terminal of the energy storage capacitor.

[0010] Preferably, a third diode is connected in series between the positive terminal of the battery and the load terminal.

[0011] Preferably, the voltage detection chip has a second capacitor connected to its detection terminal, and the other end of the second capacitor is grounded.

[0012] Preferably, a third capacitor is connected to the source of the PMOS transistor, and a third resistor is connected in series at the other end of the third capacitor. The other end of the third resistor is connected to the drain of the PMOS transistor.

[0013] In summary, the technical effects and advantages of this utility model are as follows: This low-light energy management circuit structure, through the cooperation of a battery power supply module and a capacitor power supply module with a circuit management module, enables the capacitor power supply module to supply power to the load during strong light, during short periods of weak light, and during long periods of weak light or no light. Through a PMOS transistor, an energy storage capacitor, and a voltage detection chip, the voltage of the energy storage capacitor is detected by the voltage detection chip, and the solar panel assembly is automatically disconnected when the energy storage capacitor is fully charged, in conjunction with the PMOS transistor. Compared with existing devices, this avoids the problem of low-power solar circuits failing to function properly in low-light environments, thus improving practicality. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of this utility model. Detailed Implementation

[0015] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.

[0016] Reference Figure 1A low-light energy management circuit structure includes a solar panel assembly, a capacitor power supply module, a battery power supply module, a circuit management module, and a load terminal. The circuit management module includes a PMOS transistor Q1, a voltage detection chip U1, a Zener diode D4, a first resistor R1, and a second resistor R2. The first resistor R1 and the second resistor R2 are connected in series. The other end of the first resistor R1 is connected to the positive terminal of the solar panel assembly, and the other end of the second resistor R2 is grounded. The gate G of the PMOS transistor Q1 is connected to the voltage divider point between the first resistor R1 and the second resistor R2. The source S of the PMOS transistor Q1 is connected to the positive terminal of the solar panel assembly, and the drain D of the PMOS transistor Q1 is connected to the capacitor power supply module. The voltage detection chip U1 can be a BD5250G-1TR. The detection terminal of the voltage detection chip U1 is connected to the drain D of the PMOS transistor Q1, and the output terminal of the voltage detection chip U1 is connected to the gate G of the PMOS transistor Q1 via the Zener diode D4. The capacitor-powered module includes an energy storage capacitor C1. The positive terminal of C1 is connected to the load, and the negative terminal is grounded. The drain (D) of the PMOS transistor Q1 is connected to the positive terminal of C1. C1 should be a supercapacitor, and its voltage should be lower than the open-circuit voltage of the solar panel module. The battery-powered module includes a battery BAT. The positive terminal of BAT is connected to the load through a third diode D3, and the negative terminal is grounded.

[0017] This low-light energy management circuit structure charges the energy storage capacitor C1 and supplies power to the load during periods of strong sunlight. During short periods of weak or no light, the energy storage capacitor C1 supplies power to the load. When the weak light lasts for an extended period, the energy storage capacitor C1 is depleted, and the battery BAT supplies power to the load. A voltage detection chip monitors the voltage of the energy storage capacitor. When the capacitor is fully charged, it drives the PMOS transistor to disconnect, automatically disconnecting the solar panel when C1 is fully charged, thus preventing overcharging of the energy storage capacitor.

[0018] A first diode D1 is connected in series between the positive terminal of the energy storage capacitor C1 and the load terminal. The first diode D1 prevents the energy storage capacitor C1 from being damaged by reverse input current from the load side, thereby improving the working stability and safety of the energy storage capacitor C1.

[0019] A second diode D2 is connected in series between the drain D of PMOS transistor Q1 and the positive terminal of energy storage capacitor C1. The second diode D2 prevents the energy storage capacitor C1 from being reverse-biased into the solar panel module and the circuit management module, thereby improving the working stability and safety of the solar panel module.

[0020] A third diode D3 is connected in series between the positive terminal of the battery BAT and the load terminal. The third diode D3 prevents the load terminal from inputting reverse current into the battery BAT, which could damage the battery BAT and improves the working stability and safety of the battery BAT.

[0021] The voltage detection chip U1 has a second capacitor C2 connected to its detection terminal. The other end of the second capacitor C2 is grounded. The second capacitor C2 is used to filter and reduce noise at the input terminal of the voltage detection chip U1, thereby reducing the influence of interference signals and improving the working stability of the voltage detection chip U1.

[0022] A third capacitor C3 is connected to the source S of PMOS transistor Q1. A third resistor R3 is connected in series at the other end of the third capacitor C3. The other end of the third resistor R3 is connected to the drain D of PMOS transistor Q1. When PMOS transistor Q1 is turned off, the voltage at its drain D rises sharply due to the inductive load. The third capacitor C3 reduces the peak voltage. The third resistor R3 is connected in series in the discharge circuit, which limits the magnitude of the charging and discharging current of the third capacitor C3 and dissipates the peak energy absorbed by the third capacitor C3 as heat, thus improving practicality.

[0023] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A low-light power management circuit structure, characterized in that, The system includes a solar panel assembly, a capacitor power supply module, a battery power supply module, a circuit management module, and a load terminal. The circuit management module includes a PMOS transistor, a voltage detection chip, a Zener diode, a first resistor, and a second resistor. The first resistor and the second resistor are connected in series. The other end of the first resistor is connected to the positive terminal of the solar panel assembly, and the other end of the second resistor is grounded. The gate of the PMOS transistor is connected to the voltage divider point between the first and second resistors. The source of the PMOS transistor is connected to the positive terminal of the solar panel assembly, and the drain of the PMOS transistor is connected to the capacitor power supply module. The voltage detection chip's detection terminal is connected to the drain of the PMOS transistor, and the output terminal of the voltage detection chip is connected to the gate of the PMOS transistor via a Zener diode; the capacitor power supply module includes an energy storage capacitor, the positive terminal of which is connected to the load terminal, the negative terminal of which is grounded, and the drain of the PMOS transistor is connected to the positive terminal of the energy storage capacitor; the battery power supply module includes a battery, the positive terminal of which is connected to the load terminal via a third diode, and the negative terminal of which is grounded.

2. The low-light power management circuit structure according to claim 1, characterized in that, A first diode is connected in series between the positive terminal of the energy storage capacitor and the load terminal.

3. The low-light power management circuit structure according to claim 1, characterized in that, A second diode is connected in series between the drain of the PMOS transistor and the positive terminal of the energy storage capacitor.

4. The low-light power management circuit structure according to claim 1, characterized in that, A third diode is connected in series between the positive terminal of the battery and the load terminal.

5. The low-light power management circuit structure according to claim 1, characterized in that, The voltage detection chip has a second capacitor connected to its detection terminal, and the other end of the second capacitor is grounded.

6. The low-light power management circuit structure according to claim 1, characterized in that, A third capacitor is connected to the source of the PMOS transistor, and a third resistor is connected in series at the other end of the third capacitor. The other end of the third resistor is connected to the drain of the PMOS transistor.

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