A power supply circuit suitable for HART digital communication

Abstract

The utility model belongs to HART circuit technical field especially relates to a power supply circuit suitable for HART digital communication, its characterized in that, including charge pump circuit U101, LDO integrated circuit U102 and loop transmitter U103. The utility model has the beneficial effects that: 1) voltage ripple is small: power supply passes through LDO primary voltage conversion current, then passes through charge pump inversion output, improves conversion efficiency, and ripple voltage is less than 50mV, and the bandwidth is not in digital filter ripple 38.3mV;The ripple of digital filter output is less than or equal to 17.2mV, and the output noise is low, and does not interfere with HART digital communication;2) low power consumption: the overall static current is not greater than 450uA;3) the output power is big: the maximum short-circuit output current can reach 35mA (24VDC loop current) under the condition that ripple is less than 50mV;4) the heat quantity is few: the component surface temperature rise does not exceed 50 DEG C under the working condition of 22mA load in the nominal voltage 24VDC.

Description

Technical Field

[0001] This utility model belongs to the field of HART circuit technology, and specifically relates to a power supply circuit suitable for HART digital communication. Background Technology

[0002] Industrial process control systems (IPS) are systems that use automation technology to control parameters such as temperature, pressure, and flow rate in industrial production in real time. They are broadly classified into two categories: conventional instrumentation systems and computer control systems. Their core function is to ensure the stability and efficiency of the production process, and they are widely used in continuous industrial sectors such as petrochemicals, power generation, and metallurgy. The HART module is an interface module for industrial automation equipment that integrates analog signal and digital communication transmission based on the HART protocol. This module transmits signals by superimposing a modulated sinusoidal signal onto a 4-20mA DC analog signal, making it compatible with both traditional analog control systems and digital communication requirements. In terms of hardware implementation, the module uses the RTS pin to control modulation / demodulation mode switching and supports data interaction with microcontrollers or PLC systems. Typical applications include the integration of Siemens SM331 series modules with intelligent instruments, connecting to an industrial bus DCS system via a DP / PA coupler to monitor and control process variables such as pressure and temperature.

[0003] Power management integrated circuits play a crucial role in modern electronic systems, particularly in 5G communications, the Internet of Things, new energy vehicles, and mobile terminal devices.1 With continuous advancements in semiconductor technology and system-in-package (SiP) technology, power management chips are evolving towards higher efficiency, lower noise, and higher integration. Against this backdrop, a hybrid topology combining a charge pump and a low-dropout linear regulator (LDO) has emerged, offering an innovative approach to resolving the efficiency-noise trade-off in traditional power architectures. In recent years, research on this hybrid topology has shown several distinct trends: First, capacitor-free design has become a hot topic. For example, Peng Yu's capacitor-free NMOS LDO combined with a charge pump achieves 1.2-5V adjustable output and a load capacity of 400mA by using a folded cascode amplifier and a novel cross-coupled charge pump structure, without requiring external compensation capacitors. Second, dynamic performance optimization is emphasized. For instance, research from Hefei University of Technology uses adaptive bias technology and auxiliary power transistor design to improve the transient response of the hybrid architecture, making the overshoot voltage less than 120mV when the load current jumps between 0-100mA. Third, high integration is prevalent. Chips such as MAX8821 and AAT2842 integrate charge pumps, multiple LDOs, and even audio amplifiers into a single package, greatly simplifying the power supply design of portable devices.

[0004] Currently, voltage conversion circuits use DC-DC or LDO topologies. In the field of HART digital communication, although the DC-DC structure can provide sufficient power and conversion efficiency, it generally suffers from large ripple and noise, which often interferes with HART digital communication and affects the success rate of communication. On the other hand, although the LDO structure has small ripple and low noise, it generally provides less power, has low conversion efficiency, and generates more heat. All of these factors limit the safe application of power supply circuits. Utility Model Content

[0005] The purpose of this invention is to provide a power supply circuit suitable for HART digital communication, which overcomes the shortcomings of the existing technology, abandons the DC-DC switching power supply structure, and adopts a brand-new circuit topology structure that combines a charge pump with an inverted output and an LDO. It absorbs the advantages of low output ripple of the LDO, and combines a charge pump to replace the DC-DC switching power supply, thereby improving conversion efficiency, reducing output noise, and achieving the goals of low output voltage ripple, high power, low power consumption, and no impact on HART digital communication.

[0006] To achieve the above objectives, this utility model employs the following technical solution: A power supply circuit suitable for HART digital communication includes a charge pump circuit U101, an LDO integrated circuit U102, and a loop transmitter U103. Pin 7 of the loop transmitter U103 is connected to the 24V input voltage node, one end of capacitor C102, and the collector of pin 2 of transistor Q101. Pin 4 of the loop transmitter U103 is connected to the 0V input voltage node and the other end of capacitor C102. The emitter of pin 3 of transistor Q101 is connected to pin 5 of the loop transmitter U103, and the base of pin 1 of transistor Q101 is connected to the loop transmitter U103. Pin 6 of circuit 03 and pin 4 of transistor Q101 (heat dissipation pin) are shorted to the collector of pin 2 of transistor Q101. Pin 1 of loop transmitter U103 is connected to the VREF node, pin 2 of loop transmitter U103 is connected to the DACIN node, pin 3 of loop transmitter U103 is grounded, pin 8 of loop transmitter U103 is connected to one end of resistor R102, the other end of resistor R102 is connected to one end of capacitor C103, and the other end of capacitor C103 is connected to both ground and GND nodes. The VDD node is connected to pin 4 of charge pump circuit U101 and the voltage regulator diode. The positive terminal of transistor D104 and one end of capacitor C107, with the 24V input voltage node, are connected to pins 5 and 8 of LDO integrated circuit U102, respectively. Pin 1 of LDO integrated circuit U102 is connected to one end of capacitor C106, one end of resistor R101, the negative terminals of Zener diodes D101-D103, one end of capacitor C101, pin 2 of charge pump circuit U101, and the negative terminal of Zener diode D104. Pin 2 of LDO integrated circuit U102 is connected to the other end of capacitor C106, the other end of resistor R101, and resistor R1... At one end of 03, pin 6 of LDO integrated circuit U102 is connected to one end of capacitor C105. Pin 4 of LDO integrated circuit U102 is connected to the other end of capacitor C105, the other end of resistor R103, the positive terminals of Zener diodes D101-D103, the other end of capacitor C101, one end of power-on spike current choke E101, and the other end of capacitor C107, and grounded. Pin 1 of charge pump circuit U101 is connected to the other end of power-on spike current choke E101. Capacitor C104 is connected between pins 3 and 5 of charge pump circuit U101.

[0007] Furthermore, the VDD node, GND node, VREF node, and DACIN node are connected to pins 1, 2, 3, and 4 of the XF101 pin header socket in sequence.

[0008] Furthermore, the 24V input voltage node is connected to pins 1 and 3 of the pin header socket XF102, and the 0V input voltage node is connected to pin 2 of the pin header socket XF102.

[0009] Furthermore, the charge pump circuit U101 is model TPS60403.

[0010] Furthermore, the LDO integrated circuit U102 is model number TPS7A4901.

[0011] Furthermore, the loop transmitter U103 is model XTR115.

[0012] Furthermore, the Zener diode is model number 1N5923B.

[0013] Furthermore, the power-on spike current controller is model LB2012T680K.

[0014] Compared with the prior art, the beneficial effects of this utility model are: 1) Low voltage ripple: The power supply converts the primary voltage of the LDO into current, and then the output is inverted by the charge pump, improving conversion efficiency. The ripple voltage is less than 50mV, and the ripple within the bandwidth without digital filtering is ≤38.3mV. According to the Fieldbus Foundation physical layer test specification document "HCF_TEST-002", the output voltage noise without digital filtering must be less than 138mV. This design circuit has an output ripple of ≤38.3mV without digital filtering, which fully meets the requirements. According to the Fieldbus Foundation physical layer test specification document "HCF_TEST-002", the ripple within the bandwidth after digital filtering must be less than 22mV. This design circuit has an output ripple of ≤17.2mV after digital filtering, which fully meets the requirements. The output noise is low and does not interfere with HART digital communication. 2) Low power consumption: The overall static current is no more than 450uA, which is very suitable for HART communication scenarios that require low power consumption; 3) High output power: The maximum short-circuit output current can reach 35mA when the ripple is less than 50mV; 4) Low heat generation: Under the nominal voltage of 24VDC and 22mA load, the surface temperature rise of the component does not exceed 50℃. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the circuit principle of an embodiment of this utility model; Figure 2 This is the actual output voltage noise spectrum of an embodiment of this utility model; Figure 3 This is a photograph of an actual embodiment of this utility model. Detailed Implementation

[0016] The technical solution of this utility model will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are some embodiments of this utility model, but not all embodiments.

[0017] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the specific embodiments used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the specific embodiments described below are some embodiments of this utility model. For those skilled in the art, other specific embodiments can be obtained based on these specific embodiments without creative effort.

[0018] The components of the present invention described and shown in the specific embodiments herein can be arranged and designed in numerous different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the specific embodiments is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention.

[0019] See Figure 1-3This is a schematic diagram of a power supply circuit embodiment for HART digital communication according to this utility model. It includes a charge pump circuit U101, an LDO integrated circuit U102, and a loop transmitter U103. Pin 7 of the loop transmitter U103 is connected to the 24V input voltage node, one end of capacitor C102, and the collector of pin 2 of transistor Q101. Pin 4 of the loop transmitter U103 is connected to the 0V input voltage node and the other end of capacitor C102. The emitter of pin 3 of transistor Q101 is connected to pin 5 of the loop transmitter U103. Pin 1 of transistor Q101 is connected to the base... The circuit connects to pin 6 of loop transmitter U103, and shorts the heat dissipation pin of transistor Q101 (pin 4) to the collector of pin 2. Pin 1 of loop transmitter U103 is connected to the VREF node, pin 2 is connected to the DACIN node, pin 3 is grounded, pin 8 is connected to one end of resistor R102, the other end of resistor R102 is connected to one end of capacitor C103, and the other end of capacitor C103 is connected to both ground and GND nodes. The VDD node is connected to the charge pump circuit U101. Pin 4, the positive terminal of Zener diode D104, and one end of capacitor C107 are connected to pins 5 and 8 of LDO integrated circuit U102, respectively. Pin 1 of LDO integrated circuit U102 is connected to one end of capacitor C106, one end of resistor R101, the negative terminals of Zener diodes D101-D103, one end of capacitor C101, pin 2 of charge pump circuit U101, and the negative terminal of Zener diode D104. Pin 2 of LDO integrated circuit U102 is connected to the other end of capacitor C106, the other end of resistor R101, and the positive terminal of capacitor C106. One end of resistor R103 is connected to pin 6 of LDO integrated circuit U102, which is connected to one end of capacitor C105. Pin 4 of LDO integrated circuit U102 is connected to the other end of capacitor C105, the other end of resistor R103, the positive terminals of Zener diodes D101-D103, the other end of capacitor C101, one end of power-on peak current suppressor E101, and the other end of capacitor C107, and grounded. Pin 1 of charge pump circuit U101 is connected to the other end of power-on peak current suppressor E101, and capacitor C104 is connected between pins 3 and 5 of charge pump circuit U101. Zener diode D104 acts as a clamping element in secondary output voltage control, stabilizing the frequency divider output voltage when overvoltage breakdown occurs.

[0020] To facilitate the selection of circuit nodes, the VDD, GND, VREF, and DACIN nodes are connected to pins 1, 2, 3, and 4 of the XF101 pin header socket, respectively. The 24V input voltage node is connected to pins 1 and 3 of the XF102 pin header socket, and the 0V input voltage node is connected to pin 2 of the XF102 pin header socket.

[0021] The charge pump circuit U101, model TPS60403, uses a frequency divider design on its input voltage (7.4V) and employs an inverted output to reverse the voltage, ultimately obtaining a 3.7VDC output voltage with a ripple voltage less than 50mV. The ripple is no greater than 50mV; inverting the charge pump output reverses the negative voltage. This invention innovatively inverts the charge pump output, using the GND terminal of U101 as the output to obtain a positive voltage. This results in low ripple, high power, a 3.7V output, and a maximum output current of 35mA. A charge pump, also known as a switched-capacitor voltage converter, is a DC-DC converter that uses a so-called "flying" or "pumping" capacitor (rather than an inductor or transformer) to store energy. A charge pump is a DC-DC converter that uses capacitors as energy storage elements, mostly used to generate an output voltage higher than the input voltage or a negative output voltage. Charge pump circuits have high electrical efficiency, approximately 90-95%.

[0022] The LDO integrated circuit U102, model number TPS7A4901, uses a resistor divider feedback network to convert the input voltage of 24V DC to a 7.4VDC primary output. This conversion reduces output noise ripple, and the 16.6VDC voltage drop significantly reduces heat generation, keeping it below 50℃ without surface sealing. The primary output voltage of U102 is isolated by triple voltage isolation design using D101, D102, and D103, ensuring that the output voltage does not exceed 8.62VDC under short-circuit conditions. A low-dropout regulator (LDO), also known as a low-dropout linear regulator or low-voltage regulator, is a type of linear DC regulator used to provide a stable DC voltage. Compared to typical linear DC regulators, LDOs can operate with a smaller output-input voltage difference.

[0023] The loop transmitter U103 is model XTR115. The integrated circuit U103 controls the entire loop current via the DAC_IN pin, allowing for constant current supply or dynamic current output as a HART carrier signal carrier. The U103 is an XTR11x 4-20mA current loop transmitter, a precision current output converter that transmits analog 4mA to 20mA signals via a general-purpose current loop. These devices provide precise current regulation and output current limiting. An on-chip regulator (5V) can be used to power external circuitry. A precision on-chip VREF (2.5V for XTR115, 4.096V for XTR116) can be used to excite or offset the sensor. The current loop pin (IRET) can detect any current used in external circuitry to precisely control the output current. The XTR11x is a fundamental building block for smart sensors using 4mA to 20mA current transmission. The XTR11x has an industrial-grade operating temperature range of –40°C to +85°C.

[0024] The Zener diode is model 1N5923B. Triple Zener diodes D101, D102, and D103 provide voltage isolation, which is beneficial for the intrinsically safe and explosion-proof design of subsequent circuits. Zener diodes utilize the reverse breakdown state of the PN junction, where the current can vary over a wide range while the voltage remains essentially constant, thus serving as a voltage regulator.

[0025] The power-on spike current choke is model LB2012T680K. The choke ring E101 suppresses the spike current at the moment of power-on (100ms). Within 100ms after power-on, the rapid charging of the charge pump can cause a spike current pulse of nearly 60mA. This is usually caused by the presence of safety barriers or cards in the HART digital signal field DCS control system, leading to a system reset. After matching with E101, the starting current can be controlled within 25mA to meet the starting requirements. The power-on spike current choke E101 can control the starting current within 100ms of power-on to within 25mA, achieving a soft-start function. The spike suppressor can suppress the rapid change of the reverse recovery current of the diode in the circuit, thereby reducing and suppressing circuit noise. The spike suppressor uses a magnetic core with a hysteresis loop to suppress the reverse recovery current. During normal conduction, the magnetic core is saturated and has very little resistance. When the current decreases and attempts to cross zero, the spike suppressor exhibits a large inductance, preventing the current from changing rapidly in the opposite direction. This suppresses spikes caused by the reverse recovery current and effectively reduces circuit noise.

[0026] In operation, the 24VDC power supply voltage is input through XF102 and connected to pins 5 and 8 of U102. A 7.4VDC voltage is output through pin 1 of U102. The output voltage value of pin 1 is controlled by the resistance values ​​of R101 and R103. C105 is used for noise reduction between pin 6 and GND, and C106 is used for noise reduction between pin 1 and pin 2. C105 and C106 can filter out noise in the bandgap, reducing the output noise by approximately 75% (from 69μVRMS to 17μVRMS). The C105 capacitor also acts as a soft-start capacitor to slow down the output rise time. The output rise time when using the C105 capacitor is: t (ms) = 1.4 * C105 (nF). t is the soft-start time in milliseconds. The 7.4VDC voltage is triple regulated by D101-D103. The triple voltage isolation design ensures that the output voltage does not exceed 8.62VDC under short-circuit conditions. Then, pin 1 is grounded through C101 to ensure stability. The capacitance value of C101 must be ≥2.2μF. The operating power supply current of U102 is 60uA, and the maximum output current can reach 150mA.

[0027] U101 reverses the voltage applied to its input terminal. This invention innovatively inverts the charge pump output, making the GND terminal of U101 the output to obtain a positive voltage. A 7.4VDC voltage is connected between pin 2 of U101 and GND, and connected to pin 1 through E101. E101 suppresses the occurrence of peak current at the moment of power-on (100ms). The output voltage is output through pin 4. The 7.4VDC voltage is divided by two using an inverted output design. The C104 capacitor between pins 3 and 5 and the C107 capacitor between pin 4 and GND are used to divide the input voltage by two, finally obtaining a 3.7VDC output voltage with a ripple voltage of less than 50mV and a maximum output current of 35mA. D104 provides a 5.6V clamping voltage to ensure that U101 will not be damaged when the voltage fluctuates. The thermal resistance of U101 is RΘJA = 221°C / W. The maximum temperature rise of the chip is calculated to be 10°C, resulting in low heat generation.

[0028] U103 is a loop transmitter. Its input is the voltage signal connected to XF101. It outputs a 4-20mA current signal through pin 4 and a 2.5V reference voltage signal through pin 8. Q101 provides most of the current at full scale. When the loop voltage is 40V and the output current is 20mA, the power consumption of this transistor is 0.8W. An external transistor is used to avoid on-chip thermal errors. The heat it generates can still cause ambient temperature changes that may affect XTR115. To reduce this impact, it is placed away from sensitive analog circuitry.

[0029] See Figure 2 Connect the positive terminal of the oscilloscope probe to pin 1 (VDD) of the XF101 and the negative terminal of the probe to pin 2 (GND) of the XF101. Use the AC coupling function to observe the output voltage noise waveform. The second channel shows the output noise ripple without digital filtering = 38.3mV, and the third channel shows the output noise ripple after digital filtering = 17.2mV, which fully complies with the noise limit requirements in the Fieldbus Foundation physical layer test specification document "HCF_TEST-002".

[0030] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A power supply circuit suitable for HART digital communication, characterized in that, The circuit includes a charge pump circuit U101, an LDO integrated circuit U102, and a loop transmitter U103. Pin 7 of the loop transmitter U103 is connected to the 24V input voltage node, one end of capacitor C102, and the collector of pin 2 of transistor Q101. Pin 4 of the loop transmitter U103 is connected to the 0V input voltage node and the other end of capacitor C102. The emitter of pin 3 of transistor Q101 is connected to pin 5 of the loop transmitter U103, and the base of pin 1 of transistor Q101 is connected to the loop transmitter... Pin 6 of transducer U103 and pin 4 of transistor Q101 are shorted to the collector of pin 2 of transistor Q101. Pin 1 of loop transmitter U103 is connected to the VREF node, pin 2 of loop transmitter U103 is connected to the DACIN node, pin 3 of loop transmitter U103 is grounded, pin 8 of loop transmitter U103 is connected to one end of resistor R102, the other end of resistor R102 is connected to one end of capacitor C103, and the other end of capacitor C103 is connected to the ground and GND nodes respectively. The VDD node is connected to pin 4 of charge pump circuit U101, the positive terminal of Zener diode D104, and one end of capacitor C107. The 24V input voltage node is connected to pins 5 and 8 of LDO integrated circuit U102. Pin 1 of LDO integrated circuit U102 is connected to one end of capacitor C106, one end of resistor R101, the negative terminals of Zener diodes D101-D103, one end of capacitor C101, pin 2 of charge pump circuit U101, and the negative terminal of Zener diode D104. Pin 2 of LDO integrated circuit U102 is connected to the other end of capacitor C106 and resistor R107. The other end of 101 and one end of resistor R103, pin 6 of LDO integrated circuit U102 is connected to one end of capacitor C105, pin 4 of LDO integrated circuit U102 is connected to the other end of capacitor C105, the other end of resistor R103, the positive terminals of Zener diodes D101-D103, the other end of capacitor C101, one end of power-on spike current choke E101 and the other end of capacitor C107 and grounded; pin 1 of charge pump circuit U101 is connected to the other end of power-on spike current choke E101, and capacitor C104 is connected between pins 3 and 5 of charge pump circuit U101.

2. A power supply circuit suitable for HART digital communication according to claim 1, characterized in that, The VDD node, GND node, VREF node, and DACIN node are connected to pins 1, 2, 3, and 4 of the XF101 pin header socket, respectively.

3. A power supply circuit suitable for HART digital communication according to claim 1, characterized in that, The 24V input voltage node is connected to pins 1 and 3 of the pin header socket XF102, and the 0V input voltage node is connected to pin 2 of the pin header socket XF102.

4. A power supply circuit suitable for HART digital communication according to claim 1, characterized in that, The charge pump circuit U101 is model TPS60403.

5. A power supply circuit suitable for HART digital communication according to claim 1, characterized in that, The LDO integrated circuit U102 is model TPS7A4901.

6. A power supply circuit suitable for HART digital communication according to claim 1, characterized in that, The loop transmitter U103 is model XTR115.

7. A power supply circuit suitable for HART digital communication according to claim 1, characterized in that, The Zener diode is model 1N5923B.

8. A power supply circuit suitable for HART digital communication according to claim 1, characterized in that, The power-on peak current controller is model LB2012T680K.

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