Clock signal generation circuit, signal transmission circuit, chip, audio module and electronic device

Abstract

The application relates to the technical field of electronic circuits, and provides a clock signal generation circuit, a signal transmission circuit, a chip, an audio module and electronic equipment. The clock signal generation circuit comprises a clock signal source, a programmable counter and N clock branches. The clock signal source is used for providing a main clock signal, and the programmable counter is connected with the clock signal source. Each clock branch is used for outputting N target clock signals based on the same reference clock signal according to a preset clock signal period based on the reference clock signal. Because the N target clock signals are obtained based on the same reference clock signal, each target clock signal naturally has the characteristic of phase alignment, so the phase alignment of clock signals between multiple transmission links can be ensured, thereby providing a clock signal generation scheme with a wider application range.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a clock signal generation circuit, a signal transmission circuit, a chip, an audio module, and an electronic device. Background Technology

[0002] Inter-IC Sound (I2S) is a bus standard designed for data transmission. Due to its lossless and high word width characteristics, the I2S bus interface is widely used in multi-channel data transmission and interaction scenarios. The I2S bus standard uses separate wires to transmit clock and data signals, avoiding distortion caused by time differences by separating the data and clock signals. For example, in audio data transmission scenarios, using the I2S bus interface can save users the cost of purchasing specialized equipment to combat audio jitter.

[0003] However, in multi-transmission links, different transmission links typically use their own clock signals. Here, the clock signals refer to the bit clock signal BCLK and the frame clock signal LRCLK. Therefore, even if clock signals with the same parameters are configured for different transmission links, it is difficult to guarantee that the clock signals between different transmission links will be in phase alignment. Thus, providing a solution that can guarantee the phase alignment of clock signals between multiple transmission links is a problem that urgently needs to be solved in this field. Utility Model Content

[0004] The purpose of this application is to provide a clock signal generation circuit, a signal transmission circuit, a chip, an audio module, and an electronic device, aiming to provide a clock signal generation scheme that can guarantee clock signal alignment between multiple transmission links and has a wider range of applications.

[0005] A first aspect of this application provides a clock signal generation circuit, including: Clock signal source, used to provide the master clock signal; A presettable counter is connected to a clock signal source. The presettable counter includes at least N reference signal output terminals. The presettable counter is used to output a reference clock signal through the N reference signal output terminals according to the master clock signal; where N is an integer greater than 1. N clock branches are connected to N reference signal output terminals respectively. The clock branches are used to output the corresponding target clock signal based on the reference clock signal according to the preset clock signal period.

[0006] This application provides a clock signal generation circuit, including a clock signal source, a presettable counter, and N clock branches. The clock signal source provides a master clock signal, and the presettable counter is connected to the clock signal source. Since the presettable counter includes at least N reference signal output terminals, the N clock branches can be connected to each of the N reference signal output terminals. Because the presettable counter outputs a reference clock signal through the N reference signal output terminals based on the master clock signal, the N clock branches can synchronously receive the reference clock signal. Therefore, by using each clock branch according to a preset clock signal period based on the reference clock signal, N target clock signals derived from the same reference clock signal can be output. In this way, not only can target clock signals be provided for multiple transmission links, but also, because the N target clock signals are derived from the same reference clock signal, each target clock signal naturally has phase alignment characteristics, thus ensuring phase alignment of clock signals between multiple transmission links, thereby providing a clock signal generation scheme with a wider range of applications.

[0007] A second aspect of this application provides a signal transmission circuit, including the clock signal generation circuit provided in the first aspect; and There are N communication units, each connected to one of N clock branches. The target clock signal output by the clock branches to the communication units is either a bit clock signal or a frame clock signal; or There are at least two communication units, each of which is connected to two clock branches. The two sets of target clock signals output by the two clock branches are a bit clock signal and a frame clock signal, respectively.

[0008] A third aspect of this application provides a chip that includes the clock signal generation circuit provided in the first aspect; and / or The chip includes the signal transmission circuit provided in the second aspect above.

[0009] A fourth aspect of this application provides an audio module, including the signal transmission circuit provided in the third aspect above; and A signal processing unit, connected to each communication unit, is used to process the signal to be processed upon receiving it from the communication unit; and / or The audio module includes the chip provided in the third aspect mentioned above.

[0010] The fifth aspect of this application provides an electronic device, including at least one of the clock signal generation circuit provided in the first aspect, the signal transmission circuit provided in the second aspect, the chip provided in the third aspect, and the audio module provided in the fourth aspect.

[0011] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a clock signal generation circuit provided in an embodiment of this application; Figure 2 A schematic diagram of the specific structure of a signal generation circuit provided in this application embodiment. Figure 1 ; Figure 3 A schematic diagram of the specific structure of a signal generation circuit provided in this application embodiment. Figure 2 ; Figure 4 This is a schematic diagram of a signal transmission circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of a signal transmission circuit according to another embodiment of this application; Figure 6 This is a schematic diagram of the structure of an audio module provided in an embodiment of this application. Detailed Implementation

[0013] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0014] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0015] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0016] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0017] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0018] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0019] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0020] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0021] For example, the Integrated Circuit Built-in Audio Bus (Inter-IC Sound, I2S) is a bus standard developed for data transmission. Due to its lossless and high word width characteristics, the I2S bus interface is widely used in scenarios involving multi-channel data transmission and interaction. The I2S bus standard uses separate wires to transmit clock and data signals, avoiding distortion caused by time differences by separating the data and clock signals. Taking audio data transmission as an example, using the I2S bus interface can save users the cost of purchasing specialized equipment to combat audio jitter.

[0022] For example, a standard I2S bus cable consists of three serial wires, which may include: one time division multiplexing (TDM) data line; one word select line, i.e., frame clock signal line; and one clock line, i.e. bit clock signal line.

[0023] However, in multi-transmission links, different transmission links typically use their own clock signals. Here, the clock signals refer to the bit clock signal BCLK and the frame clock signal LRCLK. Therefore, even if clock signals with the same parameters are configured for different transmission links, it is difficult to guarantee that the clock signals between different transmission links will be in phase alignment. Thus, providing a solution that can guarantee the phase alignment of clock signals between multiple transmission links is a problem that urgently needs to be solved in this field.

[0024] To address the aforementioned technical problems, this application provides a clock signal generation circuit, including a clock signal source, a presettable counter, and N clock branches. The clock signal source provides a master clock signal, and the presettable counter is connected to the clock signal source. Since the presettable counter includes at least N reference signal output terminals, the N clock branches can be connected to each of the N reference signal output terminals. Furthermore, because the presettable counter outputs a reference clock signal through the N reference signal output terminals based on the master clock signal, the N clock branches can synchronously receive the reference clock signal. Therefore, by using each clock branch according to a preset clock signal period based on the reference clock signal, N target clock signals derived from the same reference clock signal can be output. In this way, not only can target clock signals be provided for multiple transmission links, but also, because the N target clock signals are derived from the same reference clock signal, each target clock signal naturally possesses phase alignment characteristics, thus ensuring phase alignment of clock signals between multiple transmission links, thereby providing a clock signal generation scheme with a wider range of applications.

[0025] See Figure 1 , Figure 1 A schematic diagram of a clock signal generation circuit according to an embodiment of this application is shown. Figure 1As shown, the clock signal generation circuit 100 includes: a clock signal source 10, a presettable counter 20, and N clock branches 30. Specifically: A clock signal source 10 provides a master clock signal. A presettable counter 20 is connected to the clock signal source 10 and includes at least N reference signal output terminals 21. The presettable counter 20 outputs a reference clock signal through the N reference signal output terminals according to the master clock signal; where N is an integer greater than 1. N clock branches 30 are respectively connected to the N reference signal output terminals 21. The clock branches 30 output a corresponding target clock signal based on the reference clock signal according to a preset clock signal period.

[0026] In this embodiment, the master clock signal provided by the clock signal source 10 can be used as the reference clock signal for the clock signal generation circuit 100. That is, in the process of generating the target clock signal using the clock signal generation circuit 100, the master clock signal provided by the clock signal source 10 is used as the basis. In specific implementation, the clock signal source 10 can be implemented using an existing crystal oscillator clock circuit.

[0027] exist Figure 1 In the circuit, a presettable counter 20 is connected between a clock signal source 10 and N clock branches 30, and the presettable counter 20 takes the master clock signal as input and outputs N reference clock signals according to the master clock signal.

[0028] For example, in a specific implementation, the presettable counter 20 can be implemented using an existing resettable counter. For instance, the presettable counter 20 may include a counter with a modulus of M, which can count according to the master clock signal and reset the count value when the count value reaches M.

[0029] It is easy to understand that since the presettable counter 20 includes at least N reference signal output terminals 21, the N clock branches 30 can be connected one-to-one with the N reference signal output terminals 21. In this way, the N reference clock signals output by the presettable counter 20 through the N reference signal output terminals 21 can be used as input signals for the N clock branches 30. Since the N reference clock signals output through the N reference signal output terminals 21 are based on the same master clock signal, they naturally possess phase alignment characteristics.

[0030] In this embodiment, each clock branch 30 is pre-configured with a preset clock signal period, which is used to indicate the signal period of the target clock signal output by the clock branch 30. Here, the signal period of the reference clock signal can be regarded as the minimum unit period, and the signal period of the target clock signal can be a multiple of the signal period of the reference clock signal. Based on this, in the process of outputting the target clock signal using the clock branch 30, the preset clock signal period corresponding to each clock branch 30 can be determined based on the multiple relationship between the signal period of the target clock signal and the signal period of the reference clock signal.

[0031] It is easy to understand that the clock signal period corresponding to each of the N clock branches may be the same or different.

[0032] For example, in a specific implementation, the preset clock signal period corresponding to each clock branch 30 can be represented by the number of unit cycles of the reference clock signal, or it can be implemented by corresponding the flip time of the target clock signal with the number of unit cycles of the reference clock signal.

[0033] For example, the preset clock signal period can be Y times the unit period of the quasi-clock signal (Y equals an integer greater than 1), that is, when the clock branch 30 receives a reference clock signal of Y unit periods, it outputs a target clock signal of 1 period.

[0034] Taking Y as 32 as an example, the clock signal period corresponding to clock branch 30 is 32 times the number of unit cycles of the reference clock signal. When clock branch 30 receives a reference clock signal of 16 unit cycles, the signal is flipped. When clock branch 30 receives a reference clock signal of 32 unit cycles, a target clock signal of 1 cycle is output. In this embodiment, the period of the output target clock signal is 32 times the number of unit cycles of the reference clock signal.

[0035] For example, the preset clock signal period can be represented by the number of unit cycles Q of the reference clock signal corresponding to the flip time of the target clock signal, where Q = Y / 2. That is, the preset clock signal period is Q times half a unit cycle of the quasi-clock signal. During the process of receiving the reference clock signal of the first unit cycle to the reference clock signal of the Q-1th unit cycle in the clock branch 30, the target clock signal of the first half cycle is output. When the reference clock signal of the Qth unit cycle is received, the signal flips, and then the target clock signal of the second half cycle is output.

[0036] Taking Y = 32 and Q = 16 as an example, during the process of receiving the reference clock signal from the first unit cycle to the fifteenth unit cycle, clock branch 30 outputs the target clock signal for the first half cycle. When it receives the reference clock signal for the sixteenth unit cycle, it performs a signal flip and then outputs the target clock signal for the second half cycle. The period of the target clock signal output in this embodiment is also 32 times the number of unit cycles of the reference clock signal.

[0037] The above scheme utilizes a presettable counter 20 to output N reference clock signals through N reference signal output terminals 21 based on the master clock signal. This allows the N clock branches 30 to synchronously receive the N reference clock signals. Therefore, by using each clock branch 30 according to a preset clock signal period based on the reference clock signal, N target clock signals derived from the same reference clock signal can be output. In this way, not only can target clock signals be provided for multiple transmission links, but also, because the N target clock signals are derived from the same reference clock signal, each target clock signal naturally has phase alignment characteristics. Thus, phase alignment of clock signals between multiple transmission links can also be guaranteed, providing a clock signal generation scheme with a wider range of applications.

[0038] In all embodiments of this application, the target clock signal includes at least a bit clock signal BCLK. Accordingly, in a specific implementation, the clock branch 30 may include at least a bit clock branch. Accordingly, the preset clock signal period in the bit clock branch may include a preset bit clock signal period.

[0039] In other embodiments, the target clock signal may also include a frame clock signal LRCLK. Accordingly, in a specific implementation, the N clock branches 30 may also include a frame clock branch. Accordingly, the preset clock signal period in the frame clock branch may include a preset frame clock signal period.

[0040] Figure 2 This application provides a schematic diagram of the specific structure of a signal generation circuit according to an embodiment. Figure 1 .exist Figure 2 In the illustrated embodiment, the preset clock signal period includes a preset bit clock signal period.

[0041] Combination Figure 1 and Figure 2 The N clock branches 30 include N or at most N-1 bit clock branches 31, and the bit clock branches 31 include: a first selector 311.

[0042] exist Figure 2In the first selector 311, there are a first connection terminal and a second connection terminal. The first connection terminal is used to connect to the reference signal output terminal 21. The first selector 311 is used to determine the flip phase according to the preset bit clock signal period, respond to the reference clock signal, and output the target bit clock signal through the second connection terminal.

[0043] In this embodiment, the target bit clock signal generally refers to the bit clock signal output by the bit clock branch 31. In specific implementation, the target clock signal output by each bit clock branch 31 can be directly used by the subsequent power supply module. Here, in the N or at most N-1 bit clock branches 31, the preset bit clock signal period configured in each bit clock branch 31 can be different, so the target bit clock signal output by each bit clock branch 31 can be different.

[0044] For example, when the first selector 311 determines the flip phase according to a preset bit clock signal period and responds to the reference clock signal, it may specifically output a first level in response to the reference clock signal, and then flip the first level according to the preset bit clock signal period to output a second level. For example, the preset bit clock signal period is 32 unit cycles of the reference clock signal. During the process from the reference clock signal of the 1st unit cycle to the reference clock signal of the 16th unit cycle, the first selector 311 outputs the first level of the target bit clock signal, and during the process from the reference clock signal of the 17th unit cycle to the reference clock signal of the 32nd unit cycle, the first selector 311 outputs the second level of the target bit clock signal. Here, the first level and the second level are opposite, that is, when the first level is high, the second level is low, and when the first level is low, the second level is high.

[0045] It should be noted that, in order to avoid introducing more uncertainty by using a frequency divider to divide the reference clock signal, in this embodiment, the first selector 311 is used to determine the flip phase according to the preset bit clock signal period, so that when responding to the reference clock signal, the target bit clock signal can be output through the second connection terminal.

[0046] It is understandable that when N clock branches 30 include N bit clock branches 31, the signal generation circuit 100 can output N target bit clock signals.

[0047] When the N clock branches 30 include at most N-1 bit clock branches 31, the signal generation circuit 100 can output at most N-1 target bit clock signals, and the remaining 1 reference clock signal can be provided to other unit branches. For example, other unit branches can be frame clock branches used to provide frame clock signals based on the reference clock signal. Of course, in specific implementations, other unit branches can also be reference clock branches, frequency division clock branches, ADC data sampling branches, etc., and there are no restrictions here.

[0048] Combination Figure 1 and Figure 2 As an example, when the N clock branches 30 include at most N-1 bit clock branches, the N clock branches also include: 1 frame clock branch 32.

[0049] In this embodiment, the frame clock branch 32 is connected to the presettable counter 20. The frame clock branch 32 is used to output the target frame clock signal according to the reference clock signal according to the preset frame clock signal period.

[0050] It should be noted that there is an integer multiple relationship between the target bit clock signal and the target frame clock signal in terms of their periods. Furthermore, the period of the target bit clock signal is T. B The signal period of the target frame clock signal is T. L For example, T B / T L =Z, where Z is an integer greater than 1. For example, Z can be an integer value of 32, 64, 128, etc.

[0051] It is easy to understand that the target bit clock signal generally refers to the bit clock signal output by any bit clock branch 31. The target frame clock signal generally refers to the frame clock signal output by the frame clock branch 32.

[0052] For example, taking the signal generation circuit 100 applied to an audio data transmission scenario, the bit clock signal is the basic beat of data transmission, and each bit clock signal pulse corresponds to the transmission of 1 bit of audio data. Unlike the bit clock signal, the frame clock signal is used to define the data frame structure of the audio data. Each level transition of the frame clock signal (e.g., from low to high or from high to low) marks the beginning or end of a channel data block. In practical applications, as one implementation, the bit clock branch 31 can be used to connect to the data sampling module / branch, providing a target bit clock signal for controlling the sampling frequency of the data sampling module / branch. As another implementation, the bit clock branch 31 can be used to connect to a serial-to-parallel conversion module, converting the serial bit stream into parallel data at the receiving end. As yet another implementation, the bit clock branch 31 can also be used to connect to a digital filter / interpolator, using the target bit clock signal as the internal processing clock signal for a portion of the DAC chip.

[0053] In some embodiments, the frame clock branch 32 can be used to connect to the channel switching controller, that is, the target frame clock signal output by the frame clock branch 32 can be used to indicate whether the receiver is currently transmitting left channel data or right channel data.

[0054] In other embodiments, frame clock branch 32 can be used to connect a frame synchronizer to provide a frame start signal to an audio processor (such as a DSP) for buffering or processing complete sample points.

[0055] In other embodiments, the frame clock branch 32 can also be used to achieve sampling rate synchronization, that is, to use the frequency of the target frame clock signal output by the frame clock circuit 32 as its sampling clock reference directly by the ADC sampling module.

[0056] exist Figure 2 In the frame clock branch 32, a second selector 321 is included. The second selector 321 includes a first connection terminal and a second connection terminal. The first connection terminal is used to connect to the output terminal of the presettable counter 20. The second selector 321 is used to determine the flip phase according to the preset frame clock signal period, respond to the reference clock signal, and output the frame clock signal through the second connection terminal.

[0057] For example, when the second selector 321 determines the flip phase according to a preset frame clock signal period and responds to the reference clock signal, it may specifically output a first level in response to the reference clock signal, and then flip the first level according to the preset frame clock signal period to output a second level. For example, if the preset bit clock signal period is 128 units of the reference clock signal, the second selector 321 outputs the first level of the target frame clock signal from the reference clock signal in the first unit period to the reference clock signal in the 64th unit period, and outputs the second level of the target frame clock signal from the reference clock signal in the 65th unit period to the reference clock signal in the 128th unit period. Here, the first level and the second level are opposite; that is, when the first level is high, the second level is low, and when the first level is low, the second level is high.

[0058] Figure 3 This application provides a schematic diagram of the specific structure of a signal generation circuit according to an embodiment. Figure 2 .exist Figure 3 In the embodiment shown, the bit clock branch 31 further includes a register 312 connected to the second connection terminal of the first selector 311, and the register 312 is used to store the target bit clock signal.

[0059] In this embodiment, register 312 can store the target bit clock signal, thereby providing the target bit clock signal required by the subsequent circuit unit connected to it.

[0060] As one possible implementation, register 312 may include X flip-flops, where X is an integer and X≥1.

[0061] For example, the flip-flop can be a D flip-flop. Since D flip-flops can be used for data storage, in the specific implementation, the corresponding number of D flip-flops can be set to form the register 312 according to the storage length requirement of the target bit clock signal.

[0062] Figure 4 A schematic diagram of a signal transmission circuit provided in an embodiment of this application is shown, as follows: Figure 4 As shown, this application embodiment also provides a signal transmission circuit 200, including the clock signal generation circuit 100 in the above embodiment and N communication units 110. Figure 4 In this configuration, N communication units 110 are connected one-to-one with N clock branches 30. The target clock signal output by the clock branch 30 to the communication unit 110 is either a bit clock signal or a frame clock signal.

[0063] In this embodiment, the communication unit 110 can be used to transmit and / or receive signals. Since each communication unit 110 is connected to a clock branch 30, each communication unit 110 can transmit and / or receive signals according to the target clock signal. Based on the inherent phase alignment characteristic among the N target clock signals, the timing consistency of the signals transmitted or received by the communication unit 110 can be guaranteed.

[0064] Figure 5 A schematic diagram of a signal transmission circuit according to another embodiment of this application is shown, such as... Figure 5 As shown, the signal transmission circuit 200 includes the clock signal generation circuit 100 in the above embodiment and at least two communication units (110a, 110x). Each communication unit (110a / 110x) is connected to two clock branches 30, and the two sets of target clock signals output by the two clock branches are a bit clock signal and a frame clock signal, respectively.

[0065] like Figure 5 As shown, taking the signal transmission circuit 200 as an example, which includes two communication units (110a, 110x), each communication unit (110a / 110x) can be connected to two clock branches 30 respectively. One clock branch (30a / 30x) provides / outputs a bit clock signal as its target clock signal, and the other clock branch 30b provides / outputs a frame clock signal as its target clock signal.

[0066] It is readily understood that in other embodiments, the signal transmission circuit 200 may also include three or more communication units (not shown in the figure), and each communication unit may be connected to two clock branches to provide it with a bit clock signal and a frame clock signal.

[0067] As one possible implementation, communication unit 110a and communication unit 110x in this embodiment can be the same communication unit. In actual use, communication unit 110a and communication unit 110x can input bit clock signals provided by the same or different clock branches. In order to synchronize data transmission between communication unit 110a and communication unit 110x, communication unit 110a and communication unit 110x can input frame clock signals provided by the same clock branch 30b.

[0068] For example, in Figure 5 In this configuration, communication unit 110a connects clock branch 30a and clock branch 30b. Clock branch 30a provides / outputs a bit clock signal to communication unit 110a, while clock branch 30b provides / outputs a frame clock signal. Communication unit 110x connects clock branch 30x and clock branch 30b. Clock branch 30x provides / outputs a bit clock signal to communication unit 110x, while clock branch 30b provides / outputs a frame clock signal. Here, the bit clock signal provided / output by clock branch 30a to communication unit 110a and the bit clock signal provided / output by clock branch 30x to communication unit 110x can be the same or different. Since both communication unit 110a and communication unit 110x use frame clock signals provided / output by clock branch 30b, frame clock alignment can be achieved when transmitting signals through communication unit 110a and communication unit 110x. That is, when transmitting or receiving signals through communication unit 110a and communication unit 110x, frame clock alignment and timing consistency can be achieved for the two data transmission paths, improving the stability and reliability of data transmission.

[0069] For example, in an example where the signal transmission circuit 200 may include three or more communication units (not shown in the figure), each communication unit can be connected to the same clock branch 30b, that is, each communication unit can be provided with a frame clock signal by one clock branch 30b. In this way, when transmitting or receiving signals through all communication units, frame clock alignment and timing consistency of all data transmissions can be achieved, improving the stability and reliability of data transmission.

[0070] It is understood that the improvements and specific implementations of the signal transmission circuit 200 provided in this embodiment related to this application have already been... Figures 1 to 3 The embodiments are described in detail, and you can refer to them for details. Figures 1 to 3 as well as Figures 1 to 3 The corresponding implementation details will not be repeated here.

[0071] This application also provides a chip, which includes the clock signal generation circuit 100 and / or signal transmission circuit 200 described above. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. Since the chip of this application possesses the clock signal generation circuit 100 and / or the signal transmission circuit 200 provided in the above embodiments, it possesses all the beneficial effects of the clock signal generation circuit 100 and / or the signal transmission circuit 200 in the above embodiments, which will not be repeated here.

[0072] It is understood that the improvements and specific implementation methods of the chip provided in this embodiment related to this application have already been... Figures 1 to 3 The embodiments are described in detail, and you can refer to them for details. Figures 1 to 3 as well as Figures 1 to 3 The corresponding implementation details will not be repeated here.

[0073] Figure 6 This application provides a schematic diagram of the structure of an audio module according to an embodiment of the present application. Figure 6 As shown in the illustration, this application also provides an audio module 300, including the signal transmission circuit 200 provided in the above embodiment, and a signal processing unit 210 connected to each communication unit 110. The signal processing unit 210 is used to process the signal to be processed when it receives the signal to be processed transmitted by the communication unit.

[0074] In a specific implementation, the signal to be processed can be an audio signal, and correspondingly, the signal processing unit 210 can be an audio processing unit. For example, a multi-channel audio processor or a multi-track recorder, when receiving N audio signals to be processed, can fuse the N audio signals and output the fused audio signal.

[0075] In other embodiments, the audio module 300 may also include the chip provided in the above embodiments.

[0076] It is understood that the improvements and specific implementation methods of the audio module 300 provided in this embodiment related to this application have already been... Figures 1 to 4 The embodiments are described in detail, and you can refer to them for details. Figures 1 to 4 as well as Figures 1 to 4 The corresponding implementation details will not be repeated here.

[0077] This application also provides an electronic device, which includes a device body and at least one or any one of the following disposed within the device body: a clock signal generation circuit 100, a signal transmission circuit 200, a chip, and an audio module 300, as described above. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0078] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A clock signal generation circuit, characterized in that, include: Clock signal source, used to provide the master clock signal; A presettable counter is connected to the clock signal source. The presettable counter includes at least N reference signal output terminals. The presettable counter is used to output a reference clock signal through the N reference signal output terminals according to the master clock signal; where N is an integer greater than 1. N clock branches are connected to N reference signal output terminals respectively. The clock branches are used to output the corresponding target clock signal based on the reference clock signal according to a preset clock signal period.

2. The clock signal generation circuit as described in claim 1, characterized in that, The preset clock signal period includes a preset bit clock signal period; the N clock branches include N or at most N-1 bit clock branches, and the bit clock branches include: The first selector includes a first connection terminal and a second connection terminal. The first connection terminal is used to connect to the reference signal output terminal. The first selector is used to determine the flip phase according to the preset bit clock signal period, respond to the reference clock signal, and output the target bit clock signal through the second connection terminal.

3. The clock signal generation circuit as described in claim 2, characterized in that, The bit clock branch also includes: A register, which is connected to the second connection terminal of the first selector, is used to store the target bit clock signal.

4. The clock signal generation circuit as described in claim 3, characterized in that, The register includes X flip-flops, where X is an integer and X≥1.

5. The clock signal generation circuit as described in any one of claims 2 to 4, characterized in that, When the N clock branches include at most N-1 bit clock branches, the N clock branches further include: One frame clock branch is connected to the presettable counter. The frame clock branch is used to output the target frame clock signal according to the reference clock signal according to the preset frame clock signal period.

6. The clock signal generation circuit as described in claim 5, characterized in that, The frame clock branch includes a second selector, which includes a first connection terminal and a second connection terminal. The first connection terminal is used to connect to the output terminal of the presettable counter. The second selector is used to determine the flip phase according to the preset frame clock signal period, respond to the reference clock signal, and output the frame clock signal through the second connection terminal.

7. A signal transmission circuit, characterized in that, Includes the clock signal generation circuit according to any one of claims 1 to 6; and N communication units, each of which is connected to one of the N clock branches. The target clock signal output by each clock branch to the communication unit is either a bit clock signal or a frame clock signal; or At least two communication units, each of which is connected to two clock branches, and the two sets of target clock signals output by the two clock branches are a bit clock signal and a frame clock signal, respectively.

8. A chip, characterized in that, The chip includes a clock signal generation circuit as described in any one of claims 1 to 6; and / or the chip includes a signal transmission circuit as described in claim 7.

9. An audio module, characterized in that, Including the signal transmission circuit as described in claim 7; and A signal processing unit, connected to each of the communication units, is configured to process the signal to be processed upon receiving it from the communication unit; and / or The audio module includes the chip described in claim 8.

10. An electronic device, characterized in that, The electronic device includes at least one of the clock signal generation circuit according to any one of claims 1 to 6, the signal transmission circuit according to claim 7, the chip according to claim 8, and the audio module according to claim 9.

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