A reverse voltage resistant high-side ideal diode

Abstract

The utility model discloses a kind of high-end ideal diodes of reverse voltage resistance, including PMOS main pipe, comparator circuit, drive circuit, it is characterized by: the PMOS main pipe, comparator circuit, drive circuit composition circuit, the comparator circuit includes PNP pair tube, resistance, the PNP pair tube includes PNP tube V2 and PNP tube V3, the PNP tube V2 has the base B2 of connection voltage VA one end, the emitter E2 of connection voltage VA other end, and the collector C2 of connection voltage VCC, and emitter E2 connects one end of resistance R1, the other end of resistance R1 is grounded.Based on PNP pair tube+PMOS main pipe technical scheme, circuit improvement is carried out, PNP tube V2 is inverted design, and circuit software simulation verification is carried out, simulation shows that it has the function of preventing backflow, can protect front-stage circuit;Circuit is very simple and does not increase any material cost, and practicality is strong.

Description

Technical Field

[0001] This utility model relates to the field of diode technology, specifically to a high-end ideal diode that is resistant to reverse voltage. Background Technology

[0002] Diodes, due to their unidirectional conduction characteristics and reverse current prevention capabilities, are increasingly used, especially Schottky diodes connected in series, which have a smaller voltage drop across power supplies and are gaining popularity among designers. However, since the voltage drop of a Schottky diode is still greater than that of a MOSFET, for some voltage-sensitive circuits, MOSFETs with low impedance characteristics are preferred to improve product reliability. Many USB power switches (distribution switches) now have built-in reverse current prevention functions, such as the MP62055 chip. This is because when an external device is connected to a computer's USB port, the device must not allow current to flow back into the computer's VBus, otherwise it will damage the computer. Currently, orifice circuits are used in many applications to ensure that each individual power supply is independent and prevents reverse current flow. They are most commonly used in current sharing circuits to meet different power requirements.

[0003] High-end ideal diodes based on PMOS transistors are common, and existing solutions mostly consist of a PNP transistor pair (auxiliary transistor) + PMOS transistor main body or a PMOS transistor pair (auxiliary transistor) + PMOS transistor main body. One such solution is the PMOS transistor pair + PMOS transistor main body technology (an ultra-low loss ideal diode, application number: 201821304820.X), which belongs to the high-end ideal diode category. It includes a comparator circuit and a PMOS transistor main body V1. The comparator circuit consists of two independent PMOS auxiliary transistors or PMOS transistor pairs V2 and V3 with identical parameters packaged together, along with resistors R1 and R2. The gate (G) and source (S) terminals of a PMOS transistor are insulated, unlike the conduction-enabled BJT junction. Essentially, the gate and source terminals are disconnected, and the voltage between the gate and source terminals of a PMOS transistor is less than V. TP (V) TP The PMOS transistor can only be turned on when the source voltage of the PMOS transistor is reached (the threshold voltage for PMOS transistor to turn on); the PMOS transistor with the higher source voltage turns on first, while the other PMOS transistor with the lower source voltage turns off. PNP transistor pair (auxiliary transistor) + PMOS transistor main transistor technical solution: such as... Figure 1 As shown, the parameters of PNP transistors V2 and V3 are the same as those of the PMOS transistor pair in the PMOS transistor + PMOS transistor scheme. The PNP transistor with the higher emitter voltage will turn on first, while the other PNP transistor with the lower emitter voltage will turn off.

[0004] The two schemes described above effectively realize the function of an ideal diode, controlling the conduction and cutoff of the PMOS master V1: when the input power supply VCC is not less than the output power supply Vout, the PMOS master V1 conducts; otherwise, the PMOS master V1 is cut off, preventing the current from the output power supply Vout from flowing back to the input power supply VCC, thus protecting the input power supply circuit, which is equivalent to a high-side ideal diode.

[0005] For PNP transistors: the base (N-region) is very thin and has a low doping concentration, which is beneficial for carrier conduction; the emitter (P-region) has a small area and a high doping concentration, which is beneficial for carrier emission; the collector (P-region) has a large area and a low doping concentration, which is beneficial for carrier collection. Typical doping concentrations for the emitter, base, and collector regions of a PNP transistor are 10⁻⁶. 19 / cm 3 10 17 / cm 3 10 15 / cm 3 Generally, the higher the doping concentration of a PN junction, the greater the charge density and the lower the reverse breakdown voltage. Zener diodes are made based on this principle and are typically used for reverse biasing. As long as the reverse current is controlled within a certain range, the Zener diode will not be damaged by overheating. During normal use, a current-limiting resistor needs to be connected in series to prevent damage.

[0006] When the collector C is open, the voltage V at the emitter-base reverse breakdown PN junction EBO Small-power BJT transistors (NPN or PNP transistors) typically operate at a few volts (the voltage at which the PN junction reverse breaks down between the collector and base). CBO The voltage V between the collector and emitter of the reverse breakdown PN junction CEO The reverse breakdown voltages of the two are not significantly different, V CBO (Voltage ranges from tens of volts to thousands of volts), common BJT tubes V EBO =-5V=-V BEO Normal operating conditions for a BJT: Voltage | V CE |<|V CEO |Base-emitter reverse voltage|V EB |<|V EBO |=5V. For MOSFETs, the maximum gate-source voltage difference is relatively small, typically a maximum value of V. GS(MAX) =±8V or ±12V (drain-source voltage difference can reach tens of volts, common MOSFETs V DS(MAX) =30V), once the gate-source voltage difference V GS More than V GS(MAX) The gate and source are very likely to be broken down, and the MOSFET may be damaged.

[0007] Figure 1When VCC > Vout, and the circuit is normally forward-biased, VA = VCC - Vout. F ≈VCC-0.6V, PNP transistor V2 is turned on, and the on-state voltage drop is V2. EC =V2 EB ≈0.6V; V2 conducts while V3 conducts, the PNP transistor V3 is cut off, VB≈0V, the PMOS transistor V1 conducts, Vout≈VCC. For the PNP transistor V3, V3... BE =VA-Vout=VCC-V F -VCC=-V F ≈-0.6V<|V EBO Generally, it's unlikely that transistor V3 will break down. For PMOS transistor V1, V1... GS =VB-VCC<|V GS(MAX) The PMOS transistor V1 may be damaged and requires protection.

[0008] Figure 1 When Vout >> VCC, and the voltage is reversed, VA = Vout - V F ≈Vout-0.6V, PNP transistor V3 is saturated and conducting, saturation voltage drop V3 EC ≈-V CE(SAT) =0.3V, VB≈Vout-V3 EC ≈Vout-V CE(SAT) ≈Vout; V3 suppresses the conduction of V2, the PNP transistor V2 is cut off, and the PMOS transistor V1 is cut off. For the PNP transistor V2, assuming Vout = 30V and VCC = 12V, V2 BE =VA-VCC=Vout-V F -VCC = 30V - 0.6V - 12V = 17.4V > |V EBO If the voltage is 5V, there is a high possibility of V3 transistor breaking down, resulting in a reverse leakage current path. Therefore, this situation needs to be avoided. The reverse voltage (Vout) cannot exceed a certain voltage compared to the operating voltage VCC. Therefore, the reverse voltage (Vout) should not be too large. If Vout is too large, it will burn out the PNP pair or PMOS pair, which will limit the application scenarios.

[0009] Existing improved technical solution: (One-way conduction device, announcement number: CN107769759B) Figure 1 In addition to the above, add a PMOS transistor V4 and two resistors R3~R4, as follows: Figure 2As shown: When VCC > Vout, transistor V1 is normally forward biased; when Vout >> VCC, transistor V1 is reverse biased. Due to the presence of PMOS transistor V4, its body diode and source-drain junction have high reverse voltage tolerance, blocking the reverse leakage current path. Assuming Vout = 30V and VCC = 12V, transistor V2 will generally not break down, thus effectively solving the problem of high reverse voltage. The drawbacks are increased material costs and PCB area.

[0010] To address the above issues, it is necessary to consider the voltage VN of the reverse breakdown PN junction between the collector and base of a PNP transistor. CBO With the advantage of high reverse breakdown voltage resistance, a high-end ideal diode with high reverse voltage resistance is designed to expand its application range. To this end, we propose a high-end ideal diode with high reverse voltage resistance to solve the above problems. Utility Model Content

[0011] The purpose of this invention is to provide a high-end ideal diode that is resistant to reverse voltage, so as to solve the problems mentioned in the background art.

[0012] To achieve the above objectives, this utility model provides the following technical solution: a high-side ideal diode resistant to reverse voltage, comprising a PMOS transistor, a comparator circuit, and a driving circuit. The PMOS transistor, comparator circuit, and driving circuit constitute a circuit. The comparator circuit includes a pair of PNP transistors and a resistor. The pair of PNP transistors includes PNP transistor V2 and PNP transistor V3. PNP transistor V2 has a base B2 connected to one end of voltage VA, an emitter E2 connected to the other end of voltage VA, and a collector C2 connected to voltage VCC. The emitter E2 is connected to one end of resistor R1, and the other end of resistor R1 is grounded. PNP transistor V3 has a base B3 connected to one end of voltage VA, a collector C3 connected to one end of voltage VB, and an emitter E3 connected to the output power supply Vout. The collector C3 is connected to one end of resistor R2, and the other end of resistor R2 is grounded. The PNP transistor V2 at the front end of the comparator is set to an inverted operating state.

[0013] Preferably, the comparator is used to compare the magnitudes of the input power supply VCC and the output power supply Vout.

[0014] Compared with the prior art, the beneficial effects of this utility model are: based on the PNP transistor + PMOS main transistor technology, the circuit is improved, the PNP transistor V2 is designed in reverse, and the circuit is verified by software simulation. The simulation shows that it has the function of preventing backflow and can protect the front-end circuit; the circuit is very simple and does not increase any material cost, and it is highly practical. Attached Figure Description

[0015] Figure 1The schematic diagram shows a high-end ideal diode implemented using existing PNP transistor pairs as a comparator. Figure 2 This is a schematic diagram of an existing improved technical solution; Figure 3 This is a schematic diagram of the technical solution of this utility model; Figure 4 This utility model Figure 3 Forward conduction simulation test diagram; Figure 5 This utility model Figure 3 Reverse cutoff simulation test diagram. Detailed Implementation

[0016] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model. Example

[0017] Reference Figure 3 This is the first embodiment of the present invention. This embodiment provides a high-side ideal diode resistant to reverse voltage, including a PMOS transistor, a comparator circuit, and a driving circuit. The PMOS transistor, comparator circuit, and driving circuit form a circuit. The comparator circuit includes a pair of PNP transistors and a resistor. The pair of PNP transistors includes PNP transistor V2 and PNP transistor V3. PNP transistor V2 has a base B2 connected to one end of voltage VA, an emitter E2 connected to the other end of voltage VA, and a collector C2 connected to voltage VCC. The emitter E2 is connected to one end of resistor R1, and the other end of resistor R1 is grounded. PNP transistor V3 has a base B3 connected to one end of voltage VA, a collector C3 connected to one end of voltage VB, and an emitter E3 connected to the output power supply Vout. The collector C3 is connected to one end of resistor R2, and the other end of resistor R2 is grounded. Example

[0018] Reference Figure 1-5 This is the second embodiment of the present invention, which is based on the previous embodiment. Specifically, in... Figure 1 Based on this, an improvement was made by swapping the positions of the collector and emitter of transistor V2, specifically as follows: Figure 3 As shown, since the PNP tube V2 is in an inverted state, its V CBO It has a large reverse breakdown voltage, and an even higher reverse breakdown voltage in the inverted state.

[0019] Specifically, the comparator is used to compare the magnitudes of the input power supply VCC and the output power supply Vout. The comparison signal output by the comparator is transmitted to the gate of the PMOS transistor to control the conduction and cutoff of the PMOS transistor, preventing the output power supply from flowing back to the input power supply and protecting the input power supply pre-amplifier circuit. Example

[0020] Reference Figure 1-5 This is the third embodiment of the present invention. Based on the above two embodiments, when the input power supply VCC is not less than the output power supply Vout: transistor V2 conducts, suppressing transistor V3's conduction; transistor V3 is cut off; and due to the pull-down effect of resistor R2, the comparator output comparison signal VB is low, i.e., VB ≈ Vout - Vout. Z When the gate of PMOS controller V1 is low, V1 GS =VB-Vout≈-V Z <V TP The PMOS master V1 is turned on.

[0021] When the input power supply VCC is less than the output power supply Vout: transistor V3 is turned on, the comparator's output comparison signal VB≈Vout, the gate of PMOS transistor V1 is at a high level, and V1... GS =VB-Vout≈0>V TP When the PMOS transistor V1 is turned off, it prevents the Vout current from flowing back into VCC, protecting the VCC power supply's pre-amplifier circuit. Preferably, the PMOS transistor V1 can use PMOS transistors with different on-current values. For high-power power supply control, the on-resistance R between the drain and source of the PMOS transistor can be selected. DS(ON) A power transistor device with a voltage rating of several milliohms and a large current carrying capacity has a small voltage drop when carrying a large current, meaning it has a very low forward voltage and is approximately an ideal diode.

[0022] according to Figure 3 Circuit schematic simulation test: The PMOS transistor selected is NVTFS5124PLTAG, and the minimum conduction threshold voltage is V. TP(MIN) =-1.5V, maximum value V TP(MAX) =-2.5V, typical value V not given. TP The conduction current can reach -6A, and the conduction resistance R DS(ON) =0.26Ω(V GS =-10V), R DS(ON) =0.38Ω (V GS =-4.5V), V GS(MAX) =±20V,|V DS(MAX) |=60V. The PNP transistor used is a Generic 2N2905, assuming a reverse breakdown voltage V between the collector and base.CBO =60V, V EBO =5V. R1=R2=47kΩ, load resistance RL=10Ω, specific simulation test is as follows.

[0023] DC power supply forward conduction simulation test (when the input power supply VCC is not less than the output power supply Vout), VCC=VCC1=12V (switch J1 is closed, switch J2 is open), the simulation test is shown in Figure 4: the collector conduction current I2 of PNP transistor V2. C =243μA (test point PR6), emitter current I3 of transistor V3 E =9.54nA (test point PR7), PNP transistor V2 is conducting, VA=11.4V, PNP transistor V2 conduction voltage drop V2 CE =VCC-VA=12V-11.4V=0.6V; PNP transistor V3 is cut off, comparator output comparison signal VB=4.31V, V1 GS =VB-Vout=4.31V-11.7V=-7.39V<V TP And |V1 GS |<|V GS(MAX) When PMOS transistor V1 is forward-biased, the output voltage Vout of PMOS transistor V1 is 1.17A × 10Ω = 11.7V (test point PR3). The forward voltage drop of PMOS transistor V1 is approximately 0.3V (12V - 11.7V), which is lower than the forward voltage drop of the diode Vout. F The positive output current of the power supply is 1.17A (test point PR5), corresponding to the drain-source on-resistance R. DS(ON) =0.3V / 1.17A≈0.256Ω. The absolute value of the gate-source voltage difference of the PMOS transistor V1 |V1 GS |=7.39V<|V GS(MAX) With a voltage of 20V, the gate-source voltage difference of the PMOS transistor V1 meets the requirements, and the PMOS transistor is not damaged.

[0024] DC power supply reverse cutoff simulation test (input power supply VCC is less than output power supply Vout): After switch J1 is closed, switch J2 is also closed. Due to the maximum reverse voltage of the PMOS main drain-source voltage |V DS(MAX) Given |=60V>Vout, and taking VCC2=Vout=30V>VCC=12V, the simulation is as follows: Figure 5 As shown: The collector currents of PNP transistors V2 and V3 are I2 and I3, respectively. C =-222pA (test point PR6), emitter current I3 of transistor V3 E=1.26mA (test point PR7), PNP transistor V3 is saturated and conducting, V2 is cut off, the comparator outputs a comparison signal VB=29.9V, and the on-state voltage drop of PNP transistor V3 is V3. EC =Vout-VB= 30V-29.9V=0.1V, V2 of PNP transistor V2 BC =VA - VCC = 29.3V - 12V = 17.3V < V CBO =60V, V1 GS =VB - Vout = 29.9V - 30V = -0.1V < -V TP And |V1 GS |<|V GS(MAX) With a voltage of 20V, PMOS transistor V1 is cut off. The gate-source voltage difference of PMOS transistor V1 meets the requirements, and PMOS transistor V1 is undamaged. CBO The ability to withstand a large reverse voltage protects the emitter junction and base-collector of the PNP transistor V2 from damage. The forward conduction current flowing through the PMOS transistor is -355nA (test point PR5, which can be ignored), so it can be considered that there is no reverse current and it is unaffected by the reverse voltage Vout.

[0025] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-side ideal diode resistant to reverse voltage, comprising a PMOS transistor, a comparator circuit, and a drive circuit, characterized in that: The circuit consists of a PMOS transistor, a comparator circuit, and a driver circuit. The comparator circuit includes a pair of PNP transistors and a resistor. The PNP transistor pair includes PNP transistor V2 and PNP transistor V3. PNP transistor V2 has a base B2 connected to one end of voltage VA, an emitter E2 connected to the other end of voltage VA, and a collector C2 connected to voltage VCC. The emitter E2 is connected to one end of resistor R1, and the other end of resistor R1 is grounded. PNP transistor V3 has a base B3 connected to one end of voltage VA, a collector C3 connected to one end of voltage VB, and an emitter E3 connected to the output power supply Vout. The collector C3 is connected to one end of resistor R2, and the other end of resistor R2 is grounded. The PNP transistor V2 at the front end of the comparator is set to an inverted operating state.

2. The high-side ideal diode with reverse voltage tolerance according to claim 1, characterized in that: The comparator is used to compare the magnitudes of the input power supply VCC and the output power supply Vout.

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