Stroboscopic delay compensation drive circuit and stroboscopic delay compensation device
Patent Information
- Application Number
- CN202521634199.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-01
- Publication Date
- 2026-08-21
- Estimated Expiration
- 2035-08-01
AI Technical Summary
[0003]本实用新型提供一种频闪延时补偿驱动电路和频闪延迟补偿装置，用以解决现有技术中因光源驱动芯片存在延时，导致频闪灯存在延时，从而导致图像的补光效果不佳的缺陷
所述数字电位器的时钟端连接所述I2C接口中的时钟接口，所述数字电位器的数据端连接所述I2C接口中的数据接口；所述数字电位器的高电位端连接所述调整子电路的第一端，所述数字电位器的滑动端连接所述调整子电路的第二端，所述数字电位器的低电位端连接所述调整子电路的第三端，所述调整子电路的第四端连接参考电压端，所述调整子电路的第五端连接所述分压电路的第三端和所述运放比较电路的反相输入端。
Smart Images
Figure CN224669987U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power electronics technology, and in particular to a flicker delay compensation drive circuit and a flicker delay compensation device. Background Technology
[0002] Currently, strobe lights are generally installed on cameras, and their application involves matching the flash frequency to the camera's frame rate. The strobe light provides supplemental illumination during each frame's exposure to ensure that flash lighting is present in every frame. The camera's frame rate is typically 25Hz or 50Hz, while the strobe light's emission frequency is generally 100Hz. However, due to a delay between the light source driver chip's enable and actual output, the strobe light may not have outputted when a frame is triggered, resulting in poor initial illumination for each frame. Therefore, how to compensate for this delay in the strobe light is a pressing issue that needs to be addressed. Utility Model Content
[0003] This invention provides a flicker delay compensation driving circuit and a flicker delay compensation device to solve the defect in the prior art where the flicker lamp has a delay due to the delay of the light source driving chip, resulting in poor image illumination effect.
[0004] This utility model provides a flicker delay compensation driving circuit, comprising: a host, a light source driving chip, a flicker supplement light, and an operational amplifier comparator circuit, wherein: The host is connected to the light source driver chip and the operational amplifier comparator circuit. The light source driver chip is connected to the strobe fill light, and the strobe fill light is connected to the operational amplifier comparator circuit. The host is used to output an enable PWM signal to the light source driver chip; The light source driver chip is used to output a drive signal to the strobe fill light based on the enable PWM signal; the drive signal is used to control the strobe fill light to be in working state; The operational amplifier comparator circuit is used to compare the sampled voltage of the strobe lamp when it is working with the reference voltage to obtain a comparison signal; The host is also used to determine the delay duration corresponding to the light source driver chip based on the rising edge times of the enable PWM signal and the comparison signal, so as to adjust the output time of the drive signal.
[0005] According to the flicker delay compensation driving circuit provided by this utility model, the inverting input terminal of the operational amplifier comparator circuit is connected to a voltage divider circuit or a threshold adjustment circuit, wherein: The first end of the voltage divider circuit is connected to the power supply end, and the voltage divider circuit is used to generate a reference voltage; The threshold adjustment circuit is connected to the host's I2C interface; the threshold adjustment circuit is used to generate a reference voltage based on the threshold adjustment signal generated by the host.
[0006] According to the flicker delay compensation driving circuit provided by this utility model, when the inverting input terminal of the operational amplifier comparator circuit is connected to the threshold adjustment circuit, the threshold adjustment circuit includes a digital potentiometer and an adjustment sub-circuit, wherein: The clock terminal of the digital potentiometer is connected to the clock interface in the I2C interface, and the data terminal of the digital potentiometer is connected to the data interface in the I2C interface; the high-potential terminal of the digital potentiometer is connected to the first terminal of the adjustment sub-circuit, the sliding terminal of the digital potentiometer is connected to the second terminal of the adjustment sub-circuit, the low-potential terminal of the digital potentiometer is connected to the third terminal of the adjustment sub-circuit, the fourth terminal of the adjustment sub-circuit is connected to the reference voltage terminal, and the fifth terminal of the adjustment sub-circuit is connected to the third terminal of the voltage divider circuit and the inverting input terminal of the operational amplifier comparator circuit.
[0007] According to the flicker delay compensation driving circuit provided by this utility model, the adjustment sub-circuit includes a first resistor to a seventh resistor and a first capacitor, wherein: The fourth to seventh resistors are connected in series, with the first end of the fourth resistor connected to the second end of the first resistor and the reference voltage terminal. The first end of the first resistor serves as the first terminal of the adjustment sub-circuit. The second end of the fifth resistor is connected to the second end of the second resistor and the first end of the first capacitor, serving as the fifth terminal of the adjustment sub-circuit. The first end of the second resistor serves as the second terminal of the adjustment sub-circuit. The second end of the seventh resistor is connected to the second end of the third resistor and the second end of the first capacitor, both of which are grounded. The first end of the third resistor serves as the third terminal of the adjustment sub-circuit.
[0008] According to the flicker delay compensation driving circuit provided by this utility model, when the inverting input terminal of the operational amplifier comparator circuit is connected to a voltage divider circuit, the voltage divider circuit includes an eighth resistor and a ninth resistor connected in series, wherein: The first end of the eighth resistor serves as the first end of the voltage divider circuit, the second end of the eighth resistor serves as the third end of the voltage divider circuit, and the second end of the ninth resistor is grounded.
[0009] According to the stroboscopic delay compensation driving circuit provided by this utility model, the non-inverting input terminal of the operational amplifier comparator circuit is connected to the tenth resistor, the negative terminal of the stroboscopic fill light, and the negative output terminal of the light source driver chip. The positive output terminal of the light source driver chip is connected to the positive terminal of the stroboscopic fill light, and the output terminal of the operational amplifier comparator circuit is connected to the input terminal of the host.
[0010] According to the flicker delay compensation driving circuit provided by this utility model, the input terminal of the light source driving chip is also connected to the first terminal of the bias resistor, and the second terminal of the bias resistor is grounded.
[0011] According to the flicker delay compensation driving circuit provided by this utility model, the output terminal of the light source driving chip is also connected to a first filtering circuit. The first filtering circuit is used to filter the driving signal and output the filtered driving signal to the flicker fill light.
[0012] This utility model also provides a flicker delay compensation device, comprising: a flicker delay compensation drive circuit as described in any of the above claims.
[0013] The flicker delay compensation driving circuit and flicker delay compensation device provided by this utility model output an enable PWM signal to the light source driver chip via the host computer. The light source driver chip then outputs a drive signal to the flicker fill light based on the enable PWM signal, putting the flicker fill light into operation. An operational amplifier comparator circuit compares the sampled voltage of the flicker fill light with a reference voltage to obtain a comparison signal. The host computer also determines the delay duration of the light source driver chip by using the rising edge times of the enable PWM signal and the comparison signal. In this utility model, by comparing the rising edge times of the enable PWM signal and the comparison signal for corresponding periods, the actual delay duration of the light source driver chip is obtained, allowing adjustment of the drive signal output time to achieve delay compensation for the flicker lamp, improve the accuracy of the flicker lamp's fill light, and thus enhance the fill light effect for each frame of the image. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0015] Figure 1 This is a schematic diagram of the flicker delay compensation drive circuit provided in an embodiment of the present invention.
[0016] Figure 2 This is a schematic diagram of the delay duration provided in an embodiment of the present invention.
[0017] Figure 3 This is a schematic diagram of the threshold adjustment circuit provided in an embodiment of the present invention.
[0018] Figure 4 This is a schematic diagram of the adjustment sub-circuit provided in an embodiment of the present invention.
[0019] Figure 5This is a schematic diagram of the connection of the operational amplifier comparator circuit provided in an embodiment of this utility model.
[0020] Figure 6 This is a connection diagram of the light source driver chip provided in an embodiment of the present invention.
[0021] Figure label: 110: Main unit; 120: Light source driver chip; 121: First filter circuit; 122: Second filter circuit; 130: Strobe light; 140: Operational amplifier comparator circuit; 150: Voltage divider circuit; 160: Threshold adjustment circuit; 161: Digital potentiometer; 162: Adjustment sub-circuit. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.
[0023] To address the problem in existing technologies where the delay in the light source driver chip 120 leads to a delay in the strobe light, resulting in poor image illumination, this invention provides a strobe delay compensation driver circuit. Figure 1 This is a schematic diagram of the flicker delay compensation drive circuit provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the strobe delay compensation drive circuit includes: a host 110, a light source driver chip 120, a strobe fill light 130, and an operational amplifier comparator circuit 140.
[0024] The host 110 is connected to the light source driver chip 120 and the operational amplifier comparator circuit 140. The light source driver chip 120 is connected to the strobe fill light 130, and the strobe fill light 130 is connected to the operational amplifier comparator circuit 140.
[0025] The host 110 is used to output an enable PWM signal to the light source driver chip 120.
[0026] The light source driver chip 120 is used to output a drive signal to the strobe fill light 130 based on the enable PWM signal; the drive signal is used to control the strobe fill light 130 to be in working state.
[0027] The operational amplifier comparator circuit 140 is used to compare the sampled voltage of the strobe lamp 130 when it is working with the reference voltage to obtain a comparison signal.
[0028] The host 110 is also used to determine the delay duration corresponding to the light source driver chip 120 based on the rising edge times of the enable PWM signal and the comparison signal, so as to adjust the output time of the drive signal.
[0029] Specifically, while outputting an enable PWM (Pulse Width Modulation) signal to the light source driver chip 120, the host 110 simultaneously records the rising edge time and frequency of the enable PWM signal. Upon receiving the enable PWM signal, the light source driver chip 120 generates a drive signal corresponding to the strobe light 130 and outputs the drive signal to the strobe light 130, putting the strobe light 130 into operation. Due to the inherent delay in the light source driver chip 120, the rising edge time of the drive signal generated by the light source driver chip 120 is delayed compared to the rising edge time of the enable PWM signal. This results in the strobe light 130 being unable to provide supplementary lighting to the image at the rising edge time of the enable PWM signal because the rising edge time of the drive signal has not yet arrived due to the delay. Therefore, in this embodiment of the invention, the operating voltage of the strobe lamp 130 is sampled to obtain a sampled voltage, and an operational amplifier comparator circuit 140 is used to compare the sampled voltage with a reference voltage to obtain a comparison signal. For example, when the sampled voltage is less than or equal to the reference voltage, a low-level comparison signal is obtained; when the sampled voltage is greater than the reference voltage, a high-level comparison signal is obtained. After determining the comparison signal, the operational amplifier comparator circuit 140 outputs the comparison signal to the host 110. When the comparison signal is high for the first time, it indicates that the comparison signal has reached the rising edge, and the host 110 determines this moment as the rising edge moment of the comparison signal. Afterwards, Figure 2 This is a schematic diagram of the delay duration provided in an embodiment of the present invention, as shown below. Figure 2 As shown, compared to the enable PWM signal (yellow waveform) of the input light source driver chip 120, the drive signal (blue waveform) output by the light source driver chip 120 has a delay. The host 110 compares the rising edge times of the enable PWM signal and the comparison signal of the corresponding period, and determines the difference between the two rising edge times. This difference is the actual delay time of the light source driver chip 120.
[0030] After determining the actual delay duration of the light source driver chip 120, the host 110 can correct the output timing of the drive signal based on the rising edge time of the enable PWM signal, the emission frequency of the strobe lamp, the period, and the delay duration. The corrected output timing of the drive signal can be (t0 + n / f1 - Δt), where t0 represents the rising edge time of the enable PWM signal, f1 represents the emission frequency of the strobe lamp, n represents the period, and Δt represents the delay duration. Correcting the output timing can be understood as advancing the output timing of the drive signal to achieve delay compensation for the strobe lamp, ensuring that the adjusted drive signal is synchronized with the rising edge time of the enable PWM signal, improving the accuracy of the strobe lamp's supplementary lighting, and thus improving the supplementary lighting effect of each frame of the image.
[0031] Optionally, the light source driver chip 120 can be an LED (Light Emitting Diode) driver chip. The strobe fill light 130 can be an LED.
[0032] Furthermore, the inverting input terminal of the operational amplifier comparator circuit 140 is connected to the voltage divider circuit 150 or the threshold adjustment circuit 160, wherein: The first end of the voltage divider circuit 150 is connected to the first power supply end, and the voltage divider circuit 150 is used to generate a reference voltage. The threshold adjustment circuit 160 is connected to the I2C interface of the host 110; the threshold adjustment circuit 160 is used to generate a reference voltage based on the threshold adjustment signal generated by the host 110.
[0033] Specifically, on the one hand, in this embodiment of the invention, the output voltage of the first power supply terminal can be divided by the voltage divider circuit 150 and used as a reference voltage. This reference voltage is a fixed value, which facilitates subsequent comparison with the sampling voltage of the strobe fill light 130. On the other hand, since there are delay differences between different models of light source driver chips 120, or between the same model but different light source driver chips 120, in this embodiment of the invention, a threshold adjustment circuit 160 is used to generate a real-time reference voltage based on the threshold adjustment signal generated as needed by the host 110. This reference voltage is a variable value to meet the delay differences between different models or the same model but different light source driver chips 120, thereby ensuring the accuracy of delay compensation for the strobe fill light 130.
[0034] Furthermore, Figure 3 This is a schematic diagram of the threshold adjustment circuit provided in an embodiment of the present invention, as shown below. Figure 3 As shown, when the inverting input of the operational amplifier comparator circuit 140 is connected to the threshold adjustment circuit 160, the threshold adjustment circuit 160 includes a digital potentiometer 161 and an adjustment sub-circuit 162, wherein: The clock terminal of the digital potentiometer 161 is connected to the clock interface in the I2C interface, and the data terminal of the digital potentiometer 161 is connected to the data interface in the I2C interface. The high-potential terminal H of the digital potentiometer 161 is connected to the first terminal of the adjustment sub-circuit 162, the sliding terminal W of the digital potentiometer 161 is connected to the second terminal of the adjustment sub-circuit 162, the low-potential terminal L of the digital potentiometer 161 is connected to the third terminal of the adjustment sub-circuit 162, the fourth terminal of the adjustment sub-circuit 162 is connected to the reference voltage terminal VREF, and the fifth terminal of the adjustment sub-circuit 162 is connected to the third terminal of the voltage divider circuit 150 and the inverting input terminal of the operational amplifier comparator circuit 140.
[0035] Specifically, the threshold adjustment signal includes a threshold adjustment clock signal and a threshold adjustment data signal. For different models of light source driver chips 120, or for the same model but different light source driver chips 120, the host 110 can send a threshold adjustment clock signal to the clock terminal of the digital potentiometer 161 via the clock interface in the I2C (Inter-Integrated Circuit) interface. This threshold adjustment clock signal instructs the digital potentiometer 161 to start or stop communication. After instructing the digital potentiometer 161 to start communication, the host 110 can send a threshold adjustment data signal to the data terminal of the digital potentiometer 161 via the data interface in the I2C interface. This threshold adjustment data signal instructs the digital potentiometer 161 to determine the tap position (or resistance value), changing the state of the internal analog switch array in the digital potentiometer 161, thereby changing the output voltage of the sliding terminal W in the digital potentiometer 161. This changes the voltage between the fourth and fifth terminals in the adjustment sub-circuit 162, or the voltage between the fifth terminal and the ground terminal, thus changing the reference voltage output by the fifth terminal.
[0036] It should be noted that the digital potentiometer 161 can be a resistor array, that is, a variable voltage divider. The digital potentiometer 161 is connected between the high potential terminal H and the low potential terminal L, and the sliding terminal W is a tap terminal (i.e., a variable terminal).
[0037] Furthermore, Figure 4 This is a schematic diagram of the adjustment sub-circuit provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the adjustment sub-circuit 162 includes first resistors R1 to seventh resistors R7 and a first capacitor C1, wherein: The fourth resistor R4 to the seventh resistor R7 are connected in series, and the first end of the fourth resistor R4 is connected to the second end of the first resistor R1 and the reference voltage terminal VREF. The first end of the first resistor R1 serves as the first end of the adjustment sub-circuit 162. The second end of the fifth resistor R5 is connected to the second end of the second resistor R2 and the first end of the first capacitor C1, and serves as the fifth end of the adjustment sub-circuit 162. The first end of the second resistor R2 serves as the second end of the adjustment sub-circuit 162. The second end of the seventh resistor R7 is connected to the second end of the third resistor R3 and the second end of the first capacitor C1, and both are grounded. The first end of the third resistor R3 serves as the third end of the adjustment sub-circuit 162.
[0038] Specifically, the high-potential terminal H of the digital potentiometer 161 is connected to the reference voltage terminal VREF through the first resistor R1. The reference voltage terminal VREF receives a fixed voltage. After determining the tap position, the digital potentiometer 161 changes the output voltage of the sliding terminal W (i.e., the tap terminal), thereby changing the voltage between the reference voltage terminal VREF and the fifth terminal of the adjustment sub-circuit 162, or the voltage between the fifth terminal of the adjustment sub-circuit 162 and the ground terminal, that is, changing the reference voltage of the inverting input terminal in the operational amplifier comparator circuit 140.
[0039] Furthermore, when the inverting input of the operational amplifier comparator circuit 140 is connected to the voltage divider circuit 150, the voltage divider circuit 150 includes an eighth resistor R8 and a ninth resistor R9 connected in series, wherein: The first end of the eighth resistor R8 serves as the first end of the voltage divider circuit 150, the second end of the eighth resistor R8 serves as the third end of the voltage divider circuit 150, and the second end of the ninth resistor R9 is grounded.
[0040] Specifically, Figure 5 This is a connection diagram of the operational amplifier comparator circuit provided in an embodiment of this utility model, as shown below. Figure 5 As shown, the eighth resistor R8 and the ninth resistor R9 can divide the output voltage of the first power supply terminal, and the reference voltage after voltage division can be determined based on the ratio of the eighth resistor R8 to the ninth resistor R9.
[0041] Furthermore, such as Figure 5 As shown, the non-inverting input of the operational amplifier comparator circuit 140 is connected to the tenth resistor R10, the negative terminal of the strobe fill light 130, and the negative output terminal INPUT- of the light source driver chip 120. The positive output terminal INPUT+ of the light source driver chip 120 is connected to the positive terminal of the strobe fill light 130. The output terminal of the operational amplifier comparator circuit 140 is connected to the input terminal of the host 110.
[0042] Specifically, the negative terminal of the strobe fill light 130 is connected to the negative output terminal INPUT- of the light source driver chip 120, forming a closed loop. Simultaneously, the tenth resistor R10 serves as the sampling resistor for the light source driver chip 120, sampling this closed loop to obtain a sampled voltage, which is then input to the non-inverting input of the operational amplifier comparator circuit 140. After comparing the sampled voltage with a reference voltage, the operational amplifier comparator circuit 140 obtains a comparison signal and outputs this signal to the input of the host computer 110, facilitating the host computer 110's subsequent determination of the delay duration of the light source driver chip 120.
[0043] Furthermore, Figure 6 This is a connection diagram of the light source driver chip provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the input terminal of the light source driver chip is also connected to the first terminal of the bias resistor, and the second terminal of the bias resistor is grounded.
[0044] A bias resistor R11 is also connected to the DIM pin of the light source driver chip 120. When the enable PWM signal is floating or fails, the potential of the DIM pin is adjusted to the target level to avoid uncontrolled brightness.
[0045] Furthermore, such as Figure 6 As shown, the output terminal of the light source driver chip 120 is also connected to a first filter circuit 121. The first filter circuit 121 is used to filter the driving signal and output the filtered driving signal to the strobe fill light 130.
[0046] Specifically, the LX pin of the light source driver chip 120 is connected to a first filter circuit 121, which is used to filter out noise in the drive signal and output the filtered drive signal to the positive terminal of the strobe lamp 130.
[0047] In addition, the IN pin of the light source driver chip 120 is also connected to a second filter circuit 122, which is used to filter the power supply voltage of the second power supply terminal.
[0048] The flicker delay compensation driving circuit provided by this utility model outputs an enable PWM signal to the light source driver chip 120 through the host 110, and the light source driver chip 120 outputs a driving signal to the strobe fill light 130 based on the enable PWM signal, so that the strobe fill light 130 is in working state. The operational amplifier comparator circuit 140 compares the sampled voltage of the strobe fill light 130 when it is working with the reference voltage to obtain a comparison signal. The host 110 also determines the delay duration of the light source driver chip 120 by the rising edge times of the enable PWM signal and the comparison signal. In this utility model, by comparing the rising edge times of the enable PWM signal and the comparison signal of the corresponding period, the actual delay duration of the light source driver chip 120 is obtained, so as to adjust the output time of the driving signal, realize the delay compensation of the strobe light, improve the accuracy of the strobe light fill light, and thus improve the fill light effect of each frame of the image.
[0049] In addition, this utility model embodiment also provides a flicker delay compensation device, including: a flicker delay compensation drive circuit as described in any of the foregoing embodiments.
[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.
Claims
1. A flicker delay compensation driving circuit, characterized in that, include: The main unit, light source driver chip, strobe lamp, and operational amplifier comparator circuit include: The host is connected to the light source driver chip and the operational amplifier comparator circuit. The light source driver chip is connected to the strobe fill light, and the strobe fill light is connected to the operational amplifier comparator circuit. The host is used to output an enable PWM signal to the light source driver chip; The light source driver chip is used to output a drive signal to the strobe fill light based on the enable PWM signal; the drive signal is used to control the strobe fill light to be in working state; The operational amplifier comparator circuit is used to compare the sampled voltage of the strobe lamp when it is working with the reference voltage to obtain a comparison signal; The host is also used to determine the delay duration corresponding to the light source driver chip based on the rising edge times of the enable PWM signal and the comparison signal, so as to adjust the output time of the drive signal.
2. The flicker delay compensation driving circuit according to claim 1, characterized in that, The inverting input of the operational amplifier comparator circuit is connected to a voltage divider circuit or a threshold adjustment circuit, wherein: The first end of the voltage divider circuit is connected to the power supply end, and the voltage divider circuit is used to generate a reference voltage; The threshold adjustment circuit is connected to the host's I2C interface; the threshold adjustment circuit is used to generate a reference voltage based on the threshold adjustment signal generated by the host.
3. The flicker delay compensation driving circuit according to claim 2, characterized in that, When the inverting input of the operational amplifier comparator circuit is connected to the threshold adjustment circuit, the threshold adjustment circuit includes a digital potentiometer and an adjustment sub-circuit, wherein: The clock terminal of the digital potentiometer is connected to the clock interface in the I2C interface, and the data terminal of the digital potentiometer is connected to the data interface in the I2C interface; the high-potential terminal of the digital potentiometer is connected to the first terminal of the adjustment sub-circuit, the sliding terminal of the digital potentiometer is connected to the second terminal of the adjustment sub-circuit, the low-potential terminal of the digital potentiometer is connected to the third terminal of the adjustment sub-circuit, the fourth terminal of the adjustment sub-circuit is connected to the reference voltage terminal, and the fifth terminal of the adjustment sub-circuit is connected to the third terminal of the voltage divider circuit and the inverting input terminal of the operational amplifier comparator circuit.
4. The flicker delay compensation driving circuit according to claim 3, characterized in that, The adjustment sub-circuit includes a first resistor to a seventh resistor and a first capacitor, wherein: The fourth to seventh resistors are connected in series, with the first end of the fourth resistor connected to the second end of the first resistor and the reference voltage terminal. The first end of the first resistor serves as the first terminal of the adjustment sub-circuit. The second end of the fifth resistor is connected to the second end of the second resistor and the first end of the first capacitor, serving as the fifth terminal of the adjustment sub-circuit. The first end of the second resistor serves as the second terminal of the adjustment sub-circuit. The second end of the seventh resistor is connected to the second end of the third resistor and the second end of the first capacitor, both of which are grounded. The first end of the third resistor serves as the third terminal of the adjustment sub-circuit.
5. The flicker delay compensation driving circuit according to claim 2, characterized in that, When the inverting input of the operational amplifier comparator circuit is connected to a voltage divider circuit, the voltage divider circuit includes an eighth resistor and a ninth resistor connected in series, wherein: The first end of the eighth resistor serves as the first end of the voltage divider circuit, the second end of the eighth resistor serves as the third end of the voltage divider circuit, and the second end of the ninth resistor is grounded.
6. The flicker delay compensation driving circuit according to any one of claims 1-5, characterized in that, The non-inverting input of the operational amplifier comparator circuit is connected to the tenth resistor, the negative terminal of the strobe light, and the negative output terminal of the light source driver chip. The positive output terminal of the light source driver chip is connected to the positive terminal of the strobe light. The output terminal of the operational amplifier comparator circuit is connected to the input terminal of the host computer.
7. The flicker delay compensation driving circuit according to any one of claims 1-5, characterized in that, The input terminal of the light source driver chip is also connected to the first terminal of the bias resistor, and the second terminal of the bias resistor is grounded.
8. The flicker delay compensation driving circuit according to any one of claims 1-5, characterized in that, The output terminal of the light source driver chip is also connected to a first filter circuit, which is used to filter the driving signal and output the filtered driving signal to the strobe fill light.
9. A flicker delay compensation device, characterized in that, include: The flicker delay compensation drive circuit as described in any one of claims 1 to 8.