static random access memory

Abstract

A static random access memory includes a bulk semiconductor substrate; a first shallow trench isolation region on the bulk semiconductor substrate, wherein the first shallow trench isolation region includes a first portion and a second portion; a first semiconductor strip including a first edge contacting the first shallow trench isolation region, wherein the first portion of the first shallow trench isolation region is laterally between the first semiconductor strip and the second portion of the first shallow trench isolation region, a first top surface of the first portion is higher than a second top surface of the second portion; a composite hardmask contacting the first edge of the first semiconductor strip, wherein the composite hardmask is on the first portion of the first shallow trench isolation region; and a first gate stack overlapping the composite hardmask and the first shallow trench isolation region, wherein a portion of the first gate stack overlapping the second portion of the first shallow trench isolation region is lower than the composite hardmask, wherein the first gate stack is part of a first transistor.

Description

Technical Field

[0001] This utility model relates to static random access memory and its formation method, and more particularly to the configuration of a hard mask. Background Technology

[0002] Static random access memory (SRAM) is commonly used in integrated circuits (ICs). SRAM cells offer the advantage of retaining data without requiring refreshing. With the increasing speed demands of integrated circuits, the read and write speeds of SRAM cells have become more critical. Furthermore, power consumption needs to be reduced. However, meeting these requirements is challenging as already very small SRAM cells continue to shrink. Utility Model Content

[0003] The purpose of this invention is to propose a static random access memory to solve at least one of the above-mentioned problems.

[0004] This invention proposes a static random access memory (SRAM), comprising: a main semiconductor substrate; a first shallow trench isolation region on the main semiconductor substrate, wherein the first shallow trench isolation region includes a first portion and a second portion; a first semiconductor strip, including a first edge contacting the first shallow trench isolation region, wherein the first portion of the first shallow trench isolation region is laterally located between the first semiconductor strip and the second portion of the first shallow trench isolation region, and the first top surface of the first portion is higher than the second top surface of the second portion; a composite hard mask contacting the first edge of the first semiconductor strip, wherein the composite hard mask is on the first portion of the first shallow trench isolation region; and a first gate stack overlapping the composite hard mask and the first shallow trench isolation region, wherein the portion of the first gate stack overlapping the second portion of the first shallow trench isolation region is lower than the composite hard mask, and wherein the first gate stack is part of a first transistor.

[0005] According to one embodiment of the present invention, the first gate stack includes: a gate dielectric on a composite hard mask and a first shallow trench isolation region; and a gate electrode on the gate dielectric.

[0006] According to one embodiment of the present invention, a static random access memory cell includes: a first transistor as a gate transistor; a second transistor including a second gate stack; and a second shallow trench isolation region below the second gate stack, wherein a composite hard mask is located between the second shallow trench isolation region and the second gate stack.

[0007] According to one embodiment of the present invention, a group of pull-up transistors and pull-down transistors of a static random access memory cell is used to select a second transistor.

[0008] According to one embodiment of the present invention, the composite hard mask includes: a dielectric substrate; and a dielectric region on the dielectric substrate.

[0009] According to one embodiment of the present invention, a second semiconductor strip is further provided on the opposite side of the first shallow trench isolation region relative to the first semiconductor strip, wherein the second top surface of the second portion extends to the second semiconductor strip.

[0010] According to one embodiment of the present invention, the entire second top surface of the second part is lower than the entire first top surface of the first part.

[0011] This utility model proposes a static random access memory (SRAM), comprising: a main semiconductor substrate; a first dielectric isolation region, a second dielectric isolation region, a third dielectric isolation region, and a fourth dielectric isolation region on the main semiconductor substrate; a first semiconductor strip, located between the first dielectric isolation region and the second dielectric isolation region, and in contact with the first dielectric isolation region and the second dielectric isolation region; a first semiconductor layer, overlapping with and spaced apart from the first semiconductor strip; and a first gate stack on the first dielectric isolation region, the second dielectric isolation region, and the first semiconductor strip, and in contact with the first dielectric isolation region, the second dielectric isolation region, and the first semiconductor strip, wherein the first... A gate stack surrounds a first semiconductor layer; a composite hard mask is located between the first gate stack and a first dielectric isolation region; a second semiconductor strip is located between and contacts the third and fourth dielectric isolation regions; a second semiconductor layer overlaps with and is spaced apart from the second semiconductor strip; and a second gate stack is located on and contacts the third and fourth dielectric isolation regions, wherein the second gate stack surrounds the second semiconductor layer, and the interface between the second gate stack and the third dielectric isolation region extends to the opposite sidewalls of the third dielectric isolation region.

[0012] According to one embodiment of the present invention, the first dielectric isolation region includes a first top surface and a second surface, wherein the first top surface is laterally located between the first semiconductor strip and the second surface, and the second surface is lower than the first top surface.

[0013] According to one embodiment of the present invention, the first top surface is below the composite hard mask and forms an additional interface with the composite hard mask. Attached Figure Description

[0014] The embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this utility model.

[0015] Figure 1 The circuit diagram of a static random access memory cell is shown according to some embodiments.

[0016] Figure 2 The above diagram illustrates, according to some embodiments, an intermediate stage in the formation of two static random access memory cells.

[0017] Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figures 6 to 14 , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figures 19A-19C ,and Figures 20A to 20D This is a schematic diagram illustrating an intermediate stage in the formation of a static random access memory cell, according to some embodiments.

[0018] Figure 21 The above diagram illustrates two static random access memory cells according to some embodiments.

[0019] Figure 22 According to some embodiments, a flowchart of forming a static random access memory cell is shown.

[0020] The attached figures are labeled as follows:

[0021] 10: Static Random Access Memory (SRAM) Unit

[0022] 10-1: Static Random Access Memory (SRAM) Unit

[0023] 10-2: Static Random Access Memory (SRAM) Unit

[0024] 12: Wafer

[0025] 20: Base

[0026] 20': Base strip

[0027] 20C-20C: Cross-section

[0028] 20C'-20C': Section

[0029] 20D-20D: Section

[0030] 22: Multi-layer stacking

[0031] 22': Multi-layer stacking

[0032] 22A: First Floor

[0033] 22B: Second Floor

[0034] 23: Trench

[0035] 24: Semiconductor Strip

[0036] 26: Quarantine Zone

[0037] 26T: Top surface

[0038] 26T': Top surface

[0039] 27: Opening

[0040] 28: Protruding fins

[0041] 28-1: Protruding fins

[0042] 28-2: Protruding fins

[0043] 28-3: Protruding fins

[0044] 28-4: Protruding fins

[0045] 29: Disposable Mediator Layer

[0046] 30: Dummy gate stack

[0047] 30-1: Dummy Gate Stack

[0048] 30-2: Dummy Gate Stack

[0049] 32: Dummy gate dielectric

[0050] 34: Dummy gate electrode

[0051] 36: Hard Mask

[0052] 38: Gate spacer

[0053] 42: Source / Drain Groove

[0054] 44: Internal spacers

[0055] 48: Source / Drain Region

[0056] 50: Contact Etching Stop Layer

[0057] 52: Interlayer dielectric

[0058] 58: Groove

[0059] 62: Gate dielectric

[0060] 68: Gate electrode

[0061] 70: Replace gate stack

[0062] 120: Dielectric layer

[0063] 122: Hard mask layer

[0064] 123: Area

[0065] 124: Sacrifice Layer

[0066] 128: Etching Mask

[0067] 130: Opening

[0068] 134: Groove

[0069] 135: Groove

[0070] 138: Gate isolation region

[0071] 200: Process Flow

[0072] 202: Process

[0073] 204: Process

[0074] 206: Process

[0075] 208: Process

[0076] 210: Process

[0077] 212: Process

[0078] 214: Process

[0079] 216: Process

[0080] 218: Process

[0081] 220: Process

[0082] 222: Process

[0083] 224: Process

[0084] 226: Process

[0085] 228: Process

[0086] 230: Process

[0087] 232: Process

[0088] 234: Process

[0089] 236: Process

[0090] 238: Process

[0091] A1-A1: Cross-section

[0092] A2-A2: Section

[0093] BB: Section

[0094] BL: Bitline

[0095] BLB: Bit Lines

[0096] D1: Spacing

[0097] PD-1: Pull-down transistor

[0098] PD-2: Pull-down transistor

[0099] PG-1: Gate-through transistor

[0100] PG-2: Gate-through transistor

[0101] PU-1: Pull-up transistor

[0102] PU-2: Pull-up transistor

[0103] S1: Interval

[0104] SN-1: Storage Node

[0105] SN-2: Storage Node

[0106] T1: Thickness

[0107] T2: Thickness

[0108] T3: Thickness

[0109] VDD: Positive power supply node

[0110] VSS: Power supply voltage

[0111] W1: Width

[0112] W2: Width

[0113] W3: Width Detailed Implementation

[0114] The following disclosure provides numerous different embodiments or examples for implementing various components of the provided service. Specific examples of components and configurations are described below to simplify the embodiments of this utility model. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, references to a first component being formed on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this utility model. Such repetition is for simplification and clarity and does not in itself govern the relationship between the various embodiments and / or configurations discussed.

[0115] Furthermore, spatially related terms such as “below,” “under,” “lower,” “lower,” “above,” “above,” and similar terms may be used here to describe the relationship between an element or component and other elements or components, as shown in the accompanying drawings. The spatially related terms attempt to encompass different orientations of these elements beyond those depicted in the drawings. When the device is rotated to other orientations (90° rotation or other orientations), the spatially relative descriptions used herein can also be interpreted according to the orientation after rotation.

[0116] A static random access memory (SRAM) cell and a method for forming the same are provided. According to some embodiments, in forming the SRAM cell, a hard mask is formed adjacent to the pass-gate transistor. The hard mask is not formed adjacent to the pull-up and pull-down transistors. According to some embodiments using a disposable interposer (such as a disposable oxide interposer, DOI), when the disposable interposer is removed to form a replacement gate, the shallow trench isolation (STI) region adjacent to the pass-gate transistor is protected by the hard mask and is not etched. The shallow trench isolation regions adjacent to the pull-up and pull-down transistors are not protected by the hard mask and are therefore etched.

[0117] Therefore, the alternative gate stacks of pull-up and pull-down transistors extend less than those of the pass-gate transistor. Pull-up and pull-down transistors thus offer better gate control, while the pass-gate transistor can have lower bit-line (BL) capacitance. Therefore, the performance of the pass-gate transistor can be tuned separately from that of the pull-up and pull-down transistors.

[0118] The embodiments discussed herein are intended to provide examples for making or using matters related to this invention, and those skilled in the art will readily understand that modifications can be made within the scope contemplated while maintaining the various embodiments. In the various schematic and illustrative embodiments, the same components may be designated by the same symbols. Although the method embodiments discussed are performed in a specific order of steps, other method embodiments may be performed in any logical order.

[0119] Figure 1 The circuit diagram of a static random access memory (SRAM) cell 10 is shown according to some embodiments. The SRAM cell 10 includes pull-up transistors PU-1 and PU-2, which are p-type metal-oxide-semiconductor (PMOS) transistors. The SRAM cell 10 further includes pull-down transistors PD-1 and PD-2, a gate-pass transistor PG-1, and a gate-pass transistor PG-2, which are n-type metal-oxide-semiconductor (NMOS) transistors. The gates of the gate-pass transistors PG-1 and PG-2 are controlled by a word line WL, which determines whether the SRAM cell 10 is selected.

[0120] A latch formed by pull-up transistors PU-1, PU-2, PD-1, and PD-2 stores one bit, with the complementary value of the bit stored in storage nodes SN-1 and SN-2. The stored bit can be written to or read from static random access memory (SRAM) cell 10 via complementary bit lines (including bit line BL and bit line bar BLB).

[0121] Static Random Access Memory (SRAM) cell 10 is activated via the positive power supply node VDD (with a positive power supply voltage). SRAM cell 10 is also connected to the power supply voltage VSS, which may be electrically grounded. Pull-up transistor PU-1 and pull-down transistor PD-1 form a first inverter. Pull-up transistor PU-2 and pull-down transistor PD-2 form a second inverter. The input of the first inverter is connected to the output of the gate-pass transistor PG-1 and the second inverter. The output of the first inverter is connected to the input of the gate-pass transistor PG-2 and the second inverter.

[0122] It should be understood that, Figure 1A six-transistor static random access memory (SRAM) cell (which is a single-port SRAM cell) is shown as an example. However, the concepts of this application can also be applied to other types of SRAM cells (such as eight-transistor SRAM cells, ten-transistor SRAM cells, or other similar cells), and can also be applied to dual-port SRAM cells.

[0123] Figure 2 The above diagram illustrates an example of the intermediate stages during the formation of a static random access memory cell, according to some embodiments. Figure 2 The intermediate stage shown corresponds to Figure 14 The process illustrated will be discussed later. The illustrated region includes two adjacent static random access memory (SRAM) cells 10 (including SRAM cell 10-1 and SRAM cell 10-2). Each of SRAM cell 10-1 and SRAM cell 10-2 includes six transistors, as shown in the reference. Figure 1 The following discussion uses static random access memory cell 10-1 as an example, but the discussion also applies to other static random access memory cells.

[0124] According to some embodiments, the static random access memory cell 10-1 includes four protruding fins 28 (including protruding fins 28-1, 28-2, 28-3, and 28-4), which will be discussed with reference to the following figures. The transistors to be formed are marked based on the protruding fins 28-1, 28-2, 28-3, and 28-4. Figure 2 (The phase shown has not yet been formed).

[0125] According to some embodiments, in order to adjust the performance of the transistors, the width W1 of the gate transistor PG-1, the gate transistor PG-2, the pull-down transistor PD-1, and the pull-down transistor PD-2 is greater than the width W2 of the pull-up transistors PU-1 and PU-2. According to some embodiments, the ratio of width W1 to width W2 can be in the range of approximately 1.2 to 3.

[0126] According to some embodiments, dummy gate stacks 30 (including dummy gate stacks 30-1 and 30-2) are formed on protruding fins 28-1, 28-2, 28-3, and 28-4. The length direction of the dummy gate stacks 30 is perpendicular to the length direction of the protruding fins 28. Gate spacers 38 are formed on opposite sidewalls of the dummy gate stacks 30. According to some embodiments, the dummy gate stacks 30 are located at the fin ends of the protruding fins 28-2.

[0127] Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figures 6 to 14 , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figures 19A-19C ,and Figures 20A to 20D This diagram illustrates intermediate stages in the formation of a static random access memory cell, according to some embodiments of the present invention. The corresponding process is also schematically reflected in the process flow 200 shown in Figure 22.

[0128] Figure 3 , Figure 4 ,and Figure 5A The diagram illustrates, schematically, an exemplary forming process for the protruding fin 28 according to some embodiments. It should be understood that... Figure 3 , Figure 4 ,and Figure 5A The structure shown is only to illustrate how the protruding fins are formed. However, the actual relationships (such as relative positions and dimensions) of the protruding fins used to form static random access memory cells are not shown. Figure 3 , Figure 4 ,and Figure 5A middle.

[0129] Reference Figure 3 The diagram shows a perspective view. Wafer 12 includes a multilayer structure comprising a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, or other similar materials, and other substrates and / or structures may be used, such as semiconductor-on-insulator (SOI), strained semiconductor-on-insulator, silicon germanium on insulator (SGOI), or other similar materials. Doped substrate 20 is a P-type semiconductor, although in other embodiments, doped substrate 20 is an N-type semiconductor.

[0130] According to some embodiments, an interleaved material is deposited through a series of deposition processes to form a multilayer stack 22. A particular process is shown as process 202 of process flow 200 shown in Figure 22. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0131] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes the above materials such as silicon germanium, germanium (Ge), silicon, gallium arsenide (GaAs), indium antimonide (InSb), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaSbAs), or other similar materials. According to some embodiments, the first layer 22A (e.g., silicon-germanium) is deposited by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), ultra-high vacuum chemical vapor deposition (UHV-CVD), reduced-pressure chemical vapor deposition (RPCVD), or other similar methods.

[0132] A second layer 22B is deposited on the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as silicon, silicon germanium, germanium, gallium arsenide, indium antimonide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, combinations thereof, or other similar materials, and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments, if the first layer 22A is silicon germanium, then the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0133] The deposition process is repeated to form the remaining film layers of the multilayer stack 22 until the desired top layer of the multilayer stack 22 is formed. According to some embodiments, the thicknesses of the first layers 22A are the same or similar to each other, and the thicknesses of the second layers 22B are the same or similar to each other. The thickness of the first layer 22A may also be the same as or different from the thickness of the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is referred to herein instead as a sacrificial layer.

[0134] According to some embodiments, a layer of pad oxide and a hard mask (not shown) may be formed on the multilayer stack 22. These film layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0135] Reference Figure 4 In the etching process, a multilayer stack 22 and a portion of the underlying substrate 20 are patterned to form trenches 23. Individual processes are shown as follows: Figure 22 Process 204 of the process flow 200 shown. Trench 23 extends into substrate 20. The remainder of multilayer stack 22 is hereinafter referred to as multilayer stack 22'. Some portion of substrate 20 remains below multilayer stack 22', hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes a first layer 22A and a second layer 22B. First layer 22A is hereinafter alternatively referred to as sacrificial layer, and second layer 22B is hereinafter alternatively referred to as nanostructure. The portion of multilayer stack 22' and the underlying substrate strip 20' is collectively referred to as semiconductor strip 24.

[0136] Figure 5A The isolation zone 26 is shown, also referred to throughout this text as the shallow trench isolation zone. Individual processes are shown as follows. Figure 22 Process 206 of the process flow 200 shown. The portion of substrate 20 below isolation region 26 is hereinafter referred to as the body semiconductor substrate. Isolation region 26 may include a dielectric liner (see reference). Figure 5BThe dielectric material can be a thermal oxide formed by a surface film layer of the thermally oxidized substrate 20. Next, a planarization process (such as chemical mechanical polishing (CMP) or mechanical grinding) can be performed to make the top surface of the dielectric material flush with the substrate, leaving the remaining portion of the dielectric material as the isolation region 26.

[0137] Then, the isolation region 26 is etched inward so that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the isolation region 26 to form a protruding fin 28. The protruding fin 28 includes the top of the multilayer stack 22' and the substrate strip 20'.

[0138] Figure 5B A cross-section perpendicular to the length direction of the protruding fin is shown, which is similar to... Figure 5A Section A1-A1 in the middle. Figure 5A The cross-section also reflects Figure 2 The structure shown in the mid-section 20C-20C. Figure 5B The cross-section shown is composed of Figure 2 The cross-section 20C-20C shown is obtained. Therefore, protruding fins 28-1, 28-2, 28-3, and 28-4 are shown in the same cross-section. Furthermore, according to some embodiments, protruding fins 28-2 and 28-3 are shown to be narrower than protruding fins 28-1 and 28-4. The protruding fin 28-2 shown is at the end of a line (e.g., ...). Figure 2 As shown), it is located directly below the subsequently formed dummy gate stack 30-1.

[0139] Reference Figure 6 This forms dielectric layer 120 (also known as dielectric substrate). Individual processes are shown as follows: Figure 22 Process 208 of the process flow 200 shown. The material of dielectric layer 120 may be the same as or different from the material of isolation region 26. According to some embodiments, dielectric layer 120 comprises silicon dioxide (SiO2), but other materials may also be used, such as silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or other similar materials. Formation methods may include deposition processes, which may be compliant deposition processes (such as atomic layer deposition, chemical vapor deposition, or other similar methods).

[0140] Figure 7 The deposition of hard mask layer 122 (also referred to as a protective layer) is shown. Individual processes are shown as follows. Figure 22Process 210 of the process flow 200 shown. According to some embodiments, a hard mask layer 122 is formed as a non-compliant film layer, having a sidewall portion with a thickness T1, a top portion with a thickness T2, and a bottom portion with a thickness T3. Thicknesses T2 and T3 are greater than thickness T1. For example, the ratio of thickness T2 to thickness T1, and the ratio of thickness T3 to thickness T1, can be in the range of approximately 3 to 20.

[0141] The hard mask layer 122 is formed with a dielectric material that is different from that of the underlying isolation region 26 and the subsequently formed disposable oxide interposer (having a relatively high etch selectivity). For example, the etch selectivity may be higher than about 10. The material of the hard mask layer 122 is selected to have a high etch selectivity relative to some materials such as oxides, such that the hard mask layer 122 is not etched when these materials are etched.

[0142] According to some embodiments, the hard mask layer 122 may be formed of or include silicon and nitrogen dielectric materials and / or silicon and carbon dielectric materials, such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride, silicon carbide (SiC), silicon carbide, or other similar materials. The hard mask layer 122 may also include high-k dielectric materials, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium silicate (HfSiO), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), other similar materials, or combinations thereof.

[0143] Figure 8 The formation of sacrificial layer 124 is shown, which is used as an etching mask. Individual processes are shown as follows. Figure 22 Process 212 of the process flow 200 shown. According to some embodiments, the sacrificial layer 124 includes a material that can be used as a bottom antireflective coating (BARC) and may include cross-linked photoresist, silicon carbide, or other similar materials. The formation of the sacrificial layer 124 may include a deposition (or feeding) process, followed by a planarization process, and then an etch-back process. The top of the hard mask layer 122 is thus exposed.

[0144] Figure 9The etching process is shown to remove some of the top of the hard mask layer 122. Individual processes are shown as follows. Figure 22 Process 214 of the process flow 200 shown. Etching can be performed by dry etching, wet etching, or other similar methods. Etching chemicals are selected to have a very low etch rate on dielectric layer 120, and dielectric layer 120 can be used as an etch stop layer (ESL). After the etching process, the top of hard mask layer 122 can be completely removed to expose dielectric layer 120, or a thinner portion may remain.

[0145] Then, the sacrificial layer 124 is removed, followed by an etching process to remove the top (if any) and sidewall portions of the hard mask layer 122. Individual processes are shown as follows: Figure 22 The process flow 200 shown is process 216. The resulting structure is shown in Figure 10 The remaining sacrificial layer 124 extends from the edge of the protruding fin 28 to the nearest edge of the adjacent protruding fin 28. The etching process can be isotropic, which can be performed by dry etching or wet etching. The dielectric layer 120 is used as an etch stop layer.

[0146] According to some embodiments, when etching stops, the remaining hard mask layer 122 is neither too thick nor too thin. A hard mask layer 122 that is too thin makes process control challenging, and non-uniformity across the wafer surface can cause the hard mask layer 122 to be completely etched in some portions of the wafer or become too thin to protect the underlying shallow trench isolation region during subsequent wafer formation. A hard mask layer 122 that is too thick, due to its high dielectric constant, can result in excessively high capacitance between the subsequently formed gate electrode and the semiconductor strip 24. According to some embodiments, the thickness of the remaining hard mask layer 122 is in the range between approximately 2 nm and 10 nm.

[0147] like Figure 11 As shown, an etched mask 128 is formed and patterned. According to some embodiments, the etched mask 128 includes photoresist, which is patterned by a photolithography process. An opening 130 is thus formed in the etched mask 128. A protruding fin 28-1 is located directly beneath the remainder of the etched mask 128. (See reference...) Figure 2 The etched mask 128 is shown schematically.

[0148] It should be understood that the portions of the etch mask 128 adjacent to the protruding fins 28-1 and 28-4 used to form the gate transistors, while the portions of the protruding fins 28-1, 28-2, 28-3, and 28-4 used to form pull-up transistors PU-1, PU-2, PD-1, and PD-2 are located directly below the opening 130. In other words, the opening 130 is located where the etch mask 128 is not formed.

[0149] It should be noted that, in Figure 2 In section 20C'-20C', the schematic cross-section is essentially the same as... Figure 11 The same as shown, except when by Figure 2 When viewed from the left, Figure 11 The cross-section shown reflects section 20°C-20°C, while when... Figure 2 When viewed from the right, Figure 11 The cross-section shown reflects the view of section 20C'-20C'.

[0150] Reference Figure 11 and Figure 12 The hard mask layer 122 is etched, and the portion of the hard mask layer 122 adjacent to the subsequent gate transistor remains unetched. A specific process is shown as process 218 of process flow 200 shown in Figure 22. The portion of the hard mask layer 122 not below the etch mask 128 is etched and removed. During the etching of the hard mask layer 122, the dielectric layer 120 can also be used as an etch stop layer. The remaining portion of the hard mask layer 122 is alternatively referred to as the hard mask.

[0151] Then, the etch mask 128 is removed. The resulting structure is shown in... Figure 12 The remaining portion of the hard masking layer 122 also includes portions on opposite sides of the protruding fins 28-1, and portions on opposite sides of some portions of the protruding fins 28-4 (such as portions that can be made from...). Figure 2 (As learned). According to some embodiments, the width W3 of the hard mask can be between about 1 / 3 and 2 / 3 of the interval S1 between adjacent protruding fins 28-1 and 28-2.

[0152] Next, as Figure 13 As shown, dielectric layer 120 is etched to expose the protruding fins 28. A specific process is shown as process 220 of process flow 200 shown in Figure 22. Etching can be performed using either a dry etching process or a wet etching process. Dielectric layer 120 thus forms the dielectric substrate of a hard mask. Throughout this document, dielectric layer 120 and hard mask layer 122 are also referred to together as a hard mask or composite hard mask.

[0153] Reference Figure 14The diagram shows a perspective view, illustrating the formation of dummy gate stacks 30 and gate spacers 38 on the top surface and sidewalls of the protruding fins 28. Individual process details are shown below. Figure 22 Process 222 of the process flow 200 shown. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer (such as a silicon oxide layer). The dummy gate electrode 34 may be formed using, for example, polycrystalline silicon or amorphous silicon, and other materials (such as amorphous carbon) may also be used.

[0154] Each dummy gate stack 30 may also include one (or more) hard masks 36 on the dummy gate electrode 34. The hard masks 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stack 30 may extend across one or more protruding fins 28 and an isolation region 26 between the protruding fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard masks, and subsequently patterning the formed film layer by a patterning process.

[0155] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present invention, the gate spacers 38 are formed of a dielectric material (such as silicon nitride, silicon carbide, silicon dioxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or other similar materials), and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The formation of the gate spacers 38 may include depositing one or more dielectric layers, followed by an anisotropic etching process. The remaining portion of the dielectric layer constitutes the gate spacers 38.

[0156] Figure 15A The source / drain etching process is shown. Individual processes are shown as follows: Figure 22 The process flow 200 shown is process 224. Figure 15A Show Figure 14 The cross-section BB is shown. In the anisotropic etching process, the portion of the protruding fin 28 not located directly below the dummy gate stack 30 and the gate spacer 38 is etched. This forms the source / drain recess 42, as shown. Figure 15A As shown. Figure 15B shows the relationship with... Figure 13 The same cross-section is shown, which corresponds to cross-section A2-A2( Figure 14 ).

[0157] Figure 16A , Figure 16B , Figure 17A ,and Figure 17BThis illustrates replacing the first layer 22A (sacrificial layer) with a disposable intermediate layer 29. (See reference...) Figure 16A and Figure 16B They respectively show Figure 14 In the sections BB and A2-A2, the first layer 22A is first removed to form the opening 27 between the second layer 22B (nanostructure). Individual processes are shown as follows. Figure 22 The process 226 of the process flow 200 shown is shown.

[0158] Reference Figure 17A and Figure 17B A removable interlayer 29 is formed between the second layer 22B (nanostructure). Individual processes are shown as follows. Figure 22 Process 228 of the process flow 200 shown. According to some embodiments, the disposable interposer 29 comprises an oxide (such as silicon oxide) and is therefore also referred to as a disposable oxide interposer. According to other embodiments, other types of dielectric materials may also be used.

[0159] The formation of the disposable interposer 29 may include depositing a dielectric layer using a compliant deposition process (such as atomic layer deposition, chemical vapor deposition, or other similar methods). The dielectric layer thus includes a portion filling the opening 27 and the remaining portion outside the opening 27. An isotropic etching process is then performed to etch and remove the portion of the dielectric layer outside the opening 27. The remaining portion of the dielectric layer thus constitutes the disposable interposer 29.

[0160] According to an alternative embodiment, the first layer 22A (sacrificial layer) at the line tip of the protruding fin 28-2 is not replaced by a disposable interposer layer 29. This can be achieved by forming an etch mask to protect the line tip. According to an alternative embodiment, the first layer 22A at the line tip of the protruding fin 28-2 is also replaced by a disposable interposer layer 29, such as... Figure 17B As shown.

[0161] Then, the disposable intermediate layer 29 is etched laterally and filled to form an inner spacer 44. Figure 17A Individual processes are shown as follows: Figure 22 Process 230 of the process flow 200 shown. Lateral etching of the disposable interposer 29 can be achieved by wet etching or dry etching. Wet etching can be performed using immersion etching, spray etching, spin-on coating, or other similar methods. The second layer 22B (nanostructure) is not etched.

[0162] Then, an inner spacer 44 is formed. According to some embodiments, the formation of the inner spacer 44 includes depositing a compliant dielectric layer that extends into the lateral groove. Next, an etching process is performed to trim the portion of the dielectric layer outside the lateral groove (also known as a spacer trimming process), leaving the portion of the dielectric layer in the lateral groove. The remaining portion of the dielectric layer is referred to as the inner spacer 44.

[0163] Reference Figure 18A and Figure 18B Epitaxial source / drain regions 48 are formed in the source / drain trench 42 through selective epitaxy. Some processes are shown as follows: Figure 22 Process 232 of the process flow 200 shown. Depending on whether the resulting transistor is a P-type or N-type transistor, P-type or N-type impurities can be doped in situ during epitaxy. For example, when the resulting transistor is a P-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), or other similar materials can be grown. Conversely, when the resulting transistor is an N-type transistor, silicon phosphide (SiP), silicon phosphocarbide (SiCP), or other similar materials can be grown.

[0164] Then, a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52 are formed. Silicon oxide, silicon nitride, silicon carbonitride, or other similar materials can be used, and the contact etch stop layer 50 can be formed using chemical vapor deposition, atomic layer deposition, or other similar methods. The interlayer dielectric 52 can include a dielectric material formed using, for example, flowable chemical vapor deposition (FCVD), spin coating, chemical vapor deposition, or any other suitable deposition method. The interlayer dielectric 52 can be formed using an oxygen-containing dielectric material, which can include silicon oxide, phosphosilicate glass (PSG), boron-doped silicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or other similar materials.

[0165] The contact etch stop layer 50 and interlayer dielectric 52 are planarized using a planarization process (such as chemical mechanical polishing or mechanical polishing). According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, such as… Figure 18A and Figure 18B As shown. According to an alternative embodiment, the planarization process may expose and stop at the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the interlayer dielectric 52 are flush within the process variations.

[0166] Next, the dummy gate electrode 34 and dummy gate dielectric 32 (and hard mask 36, if any) are removed in one or more etching processes to form the recess 58, as shown. Figure 19A , Figure 19B ,and Figure 19C As shown. A specific process is shown as process 234 of process flow 200 shown in Figure 22. According to some embodiments, the dummy gate electrode 34 and dummy gate dielectric 32 are removed by an anisotropic dry etching process. For example, a reactive gas etching process can be used, which selectively etches the dummy gate electrode 34 and dummy gate dielectric 32 faster than etching the interlayer dielectric 52. Each recess 58 is exposed and / or on a portion of the multilayer stack 22', which includes a channel region in the subsequently completed transistor.

[0167] Then, the disposable interposer 29 is removed to extend the groove 58 between the second layer 22B (nanostructure). Individual processes are shown as follows. Figure 22 Process 236 of the process flow 200 shown. The disposable interposer 29 can be removed by performing an isotropic etching process, such as a wet etching process using an etchant selective to the material of the disposable interposer 29, while the second layer 22B and the substrate 20 remain relatively unetched compared to the disposable interposer 29. According to some embodiments where the disposable interposer 29 includes, for example, silicon oxide, the disposable interposer 29 can be removed using a mixture of nitrogen trifluoride (NF3) and ammonia (NH3), a mixture of hydrofluoric acid (HF) and ammonia, or hydrofluoric acid.

[0168] According to some embodiments, the disposable interlayer 29 in the wire ends of the protruding fins 28-2 is not removed, such as... Figure 19B As shown. This can be achieved by forming an etch mask to protect its disposable interposer layer 29. According to an alternative embodiment where the line ends of the protruding fin 28-2 include a first layer 22A (sacrificial layer) that is not replaced by the disposable interposer layer 29, the first layer 22A in the line ends of the protruding fin 28-2 is not removed, as... Figure 19B As shown. According to another alternative embodiment, the removable interlayer 29 in the wire ends of the protruding fins 28-2 is also removed, as... Figure 19C As shown.

[0169] During the etching of the disposable interposer 29, the isolation region 26 directly beneath the hard mask layer 122 is protected from etching by the hard mask layer 122 due to a high etch selectivity (the ratio of the etch rate of the disposable interposer 29 to the etch rate of the hard mask layer 122). On the other hand, the isolation region 26 not protected by the hard mask layer 122 is etched back. Thus, a groove 134 is formed, which is etched from the original top surface 26T of the isolation region 26. According to some embodiments, the etch pitch D1 can be in the range of approximately 0.5 nm to 5 nm.

[0170] It should be understood that although the groove 134 is shown with sharp corners, the corners can be rounded or sharp. For example, in a cross-sectional view, the groove 134 may be U-shaped. The isolation area 26 portion directly below the groove 134 has an etched top surface 26T'. According to some embodiments, the entire top surface 26T' is lower than the entire top surface 26T.

[0171] According to some embodiments, an undercut 135 may be formed directly beneath the hard mask layer 122, as shown by dashed lines. According to some embodiments, the lateral etch spacing of the undercut 135 may be in the range of approximately 0.5 nm to 5 nm.

[0172] Reference Figure 20A , Figure 20B ,and Figure 20C This forms the gate dielectric 62 and the gate electrode 68, thus forming the replacement gate stack 70. Individual processes are shown as follows: Figure 22 Process 238 of the process flow 200 shown. According to some embodiments, each gate dielectric 62 includes an interfacial layer (IL) and a high-k dielectric layer on the interfacial layer. The interfacial layer may be formed of or comprise silicon oxide, which may be deposited by an compliant deposition process such as atomic layer deposition or chemical vapor deposition, or an oxidation process. According to some embodiments, the high-k dielectric layer includes one or more high-k dielectric layers. For example, the high-k dielectric layer may include metal oxides, or hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), manganese (Mn), barium (Ba), titanium (Ti), lead (Pb), or combinations thereof, or silicates. According to some embodiments where the interfacial layer is formed by oxidation, the high-k dielectric layer is in physical contact with the top surface and sidewalls of the hard mask layer 122.

[0173] A gate electrode 68 is formed on the gate dielectric 62. During formation, a conductive layer is first formed on a high-dielectric-constant dielectric layer and the remainder of the groove 58 is filled. The gate electrode 68 may include a metallic material such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), cobalt (Co), ruthenium (Ru), aluminum, tungsten (W), combinations thereof, and / or multiple layers thereof. For example, the gate electrode 68 may include any number of film layers, any number of work function layers, and possible filler materials. The gate dielectric 62 and the gate electrode 68 also fill the space between adjacent second layers 22B (nanostructures) and the space between the bottom of the second layer 22B and the underlying substrate strip 20'.

[0174] After filling the recess 58, a planarization process (such as chemical mechanical polishing or mechanical polishing) is performed to remove excess portions of the gate dielectric 62 and gate electrode 68 (on the top surface of the interlayer dielectric 52). The gate electrode 68 and the gate dielectric 62 together are referred to as the replacement gate stack 70 of the resulting transistor.

[0175] Figure 21 The above diagram shows a static random access memory cell. In addition to the transistors and gate stacks, a gate isolation region 138, which is also a cut-metal gate region, is shown. The gate isolation region 138 is formed of a dielectric material. The gate isolation region 138 is used to separate gate stacks that are not intended to be interconnected.

[0176] According to some embodiments, such as Figure 20B and Figure 20C As shown, gate isolation region 138 is located on the top surface of gate dielectric 62, and in the formation of gate isolation region 138, gate dielectric 62 is used as an etch stop layer. According to an alternative embodiment, gate isolation region 138 extends through gate dielectric 62 and is located on isolation region 26, and may also be located on hard mask layer 122 (see Figure 122). Figure 20B and Figure 20C (Left gate isolation region 138). According to these embodiments, the gate dielectric 62 may be left in some vertical portions of region 123 to contact the vertical edges of individual gate isolation regions 138.

[0177] Figure 20B The diagram shows a cross-sectional view of a static random access memory (SRAM) cell, which consists of... Figure 21The cross-section 20C-20C shown is obtained. Cross-section 20C-20C cuts into the line ends of the gate stack and protruding fins. Figure 20B An embodiment of the line end is shown, which includes a disposable interposer 29 or a first layer 22A (sacrificial layer), depending on the process used. The gate transistor PG-1, the line end, the pull-up transistor PU-2, and the pull-down transistor PD-2 are shown in cross section 20C-20C.

[0178] According to some embodiments, all gate transistors in a static random access memory (SRAM) cell, and in all SRAM cells of an SRAM array, include a hard mask layer 122 on opposite sides of the channel region (second layer 22B (nanostructure)). Conversely, all pull-up and pull-down transistors in a SRAM cell, and in all SRAM cells of an SRAM array, do not include the hard mask layer 122 on opposite sides of the channel region.

[0179] Figure 20C An embodiment is shown in which the replacement gate stack 70 also extends into the line end of the protruding fin 28-2.

[0180] Figure 20D The diagram shows a cross-sectional view of a static random access memory (SRAM) cell, which consists of... Figure 21 The cross-section 20D-20D shown is obtained. The cross-section 20D-20D is obtained from the gate spacer 38. The hard mask layer 122 is also included. Figure 20D The portion shown in section 20D-20D.

[0181] The embodiments of this invention have several advantages. By forming a hard mask and partially removing the hard mask from opposite sides of the protruding structures (and channel regions) of the pull-up and pull-down transistors, the alternative gate stacks of the pull-up and pull-down transistors extend lower than the alternative gate stacks of the pass-gate transistor. The pull-up and pull-down transistors can thus have better gate control, while the pass-gate transistor can have smaller bit-line capacitance. Therefore, the performance of the pass-gate transistor can be tuned separately from the performance of the pull-up and pull-down transistors.

[0182] According to some embodiments of the present invention, a method for forming a static random access memory (SRAM) includes: forming a shallow trench isolation region in a semiconductor substrate; forming a first protruding fin and a second protruding fin above the shallow trench isolation region and on opposite sides of the shallow trench isolation region; and forming a hard mask on the shallow trench isolation region. The hard mask includes: a first portion closer to the first protruding fin and overlapping with a first portion of the shallow trench isolation region; and a second portion closer to the second protruding fin and overlapping with a second portion of the shallow trench isolation region. The method for forming the SRAM further includes: patterning the hard mask to remove the second portion of the hard mask, leaving the first portion of the hard mask on the first portion of the shallow trench isolation region; and forming a gate stack on the first portion of the hard mask, wherein the gate stack and portions of the first protruding fin together form a first transistor.

[0183] In one embodiment, the first protruding fin includes: a first semiconductor layer; a second semiconductor layer overlapping the first semiconductor layer; and a disposable interposer layer between the first semiconductor layer and the second semiconductor layer. The method of forming a static random access memory further includes removing the disposable interposer layer by etching, wherein when the disposable interposer layer is removed, a second portion of the shallow trench isolation region is etched, while a first portion of the shallow trench isolation region is protected from etching. In one embodiment, the disposable interposer layer and the shallow trench isolation region include the same dielectric material. In one embodiment, the shallow trench isolation region includes silicon oxide, and the hard mask includes silicon nitride. In one embodiment, the gate stack includes a gate dielectric and a gate electrode on the gate dielectric, wherein the gate dielectric contacts the hard mask. In one embodiment, the gate dielectric physically contacts the top surface and sidewalls of the hard mask. In one embodiment, after patterning the hard mask, the hard mask includes: a third portion overlapping the second shallow trench isolation region, wherein the third portion is on the opposite side of the first protruding fin relative to the first portion of the hard mask. In one embodiment, the hard mask includes a third portion and a fourth portion on opposite sides of the third protruding fin, wherein both the third and fourth portions are removed after the hard mask is patterned. In one embodiment, the first transistor is a gate transistor of a static random access memory (SRAM) cell. In one embodiment, the method of forming the SRAM further includes forming a second transistor of the SRAM cell, wherein the second transistor is selected by pull-up and pull-down transistors of the SRAM cell, wherein, during the patterning of the hard mask, portions of the hard mask on opposite sides of the channel region of the second transistor are removed.

[0184] According to some embodiments of the present invention, a static random access memory (SRAM) includes: a main semiconductor substrate; a first shallow trench isolation region on the main semiconductor substrate, wherein the first shallow trench isolation region includes a first portion and a second portion; a first semiconductor strip including a first edge contacting the first shallow trench isolation region, wherein the first portion of the first shallow trench isolation region is laterally located between the first semiconductor strip and the second portion of the first shallow trench isolation region, and a first top surface of the first portion is higher than a second top surface of the second portion; a composite hard mask contacting the first edge of the first semiconductor strip, wherein the composite hard mask is on the first portion of the first shallow trench isolation region; and a first gate stack overlapping the composite hard mask and the first shallow trench isolation region, wherein the portion of the first gate stack overlapping the second portion of the first shallow trench isolation region is lower than the composite hard mask, wherein the first gate stack is part of a first transistor.

[0185] In one embodiment, the first shallow trench isolation region comprises silicon oxide, and the composite hard mask comprises silicon nitride. In one embodiment, the static random access memory (SRAM) comprises a SRAM cell. The SRAM cell comprises: a first transistor as a gate transistor; a second transistor including a second gate stack; and a second shallow trench isolation region below the second gate stack, wherein the SRAM does not contain material of the composite hard mask, the composite hard mask being located between the second shallow trench isolation region and the second gate stack. In one embodiment, a group of pull-up and pull-down transistors of the SRAM cell selects the second transistor. In one embodiment, the composite hard mask comprises: a dielectric liner including a first dielectric material; and a dielectric region including a second dielectric material, different from the first dielectric material, wherein the dielectric region is on the dielectric liner. In one embodiment, the SRAM further comprises a second semiconductor strip on the opposite side of the first shallow trench isolation region relative to the first semiconductor strip, wherein a second top surface of the second portion extends to the second semiconductor strip. In one embodiment, the entire second top surface of the second portion is lower than the entire first top surface of the first portion.

[0186] According to some embodiments of the present invention, a static random access memory (SRAM) includes: a main semiconductor substrate; a first dielectric isolation region, a second dielectric isolation region, a third dielectric isolation region, and a fourth dielectric isolation region on the main semiconductor substrate; a first semiconductor strip located between and in contact with the first and second dielectric isolation regions; a first semiconductor layer overlapping with and spaced apart from the first semiconductor strip; and a first gate stack located on and in contact with the first dielectric isolation region, the second dielectric isolation region, and the first semiconductor strip. The first gate stack surrounds the first semiconductor layer; a composite hard mask is located between the first gate stack and the first dielectric isolation region; a second semiconductor strip is located between and in contact with the third and fourth dielectric isolation regions; a second semiconductor layer overlaps with and is spaced apart from the second semiconductor strip; and a second gate stack is located on and in contact with the third and fourth dielectric isolation regions, wherein the second gate stack surrounds the second semiconductor layer, and the interface between the second gate stack and the third dielectric isolation region extends to the opposite sidewalls of the third dielectric isolation region.

[0187] In one embodiment, the first dielectric isolation region includes a first top surface and a second surface, wherein the first top surface is laterally located between the first semiconductor strip and the second surface, and the second surface is lower than the first top surface. In another embodiment, the first top surface is below the composite hard mask and forms an additional interface with the composite hard mask.

[0188] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A static random access memory, characterized in that, include: A main semiconductor substrate; A first shallow trench isolation region is provided on the main semiconductor substrate, wherein the first shallow trench isolation region includes a first portion and a second portion; A first semiconductor strip includes a first edge contacting the first shallow trench isolation region, wherein a first portion of the first shallow trench isolation region is laterally located between the first semiconductor strip and a second portion of the first shallow trench isolation region, and a first top surface of the first portion is higher than a second top surface of the second portion; A composite hard mask contacts the first edge of the first semiconductor strip, wherein the composite hard mask is on the first portion of the first shallow trench isolation region; and A first gate stack overlaps with the composite hard mask and the first shallow trench isolation region, wherein the portion of the first gate stack overlapping with the second part of the first shallow trench isolation region is below the composite hard mask, wherein the first gate stack is part of a first transistor.

2. The static random access memory as described in claim 1, characterized in that, The first gate stack includes: A gate dielectric on the composite hard mask and the first shallow trench isolation region; and A gate electrode is located on the gate dielectric.

3. The static random access memory as described in claim 1, characterized in that, Includes a static random access memory unit, comprising: The first transistor serves as a gate transistor; A second transistor, including a second gate stack; and A second shallow trench isolation region is located below the second gate stack, wherein the composite hard mask is located between the second shallow trench isolation region and the second gate stack.

4. The static random access memory as described in claim 3, characterized in that, The second transistor is selected by a group consisting of a pull-up transistor and a pull-down transistor of the static random access memory cell.

5. The static random access memory as described in claim 1, characterized in that, The composite hard mask includes: A dielectric substrate; and A dielectric region on the dielectric substrate.

6. The static random access memory as described in claim 1, characterized in that, It also includes a second semiconductor strip on the opposite side of the first shallow trench isolation region relative to the first semiconductor strip, wherein the second top surface of the second portion extends to the second semiconductor strip.

7. The static random access memory as described in claim 1, characterized in that, The entire second top surface of the second part is lower than the entire first top surface of the first part.

8. A static random access memory, characterized in that, include: A main semiconductor substrate; A first dielectric isolation region, a second dielectric isolation region, a third dielectric isolation region, and a fourth dielectric isolation region are disposed on the main semiconductor substrate; A first semiconductor strip is located between the first dielectric isolation region and the second dielectric isolation region, and contacts the first dielectric isolation region and the second dielectric isolation region; A first semiconductor layer, overlapping with and spaced apart from the first semiconductor strip; A first gate stack is on and in contact with the first dielectric isolation region, the second dielectric isolation region, and the first semiconductor strip, wherein the first gate stack surrounds the first semiconductor layer; A composite hard shield is located between the first gate stack and the first dielectric isolation region; A second semiconductor strip is located between the third dielectric isolation region and the fourth dielectric isolation region, and contacts the third dielectric isolation region and the fourth dielectric isolation region; A second semiconductor layer, overlapping with and spaced apart from the second semiconductor strip; and A second gate stack is on and in contact with the third and fourth dielectric isolation regions, wherein the second gate stack surrounds the second semiconductor layer, and wherein the interface between the second gate stack and the third dielectric isolation region extends to the opposite sidewalls of the third dielectric isolation region.

9. The static random access memory as described in claim 8, characterized in that, The first dielectric isolation region includes a first top surface and a second surface, wherein the first top surface is laterally located between the first semiconductor strip and the second surface, and the second surface is lower than the first top surface.

10. The static random access memory as described in claim 9, characterized in that, The first top surface is located below the composite hard mask and forms an additional interface with the composite hard mask.

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