An SRAM cell layout structure

Abstract

The utility model provides a kind of SRAM unit layout structure, including at least one group of shared contact hole pattern pair, and each group of shared contact hole pattern pair includes two adjacently arranged shared contact hole patterns, shared contact hole pattern includes first part and second part connected, two first parts are respectively arranged on a gate pattern, two second parts are oppositely arranged between two first parts, and the straight line where second part is located does not intersect;First part extends along target straight line, and there is acute angle included angle between the straight line where the extension direction of second part is located and target straight line, and target straight line is the straight line where the extension direction of each active area pattern of the SRAM unit layout structure is located, to extend along target straight line by the first part under the premise that SRAM unit area is not changed, there is acute angle included angle between the straight line where the extension direction of second part is located and target straight line, to pull apart the spacing between two second parts, bridge leakage problem between shared contact hole is solved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing technology, and in particular to an SRAM cell layout structure. Background Technology

[0002] With the continuous iteration and advancement of integrated circuit manufacturing processes, device feature sizes are constantly shrinking, placing higher demands on the area and power consumption of Static Random Access Memory (SRAM) cells. At advanced process nodes, 6T SRAM cells, as the most common memory structure, face increasingly severe challenges in layout design. Existing 6T SRAM cell layouts typically consist of six transistors (including two pull-up transistors PU, two transmission gate transistors PG, and two pull-down transistors PD). For example... Figure 1 As shown, the 6T SRAM cell layout consists of basic components such as a long strip-shaped active area (AA) 10, a gate (GT) 20, and a contact (CT) 30. To optimize the cell area to the extreme, a shared contact (CT) 31 and 32 design is commonly used, that is, a single contact connects the source and gate of two adjacent transistors simultaneously.

[0003] However, with the advancement of process nodes, the physical size of SRAM cells has drastically decreased, leading to increasingly smaller spacing (space) h1 between two adjacent shared contact holes 31 and 32. Currently, these shared contact holes are typically designed as rectangles, a shape with inherent drawbacks under miniaturization conditions: they are large in size and have a wide etching range during etching. During the contact hole etching process, it is difficult to simultaneously achieve uniform etching across different topologies and contact hole sizes within the layout. This control challenge in the etching process leads to serious reliability risks, such as… Figure 2 As shown, bridging can easily occur between two adjacent shared contact holes 31 and 32. Once bridging occurs, an unexpected short circuit path is formed, causing leakage in the storage node, severely damaging the data retention capability and read / write stability of the SRAM cell, and ultimately having a significant negative impact on the product yield and reliability. Summary of the Invention

[0004] The purpose of this invention is to provide an SRAM cell layout structure that can solve the bridging leakage problem between shared contact holes.

[0005] To solve the above technical problems, this utility model provides an SRAM cell layout structure, including multiple active area patterns and at least one set of shared contact hole pattern pairs. Each set of shared contact hole pattern pairs includes two adjacent shared contact hole patterns. The shared contact hole pattern includes a connected first part and a second part. The two first parts are respectively disposed on a gate pattern, and the two second parts are disposed facing each other between the two first parts, and the straight lines of the two second parts do not intersect.

[0006] Wherein, the first part extends along the target straight line, and the straight line in which the extension direction of the second part is located has an acute angle with the target straight line, and the target straight line is the straight line in which the extension direction of each active area pattern of the SRAM cell layout structure is located.

[0007] Optionally, the shared contact hole pattern includes a first shared contact hole pattern and a second shared contact hole pattern. A first portion of the first shared contact hole pattern and a first portion of the second shared contact hole pattern are respectively disposed on a gate pattern. The two gate patterns are arranged in parallel. A second portion of the first shared contact hole pattern and a second portion of the second shared contact hole pattern are both located between the two gate patterns. A first gap exists between the second portion of the first shared contact hole pattern and the gate pattern on which the first portion of the second shared contact hole pattern is disposed. A second gap exists between the second portion of the second shared contact hole pattern and the gate pattern on which the first portion of the first shared contact hole pattern is disposed.

[0008] Furthermore, the straight line extending from the second part of the first shared contact hole pattern and the target straight line have an acute angle of 10° to 30°, and the straight line extending from the second part of the second shared contact hole pattern and the target straight line have an acute angle of 10° to 30°.

[0009] Furthermore, the values ​​of the first interval and the second interval are greater than 0.05 μm.

[0010] Furthermore, the values ​​of the first interval and the second interval are greater than 0.075 μm.

[0011] Furthermore, the second portion of both the first shared contact hole pattern and the second portion of the second shared contact hole pattern are parallelograms.

[0012] Furthermore, at least one of the second portion of the first shared contact hole pattern and the second portion of the second shared contact hole pattern has a misaligned structure extending in a direction away from the other.

[0013] Furthermore, the misaligned structure is composed of multiple identical spliced ​​rectangles.

[0014] Furthermore, the line width of the splicing rectangle on the target line is the same as the line width of the corresponding connected first part on the target line, but the line width of the splicing rectangle on the target line is smaller than the line width of the splicing rectangle on the target line.

[0015] On the other hand, this utility model also provides an SRAM cell layout structure, including at least one set of shared contact hole pattern pairs. Each set of shared contact hole pattern pairs includes two adjacent shared contact hole patterns. The shared contact hole pattern includes a connected first part and a second part. The two first parts are respectively disposed on a gate pattern, and the two second parts are disposed facing each other between the two first parts.

[0016] The first part and the second part both extend along the target straight line and have an overlapping area, the length of which is less than or equal to half the distance between the two first parts in the target straight line direction.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] This invention provides an SRAM cell layout structure, including multiple active area patterns and at least one pair of shared contact hole patterns. Each pair of shared contact hole patterns includes two adjacent shared contact hole patterns, each comprising a connected first part and a second part. The two first parts are respectively disposed on a gate pattern, and the two second parts are disposed facing each other between the two first parts, with the straight lines containing the two second parts not intersecting. The first part extends along a target straight line, and the straight line containing the extension direction of the second part forms an acute angle with the target straight line. The target straight line is the straight line containing the extension directions of each active area pattern in the SRAM cell layout structure. This invention, without changing the total area of ​​the SRAM cell, increases the spacing between the two second parts by having the first part extend along the target straight line and the straight line containing the extension direction of the second part form an acute angle with the target straight line, thus solving the bridging leakage problem between shared contact holes compared to existing technologies. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of an SRAM cell layout structure.

[0020] Figure 2 This is a schematic diagram of the structure of adjacent shared contact holes after etching.

[0021] Figure 3This is a schematic diagram of an SRAM cell layout structure provided in Embodiment 1 of the present invention.

[0022] Figure 4 This is a schematic diagram of an SRAM cell layout structure provided in Embodiment 2 of the present invention.

[0023] Figure 5 This is a schematic diagram of an SRAM cell layout structure provided in Embodiment 3 of this utility model.

[0024] Explanation of reference numerals in the attached figures:

[0025] Figures 1-2 In the middle: 10 - active region; 20 - gate; 30 - contact hole; 31, 32 - shared contact hole;

[0026] Figures 3-5 In the diagram: 110 - First active region pattern; 120 - Second active region pattern; 130 - Third active region pattern; 140 - Fourth active region pattern; 210 - First gate pattern; 220 - Second gate pattern; 230 - Third gate pattern; 240 - Fourth gate pattern; 301 - First single contact hole pattern; 302 - Second single contact hole pattern; 303 - Third single contact hole pattern; 304 - Fourth single contact hole pattern; 305 - Fifth single contact hole pattern; 306 - First part of the first shared contact hole pattern; 307 - Second part of the first shared contact hole pattern; 308 - First part of the second shared contact hole pattern; 309 - Second part of the second shared contact hole pattern; 310 - Sixth single contact hole pattern; 311 - Seventh single contact hole pattern; 312 - Eighth single contact hole pattern; 313 - Ninth single contact hole pattern; 314 - Tenth single contact hole pattern. Detailed Implementation

[0027] The following will provide a further detailed description of an SRAM cell layout structure according to the present invention. The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the present invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the present invention.

[0028] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would confuse the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0029] To make the objectives and features of this utility model clearer and easier to understand, the specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model.

[0030] It should be noted that the "target line" is defined as the line extending in the direction of each active region graphic (i.e., the first active region graphic 110, the second active region graphic 120, the third active region graphic 130, and the fourth active region graphic 140).

[0031] For ease of understanding and explanation, the following embodiments use an SRAM cell layout structure that includes a set of shared contact hole pattern pairs as an example. However, in other embodiments, the SRAM cell layout structure may include at least one set of shared contact hole pattern pairs.

[0032] Example 1

[0033] Figure 3 This is a schematic diagram of an SRAM cell layout structure provided in this embodiment. Figure 3 As shown, this embodiment provides an SRAM cell layout structure, including multiple active area patterns and at least one set of shared contact hole pattern pairs. Each set of shared contact hole pattern pairs includes two adjacent shared contact hole patterns. The shared contact hole pattern includes a connected first part and a second part. The two first parts are respectively disposed on a gate pattern, and the two second parts are disposed facing each other between the two first parts, and the straight lines containing the two second parts do not intersect. The first part extends along the target straight line x1, and the straight line containing the extension direction of the second part has an acute angle with the target straight line. The target straight line x1 is the straight line containing the extension direction of each active area pattern of the SRAM cell layout structure.

[0034] In this embodiment, without changing the total area of ​​the SRAM cell, the first part extends along the target straight line x1, and the straight line where the extension direction of the second part is located has an acute angle with the target straight line. The target straight line is the straight line where the extension direction of each active area pattern of the SRAM cell layout structure is located. Compared with the prior art, the spacing between the two second parts is increased, which solves the bridging leakage problem between shared contact holes.

[0035] In detail, this embodiment provides an SRAM cell layout structure, including active region patterns, gate patterns, and contact hole patterns that constitute six transistors.

[0036] The active region pattern includes a first active region pattern 110, a second active region pattern 120, a third active region pattern 130, and a fourth active region pattern 140. The first active region pattern 110, the second active region pattern 120, the third active region pattern 130, and the fourth active region pattern 140 are arranged sequentially at intervals along a certain direction (e.g., perpendicular to a second direction). The first active region pattern 110 and the fourth active region pattern 140 respectively include a connected first segment and a second segment along the target straight line x1.

[0037] In this embodiment, the first active region pattern 110 and the fourth active region pattern 140 are used to form the active regions of an NMOS, and the second active region pattern 120 and the third active region pattern 130 are used to form the active regions of a PMOS. The line widths of the first and second segments perpendicular to the target line x1 are different, and the line width of the first segment is smaller than that of the second segment. The connection direction of the first and second segments of the first active region pattern 110 is opposite to that of the first and second segments of the fourth active region pattern 140, that is, the first segment of the first active region pattern 110 and the second segment of the fourth active region pattern 140 are arranged on the same side, and the second segment of the first active region pattern 110 and the first segment of the fourth active region pattern 140 are arranged on the same side. Corresponding transistors are formed on their respective first and second segments, for example, a corresponding transmission gate transistor PG is formed at the first segment, and a corresponding pull-down transistor PD is formed at the second segment.

[0038] In this embodiment, the first and second segments of the first active region graphic 110, the first and second segments of the second active region graphic 120, the third active region graphic 130, and the fourth active region graphic 140 are all rectangular in shape. The first active region graphic 110 and the fourth active region graphic 140 have the same shape, and the second active region graphic 120 and the third active region graphic 130 have the same shape. The second active region graphic 120 and the third active region graphic 130 are parallel to and staggered along the target line x1.

[0039] The gate pattern includes a first gate pattern 210, a second gate pattern 220, a third gate pattern 230, and a fourth gate pattern 240, all extending along a line perpendicular to the target line x1. The first gate pattern 210 and the second gate pattern 220 are spaced apart on the same line, and the third gate pattern 230 and the fourth gate pattern 240 are spaced apart on the same line. The first gate pattern 210 and the second gate pattern 220 are respectively arranged parallel to the third gate pattern 230. The first gate pattern 210 overlaps with the first segment of the first active region pattern 110; the second gate pattern 220 overlaps with the second segment of the second active region pattern 120, the third active region pattern 130, and the fourth active region pattern 140, and one end of the second gate pattern 220 overlaps with one end of the second active region pattern 120, forming a first overlapping region; the third gate pattern 230 overlaps with the second segment of the first active region pattern 110, the second active region pattern 120, and the third active region pattern 130, and one end of the third gate pattern 230 overlaps with one end of the third active region pattern 130, forming a second overlapping region; the fourth gate pattern 240 overlaps with the first segment of the fourth active region pattern 140.

[0040] In this embodiment, the first gate pattern 210 and the first segment of the first active region pattern 110 can form a transmission gate transistor PG1; the third gate pattern 230 and the second segment of the first active region pattern 110 can form a pull-down transistor PD1; the third gate pattern 230 and the second active region pattern 120 can form a pull-up transistor PU1; the second gate pattern 220 and the third active region pattern 130 can form a pull-up transistor PU2; the second gate pattern 220 and the second segment of the fourth active region pattern 140 can form a pull-down transistor PD2; and the fourth gate pattern 240 and the first segment of the fourth active region pattern 140 can form a transmission gate transistor PG2.

[0041] The contact hole pattern includes a first single contact hole pattern 301 to a tenth single contact hole pattern 314, a first shared contact hole pattern, and a second shared contact hole pattern.

[0042] The first single contact hole pattern 301 is disposed on the first segment of the first active region pattern 110 and is disposed away from the second segment of the first active region pattern 110; the second single contact hole pattern 302 is disposed at the junction of the first segment and the second segment of the first active region pattern 110; the third single contact hole pattern 303 is disposed on the first gate pattern 210; the fourth single contact hole pattern 304 is disposed on the second segment of the first active region pattern 110 and is disposed on both sides of the third gate pattern 230, respectively, as is the second single contact hole pattern 302; and the fifth single contact hole pattern 305 is disposed on the second active region pattern 120.

[0043] Both the first shared contact hole pattern and the second shared contact hole pattern include a connected first portion and a second portion. The first portion 306 of the first shared contact hole pattern is disposed on the first overlapping region, and the second portion 307 of the first shared contact hole pattern is disposed between the third gate pattern 230 and the second gate pattern 220, and partially overlaps with the second active region pattern 120. The first shared contact hole pattern and the fifth single contact hole pattern 305 are respectively disposed on both sides of the third gate pattern 230. The first portion 308 of the second shared contact hole pattern is disposed on the second overlapping region, and the second portion 309 of the second shared contact hole pattern is disposed on the third active region pattern 130 between the third gate pattern 230 and the second gate pattern 220, and partially overlaps with the third active region pattern 130.

[0044] The sixth single contact hole pattern 310 is disposed on the third active region pattern 130, and is disposed on both sides of the second gate pattern 220, together with the second shared contact hole pattern; the seventh single contact hole pattern 311 is disposed on the second part of the fourth gate pattern 240; the eighth single contact hole pattern 312 is disposed at the junction of the first part and the second part of the fourth active region pattern 140, and the seventh single contact hole pattern 311 and the eighth single contact hole pattern 312 are disposed on both sides of the second gate pattern 220; the ninth single contact hole pattern 313 is disposed on the first part of the fourth active region pattern 140, and is disposed on both sides of the fourth gate pattern 240, together with the eighth single contact hole pattern 312; and the tenth single contact hole pattern 314 is disposed on the fourth gate pattern 240.

[0045] In this embodiment, there is an acute angle θ1 between the straight line x21 extending from the second part 307 of the first shared contact hole pattern and the target straight line x1, and the acute angle θ1 is between 10° and 30°.

[0046] The spacing k1 (i.e., the value of the first interval) between the second part of the first shared contact hole pattern and the third gate pattern 230 can be the same as the spacing in the prior art, and the value range is, for example, greater than 0.05 μm, specifically 0.05 μm. The spacing k1 can also be greater than the spacing in the prior art, and the value range is, for example, greater than 0.075 μm, specifically 0.075 μm, to increase the spacing between the second part of the first shared contact hole pattern and the third gate pattern 230. In this way, the overlapping area between the second part 307 of the first shared contact hole pattern and the second part 309 of the second shared contact hole pattern on the target straight line x1 will be reduced, which helps to avoid bridging leakage problems between shared contact holes.

[0047] An acute angle θ2 exists between the straight line x22 extending from the second part of the second shared contact hole pattern and the target straight line x1, with the acute angle ranging from 10° to 30°. Directions x22 and x21 can be parallel, meaning angle θ2 equals angle θ1. This ensures a fixed spacing between the second part 307 of the first shared contact hole pattern and the second part 309 of the second shared contact hole pattern, which is greater than the spacing h1 in the prior art. This increases the spacing between the two parts, preventing bridging and leakage between the shared contact holes. Alternatively, directions x22 and x21 can be non-parallel, but the change in the straight lines extending from the second part 307 of the first shared contact hole pattern and the second part 309 of the second shared contact hole pattern still increases the spacing between them.

[0048] In this embodiment, the second portion 307 of the first shared contact hole pattern and the second portion 309 of the second shared contact hole pattern are both polygons, such as quadrilaterals, preferably parallelograms. In other embodiments, the second portion 307 of the first shared contact hole pattern and the second portion 309 of the second shared contact hole pattern are both polygons with chamfers, and the chamfers can be located at the apex corners of the two second portions 309 facing each other; the edges of the second portion 307 of the first shared contact hole pattern and the second portion 309 of the second shared contact hole pattern are set to arc shape at the ends away from the corresponding first portions.

[0049] The first single contact hole pattern 301 to the tenth single contact hole pattern 314 are all square, which allows this embodiment to be compatible with square contact holes and avoid the bridging risk of current shared contact holes, thus reducing the difficulty of the process. The flexible adjustment of the shape of the second part 307 of the first shared contact hole pattern and the second part 309 of the second shared contact hole pattern increases the etching process window of the contact hole and reduces damage to the device.

[0050] Example 2

[0051] Figure 4 This is a schematic diagram of an SRAM cell layout structure provided in Embodiment 2. Figure 4 As shown, compared with Embodiment 1, the difference in this embodiment is that at least one of the second part 307 of the first shared contact hole pattern and the second part 309 of the second shared contact hole pattern is a misaligned structure extending away from the other. The misaligned structure is a misaligned structure located in the plane where the first shared contact hole pattern and the second shared contact hole pattern are located. The second part 307 of the first shared contact hole pattern and the second part 309 of the second shared contact hole pattern can be a misaligned structure and a polygon; or both can be misaligned structures. In this embodiment, both the second part 307 of the first shared contact hole pattern and the second part 309 of the second shared contact hole pattern are staggered structures. The shapes of the second part 307 of the first shared contact hole pattern and the second part 309 of the second shared contact hole pattern are multiple identical splicing rectangles arranged staggered along a line perpendicular to the target line x1, and the opposing edges of two adjacent splicing rectangles overlap. They are staggered structures that are set away from the third active area pattern 130. The splicing direction of the second part is the same as the line extending from the second part of the first embodiment. For example, the splicing direction of the second part 307 of the first shared contact hole pattern is x21, and the splicing direction of the second part 309 of the second shared contact hole pattern is x22.

[0052] The line width of the splicing rectangle on the target line x1 is the same as the line width of the corresponding connected first part on the target line x1, and the line width of the splicing rectangle on the target line x1 is smaller than the line width of the splicing rectangle on the target line x1.

[0053] Example 3

[0054] Figure 5 This is a schematic diagram of an SRAM cell layout structure provided in this embodiment. Figure 5As shown, compared with Embodiment 1, the difference in this embodiment is that the first part 306 and the second part 307 of the first shared contact hole pattern both extend along the target straight line x1 and have an overlapping area. The length of the second part located on both sides of the overlapping area on the target straight line is greater than 0.075 μm. Specifically, the distance k3 between the second part 307 of the first shared contact hole pattern and the second gate pattern 220 is larger than the existing distance (0.05 μm), specifically greater than 0.075 μm; the distance k4 between the second part 309 of the second shared contact hole pattern and the second gate pattern 220 is smaller than the existing distance (0.05 μm), specifically greater than 0.075 μm; the length of the overlapping area between the second part 307 of the first shared contact hole pattern and the second part 309 of the second shared contact hole pattern on the target straight line is reduced to a length k5. The length of the overlapping area k5 is less than or equal to half the distance between the two first parts in the direction of the target straight line, i.e., k5 ≤ 1 / 2(k3 + k4 + k5). For example, the distance between the two first parts in the direction of the target line is 0.2μm (i.e., k3+k4+k5), where the value of k3 is 0.05μm to 0.1μm, the value of k5 is less than or equal to 0.1μm, and as the value of k3 increases, the value of k5 gradually decreases.

[0055] This embodiment reduces the length of the overlapping area of ​​the second part 307 of the first shared contact hole pattern and the third gate pattern 230 by adjusting the spacing k3 between them and adjusting the spacing k4 between the second part 309 of the second shared contact hole pattern and the third gate pattern 230. This reduces the contact area of ​​the plasma at the shared contact hole during etching, lowers the plasma concentration at the shared contact hole, and prevents bridging problems in the shared contact hole. This ensures that the bridging problem of the shared contact hole is improved without increasing the resistance.

[0056] In summary, this invention provides an SRAM cell layout structure, including at least one set of shared contact hole pattern pairs. Each set of shared contact hole pattern pairs includes two adjacent shared contact hole patterns. Each shared contact hole pattern includes a connected first part and a second part. The two first parts are respectively disposed on a gate pattern, and the two second parts are disposed facing each other between the two first parts. The first part extends along a target straight line, and the straight line containing the extension direction of the second part has an acute angle with the target straight line. The target straight line is the straight line containing the extension direction of each active area pattern of the SRAM cell layout structure. This invention, without changing the total area of ​​the SRAM cell, increases the spacing between the two second parts by extending the first part along a target straight line, with the straight line containing the extension direction of the second part having an acute angle with the target straight line, and the target straight line being the straight line containing the extension direction of each active area pattern of the SRAM cell layout structure. Compared with the prior art, this solves the bridging leakage problem between shared contact holes.

[0057] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0058] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention without departing from the scope of the present invention, or equivalent embodiments can be modified based on the disclosed technical content. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. An SRAM cell layout structure, comprising multiple active region patterns, characterized in that, It also includes at least one set of shared contact hole pattern pairs, each set of shared contact hole pattern pairs includes two adjacent shared contact hole patterns, each shared contact hole pattern includes a connected first part and a second part, the two first parts are respectively disposed on a gate pattern, the two second parts are disposed facing each other between the two first parts, and the straight lines on which the two second parts are located do not intersect; Wherein, the first part extends along the target straight line, and the straight line in which the extension direction of the second part is located has an acute angle with the target straight line, and the target straight line is the straight line in which the extension direction of each active area pattern of the SRAM cell layout structure is located.

2. The SRAM cell layout structure as described in claim 1, characterized in that, The shared contact hole pattern includes a first shared contact hole pattern and a second shared contact hole pattern. A first portion of the first shared contact hole pattern and a first portion of the second shared contact hole pattern are respectively disposed on a gate pattern. The two gate patterns are arranged in parallel. A second portion of the first shared contact hole pattern and a second portion of the second shared contact hole pattern are both located between the two gate patterns. A first gap exists between the second portion of the first shared contact hole pattern and the gate pattern on which the first portion of the second shared contact hole pattern is disposed. A second gap exists between the second portion of the second shared contact hole pattern and the gate pattern on which the first portion of the first shared contact hole pattern is disposed.

3. The SRAM cell layout structure as described in claim 2, characterized in that, The extension direction of the second part of the first shared contact hole pattern has an acute angle of 10° to 30° with the target line.

4. The SRAM cell layout structure as described in claim 2, characterized in that, The values ​​of the first interval and the second interval are greater than 0.05 μm.

5. The SRAM cell layout structure as described in claim 2, characterized in that, The values ​​of the first interval and the second interval are greater than 0.075 μm.

6. The SRAM cell layout structure as described in claim 2, characterized in that, The second part of the first shared contact hole pattern and the second part of the second shared contact hole pattern are both parallelograms.

7. The SRAM cell layout structure as described in claim 2, characterized in that, At least one of the second portion of the first shared contact hole pattern and the second portion of the second shared contact hole pattern has a misaligned structure extending in a direction away from the other.

8. The SRAM cell layout structure as described in claim 7, characterized in that, The misaligned structure is composed of multiple identical spliced ​​rectangles.

9. The SRAM cell layout structure as described in claim 8, characterized in that, The line width of the splicing rectangle perpendicular to the target line is the same as the line width of the corresponding connected first part perpendicular to the target line, and the line width of the splicing rectangle on the target line is less than the line width of the splicing rectangle perpendicular to the target line.

10. An SRAM cell layout structure, characterized in that, It includes at least one set of shared contact hole pattern pairs, each set of shared contact hole pattern pairs including two adjacent shared contact hole patterns. The shared contact hole pattern includes a connected first part and a second part. The two first parts are respectively disposed on a gate pattern, and the two second parts are disposed facing each other between the two first parts. The first part and the second part both extend along the target straight line and have an overlapping area, the length of which is less than or equal to half the distance between the two first parts in the target straight line direction.

Images