Memory device

Abstract

Embodiments of the present disclosure provide a memory device including a first portion and a second portion of a memory array. The first portion includes a plurality of first read-only memory cells, each of the first read-only memory cells including a first transistor having a first conductivity type and electrically coupled to a first word line and a first bit line. The second portion includes a plurality of second read-only memory cells, each of the second read-only memory cells including a second transistor having a second conductivity type and electrically coupled to a second word line and a second bit line. The first word line and the second word line extend along a first lateral direction, and the first bit line and the second bit line extend along a second lateral direction perpendicular to the first lateral direction.

Description

Technical Field

[0001] This disclosure relates to a memory device, and more particularly to a memory device having different conductivity types. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. Utility Model Content

[0003] According to some embodiments of this disclosure, a memory device includes a plurality of first memory cells formed in a plurality of first regions on a substrate, each of the first memory cells including a first transistor having a first conductivity type. The memory device includes a plurality of second memory cells formed in a plurality of second regions on a substrate, each of the second memory cells including a second transistor having a second conductivity type. The memory device includes a plurality of first access lines extending along a first lateral direction, each of the first access lines being connected to a group of first memory cells in the first region or a group of second memory cells in the second region. The memory device includes a plurality of second access lines extending along a second lateral direction perpendicular to the first lateral direction, each of the second access lines being connected to each of the first memory cells in a corresponding group in the first region or each of the second memory cells in a corresponding group in the second region, wherein the first and second regions are arranged along the first lateral direction.

[0004] According to some embodiments of this disclosure, a memory device includes a first portion of a memory array and a second portion of the memory array. The first portion includes a plurality of first memory cells, each of which includes a first transistor having a first conductivity type and being electrically coupled to a first word line and a second bit line. The second portion includes a plurality of second memory cells, each of which includes a second transistor having a second conductivity type and being electrically coupled to a second word line and a second bit line. The first word line and the second word line extend along a first lateral direction, and the first bit line and the second bit line extend along a second lateral direction perpendicular to the first lateral direction. The first portion of the memory array and the second portion of the memory array are disposed adjacent to each other along the first lateral direction.

[0005] According to some embodiments of this disclosure, a memory device includes a first portion of a memory array located in a first region on a substrate, wherein the first portion of the memory array includes a plurality of first read-only memory cells, each of the first read-only memory cells including a first transistor having a first conductivity type. The memory device includes a second portion of a memory array located in a second region on a substrate, wherein the second portion of the memory array includes a plurality of second read-only memory cells, each of the second read-only memory cells including a second transistor having a second conductivity type. The memory device includes a word line driver located in a third region on a substrate, wherein the word line driver is operatively coupled to the first and second portions of the memory array, the first, second, and third regions being arranged along a first lateral direction. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 An exemplary block diagram of a memory device is shown according to some embodiments;

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 Illustrations are drawn according to some embodiments. Figure 1 Various configurations of memory arrays for memory devices;

[0009] Figure 10 A flowchart illustrating an exemplary method for forming a memory device is shown according to some embodiments.

[0010] [Symbol Explanation]

[0011] 100: Memory Device

[0012] 102: Memory Array

[0013] 102A, 102B, 102C, 102D, 102E, 102F, 102G, 102H, 102I: Array Section

[0014] 104: Character Line Circuit

[0015] 106:I / O circuit

[0016] 106A, 106B, 106C, 106D, 106E, 106F, 106G, 106H, 106I: I / O Section

[0017] 108: Controller

[0018] 200: Read-only memory unit

[0019] 210: Transistor

[0020] 300, 400, 500, 600, 700, 800, 900: Configuration

[0021] 1000: Method

[0022] 1010, 1020, 1030, 1040: Steps

[0023] BL, BL A :bit line

[0024] D: Leakage extreme

[0025] G: Gate terminal

[0026] n: n type

[0027] p:p type

[0028] S: Source Extreme

[0029] VSS: Grounding voltage

[0030] WL,WL A :character line

[0031] X, Y: Direction Detailed Implementation

[0032] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0033] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0034] A read-only memory (ROM) array is a semiconductor memory chip array in which data is permanently stored. A ROM array consists of multiple read-only memory cells, each including a transistor in an "on" or "off" state. Each ROM cell stores data bits reflecting its on or off state (e.g., binary). In the prior art, to improve performance, the read-only memory cells (or corresponding transistors) of a ROM array are typically formed with the same conductivity type (e.g., n-type). However, forming all n-type transistors on a single substrate presents various processing or manufacturing problems, such as uneven distribution of n-type and p-type patterns across the substrate, which adversely affects polishing. Therefore, existing ROM devices / arrays are not entirely satisfactory in certain aspects.

[0035] This disclosure provides various embodiments of a memory device (e.g., a memory array) comprising a plurality of read-only memory cells having a uniform n-type / p-type distribution. For example, a first group of read-only memory cells may be formed as n-type, while a second group of read-only memory cells may be formed as p-type, wherein the first and second groups of read-only memory cells may be uniformly distributed on a substrate. In one embodiment, some n-type read-only memory cells (forming a corresponding subset of the first group) and some p-type read-only memory cells (forming a corresponding subset of the second group) may be alternately arranged along a first lateral direction, wherein the first lateral direction may be the length direction of the word line (WL) of the memory array. In another embodiment, all n-type read-only memory cells (forming the first group) and all p-type read-only memory cells (forming the second group) may be arranged adjacent to each other along the first lateral direction (word line direction). Furthermore, input / output (I / O) circuits of the same conductivity type and corresponding number can be formed, wherein the I / O circuits are adjacent to each of the first group (n-type) or the second group (p-type) read-only memory cells along a second lateral direction perpendicular to the first lateral direction. When the read-only memory cells are configured in this way, the aforementioned manufacturing problems can be avoided, which is beneficial to improving the manufacturing yield of the memory device.

[0036] Figure 1 Block diagrams illustrating an exemplary memory device 100 (or memory circuitry) are shown according to various embodiments. The memory device 100 may include storage devices for connection to an external host device (not shown). It should be understood that, as Figure 1 As shown, memory device 100 is a simplified example, and therefore memory device 100 may include any of a variety of other components, while still remaining within the scope of this disclosure.

[0037] like Figure 1 As shown in the example, memory device 100 includes a memory array 102, word line circuitry 104, I / O circuitry 106, and a controller 108 (or logic control circuitry). In some embodiments, the controller 108 may be operatively coupled to a memory controller (not shown) via a bus, wherein the bus may send and / or receive data based on an interface. Memory device 100 is a memory for storing data. Memory array 102 includes multiple memory subarrays or memory libraries. Each memory subarray (or memory library) includes multiple memory cells. In some embodiments, each memory cell may include a read-only memory cell, wherein the read-only memory cell (e.g., ...) Figure 2 The read-only memory cell 200 may be formed from one or more transistors. The memory array 102 may be formed as an array having multiple rows and multiple columns (e.g., two-dimensional or three-dimensional), with each read-only memory cell disposed at the intersection of a corresponding row and a corresponding column. Furthermore, the memory array 102 may include multiple word lines disposed along rows and multiple bit lines (BLs) disposed along columns. However, it should be understood that the memory array 102 may include multiple other memory cells while still remaining within the scope of this disclosure.

[0038] The controller 108 may provide address information (ADD) to the word line circuitry 104 and / or the I / O circuitry 106. ADD includes, for example, a row address (RAd) and a column address (CAd). In some embodiments, the row address and column address may be used to select word lines and bit lines, respectively. For example, the word line circuitry 104 may include a word line (or row) decoder and one or more row multiplexers, and the I / O circuitry 106 may include a bit line keeper circuit, a bit line pre-charge circuit, a bit line (or column) decoder, one or more column multiplexers, an output latch, a design fortestability / test (DFT) circuit, and a buffer.

[0039] The word line circuit 104 can receive a row address from the controller 108. Based on the row address, the word line circuit 104 (which may include or integrate a driver (circuit)) accesses the corresponding word line. The word line circuit 104 may apply a generated voltage to the corresponding access line (e.g., the word line) based on, for example, the row address. For example, the word line circuit 104 may select one of the word lines through three decoding stages: pre-decoding, decoding, and post-decoding. The pre-decoding stage determines which of the potential hierarchical memory blocks contains data and re-encodes the address bits to reduce the fanout of the word line decoder for a single block. One or more word line decoders will respond with the address. Then, the post-decoding stage may select a single word line. In some embodiments, the word line circuit 104 may consist of two elements arranged in a regular, dense manner. M It is implemented using a set of logic gates (e.g., NAND gates, NOR gates, etc.).

[0040] I / O circuit 106 receives a column address from controller 108. Based on the column address, I / O circuit 106 (which may include or integrate a row decoder) accesses the corresponding bit line. For example, before accessing (reading) one of the read-only memory cells via the corresponding bit line, the bit line precharge circuit of I / O circuit 106 can precharge the bit lines of memory array 102 to a logic high state, which can be maintained by bit line hold circuitry. Then, one of the bit lines is selected based on the column address. Simultaneously or subsequently with the selection of the corresponding word line based on the row address, at least one read-only memory cell of memory array 102 can be selected based on both the row and column addresses, and the logic state of the selected read-only memory cell can be read through I / O circuit 106. For example, I / O circuit 106 can receive a small signal from the selected read-only memory cell and amplify the small signal to a large signal to identify the logic state of the data stored in the selected read-only memory cell.

[0041] In some embodiments, the memory array 102, word line circuit 104, I / O circuit 106, and controller 108 can be configured according to... Figure 1The configuration entities are arranged as shown. For example, word line circuitry 104 is arranged adjacent to memory array 102 along the Y direction, where the Y direction can be the length direction of the word lines of memory array 102, while I / O circuitry 106 is arranged adjacent to memory array 102 along the X direction, where the X direction can be the length direction of the bit lines of memory array 102. Furthermore, the read-only memory cells of memory array 102 may include a first group of n-type read-only memory cells and a second group of p-type read-only memory cells. Each n-type read-only memory cell has a corresponding portion of I / O circuitry 106 formed with the same conductivity type (n-type) and is arranged adjacent to each other along the X direction. Each p-type read-only memory cell has a corresponding portion of I / O circuitry 106 formed with the same conductivity type (p-type) and is arranged adjacent to each other along the X direction, which will be discussed below.

[0042] Figure 2 An exemplary circuit diagram of a single read-only memory cell 200 is shown according to some embodiments. Multiple such read-only memory cells 200 may be configured as follows: Figure 1 The memory array 102 shown. Although Figure 2 The read-only memory unit 200 includes a transistor, but it should be understood that... Figure 2 The circuit diagrams are for illustrative purposes only and are not intended to limit the scope of this disclosure. Therefore, Figure 2 The read-only memory unit 200 shown may include any of a variety of other components (e.g., one or more additional transistors) while still within the scope of this disclosure.

[0043] As shown in the figure, the read-only memory cell 200 includes a transistor 210, wherein the transistor 210 has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminal is connected to a word line, the drain terminal is connected to a bit line, and the source terminal is selectively connected to a power supply voltage, such as ground (VSS). In some embodiments, the read-only memory cell 200 being in a logic "1" or "0" state may depend on whether the second source / drain terminal of the transistor 210 is connected to ground. For example, when the second source / drain terminal is connected to ground, the read-only memory cell 200 presents logic 1; and when the second source / drain terminal is disconnected from ground, the read-only memory cell 200 presents logic 0. In some other embodiments ( Figure 2 (Not shown in the image), the state of read-only memory cell 200, whether it is in logic "1" or "0", depends on whether the first source / drain terminal of transistor 210 is connected to the bit line. For example, when the first source / drain terminal is connected to the bit line, read-only memory cell 200 presents logic 1; and when the first source / drain terminal is disconnected from the bit line, read-only memory cell 200 presents logic 0.

[0044] Figure 3 , Figure 4 and Figure 5 Various layouts or configurations of the read-only memory cells of the memory array 102 are illustrated according to multiple embodiments, including configuration 300, configuration 400, and configuration 500. Generally, according to various embodiments of the present disclosure, each of configurations 300 to 500 includes a separate layout for forming a plurality of n-type read-only memory cells and a plurality of p-type read-only memory cells along the substrate. It should be understood that... Figures 3 to 5 The configuration is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0045] exist Figure 3 In this configuration, the memory array 102 (or its layout) can be divided into array portions 102A, 102B, 102C, 102D, 102E, 102F, 102G, 102H, and 102I, and the I / O circuit 106 (or its layout) can be divided into I / O portions 106A, 106B, 106C, 106D, 106E, 106F, 106G, 106H, and 106I. In some embodiments, I / O portions 106A to 106I (e.g., physically) are respectively arranged adjacent to array portions 102A to 102I along the X direction, and the physically aligned array portions and I / O portions are formed with the same conductivity type. For example, I / O portion 106A is physically aligned with array portion 102A along the X direction, and the read-only memory cells formed in array portion 102A have the same conductivity type as the transistors formed in I / O portion 106A. Furthermore, each read-only memory cell formed in array portion 102A to array portion 102A is connected via at least one bit line (e.g., bit line BL). A Electrically coupled to one of the corresponding I / O portions 106A to I / O portions 106I, and via at least one word line (e.g., word line WL) A Electrically coupled to the word line circuit 104. The bit line can extend along the X direction, and the word line can extend along the Y direction.

[0046] In some embodiments, the read-only memory cells in array portions 102A to 102C and the transistors in the corresponding I / O portions 106A to 106C are all formed in n-type; the read-only memory cells in array portions 102D to 102F and the transistors in the corresponding I / O portions 106D to 106F are all formed in p-type; and the read-only memory cells in array portions 102G to 102I and the transistors in the corresponding I / O portions 106G to 106I are all formed in n-type. In some embodiments, the transistors of the word line circuit 104 (along the Y direction) adjacent to the memory array portion 102I and the controller 108 (along the Y direction) adjacent to the I / O portion 106I are all formed in n-type. In other words, the corresponding portions of the memory array 102 and the I / O circuit 106 adjacent to the word line circuit 104 and the controller 108 may have transistors formed with the same conductivity type.

[0047] Although configuration 300 only shows one memory array and its corresponding word line circuitry, I / O circuitry, and controller, it should be understood that configuration 300 can be generalized to include multiple memory arrays (and corresponding circuitry). In these embodiments, another memory array having a similar configuration to memory array 102 may be relative to it. Figure 3 The memory array 102 shown is configured in Figure 3 The other side of the I / O circuit 106 shown. Therefore, the corresponding I / O circuit of another memory array can be relative to... Figure 3 The I / O circuit 106 shown is located on the other side of another memory array.

[0048] exist Figure 4In this configuration, the memory array 102 (or its layout) can be divided into array portions 102A, 102B, 102C, 102D, 102E, 102F, 102G, and 102H, and the I / O circuit 106 (or its layout) can be divided into I / O portions 106A, 106B, 106C, 106D, 106E, 106F, 106G, and 106H. In some embodiments, I / O portions 106A to 106H (e.g., physically) are respectively arranged adjacent to array portions 102A to 102H along the X direction, and the physically aligned array portions and I / O portions are formed with the same conductivity type. For example, I / O portion 106A is physically aligned with array portion 102A along the X direction, and the read-only memory cells formed in array portion 102A have the same conductivity type as the transistors formed in I / O portion 106A. Furthermore, the read-only memory cells formed in each array portion 102A to array portion 102I are connected via at least one bit line (e.g., bit line BL). A Electrically coupled to one of the corresponding I / O portions 106A to I / O portions 106I, and via at least one word line (e.g., word line WL) A Electrically coupled to the word line circuit 104. The bit line can extend along the X direction, and the word line can extend along the Y direction.

[0049] In some embodiments, the read-only memory cells in array portions 102A to 102D and the transistors in the corresponding I / O portions 106A to 106D are all formed in p-type configurations; while the read-only memory cells in array portions 102E to 102H and the transistors in the corresponding I / O portions 106E to 106H are all formed in n-type configurations. In some embodiments, the transistors of the word line circuit 104 (along the Y direction) adjacent to the memory array portion 102H and the controller 108 (along the Y direction) adjacent to the I / O portion 106H are formed in n-type configurations. In other words, the corresponding portions of the memory array 102 and the I / O circuit 106 adjacent to the word line circuit 104 and the controller 108 may have the same conductivity type.

[0050] Although configuration 400 only shows one memory array and its corresponding word line circuitry, I / O circuitry, and controller, it should be understood that configuration 400 can be generalized to include multiple memory arrays (and corresponding circuitry). In these embodiments, another memory array having a similar configuration to memory array 102 may be relative to it. Figure 4 The memory array 102 shown is configured in Figure 4The other side of the I / O circuit 106 shown. Therefore, the corresponding I / O circuit of another memory array can be relative to... Figure 4 The I / O circuit 106 shown is located on the other side of another memory array.

[0051] exist Figure 5 In this configuration, the memory array 102 (or its layout) can be divided into array portions 102A, 102B, 102C, 102D, 102E, 102F, 102G, and 102H, and the I / O circuit 106 (or its layout) can be divided into I / O portions 106A, 106B, 106C, 106D, 106E, 106F, 106G, and 106H. In some embodiments, I / O portions 106A to 106H (e.g., physically) are respectively arranged adjacent to array portions 102A to 102H along the X direction, and the physically aligned array portions and I / O portions are formed with the same conductivity type. For example, I / O portion 106A is physically aligned with array portion 102A along the X direction, and the read-only memory cells formed in array portion 102A have the same conductivity type as the transistors formed in I / O portion 106A. Furthermore, the read-only memory cells formed in each array portion 102A to array portion 102I are connected via at least one bit line (e.g., bit line BL). A Electrically coupled to one of the corresponding I / O portions 106A to I / O portions 106I, and via at least one word line (e.g., word line WL) A Electrically coupled to the word line circuit 104. The bit line can extend along the X direction, and the word line can extend along the Y direction.

[0052] In some embodiments, the read-only memory cells in array portions 102A and 102B, and the transistors in the corresponding I / O portions 106A and 106B, are all p-type; the read-only memory cells in array portions 102C and 102D, and the transistors in the corresponding I / O portions 106C and 106D, are all n-type; the read-only memory cells in array portions 102E and 102F, and the transistors in the corresponding I / O portions 106E and 106F, are all p-type; and the read-only memory cells in array portions 102G and 102H, and the transistors in the corresponding I / O portions 106G and 106H, are all n-type. In some embodiments, the transistors of the word line circuit 104 (along the Y direction) adjacent to the memory array portion 102H and the controller 108 (along the Y direction) adjacent to the I / O portion 106H are n-type. In other words, the corresponding portions of the memory array 102 and I / O circuit 106, which are arranged adjacent to the character line circuit 104 and the controller 108, may have the same conductivity type.

[0053] Although configuration 500 only shows one memory array and its corresponding word line circuitry, I / O circuitry, and controller, it should be understood that configuration 500 can be generalized to include multiple memory arrays (and corresponding circuitry). In these embodiments, another memory array having a similar configuration to memory array 102 may be relative to it. Figure 5 The memory array 102 shown is configured in Figure 5 The other side of the I / O circuit 106 shown. Therefore, the corresponding I / O circuit of another memory array can be relative to... Figure 5 The I / O circuit 106 shown is located on the other side of another memory array.

[0054] In some embodiments, configurations 300 to 500 (respectively as follows) Figures 3 to 5 The diagram shows a memory array (and its corresponding circuitry) that can be formed along a single layer. As used herein, the term "layer" can refer to a single semiconductor substrate, a single wafer, a single metallization layer disposed on a semiconductor substrate, or any processed layer. For example, transistors for memory arrays, word line drivers, I / O circuitry, and controllers can be formed as one of the following transistor structures: gate-all-around (GAA) transistors, nanosheet transistors, fin field-effect transistors (FinFETs), planar transistors, etc., located on a semiconductor substrate. However, it should be understood that embodiments of this disclosure further include configurations that can be used for memory arrays formed across vertically spaced layers, which will be discussed below.

[0055] Figure 6 , Figure 7 , Figure 8 and Figure 9 Various layouts or configurations of the read-only memory cells of the memory array 102 are illustrated according to multiple embodiments, including configuration 600, configuration 700, configuration 800, and configuration 900. Generally, according to various embodiments of this disclosure, each of configurations 600 to 900 includes a corresponding layout for forming a plurality of n-type read-only memory cells and a plurality of p-type read-only memory cells on multiple levels on a substrate. It should be understood that... Figures 6 to 9 The configuration is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0056] exist Figure 6 In this diagram, the memory array 102 (or its layout) can be divided into array portion 102A and array portion 102B. For clarity, the corresponding I / O portions are not shown. The array portion 102A, with read-only memory cells formed in an n-type configuration, is formed in a lower layer (or layer) above the substrate, and the array portion 102B, with read-only memory cells formed in a p-type configuration, is formed in an upper layer (or layer) above the substrate. In some embodiments, the transistors forming the read-only memory cells of array portions 102A and 102B are provided with complementary field-effect transistor (CFET) structures. For example, the components of the transistors in array portion 102A (e.g., channels, source / drain structures, gate structures, etc.) are formed in the lower layer, while the components of the transistors in array portion 102B (e.g., channels, source / drain structures, gate structures, etc.) are formed in the upper layer.

[0057] exist Figure 7 In this diagram, the memory array 102 (or its layout) can be divided into array portion 102A and array portion 102B. For clarity, the corresponding I / O portions are not shown. The array portion 102A, with read-only memory cells formed in a p-type configuration, is formed in a lower layer (or layer) above the substrate, and the array portion 102B, with read-only memory cells formed in an n-type configuration, is formed in an upper layer (or layer) above the substrate. In some embodiments, the transistors forming the read-only memory cells of array portions 102A and 102B are provided with complementary field-effect transistor (CFPT) structures. For example, the components of the transistors in array portion 102A (e.g., channels, source / drain structures, gate structures, etc.) are formed in the lower layer, while the components of the transistors in array portion 102B (e.g., channels, source / drain structures, gate structures, etc.) are formed in the upper layer.

[0058] exist Figure 8In this configuration, the memory array 102 (or its layout) can be divided into array portions 102A, 102B, 102C, and 102D. For clarity, the corresponding I / O portions are not shown. The array portion 102A, with n-type read-only memory cells, is formed in the lower layer (or layer) above the substrate; the array portion 102B, with p-type read-only memory cells, is formed in the lower layer (or layer); the array portion 102C, with n-type read-only memory cells, is formed in the upper layer (or layer) above the substrate; and the array portion 102D, with p-type read-only memory cells, is formed in the upper layer (or layer). In some embodiments, the transistors forming the read-only memory cells of array portions 102A to 102D are provided with complementary field-effect transistor structures. For example, the components of the transistors in array portions 102A and 102B (e.g., channels, source / drain structures, gate structures, etc.) are formed on the lower layer, while the components of the transistors in array portions 102C and 102D (e.g., channels, source / drain structures, gate structures, etc.) are formed on the upper layer.

[0059] exist Figure 9 In the memory array 102 (or its layout), it can be divided into array section 102A, array section 102B, array section 102C, array section 102D, array section 102E, array section 102F, array section 102G and array section 102H. For clarity, the corresponding I / O sections are not shown. An array portion 102A of read-only memory cells formed in p-type configuration is formed in a lower layer (or layer) above the substrate; an array portion 102B of read-only memory cells formed in n-type configuration is formed in a lower layer (or layer); an array portion 102C of read-only memory cells formed in p-type configuration is formed in a lower layer (or layer); an array portion 102D of read-only memory cells formed in n-type configuration is formed in a lower layer (or layer); an array portion 102E of read-only memory cells formed in n-type configuration is formed in an upper layer (or layer) above the substrate; an array portion 102F of read-only memory cells formed in p-type configuration is formed in an upper layer (or layer); an array portion 102G of read-only memory cells formed in n-type configuration is formed in an upper layer (or layer); and an array portion 102H of read-only memory cells formed in p-type configuration is formed in an upper layer (or layer). In some embodiments, the transistors forming the read-only memory cells of array portions 102A to 102H are provided with complementary field-effect transistor structures. For example, the components of the transistors in array portions 102A to 102D (e.g., channels, source / drain structures, gate structures, etc.) are formed on the lower layer, while the components of the transistors in array portions 102E to 102H (e.g., channels, source / drain structures, gate structures, etc.) are formed on the upper layer.

[0060] Figure 10Flowcharts illustrating an exemplary method 1000 for forming a memory device (e.g., including a memory array and corresponding circuitry thereto) are shown according to various embodiments of this disclosure. In some embodiments, the above description may be used as a basis for... Figures 3 to 9 The configuration shown is used to form a memory device. Therefore, the following discussion of method 1000 can be referenced to some of the above-mentioned figures. It should be noted that, as Figure 10 The method 1000 shown is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that modifications are possible. Figure 10 The steps of Method 1000 may be provided in a specific order, for example, additional steps may be provided before, during and after Method 1000, and this document may only briefly describe some of the steps.

[0061] Method 1000 begins at step 1010, forming a first portion of a memory array in a first region on a substrate. In some embodiments, the first portion of the memory array includes a plurality of first read-only memory cells, and each of the first read-only memory cells includes a first transistor having a first conductivity type. Figure 3 In an example, the first portion of the memory array may include memory array portions 102A to 102C and array portions 102G to 102I. These array portions of different memory cells in the first portion may be disposed in a first region, wherein the first region has a plurality of regions physically spaced apart from each other along the Y direction. Figure 4 In an example, the first portion of the memory array may include memory array portions 102E to array portions 102H. These different memory portions of the first portion may be disposed in a first region, wherein the first region has multiple regions physically adjacent to each other along the Y direction. Figure 5 In one example, the first portion of the memory array may include memory array portion 102C, array portion 102D, array portion 102G, and array portion 102H. These different memory portions of the first portion may be disposed in a first region, wherein the first region has a plurality of regions physically spaced apart along the Y direction.

[0062] Method 1000 continues to step 1020, forming a second portion of a memory array in a second region on the substrate, wherein the second region is arranged relative to the first region along a first lateral direction. In some embodiments, the second portion of the memory array includes a plurality of second read-only memory cells, and each of the second read-only memory cells includes a plurality of second transistors having a second conductivity type. Figure 3 In one example, the second portion of the memory array may include memory array portions 102D to array portions 102F. These different memory portions of the second portion may be disposed in a second region, wherein the second region is inserted along the Y direction between multiple regions of the first region. Figure 4In one example, the second portion of the memory array may include memory array portions 102A to array portions 102D. These different memory portions of the second portion may be disposed in a second region, wherein the second region is physically adjacent to the first region along the Y direction. Figure 5 In one example, the second part of the memory array may include memory array portion 102A, array portion 102B, array portion 102E, and array portion 102F. These different memory portions of the second part may be disposed along the Y direction adjacent to or between multiple regions of the first region.

[0063] Method 1000 continues to step 1030, where a character line driver is formed in a third region on the substrate, wherein the third region is disposed relative to the first region and the second region along a first lateral direction. Figures 3 to 5 In some examples, the word line driver may be included in or integrated with the word line circuitry 104. In some embodiments, the word line driver may be operatively coupled to each of a first portion and a second portion of the memory array. In other words, the word line driver may be operatively shared by both the first portion and the second portion of the memory array.

[0064] Method 1000 continues to step 1040, forming a first word line electrically coupled to a first portion of the memory array by a word line driver, a second word line electrically coupled to a second portion of the memory array by a word line driver, a first bit line electrically coupled to the first portion of the memory array, and a second bit line electrically coupled to the second portion of the memory array. In some embodiments, the first word line and the second word line extend along a first lateral direction, and the first bit line and the second bit line extend along a second lateral direction perpendicular to the first lateral direction. Furthermore, the first word line may be coupled to the respective gate terminal of the first read-only memory cell, the second word line may be coupled to the respective gate terminal of the second read-only memory cell, the first bit line may be coupled to the respective source or drain terminal of the first read-only memory cell, and the second bit line may be coupled to the respective source or drain terminal of the second read-only memory cell.

[0065] In one embodiment of this disclosure, a memory device is disclosed. The memory device includes a plurality of first memory cells formed in a plurality of first regions on a substrate, each of the first memory cells including a first transistor having a first conductivity type. The memory device includes a plurality of second memory cells formed in a plurality of second regions on a substrate, each of the second memory cells including a second transistor having a second conductivity type. The memory device includes a plurality of first access lines extending along a first lateral direction, each of the first access lines being connected to a group of first memory cells in the first region or a group of second memory cells in the second region. The memory device includes a plurality of second access lines extending along a second lateral direction perpendicular to the first lateral direction, each of the second access lines being connected to each first memory cell in a corresponding group of the plurality of first regions or each second memory cell in a corresponding group of the plurality of second regions. The first and second regions are arranged along the first lateral direction.

[0066] In some embodiments, both the first memory cell and the second memory cell are read-only memory cells. In some embodiments, each of the first regions is inserted between adjacent cells in the second region along a first lateral direction. In some embodiments, a subset of the first region is inserted between adjacent subsets of the second region along the first lateral direction. In some embodiments, the first region is disposed adjacent to the second region along the first lateral direction. In some embodiments, the memory device further includes a plurality of first input / output transistors having a first conductivity type and a plurality of second input / output transistors having a second conductivity type. In some embodiments, the first input / output transistors are formed in a plurality of third regions on a substrate, and the second input / output transistors are formed in a plurality of fourth regions on a substrate. In some embodiments, the memory device further includes a plurality of first input / output transistors formed in a plurality of third regions on a substrate, and a plurality of second input / output transistors formed in a plurality of fourth regions on a substrate. In some embodiments, each of the third regions is disposed adjacent to a corresponding one of the first regions along a second lateral direction perpendicular to the first lateral direction, and each of the fourth regions is disposed adjacent to a corresponding one of the second regions along the second lateral direction. In some embodiments, the memory device further includes a plurality of first peripheral transistors having a first conductivity type and formed in a plurality of fifth regions on a substrate, and a plurality of second peripheral transistors having a second conductivity type and formed in a plurality of sixth regions on a substrate. In some embodiments, each transistor in the third region is inserted along a second lateral direction between a corresponding transistor in the first region and a corresponding transistor in the fifth region, and each transistor in the fourth region is inserted along a second lateral direction between a corresponding transistor in the second region and a corresponding transistor in the sixth region.

[0067] In another embodiment of this disclosure, a memory device is disclosed. The memory device includes a first portion of a memory array, the first portion including a plurality of first memory cells, each of the first memory cells including a first transistor having a first conductivity type and electrically coupled to a first word line and a second bit line. The memory device includes a second portion of the memory array, the second portion including a plurality of second memory cells, each of the second memory cells including a second transistor having a second conductivity type and electrically coupled to a second word line and a second bit line. The first word line and the second word line extend along a first lateral direction, and the first bit line and the second bit line extend along a second lateral direction perpendicular to the first lateral direction. The first portion and the second portion of the memory array are arranged adjacent to each other along the first lateral direction.

[0068] In some embodiments, both the first memory cell and the second memory cell are read-only memory cells. In some embodiments, the memory device further includes a third portion of a memory array, wherein the third portion includes a plurality of third memory cells, each of the third memory cells including a third transistor having a first conductivity type and electrically coupled to a third word line and a first bit line. In some embodiments, the third portion of the memory array is disposed adjacent to the first portion of the memory array along a second lateral direction. In some embodiments, the memory device further includes a fourth portion of the memory array, wherein the fourth portion includes a plurality of fourth memory cells, each of the fourth memory cells including a fourth transistor having a second conductivity type and electrically coupled to a fourth word line and a second bit line. In some embodiments, the fourth portion of the memory array is disposed adjacent to the second portion of the memory array along a second lateral direction. In some embodiments, the memory array includes a plurality of first portions and a plurality of second portions arranged alternately along a first lateral direction. In some embodiments, the memory array includes a plurality of first portions adjacent to each other along a first lateral direction, the memory array includes a plurality of second portions adjacent to each other along a first lateral direction, and the first portion and the second portion of the memory array are arranged relative to each other along the first lateral direction.

[0069] In another embodiment of this disclosure, a method for manufacturing a memory device is disclosed, the method comprising the following steps: forming a first portion of a memory array in a first region on a substrate, wherein the first portion of the memory array includes a plurality of first read-only memory cells, each of the first read-only memory cells including a first transistor having a first conductivity type. forming a second portion of the memory array in a second region on the substrate, wherein the second portion of the memory array includes a plurality of second read-only memory cells, each of the second read-only memory cells including a second transistor having a second conductivity type. forming a word line driver in a third region of the substrate, wherein the word line driver is operatively coupled to the first portion and the second portion of the memory array. In some embodiments, the first region, the second region, and the third region are arranged along a first lateral direction.

[0070] In some embodiments, the method further includes forming a first word line electrically coupled to a first portion of the memory array and extending along a first lateral direction, forming a second word line electrically coupled to a second portion of the memory array and extending along the first lateral direction, forming a first bit line electrically coupled to a first portion of the memory array and extending along a second lateral direction perpendicular to the first lateral direction, and forming a second bit line electrically coupled to a second portion of the memory array and extending along a second lateral direction.

[0071] In another embodiment of this disclosure, a memory device is disclosed. The memory device includes a first portion of a memory array located in a first region on a substrate, wherein the first portion of the memory array includes a plurality of first read-only memory cells, each of the first read-only memory cells including a first transistor having a first conductivity type. The memory device includes a second portion of a memory array located in a second region on a substrate, wherein the second portion of the memory array includes a plurality of second read-only memory cells, each of the second read-only memory cells including a second transistor having a second conductivity type. The memory device includes a word line driver located in a third region on a substrate, wherein the word line driver is operatively coupled to the first and second portions of the memory array, the first, second, and third regions being arranged along a first lateral direction.

[0072] As used herein, the terms “about” and “approximately” generally indicate that a value may vary from a specified value depending on a particular technology node associated with the target semiconductor device. Based on a particular technology node, the term “about” may indicate that the value varies within, for example, 10% to 30% of the specified value (e.g., ±10%, ±20%, or ±30% of the specified value).

[0073] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, characterized in that, include: A plurality of first memory cells are formed in a plurality of first regions on a substrate, each of the plurality of first memory cells including a first transistor having a first conductivity type; A plurality of second memory cells are formed in a plurality of second regions on the substrate, each of the plurality of second memory cells including a second transistor having a second conductivity type; A plurality of first access lines extend along a first lateral direction, each of the plurality of first access lines being connected to a group of the plurality of first memory cells in a plurality of first regions or a group of the plurality of second memory cells in a plurality of second regions; and A plurality of second access lines extend along a second lateral direction perpendicular to the first lateral direction, each of the plurality of second access lines being connected to each of the plurality of first memory cells in a corresponding region or to each of the plurality of second memory cells in a corresponding region of the plurality of second regions. The plurality of first regions and the plurality of second regions are arranged along the first lateral direction.

2. The memory device as claimed in claim 1, characterized in that, Each of the plurality of first regions is inserted between adjacent regions of the plurality of second regions along the first lateral direction.

3. The memory device as claimed in claim 1, characterized in that, A subset of the plurality of first regions is inserted along the first lateral direction between adjacent subsets of the plurality of second regions.

4. The memory device as claimed in claim 1, characterized in that, The plurality of first regions are arranged adjacent to the plurality of second regions along the first lateral direction.

5. The memory device as claimed in claim 1, characterized in that, Further includes: Multiple first input / output transistors are formed in multiple third regions on the substrate; and Multiple second input / output transistors are formed in multiple fourth regions on the substrate.

6. The memory device as claimed in claim 5, characterized in that, Each of the plurality of third regions is arranged adjacent to a corresponding one of the plurality of first regions along the second lateral direction perpendicular to the first lateral direction, and each of the plurality of fourth regions is arranged adjacent to a corresponding one of the plurality of second regions along the second lateral direction.

7. A memory device, characterized in that, include: A first portion of a memory array includes a plurality of first memory cells, each of the plurality of first memory cells including a first transistor having a first conductivity type and electrically coupled to a first word line and a first bit line; and A second portion of the memory array includes a plurality of second memory cells, each of which includes a second transistor having a second conductivity type and being electrically coupled to a second word line and a second bit line. The first character line and the second character line extend along a first lateral direction, and the first character line and the second character line extend along a second lateral direction perpendicular to the first lateral direction. The first part and the second part of the memory array are arranged adjacent to each other along the first lateral direction.

8. The memory device as claimed in claim 7, characterized in that, Further includes: A third portion of the memory array includes a plurality of third memory cells, each of which includes a third transistor having the first conductivity type and electrically coupled to a third word line and the first bit line.

9. The memory device as claimed in claim 7, characterized in that, Further includes: A fourth portion of the memory array includes a plurality of fourth memory cells, each of which includes a fourth transistor having the second conductivity type and electrically coupled to a fourth word line and the second bit line.

10. A memory device, characterized in that, include: A first portion of a memory array is located in a first region on a substrate, wherein the first portion of the memory array includes a plurality of first read-only memory cells, each of the plurality of first read-only memory cells including a first transistor having a first conductivity type; A second portion of the memory array is located in a second region on the substrate, wherein the second portion of the memory array includes a plurality of second read-only memory cells, each of the plurality of second read-only memory cells including a second transistor having a second conductivity type; and A word line driver is located in a third region on the substrate, wherein the word line driver is operatively coupled to the first portion and the second portion of the memory array. The first region, the second region, and the third region are arranged along a first horizontal direction.

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