Packaging structure

Abstract

The utility model provides a kind of packaging structure, the packaging structure includes substrate;Logic chip is set on substrate;Multiple groups high bandwidth memory are set on logic chip;Integrated circuit chip is set to abut logic chip;First connecting structure and second connecting structure are set between logic chip and substrate, wherein, first connecting structure is used to be electrically connected with integrated circuit chip, second connecting structure is used for the support and / or heat dissipation of logic chip, and, second connecting structure is separated from integrated circuit chip by first connecting structure. By setting multiple groups high bandwidth memory on the same logic chip, integrating all high bandwidth memories and logic chip in the same package, the signal transmission path can be greatly shortened, the access delay can be reduced, and the energy consumption required for long wiring and cross-module driving can be reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and specifically to a packaging structure. Background Technology

[0002] With the rapid development of artificial intelligence, high-performance computing, and graphics processing technologies, the demand for high-bandwidth, low-latency memory architectures is increasing. HBM (High Bandwidth Memory), with its wide memory bus, high bandwidth, and low power consumption, has become one of the most critical memory technologies in current ASIC (Application-Specific Integrated Circuit) design. As application requirements expand, ASICs need to interface with two or even more HBMs (currently up to eight), which brings challenges in latency, power consumption, and packaging design.

[0003] Most current standard HBM solutions adopt an architecture of multiple independent HBM modules. Each HBM module is connected to the ASIC through an interposer or advanced packaging technology, such as CoWoS-S (Chip on Wafer on Substrate-Silicon Interposer, wafer-level packaging based on silicon interposer), CoWoS-R (Chip on Wafer on Substrate-RedistributionLayer (RDL) Only, wafer-level packaging using redistribution layer), and CoWoS-L (Chip on Wafer on Substrate-Localized Silicon Interposer, wafer-level packaging based on localized silicon interposer).

[0004] This architecture with multiple independent HBM modules may result in an additional 10-30% increase in access latency when accessing across HBMs, and power consumption may also increase by 10-15% due to longer signal lines and additional drive requirements. Utility Model Content

[0005] This utility model proposes a packaging structure.

[0006] Firstly, this utility model proposes a packaging structure, including:

[0007] substrate;

[0008] A logic chip is disposed on the substrate;

[0009] Multiple high-bandwidth memories are disposed on the logic chip;

[0010] An integrated circuit chip is configured to be adjacent to the logic chip;

[0011] A first connection structure and a second connection structure are disposed between the logic chip and the substrate. The first connection structure is used for electrical connection with the integrated circuit chip, and the second connection structure is used for support and / or heat dissipation of the logic chip. The second connection structure is separated from the integrated circuit chip by the first connection structure.

[0012] In some alternative implementations, there is a gap between adjacent sets of the high-bandwidth memory.

[0013] In some alternative implementations, the vertical projections of the first connection structure and the second connection structure fall within the vertical projection range of the multiple sets of high-bandwidth memories.

[0014] In some alternative implementations, from a top-down view, the first connection structure is disposed around the periphery of the logic chip, and the second connection structure is disposed in the central region of the logic chip.

[0015] In some optional embodiments, the packaging structure further includes:

[0016] A molding layer is disposed on the logic chip and covers each group of high-bandwidth memories.

[0017] In some alternative implementations, each group of the high-bandwidth memory includes a plurality of dynamic random access memory chips stacked together.

[0018] In some alternative implementations, there is a gap between each of the dynamic random access memory chips in each group of the high-bandwidth memory.

[0019] In some alternative implementations, the number of dynamic random access memory chips in each group of the high-bandwidth memory may be the same or different.

[0020] In some alternative implementations, the upper surface of the molding layer is flush with the upper surface of at least one set of the high-bandwidth memories.

[0021] In some alternative implementations, the multiple sets of high-bandwidth memories further include a third connection structure disposed between the multiple dynamic random access memory chips.

[0022] To address the issues of increased access latency and power consumption when accessing multiple independent HBM modules, this invention provides a packaging structure that integrates multiple high-bandwidth memories onto the same logic chip, thereby significantly shortening signal transmission paths, reducing access latency, and minimizing the energy consumption required for long interconnects and cross-module driving. Attached Figure Description

[0023] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0024] Figure 1 This is a schematic diagram of the three-dimensional structure of an existing single HBM module;

[0025] Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure;

[0026] Figure 3 This is a schematic diagram of the existing structure where two independent HBM modules are connected to an ASIC;

[0027] Figure 4 This is a top view of the packaging structure 4a according to an embodiment of the present invention;

[0028] Figure 5 This is a three-dimensional structural diagram of an HBM module with packaging structure 4a according to an embodiment of the present invention;

[0029] Figure 6 yes Figure 5 A schematic diagram of the cross-sectional structure;

[0030] Figure 7 This is a three-dimensional structural diagram of the HBM module with packaging structure 7a according to another embodiment of the present invention;

[0031] Figures 8-11 This is a schematic diagram of the manufacturing steps of the HBM module with packaging structure 4a according to an embodiment of the present invention.

[0032] Explanation of reference numerals / symbols in the attached diagram:

[0033] 101-Logic chip; 102-High bandwidth memory; 103-Molding layer; 104-Connection structure; 105-Integrated circuit chip; 201-Substrate; 202-Logic chip; 203-High bandwidth memory; 204-Integrated circuit chip; 205-First connection structure; 206-Second connection structure; 207-Molding layer; 2031-Dynamic random access memory chip; 2032-Third connection structure; 4a-Packaging structure. Detailed Implementation

[0034] The specific embodiments of this utility model will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this utility model and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0035] It should be readily understood that the meanings of "on," "above," and "on top of" in this utility model should be interpreted in the broadest sense, such that "on" not only means "directly on something," but also means "on something" including intermediate components or layers existing between the two.

[0036] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0037] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0038] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0039] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the implementation conditions of this utility model and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this utility model, should still fall within the scope of the technical content disclosed in this utility model. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of implementation of this utility model. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this utility model.

[0040] It should also be noted that the longitudinal section corresponding to the embodiment of this utility model can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0041] Furthermore, where there is no conflict, the embodiments and features described in these embodiments can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] refer to Figures 1-3 ,in, Figure 1 This is a schematic diagram of the three-dimensional structure of an existing single HBM module. Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure; Figure 3 This is a schematic diagram of the existing structure where two independent HBM modules are connected to the ASIC.

[0043] like Figure 1 and Figure 2 As shown, a single HBM module may include a logic chip 101, a high-bandwidth memory 102, a module encapsulation layer 103, and a connection structure 104.

[0044] The high-bandwidth memory 102 is disposed on the logic chip 101, the connection structure 104 is disposed below the logic chip 101, and the encapsulation layer 103 covers the high-bandwidth memory 102 to form a single HBM module.

[0045] like Figure 3 As shown, when two independent HBM modules are connected to the integrated circuit chip 105 respectively, since each independent HBM module has its own independent logic and memory stack, when the ASIC needs to exchange data between different HBM modules, it must transmit through the interposer layer or the redistribution layer on the package. This will cause additional access latency. According to estimates, cross-HBM module access may add an additional 5 to 15 nanoseconds, increasing the total latency from about 10 to 20 nanoseconds for a single HBM module to 15 to 35 nanoseconds.

[0046] In addition, the distributed HBM module architecture requires more powerful drivers and more complex power and thermal management designs. Each additional HBM module not only requires more energy for signal driving, but the capacitive load introduced by the cross-HBM module interconnects will further increase energy consumption, which may increase by 10 to 15%.

[0047] refer to Figures 4 to 6 , Figure 4 This is a top view of the packaging structure 4a according to an embodiment of the present invention; Figure 5 This is a three-dimensional structural diagram of an HBM module with packaging structure 4a according to an embodiment of the present invention; Figure 6 yes Figure 5 A cross-sectional structural diagram.

[0048] like Figures 4 to 6 As shown, the packaging structure 4a of this utility model may include a substrate 201, a logic chip 202, multiple sets of high-bandwidth memory 203, an integrated circuit chip 204, a first connection structure 205, and a second connection structure 206.

[0049] The system includes a logic chip 202 disposed on a substrate 201; multiple high-bandwidth memory modules 203 disposed on the logic chip 202; an integrated circuit chip 204 disposed adjacent to the logic chip 202; a first connection structure 205 and a second connection structure 206 disposed between the logic chip 202 and the substrate 201. The first connection structure 205 is used for electrical connection with the integrated circuit chip 204, and the second connection structure 206 is used for support and / or heat dissipation of the logic chip 202. Furthermore, the second connection structure 206 and the integrated circuit chip 204 are separated by the first connection structure 205.

[0050] Thus, by placing multiple sets of high-bandwidth memory 203 on the same logic chip 202, all high-bandwidth memory 203 and logic chip 202 can be integrated into the same package. In other words, by integrating all high-bandwidth memory 203 and logic chip 202 into one HBM module, compared with multiple independent HBM modules, the signal transmission path can be significantly shortened, the latency can be reduced by approximately 10-30% (i.e., reduced by 5-15 nanometers), and the energy consumption required for long interconnects and cross-module driving can be reduced, saving 10-15% of power consumption.

[0051] Here, when multiple sets of high-bandwidth memory 203 are set on the same logic chip 202, significant heat accumulation problems are likely to occur as the number of multiple sets of high-bandwidth memory increases.

[0052] To address this issue, the package structure 4a is provided with a first connection structure 205 and a second connection structure 206. The first connection structure 205 is used to electrically connect with the integrated circuit chip 204 to realize data transmission, while the second connection structure 206 is set to support and / or dissipate heat for the logic chip 202. This can prevent the logic chip 202 or the package structure 4a from deforming or being damaged, and can also serve as an effective heat conduction path to quickly dissipate the heat generated by the logic chip 202 to the external environment.

[0053] In some alternative implementations, the first connection structure 205 and the second connection structure 206 may be, for example, solder balls.

[0054] In some alternative implementations, there is a gap between adjacent sets of high-bandwidth memories 203.

[0055] Thus, setting a gap between two adjacent sets of high-bandwidth memories 203 can provide better electrical isolation, which helps to ensure the accuracy and stability of data transmission. It can also help reduce the direct conduction of heat between different high-bandwidth memories 203, reducing the risk of performance degradation or damage caused by local overheating.

[0056] In some alternative implementations, the projection range of the first connection structure 205 and the second connection structure 206 falls within the vertical projection range of the multiple sets of high-bandwidth memories 203.

[0057] In some alternative implementations, from a top-down view (see reference) Figure 4 (The dashed box), the first connection structure 205 is disposed around the periphery of the logic chip 202, and the second connection structure 206 is disposed in the central area of ​​the logic chip 202.

[0058] Here, the first connection structure 205 for connecting with the integrated circuit chip 204 is disposed around the periphery of the logic chip 202, that is, disposed close to the integrated circuit chip 204. This can shorten the signal transmission path and improve the electrical connection efficiency. At the same time, the first connection structure 205 can also serve to support the logic chip 202.

[0059] By placing the second connection structure 206 for supporting and / or dissipating heat for the logic chip 202 in the central region of the logic chip 202, the heat generated by the logic chip 202 during operation can be effectively conducted, improving thermal management performance and providing mechanical support for the logic chip 202.

[0060] In some alternative implementations, the package structure 4a may also include a molding layer 207 disposed on the logic chip 202 and covering each group of high-bandwidth memory 203.

[0061] Here, the sealing layer 207 may include one or more of the following materials in combination: epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, and ion trapping agent.

[0062] The module encapsulation layer 207 can integrate the logic chip 202 and each group of high-bandwidth memory 203 into a single HBM module. At the same time, the module encapsulation layer 207 can also protect each group of high-bandwidth memory 203.

[0063] In some alternative implementations, refer to Figure 6 Each high-bandwidth memory 203 includes multiple dynamic random access memory chips 2031 stacked together.

[0064] In some alternative implementations, there is a gap between each dynamic random access memory chip 2031 of each high-bandwidth memory 203 group.

[0065] In some alternative implementations, the multiple high-bandwidth memories also include a third connection structure 2032 disposed among the multiple dynamic random access memory chips 2031.

[0066] Here, the interconnection between multiple dynamic random access memory chips 2031 can be achieved through the third connection structure 2032.

[0067] The third connection structure 2032 can be, for example, a metal bump.

[0068] In some alternative implementations, the number of dynamic random access memory chips 2031 in each group of high-bandwidth memory 203 may be the same or different.

[0069] Here, when the number of dynamic random access memory chips 2031 in each high-bandwidth memory 203 is the same, it can be ensured that each high-bandwidth memory 203 provides the same bandwidth and capacity, which helps to achieve balanced performance between the parts within the package structure, and also makes the design more standardized and reduces complexity.

[0070] Depending on different application requirements, such as certain tasks having higher memory requirements while other tasks have lower requirements, the number of dynamic random access memory chips 2031 in each high-bandwidth memory 203 group can be flexibly configured to optimize resource utilization.

[0071] In some alternative implementations, the number of dynamic random access memory chips 2031 in each high-bandwidth memory 203 group is up to 16.

[0072] In some alternative implementations, the upper surface of the molding layer 207 is flush with the upper surface of at least one set of high-bandwidth memories 203.

[0073] Here, the upper surface of the molding layer 207 can be flush with the upper surface of the high-bandwidth memory 203 (i.e., the highest high-bandwidth memory 203) with the most dynamic random access memory chips 2031, thus providing a more uniform surface and reducing stress concentration problems caused by differences in the height of different components.

[0074] In some alternative embodiments, the package structure 4a may further include a fourth connection structure disposed between the integrated circuit chip 204 and the substrate 201 for electrically connecting the integrated circuit chip 204 and the substrate 201.

[0075] The fourth connection structure can be, for example, a solder ball, a copper pillar, etc., and there are no restrictions here.

[0076] The circuit integrated chip 204 and the substrate 201 are electrically connected through the fourth connection structure. Furthermore, the circuit integrated chip 204 and the logic chip 202 can be electrically connected through the substrate 201 and the first connection structure 205.

[0077] The above describes the packaging structure 4a of one embodiment of the present invention.

[0078] refer to Figure 7 , Figure 7This is a three-dimensional structural diagram of the HBM module with packaging structure 7a according to another embodiment of the present invention.

[0079] Package structure 7a and package structure 4a are basically similar, the difference being:

[0080] In package structure 4a, two sets of high-bandwidth memory 203 can be provided on logic chip 202. In package structure 7a, four sets of high-bandwidth memory can be provided on logic chip 202. It should be noted that in other embodiments, more sets of high-bandwidth memory 203 can be provided on logic chip 202, which is not limited here.

[0081] The above describes the HBM module of the packaging structure 7a of one embodiment of this utility model.

[0082] Figures 8-11 This is a schematic diagram of the manufacturing steps of the HBM module with packaging structure 4a according to an embodiment of the present invention.

[0083] refer to Figure 8 , providing logic chip 202.

[0084] refer to Figure 9 Multiple high-bandwidth memories 203 are set on the logic chip 202.

[0085] refer to Figure 10 A molding layer 207 is set on the logic chip 202 to mold multiple high-bandwidth memories 203.

[0086] refer to Figure 11 ,right Figure 10 The resulting structure is cut to form individual HBM modules.

[0087] Although the present invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of the invention. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation of the invention and actual implementation due to variables in the manufacturing process, etc. Other embodiments of the invention may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the invention.

Claims

1. A packaging structure, characterized in that, The packaging structure includes: substrate; A logic chip is disposed on the substrate; Multiple high-bandwidth memories are disposed on the logic chip; An integrated circuit chip is configured to be adjacent to the logic chip; A first connection structure and a second connection structure are disposed between the logic chip and the substrate. The first connection structure is used for electrical connection with the integrated circuit chip, and the second connection structure is used for support and / or heat dissipation of the logic chip. The second connection structure is separated from the integrated circuit chip by the first connection structure.

2. The packaging structure according to claim 1, characterized in that, There is a gap between two adjacent sets of the high-bandwidth memory.

3. The packaging structure according to claim 1, characterized in that, The projection ranges of the first connection structure and the second connection structure fall within the vertical projection range of the multiple sets of high-bandwidth memories.

4. The packaging structure according to claim 3, characterized in that, From a top-down view, the first connection structure is disposed around the periphery of the logic chip, and the second connection structure is disposed in the central area of ​​the logic chip.

5. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: A molding layer is disposed on the logic chip and covers each group of high-bandwidth memories.

6. The packaging structure according to claim 1, characterized in that, Each group of high-bandwidth memories includes multiple dynamic random access memory chips stacked together.

7. The packaging structure according to claim 6, characterized in that, Each of the dynamic random access memory chips in each group of the high-bandwidth memory is spaced apart.

8. The packaging structure according to claim 6, characterized in that, The number of dynamic random access memory chips in each group of high-bandwidth memories may be the same or different.

9. The packaging structure according to claim 5, characterized in that, The upper surface of the molding layer is flush with the upper surface of at least one set of the high-bandwidth memories.

10. The packaging structure according to claim 6, characterized in that, The multiple sets of high-bandwidth memories also include a third connection structure disposed between the multiple dynamic random access memory chips.

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