Semiconductor structure

Abstract

A semiconductor structure includes a first transistor including a first gate stack; a second transistor including a second gate stack, wherein in a top-down view of the semiconductor structure, longitudinal directions of the first gate stack and the second gate stack are aligned to a same straight line; a first shallow trench isolation region overlapping the first gate stack; a second shallow trench isolation region overlapping the second gate stack; a dielectric isolation region including: an upper portion separating the first gate stack and the second gate stack; and a lower portion separating the first shallow trench isolation region and the second shallow trench isolation region, wherein an entirety of the dielectric isolation region is formed of a homogeneous dielectric material; and a backside dielectric layer located below the lower portion of the dielectric isolation region and contacting the lower portion of the dielectric isolation region.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor structures and methods for forming them. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate. These material layers can also be patterned using lithography techniques to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continuously reduces the size of the smallest feature, thereby improving the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) and enabling more components to be integrated into a given area. However, reducing the size of the smallest feature has brought about additional problems that need to be addressed. Utility Model Content

[0004] The purpose of this invention is to propose a semiconductor structure to solve at least one of the above-mentioned problems.

[0005] In some embodiments, a semiconductor structure is provided, the semiconductor structure comprising a plurality of first semiconductor nanostructures, wherein upper semiconductor nanostructures of the plurality of first semiconductor nanostructures overlap with lower semiconductor nanostructures of corresponding plurality of first semiconductor nanostructures; a first gate stack located on the plurality of first semiconductor nanostructures; a plurality of second semiconductor nanostructures, wherein upper semiconductor nanostructures of the plurality of second semiconductor nanostructures overlap with lower semiconductor nanostructures of corresponding plurality of second semiconductor nanostructures; a second gate stack located on the plurality of second semiconductor nanostructures; a first shallow trench isolation region and a second shallow trench isolation region, lower than the plurality of first semiconductor nanostructures and the plurality of second semiconductor nanostructures; a dielectric isolation region located between and contacting the first gate stack and the second gate stack, and located between and contacting the first shallow trench isolation region and the second shallow trench isolation region; and a back-side dielectric layer located below the dielectric isolation region and contacting the dielectric isolation region.

[0006] According to one embodiment of the present invention, it further includes: a semiconductor substrate located below the first shallow trench isolation region and the second shallow trench isolation region, wherein the semiconductor substrate is located above the back-side dielectric layer and in contact with the back-side dielectric layer.

[0007] According to one embodiment of the present invention, it further includes: a back-side metal wire located below the back-side dielectric layer and in contact with the back-side dielectric layer.

[0008] According to one embodiment of the present invention, the first gate stack includes a gate dielectric, wherein a vertical portion of the gate dielectric contacts the dielectric isolation region to form a vertical interface.

[0009] According to one embodiment of the present invention, the dielectric isolation region includes a dielectric pad and a dielectric filling region above the dielectric pad.

[0010] According to one embodiment of the present invention, the back dielectric layer contacts the dielectric pad and the dielectric filling area.

[0011] In other embodiments, a semiconductor structure is provided, the semiconductor structure including a first transistor including a first gate stack; a second transistor including a second gate stack, wherein, in a top view of the semiconductor structure, the longitudinal directions of the first gate stack and the second gate stack are aligned with the same straight line; a first shallow trench isolation region overlapping the first gate stack; a second shallow trench isolation region overlapping the second gate stack; a dielectric isolation region including: an upper portion separating the first gate stack and the second gate stack; and a lower portion separating the first shallow trench isolation region and the second shallow trench isolation region, wherein the entire dielectric isolation region is formed of a homogeneous dielectric material; and a back-side dielectric layer located below the lower portion of the dielectric isolation region and contacting the lower portion of the dielectric isolation region.

[0012] According to one embodiment of the present invention, the first shallow trench isolation area includes a dielectric liner and a dielectric filling area above the dielectric liner.

[0013] According to one embodiment of the present invention, the back-side dielectric layer is separated from the first shallow trench isolation region.

[0014] According to one embodiment of the present invention, the back-side dielectric layer contacts the first shallow trench isolation region. Attached Figure Description

[0015] The embodiments of this utility model can be better understood from the following detailed description and the accompanying drawings. It should be noted that, according to standard industry practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0016] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12 , Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16 , Figure 17A , Figure 17B , Figure 18 , Figure 19 , Figure 20A , Figure 20B This diagram illustrates, according to some embodiments, an intermediate stage in forming a transistor and a continuous polysilicon on diffusion edge (CPODE) isolation region.

[0017] Figure 21 and Figure 22 This diagram illustrates an intermediate stage of a continuous polysilicon isolation region on a transistor and a diffusion edge, according to an alternative embodiment.

[0018] Figure 23 and Figure 24 This diagram illustrates an intermediate stage of a continuous polysilicon isolation region on a transistor and a diffusion edge, according to an alternative embodiment.

[0019] Figure 25 This illustrates, according to some embodiments, a leakage path that may be formed in a structure without a continuous polysilicon isolation region on a diffusion edge.

[0020] Figure 26 The diagram illustrates, based on some embodiments, the process flow for forming nanostructured transistors.

[0021] The attached figures are labeled as follows:

[0022] 10: Wafer

[0023] 20: Base

[0024] 20': Base strip

[0025] 22,22': Multi-layer stacked material

[0026] 22A: First Floor

[0027] 22B: Second Floor

[0028] 23: Trench

[0029] 24: Semiconductor strips

[0030] 26: Quarantine Zone

[0031] 26A, 66A: Dielectric Pads

[0032] 26B, 66B: Dielectric-filled regions

[0033] 26T: Top surface

[0034] 27,56: Opening

[0035] 28: Fins

[0036] 29: Disposable intermediate layer

[0037] 30: Dummy gate stack

[0038] 32: Dummy gate dielectric

[0039] 34: Dummy gate electrode

[0040] 36: Hard mask layer

[0041] 38: Gate spacer

[0042] 39: Fin spacer

[0043] 42: Source / Drain notch

[0044] 44: Internal spacers

[0045] 48: Epitaxial source / drain region

[0046] 50: Contact Etching Stop Layer

[0047] 52: Interlayer dielectric

[0048] 54: Hard Mask

[0049] 55, 64: Dashed lines

[0050] 58: Etching Mask

[0051] 60, 62: Trench

[0052] 66: Continuous polysilicon isolation region on the diffusion edge

[0053] 67: Gap

[0054] 68: Backside dielectric layer

[0055] 70: Notch

[0056] 72,73: Area

[0057] 74: Gate dielectric

[0058] 75: Arrow

[0059] 76: Gate electrode

[0060] 78: Replacement gate stack

[0061] 80: Dielectric layer

[0062] 82: Gate contact plug

[0063] 84A, 84B: Fully wound gate transistors

[0064] 86: Backside metal wire

[0065] 88: Dielectric layer

[0066] 90: Conductive components

[0067] 200: Process Flow

[0068] 202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232,234,236: Process

[0069] Nwell: N-type well area

[0070] Pwell: P-type well area

[0071] NMOS: n-type metal oxide semiconductor

[0072] PMOS: p-type metal-oxide semiconductor Detailed Implementation

[0073] It is important to understand that the following content provides many different embodiments or examples to implement different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the explanation. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment of this disclosure, but may depend on the processing conditions and / or required nature of the components. Furthermore, the embodiments in the following description where the first component is formed above or on the second component include those where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components, such that the first and second components are not in direct contact. In addition, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0074] Furthermore, to facilitate the description of the relationship between one element or component and another (or multiple elements or components) in the accompanying drawings, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms may be used. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device during use or operation. The device may also be positioned otherwise (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly.

[0075] A continuous polysilicon isolation region (CPODE) on a diffusion edge (which may be a dielectric isolation region) and a method thereof are provided. According to some embodiments of the present invention, a single-layer continuous polysilicon isolation region on a diffusion edge is formed. The single-layer continuous polysilicon isolation region on a diffusion edge may be without an oxide pad. According to some embodiments, wherein the sacrificial layer between the Gate-All-Around (GAA) transistors is formed of oxide, if the continuous polysilicon isolation region on the diffusion edge includes an oxide pad, the oxide pad may be damaged when the sacrificial layer is removed, leading to leakage problems. According to some embodiments of the present invention, the continuous polysilicon isolation region on the diffusion edge is formed using a dielectric material different from the material of the sacrificial layer.

[0076] While this document discusses fully wound gate transistors to explain the concepts of embodiments of the present invention, these embodiments are applicable to other types of transistors, including but not limited to planar transistors, FinFETs, Complementary Field-Effect Transistors (CFETs), and the like. The embodiments discussed herein provide examples of how the subject matter can be implemented or used, and modifications that can be made will be readily understood by those skilled in the art while remaining within the contemplation of the various embodiments. Similar reference numerals are used to label similar elements in the various views and illustrative embodiments. Although method embodiments may be discussed in a particular order, other method embodiments can be performed in any logical order.

[0077] Figures 1 to 20A and Figure 20B The diagram shows a cross-sectional view of an intermediate stage in forming a fully wound gate transistor and a continuous polysilicon isolation region on the diffusion edge, according to some embodiments. The corresponding process is also schematically reflected in... Figure 26 The process flow shown is as follows.

[0078] Please refer to Figure 1The image shows a perspective view of the wafer. Wafer 10 comprises a multilayer structure, including a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, or the like. However, other substrates and / or structures may also be used, such as semiconductor-on-insulator (SOI), strained semiconductor-on-insulator, silicon-germanium-on-insulator, or the like. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0079] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes involving alternating materials. The corresponding process is shown in process 202 in process flow 200. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0080] According to some embodiments, the first semiconductor material of the first layer 22A is formed from or includes semiconductors such as SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. According to some embodiments, the first layer 22A (e.g., SiGe) is deposited via epitaxial growth, and the corresponding deposition method may be vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), ultra-high vacuum chemical vapor deposition (UHVCVD), reduced-pressure chemical vapor deposition (RPCVD), or similar methods. According to some embodiments, the first layer 22A is formed to a first thickness of approximately... With the agreement Within the range between. However, any suitable thickness can be used while remaining within the range of the embodiments.

[0081] After the first layer 22A is deposited over the substrate 20, a second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or comprises a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, where the second semiconductor material differs from the first semiconductor material of the first layer 22A. For example, according to some embodiments, the first layer 22A is silicon-germanium, and the second layer 22B is formed of silicon, or vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0082] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a thickness different from that of the first layer 22A. According to some embodiments, for example, the first layer 22A has a thickness in the range of about 4 nm to about 7 nm, while the second layer 22B has a thickness in the range of about 8 nm to about 12 nm.

[0083] After the second layer 22B is formed over the first layer 22A, the deposition process is repeated to form the remaining layers of the multilayer stack 22 until the desired top layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other, and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process, and in this description, the first layer 22A may alternatively be referred to as a sacrificial layer. According to some other embodiments, the second layer 22B is a sacrificial layer and is removed in a subsequent process.

[0084] According to some embodiments, some pad oxide layers and hard mask layers may be formed on top of the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0085] Please refer to Figure 2 In the etching process, a portion of the multilayer stack 22 and the underlying substrate 20 are patterned to form trenches 23. The corresponding process is shown in... Figure 26Process 204 of process flow 200. Trench 23 extends into substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as multilayer stack 22'. Below multilayer stack 22', portions of substrate 20 are retained, these portions are hereinafter referred to as substrate strip 20'. Multilayer stack 22' comprises a first layer 22A and a second layer 22B. The first layer 22A is also alternatively referred to as a sacrificial layer, and the second layer is also alternatively referred to as a nanostructure. These portions of multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0086] In the above embodiments, the fully wrapped gate transistor structure can be patterned by any suitable method. For example, these structures can be patterned using one or more photolithography processes (including dual-patterning or multi-patterning processes). Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fully wrapped gate transistor structure.

[0087] Figure 3 This illustrates the formation of isolation region 26, which is also referred to herein as the Shallow Trench Isolation (STI) region. The corresponding process is shown in [the diagram / document / etc.]. Figure 26 Process 206 of process flow 200. Isolation region 26 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20 or by deposition. The pad oxide may also be a deposited silicon oxide layer formed by atomic layer deposition, high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition, or the like. Isolation region 26 may also include a dielectric material above the pad oxide, wherein the dielectric material may be formed by using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, or similar methods. Next, a planarization process (e.g., chemical mechanical polishing (CMP) or mechanical polishing) may be performed to flush the top surface of the dielectric material with the remaining portion of the dielectric material in isolation region 26.

[0088] Next, the isolation region 26 is recessed such that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the isolation region 26, forming a fin 28 (sometimes referred to as a protruding fin). The fin 28 comprises the top of the multilayer stack 22' and the substrate strip 20'. The recess of the isolation region 26 can be performed by a dry etching process, wherein NF3 and NH3 are used as etching gases. Plasma may be generated during the etching process. Argon gas may also be included. According to some other failures of this invention, the recess of the isolation region 26 is performed by a wet etching process. The etching chemicals may include, for example, HF.

[0089] Please refer to Figure 4 A dummy gate stack 30 and a gate spacer 38 are formed on the top surface and sidewalls of the fin 28. The corresponding process is shown in... Figure 26 The process flow 200 is process 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by partially oxidizing the surface of the fin 28 to form an oxide layer, or by depositing a dielectric layer (e.g., a silicon oxide layer). The dummy gate electrode 34 may be formed, for example, by using polycrystalline silicon or amorphous silicon, and may also use other materials, such as amorphous carbon.

[0090] Each dummy gate stack 30 may also include one (or more) hard mask layers 36 above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbide nitride, silicon carbide nitride, or a multilayer thereof. The dummy gate stack 30 may span one or more fins 28 and isolation regions 26 between the fins 28. The dummy gate stack 30 may have a longitudinal direction perpendicular to the longitudinal direction of the fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer above the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning these layers using a patterning process.

[0091] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of the present invention, the gate spacer 38 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon oxide (SiO2), silicon carbide nitride (SiCN), silicon oxynitride (SiON), silicon oxynitride carbon (SiOCN), or the like, and may have a single-layer structure or a multilayer structure comprising multiple dielectric layers. The formation process of the gate spacer 38 may include depositing one or more dielectric layers, followed by an anisotropic etching process on the dielectric layers. The remaining portion of the dielectric layer constitutes the gate spacer 38.

[0092] Figure 5A and Figure 5B show Figure 4 A cross-sectional view of the structure. Figure 5A show Figure 4 Reference section AA is shown, which cuts through the portion of fin 28 not covered by the dummy gate stack 30 and gate spacer 38, and is perpendicular to the gate length direction. Fin spacers 39 on the sidewalls of fin 28 are also shown. Figure 5B show Figure 4 The reference section BB is parallel to the longitudinal direction of fin 28.

[0093] Please refer to Figure 6A and Figure 6B This shows the source / drain recess process. The corresponding process is shown in [the diagram / documentation]. Figure 26 In the process flow 200, process 210 is performed. In the anisotropic etching process, the fins 28 not directly below the dummy gate stack 30 and the gate spacer 38 are etched, thereby forming the source / drain notch 42.

[0094] Figure 7A , Figure 7B , Figure 8A and Figure 8B This shows that the first layer 22A is replaced by a disposable intermediate layer 29. Please refer to [link / reference]. Figure 7A and Figure 7B First, remove the first layer 22A, and then form an opening 27 between the second layer 22B. The corresponding process is shown in [the diagram / document / etc.]. Figure 26 The process flow in process 200 is process 212.

[0095] Please refer to Figure 8A and Figure 8B A disposable interposer layer 29 is formed between the second layer 22B. The corresponding process is shown in... Figure 26 Process 214 of process flow 200. According to some embodiments, the disposable interposer 29 comprises an oxide, such as silicon oxide, and is therefore also referred to as a disposable oxide interposer (DOI). According to some other embodiments, the disposable interposer 29 may comprise other types of dielectric materials, such as AlO, SiON, SiC, SiCN, or the like.

[0096] The formation of the disposable interposer 29 may involve depositing a dielectric layer using a compliant deposition process, such that the dielectric layer includes portions filling the opening 27 and other portions outside the opening 27. Next, a finishing process (which may include an isotropic etching process or an anisotropic etching process followed by an isotropic etching process) is performed to etch or remove portions of the dielectric layer outside the opening 27. The remaining portion of the dielectric layer forms the disposable interposer 29.

[0097] Please refer to Figure 9A and Figure 9BA laterally recessed, polishable interlayer 29 is formed, and the recess is filled with a dielectric material to form an internal spacer 44. Figure 9B The corresponding process is shown in Figure 26 Process 216 of process flow 200. The lateral recesses of the polishable interposer 29 can be achieved by a wet etching process or a dry etching process. The wet etching process can be performed using a dip-plating process, a spray-plating process, a spin-coating process, or a similar method. The second layer 22B is not etched.

[0098] Following the lateral recess, an internal spacer 44 is formed. According to some embodiments, the formation of the internal spacer 44 includes depositing a compliant dielectric layer that extends into the lateral recess. Next, an etching process (also known as a spacer trimming process) is performed to trim the portion of the dielectric layer outside the lateral recess, retaining the portion of the dielectric layer within the lateral recess. The remaining portion of the dielectric layer is referred to as the internal spacer 44.

[0099] Please refer to Figure 10A and Figure 10B The epitaxial source / drain region 48 is formed in the source / drain notch 42 by selective epitaxy. The corresponding process is shown in... Figure 26 Process 218 of process flow 200. Depending on whether the final transistor is a p-type or n-type transistor, p-type or n-type impurities can be doped in situ as epitaxy progresses. For example, when the final transistor is a p-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), or similar materials can be grown. Conversely, when the final transistor is an n-type transistor, silicon phosphide (SiP), silicon carbon phosphide (SiCP), or similar materials can be grown.

[0100] Figure 11A and Figure 11B This is a cross-sectional schematic diagram showing the structure after the formation of the Contact Etch Stop Layer (CESL) 50 and the Inter-Layer Dielectric (ILD) 52. The corresponding process is shown in... Figure 26Process 220 of process flow 200. The contact etch stop layer 50 may be formed of silicon oxide, silicon nitride, silicon carbide nitride, or the like, and may be formed using chemical vapor deposition, atomic layer deposition, or similar methods. The interlayer dielectric 52 may comprise a dielectric material, formed using, for example, flowable chemical vapor deposition, spin coating, chemical vapor deposition, or any other suitable deposition method. The interlayer dielectric 52 may be formed of an oxygen-containing dielectric material, which may comprise silicon oxide, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like.

[0101] The contact etch stop layer 50 and interlayer dielectric 52 are planarized by a planarization process (e.g., chemical mechanical polishing or mechanical polishing). According to some embodiments, the planarization process may remove the hard mask layer 36 to expose the dummy gate electrode 34, such as... Figure 11A and Figure 11B As shown. According to some other embodiments, the planarization process may expose or stop at the hard mask layer 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask layer 36), gate spacer 38, and interlayer dielectric 52 are flush within the process variation range.

[0102] Figure 12 The illustration is based on some embodiments, Figure 11A and Figure 11B A top view of the structure shown. Multilayer stack 22', base strip 20', and fin 28 (see reference). Figure 11A The cross-sectional view of the dummy gate stack 30 (including the dummy gate electrode 34 (e.g., a polysilicon strip)) has a longitudinal orientation in the X direction, and the corresponding cross-sectional view is called the X-section view. Epitaxial source / drain regions 48 are formed on portions of the multilayer stack 22' (as shown in Figure 11B). The edges of the source / drain regions may contact or be spaced apart from the gate spacer 38. Although shown as epitaxial source / drain regions 48 formed on fin 28 and spaced apart from each other, some adjacent epitaxial source / drain regions 48 may merge together.

[0103] Figure 13A and Figure 13B Top view and cross-sectional view of the hard mask 54 formed according to some embodiments are shown respectively. Figure 13B show Figure 13A Section 13B-13B in the middle. For example... Figure 13B As shown, a hard mask 54 is formed over the dummy gate electrode 34. The hard mask 54 may comprise materials such as SiN, silicon (e.g., amorphous silicon), TiN, BN, or the like, or multiple layers thereof. A patterned etch mask 58 is formed over the hard mask 54. According to some embodiments, the etch mask 58 comprises photoresist and may have a single-layer structure, a three-layer structure, or the like. The etch mask 58 is patterned.

[0104] The hard mask 54 is etched using an etch mask 58 to define a pattern and form an opening 56 that exposes the dummy gate electrode 34. (As...) Figure 13A As shown in the top view, the opening 56 may be elongated and located directly above a dummy gate electrode 34. Furthermore, the opening 56 is above and spans one or more multilayer stacks 22'. The opening 56 may have a longer edge aligned with the interface between the dummy gate stack 30 and the gate spacer 38, or it may overlap with the gate spacer 38, or it may overlap or not overlap with the contact etch stop layer 50 and the interlayer dielectric 52. The etch mask 58 may be removed (or not removed) after the hard mask 54 has been patterned.

[0105] Next, a hard mask 54 is used to etch the underlying dummy gate electrode 34 until the dummy gate dielectric 32 is exposed. Then, for example, the dummy gate dielectric 32 is removed by an isotropic etching process to expose the multilayer stack 22', resulting in... Figure 14 The structure shown. The corresponding process is shown in [the diagram / document / etc.]. Figure 26 The process flow 200 is process 222. Therefore, trench 60 is formed in dummy gate electrode 34. This etching can be anisotropic, such that the edge of dummy gate electrode 34 facing trench 60 is perpendicular and straight.

[0106] Next, an etching process is performed to remove the exposed multilayer stack 22', followed by further etching of the underlying semiconductor material, such as the substrate strip 20'. The corresponding process is shown in... Figure 26 The process flow 200 is process 224. Therefore, the trench 62 is formed between adjacent isolation zones 26, such as... Figure 15 As shown. According to some embodiments, the trench 62 extends to a horizontal level below the bottom surface of the isolation zone 26, such as... Figure 15 As shown. According to some other embodiments, the bottom of the trench 62 may also be flush with or higher than the bottom surface of the isolation area 26, as shown by the dashed line 64.

[0107] It should be understood that isolation region 26 may be worn out during the removal of multilayer stack 22'. For example, etching of the polishable interposer layer 29 (sometimes referred to as the sacrificial layer) in multilayer stack 22' can lead to wear out of isolation region 26 due to the similarity of materials between isolation region 26 and multilayer stack 22', resulting in low etch selectivity between isolation region 26 and multilayer stack 22'. Therefore, exposed portions of isolation region 26 may be recessed. Dashed line 55 schematically shows the corresponding contour of isolation region 26 caused by wear.

[0108] Figure 16 Showing filled trenches 60 and 62 to form a continuous polysilicon (CPODE) isolation region 66 on the diffusion edge. Corresponding process is shown in... Figure 26 The process flow 200 is process 226. According to some embodiments, the filling process may include depositing one or more dielectric materials to completely fill trenches 60 and 62. Next, a planarization process (e.g., chemical mechanical polishing or mechanical polishing) may be performed to remove excess dielectric material above the dummy gate electrode 34, thereby forming a continuous polysilicon isolation region 66 on the diffusion edge.

[0109] According to some embodiments, the continuous polysilicon isolation region 66 on the diffusion edge may be selected from a dielectric material that has relatively high etch selectivity when the polishable interposer 29 is subsequently removed. For example, the continuous polysilicon isolation region 66 on the diffusion edge may be selected from SiN, SiON, SiOCN, SiCN, or the like or combinations thereof. According to some embodiments, the continuous polysilicon isolation region 66 on the diffusion edge has a monolayer structure, and the entire continuous polysilicon isolation region 66 on the diffusion edge is formed of a homogeneous dielectric material such as SiN.

[0110] According to some other embodiments, the continuous polysilicon isolation region 66 on the diffusion edge may have a multilayer structure, the multilayer structure including a dielectric pad 66A and a dielectric filling region 66B above the dielectric pad 66A. The dielectric filling region 66B and the dielectric pad 66A may also have high etch selectivity relative to the disposable interposer 29, such that when the disposable interposer 29 is etched, the continuous polysilicon isolation region 66 on the diffusion edge is not etched.

[0111] In subsequent processes, a back-side polishing process is performed from the back side of wafer 10. The corresponding process is shown in [the diagram / document / etc.]. Figure 26 Process 228 of process flow 200. Thinning of substrate 20. Performing a back-side polishing process until the continuous polysilicon isolation region 66 on the diffusion edge is exposed on the back side of wafer 10. According to some embodiments, such as Figure 17AAs shown, after the backside polishing process, a portion of the substrate 20 (sometimes referred to as a bulk semiconductor substrate) may remain beneath the isolation region 26. When the continuous polysilicon isolation region 66 on the diffusion edge includes a dielectric pad 66A, the bottom of the dielectric pad 66A may be removed, exposing the dielectric fill region 66B to the backside of the wafer 10.

[0112] Next, as Figure 17A As shown, the back-side dielectric layer 68 is formed by a deposition process. The corresponding process is shown in [the diagram / document / etc.]. Figure 26 Process 230 of process flow 200. According to some embodiments, the back-side dielectric layer 68 is formed of oxides, nitrides, or the like, or includes the aforementioned materials. For example, the back-side dielectric layer 68 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon oxycarbonide, or the like.

[0113] According to some embodiments, in forming Figure 20A and Figure 20B The structure shown (or Figure 22 In the case of the structure shown, the back dielectric layer 68 can still be a blank layer that does not include other materials / components (e.g., conductive components). The back dielectric layer 68 can also be referred to as an insulating substrate.

[0114] It should be understood that when the continuous polysilicon isolation region 66 on the diffusion edge is formed of silicon nitride, due to the high defect density in silicon nitride, the continuous polysilicon isolation region 66 on the diffusion edge may attract charges from the substrate 20. This may lead to region 73 ( Figure 16 The leakage path in ). For example, Figure 25 This diagram shows two adjacent semiconductor fins formed above a p-type well (used to form an n-type metal-oxide-semiconductor NMOS) and an N-type well (used to form a p-type metal-oxide-semiconductor PMOS). Shallow trench isolation regions are formed in the p-type and N-type wells. It should be understood that the shallow trench isolation regions may include nitride pads contacting the p-type and N-type wells. Silicon nitride has a high-density defect density and can trap and accumulate charges to form a leakage path. Furthermore, negative charges are attracted by the accumulated positive charges to form a leakage path.

[0115] By removing portions of the semiconductor substrate that could form leakage paths, and by forming a back-side dielectric layer 68 on which a continuous polysilicon isolation region 66 sits at the diffusion edge, leakage paths are eliminated.

[0116] Figure 17B show Figure 17A The top view of the structure shown shows a continuous polysilicon isolation region 66 on the diffusion edge.

[0117] Next, the dummy gate electrode 34 and the dummy gate dielectric 32 (and any remaining hard mask layer 36) are removed in one or more etching processes to form a notch 70, as shown. Figure 18 As shown. The corresponding process is displayed in Figure 26 Process 232 of process flow 200. According to some embodiments, the dummy gate electrode 34 and dummy gate dielectric 32 are removed by an anisotropic dry etching process. For example, the etching process can be performed using a reactive gas that selectively etches the dummy gate electrode 34 and dummy gate dielectric 32 at a rate faster than that that etches the interlayer dielectric 52. Each notch 70 exposes a portion of the multilayer stack 22' and / or over a portion of the multilayer stack 22', which contains future channel regions in subsequently completed transistors.

[0118] The dummy gate electrode 34 and the dummy gate dielectric 32 can also have high etch selectivity relative to the continuous polysilicon isolation region 66 on the diffusion edge, so that the dummy gate electrode 34 and the dummy gate dielectric 32 are etched without etching the continuous polysilicon isolation region 66 on the diffusion edge.

[0119] Next, the polishable interlayer 29 is removed to extend the notch 70 to the second layer 22B. The corresponding process is shown in... Figure 26 In the process flow 200, process 234 is used to form Figure 19 The structure. The polishable interposer 29 can be removed by an isotropic etching process, such as a wet etching process using an etchant selective to the material of the polishable interposer 29, while the second layer 22B and the substrate 20 remain relatively unetched compared to the polishable interposer 29. The isolation region 26 may be slightly recessed or not recessed. For example, (in Figure 3 In the steps shown, a silicon nitride capping layer may be formed on each isolation region 26 to protect the isolation region 26.

[0120] According to some embodiments, the polishable interposer 29 is formed of silicon oxide (DOI), and when dry etching is performed, the etching gas may contain a mixture of NF3 and NH3, a mixture of HF and NH3, or the like. When wet etching is performed, diluted HF may be used.

[0121] When etching the polishable interposer 29, because the material of the continuous polysilicon isolation region 66 on the diffusion edge has a high etch selectivity relative to the polishable interposer 29, the continuous polysilicon isolation region 66 on the diffusion edge is not etched. For example, the etch selectivity ER29 / ER66 can be greater than about 5, greater than about 10, 10, 50 or larger, where ER29 is the etch rate of the polishable interposer 29 and ER66 is the etch rate of the continuous polysilicon isolation region 66 on the diffusion edge. Therefore, when etching the polishable interposer 29, [the following is avoided:] Figure 19 Arrow 75 in the diagram represents the lateral etching of the continuous polysilicon isolation region 66 on the diffusion edge. For example, if the continuous polysilicon isolation region 66 on the diffusion edge comprises silicon nitride and the polishable interposer 29 comprises silicon oxide, the continuous polysilicon isolation region 66 on the diffusion edge will not be damaged.

[0122] According to some embodiments, the gap 67 is formed in a continuous polysilicon isolation region 66 on the diffusion edge. According to some other embodiments, no gap is formed.

[0123] Please refer to Figure 20B Region 72 is marked as such. Region 72 is the area on the diffusion edge where the continuous polysilicon isolation region 66 may be unfavorably removed if it contains a material (e.g., a silicon oxide pad) that has low etch selectivity relative to the material (e.g., silicon oxide) of the polishable interposer 29. When these portions of the silicon oxide pad are removed, the subsequently formed metal gate will be located closer to the corresponding source / drain plug, potentially causing problems such as electrical short circuits or leakage. Furthermore, the bottom of the silicon oxide pad may be eroded, making it difficult to form a compliant replacement gate dielectric, which may also lead to electrical short circuits or leakage.

[0124] According to some embodiments of the present invention, by increasing the etching selectivity ER29 / ER66, the area 72 shown in FIG20 will be reduced or undamaged.

[0125] Please refer to Figure 20A and Figure 20B This forms the gate dielectric 74 and the gate electrode 76, thus forming the gate replacement stack 78. The corresponding process is shown in [the diagram / illustration]. Figure 26 Process 236 of process flow 200. According to some embodiments, each gate dielectric 74 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer may be formed of or comprise silicon oxide, which can be deposited by a compliant deposition process (e.g., atomic layer deposition or chemical vapor deposition) or by an oxidation process. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, the high-k dielectric layer may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof.

[0126] A gate electrode 76 is also formed. In the formation process, a conductive layer is first formed on a high-dielectric-constant dielectric layer and completely fills the remaining portion of the notch 70. The gate electrode 76 may contain a metallic material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, the gate electrode 76 may include any number of layers, any number of work function adjustment layers, and possible filler materials. The replacement gate stack 78 also fills the space between adjacent second layers 22B and the space between the bottommost second layer 22B and the underlying substrate strip 20'.

[0127] After filling the notch 70, a planarization process (e.g., chemical mechanical polishing or mechanical polishing) is performed to remove excess portions of the gate dielectric 74 and gate electrode 76, which are located in the interlayer dielectric 52. Figure 11B Above the top surface of the transistor. The gate dielectric 74 and the gate electrode 76 are collectively referred to as the replacement gate stack 78 of the final transistor.

[0128] Figure 20A The diagram further illustrates the formation of a dielectric layer 80 and a gate contact plug 82 according to some embodiments. The dielectric layer 80 may include an interlayer dielectric and may or may not include an etch stop layer between the interlayer dielectric and the substituted gate stack 78. The gate contact plug 82 is electrically connected to the gate electrode 76, thereby forming fully wound gate transistors 84A and 84B.

[0129] Although not shown perpendicular to Figure 20A The structure of the fully wound gate transistors 84A and 84B in another cross-section of the cross-section, but can be obtained from... Figure 11B Understanding the structure in another cross-section, besides replacing the gate stack 78 Figure 11B The dummy gate stack 30 in the middle.

[0130] Figure 21 and Figure 22 This diagram illustrates an intermediate stage of structure formation according to alternative embodiments. These embodiments are essentially the same as the previously described embodiments, except that in the back-side polishing process, the substrate 20 is removed, and the isolation region 26 is exposed from the bottom. According to these embodiments, the back-side dielectric layer 68 may still be without any other material / component (e.g., conductive components) on it. Figure 22 The blank layer in the structure shown is the structure formed after the corresponding replacement gate stack 78 is formed.

[0131] It should be understood that the isolation region 26 may include dielectric pads 26A and dielectric fill regions 26B that are distinguishable from each other. For example, dielectric pads 26A and dielectric fill regions 26B may be formed of the same material but have different properties, such as different densities. Dielectric pads 26A and dielectric fill regions 26B may also be formed of different materials. For example, dielectric pads 26A may be formed of silicon oxide, and dielectric fill regions 26B may be formed of silicon nitride.

[0132] According to some other embodiments, the dielectric pad 26A may be formed of silicon nitride, and the dielectric filling region 26B may be formed of silicon oxide. In a back-side polishing process, the bottom of the dielectric pad 26A is removed, thus the dielectric filling region 26B physically contacts the back-side dielectric layer 68. In contrast, as... Figure 20A In the structure shown, the bottom of the dielectric pad 26A may still exist in the final structure.

[0133] Figure 23 and Figure 24 This diagram illustrates an intermediate stage of the structure formation according to alternative embodiments. These embodiments are essentially the same as the previously described embodiments, except for the formation of a back-side wiring structure. For example, a dielectric layer 88 is formed, and a back-side metal line 86 is formed in the dielectric layer 88.

[0134] The back-side metal wire 86 is electrically connected to the front-side component via a conductive member 90, which can penetrate the isolation zone 26. The conductive member 90 is schematically shown using dashed lines. The back-side metal wire 86 can be used to conduct electricity and / or signals. Therefore, the structure according to this embodiment is also compatible with the formation of back-side wiring.

[0135] This invention has several advantages. By using a dielectric material (e.g., silicon nitride) different from the sacrificial layer material in the multilayer stack for the continuous polysilicon isolation region on the diffusion edge, damage to the continuous polysilicon isolation region on the diffusion edge during etching of the sacrificial layer is eliminated. However, silicon nitride can cause leakage paths to occur below the continuous polysilicon isolation region on the diffusion edge and in contact with a portion of the semiconductor substrate of the continuous polysilicon isolation region on the diffusion edge. Leakage paths are further eliminated by removing the lower portion of the semiconductor substrate and replacing it with a dielectric layer.

[0136] According to some embodiments of the present invention, the method includes forming a dummy gate stack on a first protruding structure of a wafer, wherein the first protruding structure includes a first semiconductor layer; etching the dummy gate stack to form a trench in the dummy gate stack and expose the first semiconductor layer; removing the first semiconductor layer and a semiconductor strip below the first semiconductor layer to extend the trench downward; filling the trench with a dielectric material to form a dielectric isolation region; performing a back-side polishing process on the semiconductor substrate of the wafer, wherein the dielectric isolation region is exposed from the back side of the wafer; and forming a back-side dielectric layer on the back side of the wafer, wherein the back-side dielectric layer contacts the dielectric isolation region.

[0137] In one embodiment, the entire dielectric isolation region is formed of a homogeneous dielectric material. In another embodiment, a dummy gate stack is further located above a second protruding structure, the second protruding structure including: a second semiconductor layer; and a sacrificial layer located below and in contact with the second semiconductor layer, wherein the method further includes, after forming the dielectric isolation region, etching the sacrificial layer with an etching chemical to create a space, wherein the dielectric isolation region is exposed to the etching chemical, and the sacrificial layer and the dielectric isolation region include different dielectric materials; and forming a replacement gate stack, the replacement gate stack being included as a portion of the space.

[0138] In one embodiment, the etching chemicals do not etch the dielectric isolation region. In one embodiment, the sacrificial layer comprises silicon oxide, and the dielectric isolation region comprises silicon nitride. In one embodiment, a replacement gate stack surrounds the second semiconductor layer. In one embodiment, when the sacrificial layer is etched, the sidewalls of the dielectric isolation region are exposed to the etching chemicals. In one embodiment, after a back-side polishing process, a portion of the semiconductor substrate is left to separate the shallow trench isolation region from the back-side dielectric layer. In one embodiment, the dielectric isolation region is located between two shallow trench isolation regions, and wherein the two shallow trench isolation regions are polished during the back-side polishing process. In one embodiment, the method further includes forming a metal line on the back side of the wafer, wherein the metal line contacts the back-side dielectric layer.

[0139] According to some embodiments of the present invention, the structure includes a plurality of first semiconductor nanostructures, wherein the upper semiconductor nanostructures of the plurality of first semiconductor nanostructures overlap with the lower semiconductor nanostructures of the corresponding plurality of first semiconductor nanostructures; a first gate stack located on the plurality of first semiconductor nanostructures; a plurality of second semiconductor nanostructures, wherein the upper semiconductor nanostructures of the plurality of second semiconductor nanostructures overlap with the lower semiconductor nanostructures of the corresponding plurality of second semiconductor nanostructures; a second gate stack located on the plurality of second semiconductor nanostructures; a first shallow trench isolation region and a second shallow trench isolation region, which are lower than the plurality of first semiconductor nanostructures and the plurality of second semiconductor nanostructures; a dielectric isolation region located between and in contact with the first gate stack and the second gate stack, and located between and in contact with the first shallow trench isolation region and the second shallow trench isolation region; and a back-side dielectric layer located below the dielectric isolation region and in contact with the dielectric isolation region.

[0140] In one embodiment, the entire dielectric isolation region is formed of a homogeneous dielectric material. In another embodiment, the entire dielectric isolation region is formed of silicon nitride. In one embodiment, the structure further includes a semiconductor substrate located below the first shallow trench isolation region and the second shallow trench isolation region, wherein the semiconductor substrate is located above and contacts the back-side dielectric layer. In one embodiment, the structure further includes a back-side metal line located below and contacts the back-side dielectric layer. In one embodiment, the first gate stack includes a gate dielectric, and wherein a vertical portion of the gate dielectric contacts the dielectric isolation region to form a vertical interface.

[0141] According to some embodiments of the present invention, the structure includes a first transistor including a first gate stack; a second transistor including a second gate stack, wherein in a top view of the semiconductor structure, the longitudinal directions of the first gate stack and the second gate stack are aligned with the same straight line; a first shallow trench isolation region overlapping the first gate stack; a second shallow trench isolation region overlapping the second gate stack; a dielectric isolation region including: an upper portion separating the first gate stack and the second gate stack; and a lower portion separating the first shallow trench isolation region and the second shallow trench isolation region, wherein the entire dielectric isolation region is formed of a homogeneous dielectric material; and a back-side dielectric layer located below the lower portion of the dielectric isolation region and in contact with the lower portion of the dielectric isolation region.

[0142] In one embodiment, the dielectric isolation region comprises silicon nitride. In one embodiment, the back-side dielectric layer comprises silicon nitride. In one embodiment, the back-side dielectric layer comprises silicon oxide.

[0143] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various perspectives. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A plurality of first semiconductor nanostructures, wherein the upper semiconductor nanostructure of the plurality of first semiconductor nanostructures overlaps with the lower semiconductor nanostructure of the corresponding plurality of first semiconductor nanostructures; A first gate stack is located on the plurality of first semiconductor nanostructures; A plurality of second semiconductor nanostructures, wherein the upper semiconductor nanostructure of the plurality of second semiconductor nanostructures overlaps with the lower semiconductor nanostructure of the corresponding plurality of second semiconductor nanostructures; A second gate stack is located on the plurality of second semiconductor nanostructures; A first shallow trench isolation region and a second shallow trench isolation region are lower than the plurality of first semiconductor nanostructures and the plurality of second semiconductor nanostructures; A dielectric isolation region is located between the first gate stack and the second gate stack and contacts the first gate stack and the second gate stack, and is located between the first shallow trench isolation region and the second shallow trench isolation region and contacts the first shallow trench isolation region and the second shallow trench isolation region. as well as A back-side dielectric layer is located below the dielectric isolation region and contacts the dielectric isolation region.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A semiconductor substrate is located below the first shallow trench isolation region and the second shallow trench isolation region, wherein the semiconductor substrate is located above the back-side dielectric layer and in contact with the back-side dielectric layer.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: A back-side metal line is located below the back-side dielectric layer and contacts the back-side dielectric layer.

4. The semiconductor structure as described in claim 1, characterized in that, The first gate stack includes a gate dielectric, wherein a vertical portion of the gate dielectric contacts the dielectric isolation region to form a vertical interface.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The dielectric isolation region includes a dielectric pad and a dielectric filling region above the dielectric pad.

6. The semiconductor structure as described in claim 5, characterized in that, The back dielectric layer contacts the dielectric pad and the dielectric filling area.

7. A semiconductor structure, characterized in that, include: A first transistor, including a first gate stack; A second transistor includes a second gate stack, wherein, in a top view of the semiconductor structure, the longitudinal directions of the first gate stack and the second gate stack are aligned with the same straight line; A first shallow trench isolation region overlaps with the first gate stack; A second shallow trench isolation region overlaps with the second gate stack; A dielectric isolation zone includes: The upper part separates the first gate stack and the second gate stack; and The lower part separates the first shallow trench isolation area and the second shallow trench isolation area; as well as A back-side dielectric layer is located below the lower portion of the dielectric isolation region and contacts the lower portion of the dielectric isolation region.

8. The semiconductor structure as described in claim 7, characterized in that, The first shallow trench isolation region includes a dielectric liner and a dielectric filling region above the dielectric liner.

9. The semiconductor structure as described in claim 7 or 8, characterized in that, The back dielectric layer is separated from the first shallow trench isolation region.

10. The semiconductor structure as described in claim 7 or 8, characterized in that, The back dielectric layer contacts the first shallow trench isolation area.

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