Semiconductor device

Abstract

A semiconductor device includes a first semiconductor fin and a second semiconductor fin; a first nanostructure over the first semiconductor fin; a second nanostructure over the second semiconductor fin; a dummy region extending between the first semiconductor fin and a bottom surface of the first nanostructure; and a gate structure on a top surface of the first nanostructure and on a top surface of the second nanostructure and extending between the second semiconductor fin and a bottom surface of the second nanostructure.

Description

Technical Field

[0001] This utility model relates to semiconductor devices, and more particularly to hybrid nanostructure devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically formed by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit elements and components on the semiconductor substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest components, allowing more components to be integrated into a given area. However, as the size of the smallest components decreases, more problems arise that need to be solved. Utility Model Content

[0004] This utility model provides a semiconductor device comprising a first semiconductor fin and a second semiconductor fin; a first nanostructure above the first semiconductor fin; a second nanostructure above the second semiconductor fin; a dummy region extending between the bottom surfaces of the first semiconductor fin and the first nanostructure; and a gate structure located on the top surface of the first nanostructure and on the top surface of the second nanostructure, and extending between the bottom surface of the second semiconductor fin and the second nanostructure.

[0005] In some embodiments, the dummy region is not in physical contact with the gate structure.

[0006] In some embodiments, the semiconductor device further includes: an isolation region surrounding the first semiconductor fin; and

[0007] A protective layer is provided on the isolation region, wherein the protective layer extends along the sidewall of the dummy region and along the sidewall of the first nanostructure, wherein the sidewall of the second nanostructure is not in physical contact with the protective layer, and wherein the gate structure extends on the top surface of the protective layer.

[0008] In some embodiments, the semiconductor device further includes a source / drain region in a first semiconductor fin, wherein the bottom surface of the source / drain region is lower than the top surface of the dummy region.

[0009] In some embodiments, the semiconductor device further includes a gate spacer on a first semiconductor fin, wherein the gate spacer extends along the sidewall of the dummy region.

[0010] This utility model provides a semiconductor device comprising a first fin and a second fin above a semiconductor substrate; a plurality of first nanostructures above the first fin; a plurality of second nanostructures above the second fin; a dielectric region above the first fin, wherein the dielectric region separates the first nanostructures from the first fin; a first gate structure above the first fin, wherein the first gate structure separates adjacent first nanostructures; and a second gate structure above the second fin, wherein the second gate structure separates the second nanostructures from the second fin, wherein the second gate structure separates adjacent second nanostructures.

[0011] In some embodiments, the semiconductor device further includes: a first shallow trench isolation region surrounding the first fin;

[0012] A second shallow trench isolation region surrounds the second fin; a first hard mask is on the first shallow trench isolation region; and a second hard mask is on the second shallow trench isolation region, wherein the thickness of the second hard mask is less than that of the first hard mask, and wherein the top surface of the second shallow trench isolation region is closer to the semiconductor substrate than the top surface of the first shallow trench isolation region.

[0013] In some embodiments, the bottom surface of the bottommost first nanostructure of the plurality of first nanostructures is not in physical contact with the first gate structure.

[0014] In some embodiments, the number of the plurality of first nanostructures is the same as the number of the plurality of second nanostructures.

[0015] In some embodiments, the bottom surface of the second gate structure is closer to the semiconductor substrate than the bottom surface of the first gate structure. Attached Figure Description

[0016] The embodiments of this utility model can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this utility model.

[0017] Figure 1 Examples of nanostructured field-effect transistors are illustrated in a three-dimensional schematic diagram based on some embodiments.

[0018] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A as well as Figure 23B This is a cross-sectional schematic diagram illustrating an intermediate stage in the fabrication of a nanostructured field-effect transistor, based on some embodiments.

[0019] Figure 24 The diagram illustrates, according to some embodiments, the intermediate stages of fabricating nanostructured field-effect transistors.

[0020] Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B as well as Figure 26C This is a cross-sectional schematic diagram illustrating an intermediate stage in the fabrication of a nanostructured field-effect transistor, based on some embodiments.

[0021] The reference numerals in the attached figures are explained as follows:

[0022] 40: Protective materials

[0023] 42: Protective layer

[0024] 50: Substrate

[0025] 50H: Higher power region

[0026] 50L: Lower power range

[0027] 50N: n-type region

[0028] 50P: p-type area

[0029] 52: Multilayer stacking

[0030] 54: First semiconductor layer

[0031] 56: Second semiconductor layer

[0032] 56': Bottom semiconductor layer

[0033] 62: Fins

[0034] 64: First Nanostructure

[0035] 64': Bottom nanostructure

[0036] 65: Opening

[0037] 66: Second Nanostructure

[0038] 66': Bottom nanostructure

[0039] 68: Insulation materials

[0040] 70: Shallow trench isolation zone

[0041] 71: Dummy Materials

[0042] 72: Virtual Area

[0043] 72': Bottom Dotted Area

[0044] 73: Dummy gate region

[0045] 82: Dummy Dielectric

[0046] 84: Dummy Gate

[0047] 86: Mask

[0048] 90: Spare layer

[0049] 92: Gate spacer

[0050] 94: Fin spacers

[0051] 96: Source / Drain Groove

[0052] 97: Side wall groove

[0053] 98: Internal spacer

[0054] 100: Epitaxial source / drain region

[0055] 100': Semiconductor layer

[0056] 102: Contact Etching Stop Layer

[0057] 104: First interlayer dielectric

[0058] 108: Groove

[0059] 110: Gate dielectric layer

[0060] 112: Gate electrode

[0061] 114: Etching Stop Layer

[0062] 116: Interlayer dielectric of the second layer

[0063] 126: Gate contact

[0064] 128: Source / Drain Contacts

[0065] 129: Metal-Semiconductor Alloy Region

[0066] A-A': Cross-section

[0067] B-B': Section

[0068] C-C': Cross section Detailed Implementation

[0069] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of this utility model. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of the embodiments of this utility model. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0070] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0071] The embodiments described below are in the specific context of a die containing nanostructure field-effect transistors (“nanostructure-FETs” or “nano-FETs”). However, various embodiments can be applied to dies containing other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, stacked transistors, or the like) that are alternatives to or in combination with nanostructure field-effect transistors.

[0072] According to various embodiments, dummy gate regions are used to form both low-power and high-power nanostructured field-effect transistors (FETs) on the same substrate. In embodiments where dummy regions (e.g., disposable oxide interposers or the like) are formed between nanostructures, some dummy regions are not removed for the low-power FETs, thus forming dummy gate regions on some nanostructures of the low-power FETs. Forming dummy gate regions allows for the formation of both low-power and high-power FETs. For example, dummy gate regions are formed in the wafer region of the low-power FETs but not in the wafer region of the high-power FETs.

[0073] Figure 1 The illustrations, based on some embodiments, depict examples of nanostructured field-effect transistors (e.g., nanowire FETs, nanosheet FETs, nanoFETs, gate-all-around (GAA) FETs, or the like) in a three-dimensional schematic diagram. For simplicity, Figure 1 Some components of the nanostructured field-effect transistor (FET) can be simplified and / or omitted. The nanostructured FET includes a second nanostructure 66 (e.g., nanosheet, nanowire, or the like) above fins 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the second nanostructure 66 is a semiconductor component serving as a channel region of the nanostructured FET. The second nanostructure 66 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation regions 70, such as shallow trench isolation (STI) regions, are disposed between adjacent fins 62, and the fins 62 may protrude from and above adjacent shallow trench isolation regions 70. The second nanostructure 66 is disposed above and between adjacent shallow trench isolation regions 70. Some portions of the shallow trench isolation regions 70 may be covered by a protective layer (not shown). Figure 1(In the context of this disclosure). Although the shallow trench isolation region 70 is described / illustrated as separate from the substrate 50, as used herein, the term "substrate" can refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fin 62 is illustrated as being a single, continuous material with the substrate 50, the bottom portion of the fin 62 and / or the substrate 50 may comprise a single material or multiple materials. In this disclosure, fin 62 refers to the portion extending between adjacent shallow trench isolation regions 70.

[0074] The gate dielectric layer 110 is located above the top surface of the fin 62 and along the top surface, sidewalls, and bottom surface of the second nanostructure 66. The gate electrode 112 is located above the gate dielectric layer 110. The gate dielectric layer 110 and the gate electrode 112 can be collectively referred to as a "gate structure" or "gate stack." A dummy gate region (not shown) Figure 1 (As described in more detail below) can be formed on the bottom surface of some of the bottommost second nanostructures 66 and on the top surface of some fins 62. Epitaxial source / drain regions 100 are disposed on the fins 62 on both sides of the gate dielectric layer 110 and the gate electrode 112. Depending on the context, the epitaxial source / drain regions 100 may be referred to individually or collectively as source or drain. A first-layer dielectric (ILD) 104 is formed above the epitaxial source / drain regions 100. The contacts of the epitaxial source / drain regions 100 (described later) will be formed by the first-layer dielectric 104. The epitaxial source / drain regions 100 may be shared among various second nanostructures 66. For example, epitaxial source / drain regions 100 can be combined or merged by epitaxial growth, or adjacent epitaxial source / drain regions 100 can be electrically connected by coupling epitaxial source / drain regions 100 with the same contact.

[0075] Figure 1 Further illustrations are provided of the reference cross-sections used in the figures below. Cross-section A-A' runs along the longitudinal axis of the fin 62 of the nanostructured field-effect transistor and along, for example, the direction of current flow between the epitaxial source / drain regions 100 of the nanostructured field-effect transistor. Cross-section B-B' is perpendicular to cross-section A-A' and extends along the longitudinal axis of the gate electrode 112. Cross-section C-C' is parallel to cross-section B-B' (e.g., perpendicular to cross-section A-A') and extends through the epitaxial source / drain regions 100 of the nanostructured field-effect transistor. For clarity, subsequent figures will refer to these reference cross-sections.

[0076] Some embodiments discussed in this disclosure are discussed in the context of nanostructured field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate orientations for use in planar devices, such as planar FETs or FinFETs, to replace or combine with nanostructured field-effect transistors. For example, a FinFET may comprise semiconductor fins on a substrate, wherein the semiconductor fins are semiconductor components serving as channel regions of the FinFET. Similarly, a planar FET may comprise a substrate, wherein the planar portion of the substrate is the semiconductor component serving as the channel region of the planar FET. Other FETs or FET configurations are also possible.

[0077] Figures 2 to 26C This is a schematic diagram illustrating an intermediate stage in the fabrication of nanostructured field-effect transistors, based on some embodiments. Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 17B , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24 , Figure 25A as well as Figure 26A The diagram shows the approximation along the path. Figure 1 A schematic diagram of the cross section A-A'. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 25B Figure and Figure 26B The diagram shows the approximation along the path. Figure 1A schematic diagram of the cross-section B-B'. Figure 10C , Figure 11C , Figure 12C , Figure 18C , Figure 18D , Figure 25C as well as Figure 26C The diagram shows the approximation along the path. Figure 1 A schematic diagram of the cross section C-C'.

[0078] exist Figure 2 In some embodiments, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0079] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as n-type metal-oxide-semiconductor (NMOS) transistors, e.g., n-type nano-FETs, and the p-type region 50P can be used to form p-type devices, such as p-type metal-oxide-semiconductor (PMOS) transistors, e.g., p-type nano-FETs. The n-type region 50N may (or may not) be physically separated from the p-type region 50P (not shown separately), and any number of device elements (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although only one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided. Unless otherwise stated, the following illustrations depict process steps that can be performed in either the n-type region 50N or the p-type region 50P.

[0080] The substrate 50 also has a lower power region 50L and a higher power region 50H. The lower power region 50L can be used to form a relatively low-power nanostructure field-effect transistor, while the higher power region 50H can be used to form a relatively high-power nanostructure field-effect transistor. As described in more detail later, the lower power nanostructure field-effect transistor formed in the lower power region 50L has lower current performance than the higher power nanostructure field-effect transistor formed in the higher power region 50H. The technology disclosed herein allows both lower power nanostructure field-effect transistors and higher power nanostructure field-effect transistors to be formed on the same substrate 50. The lower power region 50L may (or may not) be physically separated from the higher power region 50H (not shown separately), and any number of device elements (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the lower power region 50L and the higher power region 50H. The n-type region 50N may have a low-power region 50L for a low-power n-type nanostructure field-effect transistor and a high-power region 50H for a high-power n-type nanostructure field-effect transistor, while the p-type region 50P may have a low-power region 50L for a low-power p-type nanostructure field-effect transistor and a high-power region 50H for a high-power p-type nanostructure field-effect transistor. Although only one low-power region 50L and one high-power region 50H are shown in the n-type region 50N and the p-type region 50P, any number of low-power regions 50L and high-power regions 50H may be provided. In some cases, a die or wafer having both the low-power nanostructure field-effect transistor and the high-power nanostructure field-effect transistor described in this disclosure may be considered a "hybrid sheet structure" or a "hybrid nanostructure device".

[0081] In addition, Figure 2In some embodiments, a multilayer stack 52 is formed over a substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layer 54 is formed of a first semiconductor material, and the second semiconductor layer 56 is formed of a second semiconductor material. The semiconductor materials can each be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, and which will be described in more detail later, the first semiconductor layer 54 will be removed and the second semiconductor layer 56 will be patterned to form channel regions for nanostructured field-effect transistors in both the n-type region 50N and the p-type region 50P. In such an embodiment, the channel regions in both the n-type region 50N and the p-type region 50P can have the same material composition (e.g., silicon or another semiconductor material) and can be formed simultaneously. The first semiconductor layer 54 is a dummy layer that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity for etching the second semiconductor layer 56, such as silicon-germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0082] In other embodiments (not shown separately), the first semiconductor layer 54 will be patterned to form a channel region for a nanostructured field-effect transistor in one region (e.g., p-type region 50P), while the second semiconductor layer 56 will be patterned to form a channel region for a nanostructured field-effect transistor in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si). x Ge 1-x The first semiconductor material 56 can be a material suitable for an n-type device, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material 56 can be a material suitable for an n-type device, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first and second semiconductor materials can have high etch selectivity relative to each other, such that the first semiconductor layer 54 can be removed without significantly removing the second semiconductor layer 56 in the n-type region 50N, and the second semiconductor layer 56 can be removed without significantly removing the first semiconductor layer 54 in the p-type region 50P.

[0083] The multilayer stack 52 is illustrated as comprising four first semiconductor layers 54 and four second semiconductor layers 56. It should be understood that the multilayer stack 52 may comprise any number of first semiconductor layers 54 and any number of second semiconductor layers 56. Each layer of the multilayer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes. In some embodiments, some layers of the multilayer stack 52 are formed to be thinner than the other layers of the multilayer stack 52. For example, Figure 2 The bottommost second semiconductor layer 56 (e.g., the second semiconductor layer 56 closest to the substrate 50) is thinner than the uppermost second semiconductor layer 56. Therefore, the bottommost second semiconductor layer 56 can be referred to as the bottom semiconductor layer 56' to distinguish it from the other second semiconductor layers 56. In some cases, the bottom semiconductor layer 56' can be relatively thin to improve short-channel control in the resulting nanostructured field-effect transistor. In some cases, the difference in thickness between the bottom semiconductor layer 56' and the uppermost second semiconductor layer 56 can be about 1 nm or greater. Other combinations or variations in film thickness are also possible.

[0084] exist Figure 3 In some embodiments, protrusions such as fins 62 are formed in the substrate 50, and a first nanostructure 64 and a second nanostructure 66 are formed in the multilayer stack 52. The first nanostructure 64 and the second nanostructure 66 may be collectively referred to as nanostructures 64 / 66 in this disclosure. Figure 3 The lower power region 50L and the higher power region 50H of the substrate 50 are shown. Unless specifically discussed, they may be located in either the n-type region 50N or the p-type region 50P of the substrate 50. Figure 3 The exemplary fins 62 and nanostructures 64 / 66 illustrated for the lower power region 50L and the higher power region 50H may be the same fins 62 and nanostructures 64 / 66 (e.g., they may be continuous structures extending between the lower power region 50L and the higher power region 50H), or the fins 62 and nanostructures 64 / 66 of the lower power region 50L may be separated from or adjacent to the fins 62 and nanostructures 64 / 66 of the higher power region 50H.

[0085] In some embodiments, nanostructures 64 / 66 and fins 62 can be formed in the multilayer stack 52 and the substrate 50, respectively, by etching trenches in the multilayer stack 52 and the substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof. Etching can be anisotropic. The nanostructures 64 / 66 can be formed by etching the multilayer stack 52, and the first nanostructure 64 can be defined from the first semiconductor layer 54, and the second nanostructure 66 can be defined from the second semiconductor layer 56. For example, the bottom semiconductor layer 56' is patterned to form the bottommost second nanostructure 66, which may sometimes be referred to as the second nanostructure 66' or the bottom nanostructure 66' in the description below. Therefore, in some embodiments, the bottom nanostructure 66' can be thinner than the overlying second nanostructure 66. The bottommost first semiconductor layer 54 is patterned to form the bottommost first nanostructure 64, which may sometimes be referred to as the first nanostructure 64' or the bottom nanostructure 64' in the description below. The thickness of the nanostructure may have other combinations or variations.

[0086] The fins 62 and nanostructures 64 / 66 can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fins 62 and nanostructures 64 / 66, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with self-aligned processes to create patterns with, for example, smaller pitches than those obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern the fins 62 and nanostructures 64 / 66.

[0087] Fins 62 are depicted as having substantially equal widths in both the n-type region 50N and the p-type region 50P. In some embodiments, the width of fin 62 in the n-type region 50N may be greater than or less than the width of fin 62 in the p-type region 50P. In some embodiments, the width of fin 62 in the lower power region 50L may be greater than or less than the width of fin 62 in the higher power region 50H. Furthermore, while each of the fins 62 and nanostructures 64 / 66 is depicted as always having a consistent width, in other embodiments, the fins 62 and / or nanostructures 64 / 66 may have tapered sidewalls such that the width of each of the fins 62 and / or nanostructures 64 / 66 continuously increases in the direction toward the substrate 50. In these embodiments, each nanostructure 64 / 66 may have a different width and a trapezoidal shape.

[0088] exist Figure 4 An insulating material 68 is formed over the substrate 50 and between adjacent fins 62 and adjacent nanostructures 64 / 66. The insulating material 68 can be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), similar processes, or combinations thereof. Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material 68 comprises silicon oxide formed by an FCVD process. Once the insulating material 68 is formed, an annealing process can be performed. Although the insulating material 68 is depicted as a single layer, multiple layers can be used in some embodiments. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 62, and nanostructures 64 / 66. Subsequently, a filler material, such as those mentioned above, can be formed over the liner.

[0089] Insulating material 68 can be deposited over fins 62 and nanostructures 64 / 66, such that excess insulating material 68 covers nanostructures 64 / 66. Next, a removal process is applied to the insulating material 68 to remove the excess insulating material 68 over the nanostructures 64 / 66. Planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, or similar processes, can be used. The planarization process exposes the nanostructures 64 / 66, ensuring that the top surfaces of the nanostructures 64 / 66 and the insulating material 68 remain flush after the planarization process is completed.

[0090] exist Figure 5In this process, insulating material 68 is etched to form shallow trench isolation regions 70. The shallow trench isolation regions 70 are adjacent to fins 62. The etching of insulating material 68 causes the upper portions of fins 62 and / or nanostructures 64 / 66 to protrude from between adjacent shallow trench isolation regions 70. The upper portions of fins 62 and / or nanostructures 64 / 66 are located above the shallow trench isolation regions 70. In some cases, multiple portions of fins 62 and / or nanostructures 64 / 66 may be below the top surface of the shallow trench isolation regions 70. Furthermore, the top surface of the shallow trench isolation regions 70 can be a flat surface, a convex surface, a concave surface (such as a dish-shaped surface), or a combination thereof, as shown in the figure. The top surface of the shallow trench isolation regions 70 can be formed into a flat, convex, and / or concave shape by appropriate etching. The shallow trench isolation region 70 can be etched using an acceptable etching process, such as an etching process selective for the material of the insulating material 68 (e.g., etching the material of the insulating material 68 at a faster rate than the fins 62 and the nanostructures 64 / 66). For example, oxide removal can be performed using, for instance, diluted hydrofluoric acid (dHF).

[0091] The process described above is merely one example of how the fins 62 and nanostructures 64 / 66 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 62 and / or nanostructures 64 / 66. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be etched so that the epitaxial structure protrudes from the dielectric layer to form the fins 62 and / or nanostructures 64 / 66. The epitaxial structure can comprise the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially growing the epitaxial structure, the material being epitaxially grown can be in-situ doped during growth. Although in-situ doping and implantation doping can be used together, in-situ doping avoids prior and subsequent implantation.

[0092] In addition, Figure 5In this process, suitable traps (not shown separately) can be formed in fins 62, nanostructures 64 / 66, and / or shallow trench isolation regions 70. In embodiments with different trap types, photoresist or other masks (not shown separately) can be used to implement different placement steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over fins 62, nanostructures 64 / 66, and shallow trench isolation regions 70 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity placement is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being placed into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, with a concentration range of 10 in the region. 13 atoms / cm 3 Up to 10 14 atoms / cm 3 After the photoresist is applied, it is removed using a process such as acceptable ashing.

[0093] Before or after the implantation of the p-type region 50P, photoresist or other masks (not shown separately) are formed over the fins 62, nanostructures 64 / 66, and shallow trench isolation regions 70 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation is performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or the like, with a concentration in the region ranging from 10. 13 atoms / cm 3 Up to 10 14 atoms / cm 3 After the photoresist is applied, it is removed using a process such as an acceptable ashing process.

[0094] After the implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth. Although in-situ doping and implantation doping can be used together, in-situ doping avoids the need for prior and subsequent implantation.

[0095] exist Figure 6 In some embodiments, a protective material 40 is deposited over the shallow trench isolation zone 70. The protective material 40 then forms a protective layer 42 (see [link to relevant documentation]). Figures 7 to 8A protective layer 42 may be formed on some of the top surfaces of the shallow trench isolation region 70. Protective material 40 is deposited above the top surfaces of the shallow trench isolation region 70 and may be deposited above the top surfaces of the nanostructures 64 / 66. Protective material 40 may also be deposited above and along the sidewalls of the fins 62 and / or nanostructures 64 / 66. Therefore, in some cases, protective material 40 may be deposited as a continuous film. Protective material 40 may comprise one or more materials that have high etch selectivity for etching the material of the shallow trench isolation region 70 and / or nanostructures 64 / 66. In some embodiments, protective material 40 may comprise nitrides, such as silicon nitride, silicon oxynitride, silicon carbon oxynitride, or the like. In some embodiments, protective material 40 comprises oxides, such as hafnium oxide, zirconium oxide, or the like. Other materials may also be used, and in some cases, protective material 40 may comprise multiple layers of different materials. The protective material 40 can be deposited using appropriate processes, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), ALD, or similar processes. The deposition process can be conformal. In some cases, multiple portions of the protective material 40 deposited on the sidewall surface can be thinner than multiple portions of the protective material 40 deposited on the transverse surface (e.g., the top surface).

[0096] exist Figure 7 In some embodiments, the upper portion of the protective material 40 is removed to form a protective layer 42. The upper portion of the protective material 40 may include multiple portions on the sidewalls of the fins 62 and / or the sidewalls of the nanostructures 64 / 66, and may include multiple portions on the top surface of the nanostructures 64 / 66. For example... Figure 7 As illustrated, the remaining portion of the protective material 40 on the top surface of the shallow trench isolation region 70 forms a protective layer 42. The upper portion of the protective material 40 can be removed using one or more acceptable etching processes, such as dry etching, wet etching, or a combination thereof. The etching process can be anisotropic. In some cases, the etching process can thin the lateral portions of the protective material 40 forming the protective layer 42. In some cases, the protective layer 42 can be considered a hard mask (e.g., a shallow trench isolation hard mask) or the like.

[0097] The protective layer 42 may cover some sidewall surfaces of the fins 62 and / or nanostructures 64 / 66, such as Figure 7As illustrated. In some cases, the protective layer 42 may completely cover the sidewalls of the bottom nanostructure 64'. In some cases, the top surface of the protective layer 42 may be higher than the top surface of the bottom nanostructure 64' (e.g., farther from the substrate 50). In some cases, the top surface of the protective layer 42 may be higher than the bottom surface of the bottom nanostructure 66' and / or lower than (e.g., closer to the substrate 50) the top surface of the bottom nanostructure 66'. Therefore, in some embodiments, the protective layer 42 may partially or completely cover the sidewalls of the bottom nanostructure 66'. Furthermore, the top surface of the protective layer 42 may have a flat surface, a convex surface, a concave surface (such as a dish-shaped surface), or a combination thereof, as shown.

[0098] exist Figure 8 In some embodiments, the remaining portion of the protective layer 42 in the higher power region 50H is removed. Removal of the protective layer 42 in the higher power region 50H may include depositing a mask layer (not shown) over the lower power region 50L and the higher power region 50H. In some embodiments, the mask layer is a backside anti-reflective coating (BARC) deposited by physical vapor deposition (PVD) or a similar process. In other embodiments, other materials and / or deposition processes may be used. For example, in some embodiments, the mask layer is a photoresist or the like, which can be formed using a spin coating technique. The mask layer is patterned to expose the higher power region 50H. The mask layer can be patterned using acceptable photolithography and etching techniques. The protective layer 42 in the higher power region 50H can be removed using techniques similar to those described above for removing the upper portion of the protective material 40. For example, in some embodiments, anisotropic dry etching can be used.

[0099] In some embodiments, when the protective layer 42 is removed, the shallow trench isolation region 70 in the higher power region 50H may also be etched. Etching may recess multiple portions of the shallow trench isolation region 70 between the fins 62. In some embodiments, in the higher power region 50H, the shallow trench isolation region 70 may be etched such that the top surface of the shallow trench isolation region 70 is lower (e.g., closer to the substrate 50) than the bottom surface of the bottom nanostructure 64', such as... Figure 8 As illustrated. In this manner, the shallow trench isolation region 70 in the higher power etched region 50H can completely expose the sidewalls of the bottom nanostructure 64', as shown. Figure 8As illustrated. The shallow trench isolation region 70 may be etched to a depth less than or greater than illustrated. In other embodiments, the top surface of the recessed shallow trench isolation region 70 in the higher power region 50H may be approximately flush with or higher than the bottom surface of the bottom nanostructure 64'. The top surface of the recessed shallow trench isolation region 70 in the higher power region 50H may be higher than, approximately flush with, or lower than the top surface of the fin 62. Although the top surface of the recessed shallow trench isolation region 70 is illustrated as a flat surface, the top surface may also be concave or convex.

[0100] In other embodiments, the shallow trench isolation region 70 in the higher power region 50H is not significantly etched when the protective layer 42 is removed. Figure 9A An example is illustrated, which is approximately Figure 8 The higher power region 50H is illustrated, but the difference is that the shallow trench isolation region 70 is not etched when the protective layer 42 is removed. In such an embodiment, removing the protective layer 42 in the higher power region 50H exposes at least a portion of the sidewalls of the bottom nanostructure 64'.

[0101] In other embodiments, the protective layer 42 in the higher power region 50H is thinned but not completely removed. Figure 9B An example is illustrated, which is approximately Figure 7 The higher power region 50H is illustrated, but the difference lies in that the protective layer 42 is thinned but still covers the shallow trench isolation region 70. In such an embodiment, the thinned protective layer 42 in the higher power region 50H exposes at least a portion of the sidewalls of the bottom nanostructure 64'. Therefore, the top surface of the thinned protective layer 42 can be lower than the top surface of the bottom nanostructure 64'.

[0102] Figures 10A to 10C yes Figure 8 The diagram following the drawn structure shows that the shallow trench isolation region 70 in the higher power region 50H is etched. Figure 10A The diagram shows the approximation along the path. Figure 1 A schematic diagram of the cross section A-A'. Figure 10B The diagram shows the approximation along the path. Figure 1 A schematic diagram of the cross-section B-B'. Figure 10C The diagram shows the approximation along the path. Figure 1 A schematic diagram of the cross section C-C'.

[0103] exist Figures 10A to 10CIn some embodiments, a dummy dielectric 82, a dummy gate 84, and a mask 86 are formed over the fins 62 and / or nanostructures 64 / 66 and along the sidewalls of the fins 62 and / or nanostructures 64 / 66. In some embodiments, a dummy dielectric layer is formed on the fins 62 and / or nanostructures 64 / 66. The dummy dielectric layer may be formed of silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed over the dummy dielectric layer, and a mask layer is formed over the dummy gate layer. The dummy gate layer may be deposited over the dummy dielectric layer and then planarized by a process such as CMP or a similar process. The dummy gate layer can be formed of a conductive or non-conductive material, and can be selected from the group consisting of amorphous silicon, polycrystalline silicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The material of the dummy gate layer can be deposited by CVD, physical vapor deposition (PVD), sputtering deposition, or other suitable techniques. The dummy gate layer can be formed of other materials with high etch selectivity for etching insulating materials (e.g., shallow trench isolation region 70 and / or dummy dielectric layer). A masking layer can be deposited over the dummy gate layer. The masking layer can be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like.

[0104] Subsequently, the mask layer can be patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 can then be transferred to a dummy gate layer and a dummy dielectric layer to form dummy gates 84 and dummy dielectrics 82, respectively. The dummy gates 84 cover the corresponding channel regions of the nanostructures 64 / 66. The pattern of mask 86 can be used to physically separate each dummy gate 84 from adjacent dummy gates 84. The dummy gates 84 may also have a length direction substantially perpendicular to the length direction of the respective fins 62. Mask 86 can optionally be removed after patterning, such as by any acceptable etching technique.

[0105] In this example, a single dummy gate layer and a single mask layer are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer covers the protective layer 42 in the lower power region 50L and the shallow trench isolation region 70 in the higher power region 50H, such that the dummy dielectric 82 extends between the dummy gate 84 and the protective layer 42 in the lower power region 50L, and between the dummy gate 84 and the shallow trench isolation region 70 in the higher power region 50H. In another embodiment, the dummy dielectric 82 covers only the fins 62 and / or the nanostructures 64 / 66.

[0106] exist Figures 11A to 11C In some embodiments, a spacer layer 90 is compliantly formed over the structure. The spacer layer 90 is formed over the nanostructures 64 / 66, the protective layer 42, and the shallow trench isolation region 70. The spacer layer 90 is also formed on the exposed sidewalls of the mask 86 (if present), the dummy gate 84, the dummy dielectric 82, the nanostructures 64 / 66, and / or the fins 62. The spacer layer 90 may be formed of one or more dielectric materials. Figures 11A to 11C The illustration depicts a spacer layer 90 formed of a single layer of dielectric material, but in other embodiments, the spacer layer 90 may be formed of two or more layers of dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or the like, which may be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar deposition processes. Other insulating materials formed by any acceptable process may also be used. The spacer layer 90 is then etched to form spacers.

[0107] exist Figures 12A to 12C In this process, spacer layer 90 is patterned to form gate spacers 92 and fin spacers 94. Any acceptable etching process, such as dry etching, wet etching, similar processes, or combinations thereof, can be performed to pattern spacer layer 90. The etching can be anisotropic. When spacer layer 90 is etched, spacer layer 90 has multiple portions remaining on the sidewalls of dummy gate 84 (thus forming gate spacers 92) and multiple portions remaining on the sidewalls of fins 62 and / or nanostructures 64 / 66 (thus forming fin spacers 94). After etching, fin spacers 94 and / or gate spacers 92 can have straight sidewalls or can have curved sidewalls. In some embodiments, when patterning spacer layer 90, protective layer 42 and / or shallow trench isolation regions 70 can also be etched. For example, etching can recess multiple portions of protective layer 42 and / or shallow trench isolation regions 70 between fins 62. The gate spacer 92 and / or fin spacer 94 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0108] Furthermore, the placement of lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments with different device types, approximating the placement of a well as previously described, a mask such as a photoresist can be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurity can be placed into the exposed fins 62 and nanostructures 64 / 66 in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist can be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurity can be placed into the exposed fins 62 and nanostructures 64 / 66 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain region can have a range of 10. 15 atoms / cm 3 Up to 10 19 atoms / cm 3 The concentration of impurities. Annealing can be used to repair implant damage and revitalize the implants.

[0109] It should be noted that the above description provides a general overview of the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, and / or similar steps can be performed. Furthermore, n-type and p-type devices can be formed using different structures and steps.

[0110] See still Figures 12A to 12C According to some embodiments, source / drain recesses 96 are patterned in the fins 62, nanostructures 64 / 66, and substrate 50. Epitaxial source / drain regions are then formed in the source / drain recesses 96. The source / drain recesses 96 can extend through the nanostructures 64 / 66 into the substrate 50. In some embodiments, the fins 62 can be etched such that the bottom surface of the source / drain recesses 96 is lower than the top surface of the shallow trench isolation region 70, such as... Figure 12CAs illustrated. In other embodiments, the bottom surface of the source / drain recess 96 is approximately flush with or higher than the top surface of the shallow trench isolation region 70. The source / drain recess 96 can be formed by etching the fins 62, nanostructures 64 / 66, and substrate 50 using anisotropic etching processes such as RIE, NBE, or similar processes. In some embodiments, the gate spacer 92 and the dummy gate 84 cover multiple portions of the fins 62, nanostructures 64 / 66, and substrate 50 during the etching process for forming the source / drain recess 96. Each layer of the nanostructures 64 / 66 and / or fins 62 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the source / drain recess 96 after it has reached the desired depth.

[0111] exist Figures 13A to 13B Next, the remaining portion of the first nanostructure 64 is removed to form an opening 65 in the region between the second nanostructures 66. The remaining portion of the first nanostructure 64 can be removed using an etching process performed via source / drain recesses 96. The etching process can include any acceptable etching process that selectively etches the material of the first nanostructure 64 at a rate faster than the material of the second nanostructure 66 and the fins 62. The etching process can include wet etching and / or dry etching processes, and the etching can be isotropic. For example, when the first nanostructure 64 is formed of, for example, silicon germanium and the second nanostructure 66 is formed of, for example, silicon or silicon carbide, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In other embodiments, the etching process can be a dry etching using fluorine (F2), ammonia (NH3), hydrofluoric acid (HF), chlorine trifluoride (ClF3), XeF3, or the like. In some embodiments, a trimming process (not shown) is performed to reduce the thickness of the exposed portion of the second nanostructure 66 and enlarge the opening 65. After this, the second nanostructure 66 may be referred to as nanostructure 66, and the collection of second nanostructures 66 vertically adjacent above each fin 62 may be referred to as a “stack” of nanostructures 66.

[0112] exist Figures 14A to 15BIn some embodiments, the first nanostructure 64 is replaced with dummy material 71 to form a dummy region 72. In some cases, the dummy material 71 can be considered a sacrificial material or a sacrificial oxide. In some cases, the dummy region 72 can be considered a sacrificial region, a dummy oxide region, a dummy nanostructure, or a disposable oxide interposer (DOI). Replacing the first nanostructure 64 with the dummy region 72 can provide several advantages. For example, in subsequent source / drain formation steps, one or more high-temperature processes may be performed to, for example, activate the dopants in the source / drain regions. When the material of the first nanostructure 64 (e.g., silicon-germanium, or the like) is exposed to high temperatures, germanium mixing and increased roughness may occur at the interface between the first nanostructure 64 and the second nanostructure 66. Such manufacturing defects may degrade the performance of the resulting transistor device. For example, when germanium diffuses into the second nanostructure 66, germanium residue may remain in the channel region of the formed transistor device, negatively impacting the performance of the channel region. By replacing the first nanostructure 64 with an insulating material (e.g., dummy region 72) before a high-temperature process (e.g., source / drain annealing), manufacturing defects can be reduced and device performance can be improved (e.g., increased current drive, reduced capacitance, and improved short-channel effect).

[0113] exist Figures 14A to 14B In some embodiments, dummy material 71 is deposited in the source / drain recesses 96 and the openings 65. The dummy material 71 can be deposited using compliant deposition processes such as CVD, ALD, or similar methods. The dummy material 71 may comprise an insulating material such as silicon oxide or the like, which can be selectively etched from the second nanostructure 66 and the fins 62. Figures 14A to 14B As illustrated, dummy material 71 may fill or overfill opening 65 and may cover the sidewalls of the second nanostructure 66. For example, dummy material 71 fills opening 65 formed by removing bottom nanostructure 64'. Dummy material 71 may cover the top surface of fin 62. In some embodiments, dummy material 71 does not completely fill source / drain recess 96.

[0114] exist Figures 15A to 15BIn this process, dummy material 71 can then be etched to form dummy region 72. The etching can be isotropic or anisotropic. For example, a wet etching process such as diluted HF or the like can be used to etch dummy material 71. In some embodiments, etching is performed until the sidewalls of dummy material 71 are etched beyond the sidewalls of the second nanostructure 66, forming a sidewall recess 97. Therefore, dummy region 72 can have a width smaller than that of the second nanostructure 66. In some cases, the sidewall recess 97 can be considered part of the source / drain recess 96. Although the sidewalls of dummy region 72 within the sidewall recess 97 are depicted as flat, the sidewalls can be concave or convex. The bottommost dummy region 72 (e.g., the dummy region 72 replacing the bottom nanostructure 64') can be referred to herein as bottom dummy region 72' or dummy gate region 72'.

[0115] exist Figures 16A to 16B In some embodiments, an inner spacer 98 is formed in a sidewall recess 97. In other words, the inner spacer 98 is formed on the sidewall of the dummy region 72. As will be described in more detail later, source / drain regions are subsequently formed in source / drain recesses 96, and the first nanostructure 64 is subsequently replaced by a corresponding gate structure. The inner spacer 98 serves as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the inner spacer 98 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes. Figures 16A to 16B As shown in the drawing, Figure 16A In the cross-sectional schematic diagram, the sidewall of the bottom dummy region 72' in the lower power region 50L is completely covered by the inner spacer 98, while Figure 16B In the cross-sectional view, the sidewalls of the bottom dummy region 72' are completely covered by the protective layer 42. In this way, the inner spacer 98 and the protective layer 42 together surround (e.g., enclose) the corresponding bottom dummy region 72' in the lower power region 50L.

[0116] In some embodiments, the inner spacer 98 is formed by compliantly depositing an insulating material in the source / drain recess 96 and in the sidewall recess 97, followed by etching the insulating material. The insulating material may be silicon nitride, silicon oxynitride, or the like. However, any suitable material may be used, such as a low-k material having a dielectric constant (k value) less than about 3.5. The insulating material may be formed by deposition processes such as ALD, CVD, or similar methods. The etching of the insulating material may be anisotropic. For example, the etching process may be dry etching such as RIE, NBE, or similar methods. After etching of the insulating material, the remaining portion of the insulating material within the sidewall recess 97 forms the inner spacer 98. The thickness of the inner spacer 98 may be less than, approximately equal to, or greater than the thickness of the adjacent dummy region 72.

[0117] Although the outer sidewall of the inner spacer 98 is depicted as flush with (e.g., substantially coplanar with) the sidewall of the second nanostructure 66, the outer sidewall of the inner spacer 98 may extend beyond or be recessed from the sidewall of the second nanostructure 66. In other words, the inner spacer 98 may partially fill, completely fill, or overfill the sidewall recess 97. Furthermore, although the sidewall of the inner spacer 98 is... Figure 16A The center is depicted as flat, but the sidewalls of the inner spacer 98 can be concave or convex. As an example, Figure 17A An embodiment is illustrated where the sidewall of the dummy region 72 is concave, the outer sidewall of the inner spacer 98 is concave, and the inner spacer 98 is recessed from the sidewall of the second nanostructure 66. As another example, Figure 17B The illustration shows an embodiment where the sidewalls of the dummy region 72 are concave, the outer sidewalls of the inner spacer 98 are flat, and the inner spacer 98 is flush with the sidewalls of the second nanostructure 66. Other configurations are also possible.

[0118] exist Figures 18A to 18C In some embodiments, epitaxial source / drain regions 100 are formed in the source / drain recesses 96 of the n-type region 50N and in the source / drain recesses 96 of the p-type region 50P. The epitaxial source / drain regions 100 may also be referred to as "source / drain regions 100". For example, the epitaxial source / drain region 100 in the n-type region 50N may be referred to as "n-type source / drain region", and the epitaxial source / drain region 100 in the p-type region 50P may be referred to as "p-type source / drain region". The formation of the n-type epitaxial source / drain region 100 may occur before, after, or simultaneously with the formation of the p-type epitaxial source / drain region 100. The epitaxial source / drain regions 100 may be formed by epitaxial processes such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar processes.

[0119] In some embodiments, a semiconductor layer 100' may be formed in the source / drain recess 96 prior to forming the epitaxial source / drain region 100 in the source / drain recess 96. The semiconductor layer 100' may comprise, for example, undoped silicon or the like. Although the top surface of the semiconductor layer 100' is depicted as flat (e.g., planar), the top surface of the semiconductor layer 100' may be concave or convex. In other embodiments, an insulating layer (not shown) may be deposited in the source / drain recess 96 prior to forming the epitaxial source / drain region 100 in the source / drain recess 96. The top surface of the semiconductor layer 100' may be higher than, approximately flush with, or lower than the top surface of the fin 62. In some embodiments, the semiconductor layer 100' does not physically contact the inner spacers 98. In other embodiments, the semiconductor layer 100' may physically contact some of the sidewalls of the inner spacers 98. In other embodiments, the semiconductor layer 100' may be formed prior to the formation of the inner spacer 98, such that the material of the inner spacer 98 may cover the semiconductor layer 100'. In such an embodiment, the epitaxial source / drain region 100 may be formed on the material of the inner spacer 98, such that the material of the inner spacer 98 is located between the epitaxial source / drain region 100 and the semiconductor layer 100'. In other embodiments, a dielectric material may be deposited on the semiconductor layer 100' in a separate deposition step, such that the dielectric material is located between the epitaxial source / drain region 100 and the semiconductor layer 100'.

[0120] In some embodiments, the epitaxial source / drain region 100 applies stress to the channel region of the second nanostructure 66 within the n-type region 50N and / or the p-type region 50P, thereby improving performance. The epitaxial source / drain region 100 is formed in the source / drain recess 96 such that each dummy gate 84 of the p-type region 50P is disposed between adjacent pairs of the corresponding epitaxial source / drain region 100. In some embodiments, gate spacers 92 are used to separate the epitaxial source / drain region 100 from the dummy gates 84, while inner spacers 98 are used to separate the epitaxial source / drain region 100 from the first nanostructure 64 by an appropriate lateral distance, such that the epitaxial source / drain region 100 is not short-circuited to the gate of the subsequently formed final nanostructure field-effect transistor.

[0121] The epitaxial source / drain region 100 in the n-type region 50N can be formed by covering the p-type region 50P. Next, the n-type epitaxial source / drain region 100 is epitaxially grown in the source / drain groove 96 in the n-type region 50N. The n-type epitaxial source / drain region 100 can contain any acceptable material suitable for n-type nano-FETs. For example, if the second nanostructure 66 is silicon, the n-type epitaxial source / drain region 100 can contain a material that applies tensile strain to the second nanostructure 66, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0122] The epitaxial source / drain region 100 in the p-type region 50P can be formed by covering the n-type region 50N. Next, the p-type epitaxial source / drain region 100 is epitaxially grown in the source / drain groove 96 in the p-type region 50P. The p-type epitaxial source / drain region 100 can contain any acceptable material suitable for p-type nano-FETs. For example, if the second nanostructure 66 is silicon, the p-type epitaxial source / drain region 100 can contain a material that applies compressive strain to the second nanostructure 66, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like.

[0123] The epitaxial source / drain region 100, the second nanostructure 66, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain region can have a size in the range of 1 × 10⁻⁶. 19 atoms / cm 3 Up to 1×10 21 atoms / cm 3 The impurity concentration. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 100 can be doped in situ during growth.

[0124] Due to the epitaxial process used to form the epitaxial source / drain regions 100 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 100 has facets that extend laterally outward beyond the sidewalls of the second nanostructure 66. In some embodiments, adjacent epitaxial source / drain regions 100 remain separated after the epitaxial process is completed, such as... Figure 18C As illustrated. In other embodiments, these facets cause adjacent epitaxial source / drain regions 100 of the same nanostructure field-effect transistor to merge, such as Figure 18D As shown in the drawing. Figure 18C as well as Figure 18DIn the illustrated embodiments, fin spacers 94 may be formed on the top surface of the protective layer 42 or the shallow trench isolation region 70 to prevent epitaxial growth. In some other embodiments, fin spacers 94 may cover multiple portions of the sidewalls of the second nanostructure 66 to further prevent epitaxial growth. In some other embodiments, the spacer etching used to form the fin spacers 94 may be adjusted to remove spacer material and allow the epitaxial growth region to extend to the surface of the protective layer 42 or the shallow trench isolation region 70.

[0125] The n-type epitaxial source / drain region 100 and / or the p-type epitaxial source / drain region 100 may comprise one or more semiconductor material layers. Any number of semiconductor material layers can be used for the epitaxial source / drain region 100. Each semiconductor material layer can be formed of a different semiconductor material and can be doped to different dopant concentrations. In an embodiment where the epitaxial source / drain region 100 comprises three semiconductor material layers, a first semiconductor material layer can be deposited, a second semiconductor material layer can be deposited over the first semiconductor material layer, and a third semiconductor material layer can be deposited over the second semiconductor material layer. In some embodiments, the first semiconductor material layer may have a dopant concentration smaller than that of the second semiconductor material layer and greater than that of the third semiconductor material layer. Other semiconductor material layers, dopant concentrations, or the above-described configurations may also be used.

[0126] exist Figures 19A to 19B In this process, a first interlayer dielectric 104 is deposited over the epitaxial source / drain region 100, fin spacers 94, gate spacers 92, mask 86 (if present), and / or dummy gate 84. The first interlayer dielectric 104 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials may include silicon oxide, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may also be used.

[0127] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first interlayer dielectric 104 and the epitaxial source / drain region 100, fin spacer 94, gate spacer 92, mask 86 (if present), and / or dummy gate 84. The contact etch stop layer 102 may be formed of a dielectric material with high etch selectivity for etching the first interlayer dielectric 104, such as silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or the like, and may be formed using any suitable deposition process, such as CVD, ALD, or similar processes.

[0128] exist Figures 20A to 20B In this process, a removal process is performed to make the top surface of the first interlayer dielectric 104 flush with the top surface of the gate spacer 92 and the mask 86 (if present) or dummy gate 84. In some embodiments, the removal process includes a planarization process, such as chemical mechanical polishing (CMP), polishing, etch-back, a combination of the above, or similar processes. After the planarization process, the top surfaces of the first interlayer dielectric 104, the gate spacer 92, the mask 86 (if present), and / or the dummy gate 84 may be substantially flush or coplanar (within process variations). Thus, the top surface of the mask 86 (if present) or the dummy gate 84 can be exposed through the first interlayer dielectric 104. In some embodiments, the planarization process removes the mask 86 and multiple portions of the gate spacer 92 along the sidewalls of the mask 86. In such an embodiment, after the planarization process, the top surfaces of the first interlayer dielectric 104, the gate spacer 92, and the dummy gate 84 can be substantially flush or coplanar (within process variations).

[0129] exist Figures 21A to 21B In one or more etching steps, the mask 86 (if present) and the dummy gate 84 are removed, such that a groove 108 is formed between the gate spacers 92. In some embodiments, the dummy gate 84 and the dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (multiple) reactive gases, which selectively etches the material of the dummy gate 84 at a faster rate than the material of the first interlayer dielectric 104 and the gate spacers 92. Each groove 108 exposes and / or covers multiple portions of the second nanostructure 66, which serves as a channel region in the subsequently completed nanostructured field-effect transistor. The multiple portions of the second nanostructure 66 serving as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 100. During removal, the dummy dielectric 82 may be used as an etch stop layer as the dummy gate 84 is etched. After the dummy gate 84 is removed, the dummy dielectric 82 may then be removed.

[0130] exist Figures 22A to 22B In the process, dummy region 72 is removed, and recess 108 is extended. The bottom dummy region 72' in the lower power region 50L is not removed and forms dummy gate region 73, which will be described in more detail below. Removing dummy region 72 may involve performing an isotropic etching process such as wet etching or similar etching. The etching process may use an etchant that is selective to the material of dummy region 72, while the second nanostructure 66 remains relatively unetched relative to dummy region 72. Dummy region 72 may be removed completely, or a residue of dummy region 72 may remain on some sidewall portions of the inner spacer 98 in recess 108 (see, for example...). Figure 24 ).

[0131] In some embodiments, the shallow trench isolation region 70 in the higher power region 50H can be etched while removing the dummy region 72, but the total loss in the shallow trench isolation region 70 can be reduced by controlling the etching parameters (e.g., timing) during the removal of the dummy region 72. The protective layer 42 in the lower power region 50L can protect the shallow trench isolation region 70 from etching during the removal of the dummy region 72. In embodiments where the protective layer 42 remains above the shallow trench isolation region 70 in the higher power region 50H (e.g., in...), Figure 9B In the middle), the shallow trench isolation region 70 in the higher power region 50H can be protected from etching by the protective layer 42.

[0132] As previously described, the sidewalls of the bottom dummy region 72' in the lower power region 50L are covered by the inner spacer 98 and the protective layer 42. The top surface of the bottom dummy region 72' is covered by the bottom nanostructure 66', while the bottom surface of the bottom dummy region 72' is covered by the top surface of the fin 62. Therefore, the bottom dummy region 72' in the lower power region 50L is protected from the etching process that removes the overlying dummy region 72. The protective layer 42 in the higher power region 50H is removed or thinned to expose the bottom nanostructure 64' (see...). Figures 8 to 9B This allows for the subsequent removal of the bottom dummy region 72' in the higher power region 50H. In this way, the etching process removes the dummy region 72' containing the bottom dummy region 72' in the higher power region 50H, but does not remove the bottom dummy region 72' in the lower power region 50L. The remaining bottom dummy region 72' in the lower power region 50L is subsequently referred to as the dummy gate region 73. In some cases, the dummy gate region 73 can be identified as a bottom channel oxide region, a dummy nanostructure, an isolation region, or the like. The dummy gate region 73 covers the bottom surface of the bottom nanostructure 66' in the lower power region 50L, and therefore the bottom channel region of the bottom nanostructure 66' is not controlled by the gate structure below in the subsequently formed nanostructure field-effect transistor, as will be described in more detail below.

[0133] exist Figures 23A to 23BIn this process, a gate dielectric layer 110 and a gate electrode 112 are formed to replace the gate structure. The gate dielectric layer 110 is compliantly deposited in the trench 108. The gate dielectric layer 110 can be formed on the top surface and sidewalls of the substrate 50, and on the exposed top surface, sidewalls, and bottom surface of the second nanostructure 66. However, the dummy gate region 73 prevents the gate dielectric layer 110 from forming on the bottom surface of the bottom nanostructure 66' in the lower power region 50L. The gate dielectric layer 110 can also be deposited on the top surface of the first interlayer dielectric 104, the contact etch stop layer 102, the gate spacer 92, the protective layer 42, and / or the shallow trench isolation region 70. Since the dummy gate region 73 is completely covered, the gate dielectric layer 110 is not formed on the dummy gate region 73 and does not physically contact the dummy gate region 73. In some cases, the bottom surface of the dummy gate region 73 in the lower power region 50L can be approximately flush with the bottom surface of the gate structure in the higher power region 50H.

[0134] According to some embodiments, the gate dielectric layer 110 comprises one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layer 110 may comprise a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 110 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 110 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 110 in the n-type region 50N and the p-type region 50P may be the same or different. The method of forming the gate dielectric layer 110 may include molecular beam deposition (MBD), ALD, PECVD, and similar processes.

[0135] Gate electrodes 112 are deposited above the gate dielectric layer 110 and fill the remaining portion of the trench 108. Gate electrodes 112 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although... Figures 23A to 23B The diagram illustrates a single-layer gate electrode 112, but the gate electrode 112 may include any number of substrates, any number of work function adjustment layers, and filler material. Any combination of films constituting the gate electrode 112 may be deposited between adjacent second nanostructures 66 in the lower power region 50L and the higher power region 50H, and between the bottom nanostructure 66' and the fin 62 in the higher power region 50H.

[0136] The formation of the gate dielectric layer 110 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 110 in each region is formed of the same material, and the formation of the gate electrode 112 can occur simultaneously, such that the gate electrode 112 in each region is formed of the same material. In some embodiments, the gate dielectric layer 110 in each region can be formed by different processes, such that the gate dielectric layer 110 in each region can be made of different materials and / or have different numbers of layers, and / or the gate electrode 112 in each region can be formed by different processes, such that the gate electrode 112 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to cover and expose appropriate areas.

[0137] After filling the recess 108, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 110 and the gate electrode 112, which lies above the top surface of the first interlayer dielectric 104. The remaining material of the gate electrode 112 and the gate dielectric layer 110 thus forms the replacement gate structure for the final nanostructure field-effect transistor. The gate electrode 112 and the gate dielectric layer 110 can be collectively referred to as the gate structure or gate stack.

[0138] In the lower power region 50L, due to the presence of the dummy gate region 73, the bottommost gate structure below the bottom nanostructure 66' is not formed. In other words, only the upper portion of the bottom nanostructure 66' in the lower power region 50L is covered by the gate structure. Because the bottom nanostructure 66' in the higher power region 50H is completely surrounded by the gate structure, while the bottom nanostructure 66' in the lower power region 50L is only partially covered by the gate structure, the bottom nanostructure 66' in the higher power region 50H provides more on-current than the bottom nanostructure 66' in the lower power region 50L. Therefore, the nanostructure field-effect transistor in the lower power region 50L is a lower power (e.g., lower current) device compared to the nanostructure field-effect transistor in the higher power region 50H. In this way, both the higher power nanostructure field-effect transistor and the lower power nanostructure field-effect transistor can be formed in different regions on the same substrate with only minor changes to the existing process flow. Furthermore, the use of a dummy gate region 73 in the lower power region 50L allows for the formation of a lower power nanostructure field-effect transistor with reduced parasitic capacitance and improved alternating current (AC) performance.

[0139] In some cases, because only the upper portion of the bottom nanostructure 66' in the lower power region 50L is covered by the gate structure, the bottom nanostructure 66' in the lower power region 50L can be referred to as a "half-nanostructure." Therefore, Figures 23A to 23B The nanostructured field-effect transistor in the higher power region 50H can be identified as a stack of nanostructures containing four nanostructures, but Figures 23A to 23B The nanostructured field-effect transistor in the lower power region 50L can be considered as having a nanostructure stack containing 3.5 nanostructures. The technique described in this disclosure allows for the formation of nanostructured field-effect transistors, which can have any suitable number of nanostructures in the nanostructure stack. For example, a higher power nanostructured field-effect transistor can have 2 or 3 nanostructures in the nanostructure stack, while the corresponding lower power nanostructured field-effect transistor has 1.5 or 2.5 nanostructures in the nanostructure stack, respectively. Other numbers of nanostructures can also be present in the nanostructure stack. It should be noted that the number of nanostructures in the nanostructure stack (e.g., 1.5, 2, 3.5, 4, or similar numbers) can be substantially proportional to or disproportionate to the on-current generated by the corresponding nanostructured field-effect transistor.

[0140] Figure 24 draw Figure 23A Detailed schematic diagrams of various components, including epitaxial source / drain regions 100, gate dielectric layer 110, gate electrode 112, second nanostructure 66, and internal spacers 98. Figure 24 The schematic diagram may be an enlarged schematic diagram of a portion of a nanostructured field-effect transistor in any one of the n-type region 50N, p-type region 50P, lower power region 50L, or higher power region 50H. In some embodiments, such as Figure 24 As illustrated, residues of dummy material 71 may remain on the inner spacer 98, such as between the inner spacer 98 and the gate dielectric layer 110. For example, the dummy region 72 may not be completely removed, and the gate dielectric layer 110 may be formed on the remaining dummy material 71 in the dummy region 72. Because the dummy material 71 is an insulating material (e.g., silicon oxide or the like), the remaining residue may not have a significant impact on the electrical performance of the final device.

[0141] exist Figures 25A to 25CIn some embodiments, a second interlayer dielectric 116 is deposited over the gate spacer 92, the contact etch stop layer 102, the first interlayer dielectric 104, the gate dielectric layer 110, and the gate electrode 112. In some embodiments, the second interlayer dielectric 116 is a flowable thin film formed by a flowable CVD method. In some embodiments, the second interlayer dielectric 116 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, which can be formed by any suitable deposition process such as CVD, PECVD, or similar methods.

[0142] In some embodiments, an etch stop layer (ESL) 114 is formed between the second interlayer dielectric 116 and the gate spacer 92, the contact etch stop layer 102, the first interlayer dielectric 104, the gate dielectric layer 110, and the gate electrode 112. The etch stop layer 114 may be formed of a dielectric material that has high etch selectivity for etching the second interlayer dielectric 116, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by any suitable deposition process, such as CVD, ALD, or similar processes.

[0143] In other embodiments, the gate structure (including the gate dielectric layer 110 and the corresponding overlying gate electrode 112) is etched to form a groove directly above the gate structure and between the two sides of the gate spacer 92. A gate mask (not shown separately) comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, may be filled in the groove, followed by a planarization process to remove excess dielectric material extending above the first interlayer dielectric 104. Gate contacts (such as gate contact 126, which will be matched below) are then formed. Figures 26A to 26C (Discussion) Penetrates through the gate shield to contact the top surface of the recessed gate electrode 112.

[0144] exist Figures 26A to 26C In this configuration, a gate contact 126 and a source / drain contact 128 are formed to contact the gate electrode 112 and the epitaxial source / drain region 100, respectively. The gate contact 126 can be physically and electrically coupled to the gate electrode 112. The source / drain contact 128 can be physically and electrically coupled to the epitaxial source / drain region 100.

[0145] As an example of forming the gate contact 126 and the source / drain contact 128, an opening for the gate contact 126 is formed through the second interlayer dielectric 116 and the etch stop layer 114, and an opening for the source / drain contact 128 is formed through the second interlayer dielectric 116, the etch stop layer 114, the first interlayer dielectric 104, and the contact etch stop layer 102. The openings can be formed using acceptable photolithography and etching techniques. A diffusion barrier layer, an adhesive layer, or similar substrate (not shown separately) and conductive material are formed in the openings. The substrate may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP can be performed to remove excess material from the surface of the second interlayer dielectric 116. The remaining substrate and conductive material form the gate contact 126 and the source / drain contact 128 in the openings. The gate contact 126 and the source / drain contact 128 can be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 126 and the source / drain contact 128 can be formed in different cross-sections, which can prevent short circuits in the contacts.

[0146] Optionally, a metal-semiconductor alloy region 129 is formed at the interface between the epitaxial source / drain region 100 and the source / drain contact 128. The metal-semiconductor alloy region 129 may be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanide region formed from both metal silicides and metal germanides, or a similar region. The metal-semiconductor alloy region 129 can be formed before the material of the source / drain contact 128 by depositing metal into the opening of the source / drain contact 128 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the epitaxial source / drain region 100 (e.g., silicon, silicon carbide, silicon-germanium, germanium, etc.) to form a low-resistivity metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be formed by deposition processes such as ALD, CVD, PVD, or similar methods. After a thermal annealing process, a cleaning process such as wet cleaning can be performed to remove any residual metal from the openings in the source / drain contact 128 (e.g., from the surface of the metal-semiconductor alloy region 129). The material of the source / drain contact(s) 128 can then be formed on the metal-semiconductor alloy region 129.

[0147] Several advantages can be achieved through these embodiments. The techniques described in this disclosure allow for the formation of both low-power and high-power nanostructure field-effect transistors (FETs) on the same substrate (e.g., on the same wafer). The techniques described in this disclosure allow for the formation of both low-power and high-power nanostructure FETs within the same wafer or die without the need for expensive or time-consuming small-die packaging processes. The techniques described in this disclosure can form “hybrid nanostructure” devices comprising both relatively low-power and relatively high-power nanostructure FETs. The techniques described in this disclosure can use more reliable process flows and require fewer additional process steps to form hybrid nanostructure devices. The low-power nanostructure FETs described in this disclosure include an insulated dummy gate structure that at least partially covers the channel region of the nanostructure. This allows for the formation of low-power nanostructures with smaller parasitic capacitances, which can improve the speed and AC performance of the corresponding nanostructure FETs. For example, higher-power nanostructure FETs can be used in higher-power or high-performance applications, while lower-power nanostructure FETs can be used in lower-power or high-speed applications. Other applications, devices, or configurations are also possible.

[0148] In embodiments of this disclosure, a semiconductor device includes a first semiconductor fin and a second semiconductor fin; a first nanostructure above the first semiconductor fin; a second nanostructure above the second semiconductor fin; a dummy region extending between the bottom surfaces of the first semiconductor fin and the first nanostructure; and a gate structure located on the top surface of the first nanostructure and on the top surface of the second nanostructure, extending between the bottom surfaces of the second semiconductor fin and the second nanostructure. In embodiments, the dummy region comprises an oxide material. In embodiments, the dummy region is not in physical contact with the gate structure. In embodiments, the semiconductor device further includes an isolation region surrounding the first semiconductor fin; and a protective layer on the isolation region, wherein the protective layer extends along the sidewalls of the dummy region and along the sidewalls of the first nanostructure. In embodiments, the sidewalls of the second nanostructure are not in physical contact with the protective layer. In embodiments, the gate structure extends on the top surface of the protective layer. In embodiments, the semiconductor device further includes a source / drain region in the first semiconductor fin, wherein the bottom surface of the source / drain region is lower than the top surface of the dummy region. In one embodiment, the semiconductor device further includes a gate spacer on the first semiconductor fin, wherein the gate spacer extends along the sidewall of the dummy region.

[0149] In embodiments of this disclosure, a semiconductor device includes a first fin and a second fin above a semiconductor substrate; a plurality of first nanostructures above the first fin; a plurality of second nanostructures above the second fin; a dielectric region above the first fin, wherein the dielectric region separates the first nanostructures from the first fin; a first gate structure above the first fin, wherein the first gate structure separates adjacent first nanostructures; and a second gate structure above the second fin, wherein the second gate structure separates the second nanostructures from the second fin, wherein the second gate structure separates adjacent second nanostructures. In embodiments, the semiconductor device further includes a first shallow trench isolation region surrounding the first fin; a second shallow trench isolation region surrounding the second fin; and a first hard mask on the first shallow trench isolation region. In embodiments, the semiconductor device further includes a second hard mask on the second shallow trench isolation region, wherein the thickness of the second hard mask is less than that of the first hard mask. In embodiments, the first hard mask comprises a nitride material. In one embodiment, the top surface of the second shallow trench isolation region is closer to the semiconductor substrate than the top surface of the first shallow trench isolation region. In another embodiment, the bottom surface of the lowest first nanostructure is not in physical contact with the first gate structure. In another embodiment, the number of first nanostructures is the same as the number of second nanostructures. In yet another embodiment, the bottom surface of the second gate structure is closer to the semiconductor substrate than the bottom surface of the first gate structure.

[0150] In embodiments of this disclosure, a method of forming a semiconductor device includes forming a first fin and a second fin over a semiconductor substrate; forming a plurality of first nanostructures over the first fin and forming a plurality of second nanostructures over the second fin; depositing a dielectric material on the first fin, the second fin, the first nanostructures, and the second nanostructures; etching the dielectric material to form a first dummy gate region on the first fin, a second dummy gate region on the second fin, a plurality of first dummy nanostructures between the first nanostructures, and a plurality of second dummy nanostructures between the second nanostructures; performing an etching process to remove the first dummy nanostructures, the second dummy nanostructures, and the second dummy gate region, wherein the first dummy gate region remains on the first fin after the etching process; and depositing a plurality of gate structure layers on the second fin, the first nanostructures, and the second nanostructures. In embodiments, the method of forming a semiconductor device further includes forming a first isolation region around the first fin and forming a second isolation region around the second fin; forming a protective layer on the first isolation region and on the second isolation region; and removing the protective layer from the second isolation region. In one embodiment, the method of forming a semiconductor device further includes forming a plurality of gate spacers on the sidewalls of a first dummy gate region. In another embodiment, the first dummy gate region covers the bottom surface of one of the first nanostructures.

[0151] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of this utility model. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this utility model to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the concept and scope of this utility model, and various changes, substitutions, and replacements can be made without departing from the concept and scope of this utility model. Therefore, the scope of protection of this utility model shall be determined by the claims.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor fin and a second semiconductor fin; A first nanostructure is located above the first semiconductor fin; A second nanostructure is located above the second semiconductor fin; A dummy region extends between the first semiconductor fin and the bottom surface of the first nanostructure; as well as A gate structure is located on the top surface of the first nanostructure and on the top surface of the second nanostructure, and extends between the second semiconductor fin and the bottom surface of the second nanostructure.

2. The semiconductor device as claimed in claim 1, characterized in that, The dummy region is not in physical contact with the gate structure.

3. The semiconductor device as claimed in claim 1 or claim 2, characterized in that, Also includes: An isolation zone surrounds the first semiconductor fin; as well as A protective layer is provided on the isolation region, wherein the protective layer extends along the sidewall of the dummy region and along the sidewall of the first nanostructure, wherein the sidewall of the second nanostructure is not in physical contact with the protective layer, and wherein the gate structure extends on the top surface of the protective layer.

4. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A source / drain region is provided in the first semiconductor fin, wherein the bottom surface of the source / drain region is lower than the top surface of the dummy region.

5. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A gate spacer is provided on the first semiconductor fin, wherein the gate spacer extends along the sidewall of the dummy region.

6. A semiconductor device, characterized in that, include: A first fin and a second fin are positioned above a semiconductor substrate; Multiple first nanostructures are located above the first fin; Multiple second nanostructures are located above the second fin; A dielectric region is located above the first fin, wherein the dielectric region separates the plurality of first nanostructures from the first fin; A first gate structure is located above the first fin, wherein the first gate structure separates adjacent pairs of the plurality of first nanostructures; and A second gate structure is provided above the second fin, wherein the second gate structure separates the plurality of second nanostructures from the second fin, and wherein the second gate structure separates adjacent pairs of the plurality of second nanostructures.

7. The semiconductor device as claimed in claim 6, characterized in that, Also includes: A first shallow trench isolation zone surrounds the first fin; A second shallow groove isolation zone surrounds the second fin; A first hard shield is placed on the first shallow trench isolation area; as well as A second hard mask is provided on the second shallow trench isolation region, wherein the thickness of the second hard mask is less than that of the first hard mask, and wherein the top surface of the second shallow trench isolation region is closer to the semiconductor substrate than the top surface of the first shallow trench isolation region.

8. The semiconductor device as claimed in claim 6, characterized in that, The bottom surface of the lowest first nanostructure among the plurality of first nanostructures is not in physical contact with the first gate structure.

9. The semiconductor device as claimed in claim 6, characterized in that, The number of the plurality of first nanostructures is the same as the number of the plurality of second nanostructures.

10. The semiconductor device as claimed in claim 6, characterized in that, The bottom surface of the second gate structure is closer to the semiconductor substrate than the bottom surface of the first gate structure.

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