Semiconductor device

Abstract

A semiconductor device includes first and second nanostructures on a substrate; a source / drain region between a first sidewall of the first nanostructure and a second sidewall of the second nanostructure; a gate dielectric layer between an upper surface of the first nanostructure and a lower surface of the second nanostructure; a gate between the first and second nanostructures in a cross-sectional view; and an inner spacer between the first nanostructure, the second nanostructure, the source / drain region, and the gate dielectric layer in the cross-sectional view, and the inner spacer includes a first inner spacer layer between the first nanostructure, the second nanostructure, the source / drain region, and the gate dielectric layer, and a second inner spacer layer between the source / drain region and the first inner spacer layer.

Description

Technical Field

[0001] This utility model relates to semiconductor devices, and more particularly to semiconductor devices with reduced gaps in the inner spacers. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce minimum structural dimensions to improve the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, or the like, in order to integrate more components into a given area. However, as the minimum structural dimensions decrease, additional problems arise that need to be addressed. Utility Model Content

[0004] In one embodiment, the semiconductor device is characterized by including a first nanostructure and a second nanostructure located on a substrate; a source / drain region sandwiched between a first sidewall of the first nanostructure and a second sidewall of the second nanostructure; a gate dielectric layer sandwiched between an upper surface of the first nanostructure and a lower surface of the second nanostructure, with the upper surface of the first nanostructure facing the lower surface of the second nanostructure; a gate located between the first nanostructure and the second nanostructure in a cross-sectional view; and an inner spacer located between the first nanostructure, the second nanostructure, the source / drain region, and the gate dielectric layer in a cross-sectional view, wherein the inner spacer includes: a first inner spacer layer located between the first nanostructure, the second nanostructure, the source / drain region, and the gate dielectric layer; and a second inner spacer layer located between the source / drain region and the first inner spacer layer.

[0005] In one embodiment, the semiconductor device further includes a first oxide material that physically contacts the first nanostructure, the first inner spacer layer, and the gate dielectric layer; and a second oxide material that physically contacts the second nanostructure, the first inner spacer layer, and the gate dielectric layer.

[0006] In one embodiment, the second inner spacer layer is completely defined by the source / drain region and the first inner spacer layer in a cross-sectional view.

[0007] In one embodiment, the first inner spacer layer includes a gap extending from the first inner spacer layer toward the gate dielectric layer and the gate.

[0008] In one embodiment, the inner spacer does not contain gaps.

[0009] In one embodiment, the semiconductor device is characterized by comprising: a first nanostructure located on a substrate; a second nanostructure located on the first nanostructure; a gate and a gate dielectric layer located between the first nanostructure and the second nanostructure; a first inner spacer layer located between the first nanostructure and the second nanostructure, and the first inner spacer layer is located between the gate dielectric layers, wherein a first sidewall of the first inner spacer layer is flush with a sidewall of the first nanostructure, and a second sidewall of the first inner spacer layer is flush with a sidewall of the second nanostructure; a second inner spacer layer located between the first nanostructure and the second nanostructure, wherein a third sidewall of the second inner spacer layer is flush with both the first and second sidewalls; and a source / drain region located on the substrate, wherein the source / drain region is adjacent to the first nanostructure, the second nanostructure, the first inner spacer layer, and the second inner spacer layer.

[0010] In one embodiment, the first inner spacer layer includes a slit, wherein a first end of the slit is located at the interface between the first inner spacer layer and the second inner spacer layer, and a second end of the slit is located in the matrix portion of the first inner spacer layer.

[0011] In one embodiment, the first inner spacer layer is U-shaped in a cross-sectional view, wherein the second inner spacer layer is located within the U-shape in the cross-sectional view, and wherein the second inner spacer layer is triangular in the cross-sectional view.

[0012] In one embodiment, the semiconductor device further includes a first oxide material that physically contacts the first nanostructure, the first inner spacer layer, and the gate dielectric layer; and a second oxide material that physically contacts the second nanostructure, the first inner spacer layer, and the gate dielectric layer.

[0013] In one embodiment, the first inner spacer layer has no gaps. Attached Figure Description

[0014] Figure 1 These are three-dimensional diagrams of nanostructured field-effect transistors in some embodiments.

[0015] Figure 2 , Figure 3 , Figure 4 , Figure 5A and 5B , Figure 6A and 6B , Figures 7A to 7C , Figure 8A and 8B , Figures 9A to 9D , Figures 10A to 10D , Figures 11A to 11D , Figures 12A to 12D , Figures 13A to 13H , Figures 14A to 14F , Figure 15A and 15B, Figure 16A and 16B , Figures 17A to 17D , Figures 18A to 18D , Figures 19A to 19C , Figures 20A to 20C ,and Figures 21A to 21C These are various figures illustrating intermediate steps in the fabrication of nanostructured field-effect transistors in some embodiments.

[0016] The reference numerals in the attached figures are explained as follows:

[0017] A-A', B-B', C-C': Cross-section

[0018] D1, D2, D3: Depth

[0019] T1, T2, T3: Thickness

[0020] 20: Divider

[0021] 50: Substrate

[0022] 50N: n-type region

[0023] 50P: p-type area

[0024] 51, 51A, 51B, 51C: First semiconductor layer

[0025] 52, 52A, 52B, 52C: First Nanostructures

[0026] 53, 53A, 53B, 53C: Second semiconductor layer

[0027] 54, 54A, 54B, 54C: Second nanostructures

[0028] 55: Nanostructures

[0029] 56: Hard mask

[0030] 58: Trench

[0031] 64: Multi-layer stacking

[0032] 66: Fins

[0033] 68: Shallow trench isolation zone

[0034] 70: Dummy gate dielectric layer

[0035] 71: Sacrificial Material Layer

[0036] 72: Sacrificial Materials

[0037] 72': Residue of sacrificial material

[0038] 76: Dummy Gate

[0039] 78: Mask

[0040] 81: Gate spacer

[0041] 83: Fin-shaped spacers

[0042] 86: First Depression

[0043] 87,87': Depression

[0044] 90: Inner spacer

[0045] 90A: First inner spacer layer

[0046] 90B: Second inner spacer layer

[0047] 90M: Gap

[0048] 92: Source / Drain Region

[0049] 92A: First semiconductor material layer

[0050] 92B: Second semiconductor material layer

[0051] 92C: Third semiconductor material layer

[0052] 94: Contact Etching Stop Layer

[0053] 96: First interlayer dielectric layer

[0054] 98: Second depression

[0055] 100: Gate dielectric layer

[0056] 102: Gate

[0057] 104: Gate mask

[0058] 106: Second interlayer dielectric layer

[0059] 108: Third Depression

[0060] 110: Silicide region

[0061] 112,114: Contact Detailed Implementation

[0062] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity.

[0063] The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the present invention. For example, a description of forming a first component on a second component includes direct contact between the two, or the two being spaced apart by other additional components rather than in direct contact. Furthermore, various embodiments of the present invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0064] In addition, spatial relative terms such as “below,” “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures and another element or structure in the accompanying drawings. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0065] The following embodiments are specifically illustrated using a die containing a nanostructured field-effect transistor. However, various embodiments can be used in dies containing other types of transistors (such as stacked transistors or the like) to replace or combine with nanostructured field-effect transistors.

[0066] In various embodiments, the fabrication method of a nanostructured field-effect transistor involves forming a stack of layers (such as semiconductor layers) on a semiconductor substrate and patterning the stack into a nanostructure. Some nanostructures include a semiconductor layer that serves as a channel region (such as a nanostructured channel region) for the nanostructured field-effect transistor, while other nanostructures include sacrificial material (such as an additional semiconductor layer or oxide layer) that is subsequently removed and replaced as a gate structure. Before removing the sacrificial material, it is recessed from the sidewalls of the nanostructured channel. A first inner spacer layer is deposited, portions of the first inner spacer layer are etched, a second inner spacer layer is deposited, and portions of the first and second inner spacer layers are etched to form inner spacers in these recesses. The composition, deposition process, and shape of the first and second inner spacer layers are selected to eliminate or reduce gaps in the inner spacers, thereby improving the integrity and function of the inner spacers. Source / drain regions are then epitaxially grown on the sidewalls of the nanostructured channel, so that the source / drain regions ultimately extend onto the inner spacers. The sacrificial material is then replaced with a gate structure (such as one or more gate dielectric layers and a gate) to form a nanostructured field-effect transistor. The embodiments described herein can provide fabrication yield and functionality of nanostructured field-effect transistors, and improve their reliability and performance.

[0067] Figure 1These are three-dimensional images of nanostructured field-effect transistors (such as nanowire field-effect transistors, nanosheet field-effect transistors, or the like) in some embodiments. Figure 1 Some structures are simplified and / or omitted to simplify the figures. The nanostructured field-effect transistor includes a second nanostructure 54 (such as a nanosheet, nanowire, or the like) situated on a fin 66 on a substrate 50 (such as a semiconductor substrate), wherein the second nanostructure 54 serves as a channel region for the nanostructured field-effect transistor. The second nanostructure 54 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. A shallow trench isolation region 68 (also considered a shallow trench isolation structure) is located between adjacent fins 66, and may protrude above the shallow trench isolation regions 68 from between adjacent shallow trench isolation regions 68. Although the shallow trench isolation region 68 is described separately from the substrate 50 in the figures, the term "substrate" as used herein may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom of the fin 66 in the figures is a single continuous material with the substrate 50, the bottom of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this description, fin 66 is considered as the portion extending between adjacent shallow trench isolation zones 68.

[0068] The gate dielectric layer 100 is located on the upper surface of the fin 66 and extends along the upper surface, sidewalls, and lower surface of the second nanostructure 54. The gate 102 is located on the gate dielectric layer 100. Epitaxial source / drain regions 92 are located on the fins 66 on both sides of the gate dielectric layer 100 and the gate 102. The source / drain regions 92 can be considered as sources or drains independently or together, depending on their configuration.

[0069] Figure 1 The reference cross-sections used in the following figures are also shown. Cross-section A-A' is along the longitudinal axis of the gate 102 and perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the fin 66 of the nanostructured field-effect transistor, and lies within the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross-section C-C' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions of the nanostructured field-effect transistor. The following figures will be based on these reference cross-sections for clarity.

[0070] Some embodiments described herein are illustrated using nanostructured field-effect transistors formed using a post-gate fabrication process. In other embodiments, a gate-first fabrication process may be used. Furthermore, some embodiments can be used for planar devices (such as planar field-effect transistors) or fin field-effect transistors.

[0071] Figures 2 to 21C This is a cross-sectional view of an intermediate stage in the fabrication of nanostructured field-effect transistors in some embodiments. Figures 2 to 4 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A ,and Figure 21A yes Figure 1 The sectional view shown is a section A-A'. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figures 9B to 9D , Figures 10B to 10D , Figures 11B to 11D , Figures 12B to 12D , Figures 13B to 13H , Figures 14B to 14D , Figure 15B , Figure 16B , Figures 17B to 17D , Figures 18B to 18D , Figure 19B , Figure 20B ,and Figure 21B yes Figure 1 The sectional view shown is a section B-B'. Figure 7C , Figure 14E , Figure 14F , Figure 19C , Figure 20C ,and Figure 21C yes Figure 1 The cross-sectional view shown is a section C-C'.

[0072] also, Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 17D ,and Figure 18D In these embodiments, some units have adjusted shapes and / or sizes due to the practicality of the corresponding process steps (as is actually the case). For simplicity and clarity, these embodiments may be considered as actual embodiments. For example, the accompanying drawings of actual embodiments may indicate areas where some units may have roundness or curvature after being formed or modified by subsequent processes (or other significant differences from other drawings of the corresponding process steps). Furthermore, these drawings may be continuous with each other, so subsequent drawings may each be actually influenced by previous drawings.

[0073] exist Figure 2In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a substrate semiconductor, a semiconductor-on-insulator (SIA) substrate, or the like, and may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, a SIA substrate has a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. The insulating layer is provided on the substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium), or combinations thereof.

[0074] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices such as n-type metal-oxide-semiconductor transistors (e.g., n-type nanostructure field-effect transistors), while the p-type region 50P can be used to form p-type devices such as p-type metal-oxide-semiconductor transistors (e.g., p-type nanostructure field-effect transistors). The n-type region 50N and the p-type region 50P can be physically separated (e.g., separated by the illustrated separator 20), and any number of device structures (e.g., other active devices, doped regions, isolation structures, or the like) can be located between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P can be provided. The process steps in the following figures can be performed in either the n-type region 50N or the p-type region 50P, unless otherwise stated.

[0075] like Figure 2 As shown, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes interleaved first semiconductor layers 51A to 51C (collectively considered as first semiconductor layer 51) and second semiconductor layers 53A to 53C (collectively considered as second semiconductor layer 53). For illustrative purposes, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions of nanostructured field-effect transistors in the n-type region 50N and the p-type region 50P, as detailed below. However, in some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions of nanostructured field-effect transistors in the n-type region 50N and the p-type region 50P. For example, the channel regions in the n-type region 50N and the p-type region 50P may have the same material composition, such as silicon or another semiconductor material, and may be formed simultaneously.

[0076] In other embodiments, the first semiconductor layer 51 may be removed from the p-type region 50P and the second semiconductor layer 53 may be patterned to form a channel region of the nanostructured field-effect transistor in the p-type region 50P, and the second semiconductor layer 53 may be removed from the n-type region 50N and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructured field-effect transistor in the n-type region 50N. In other embodiments, the first semiconductor layer 51 may be removed from the n-type region 50N and the second semiconductor layer 53 may be patterned to form a channel region of the nanostructured field-effect transistor in the n-type region 50N, and the second semiconductor layer 53 may be removed from the p-type region 50P and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructured field-effect transistor in the p-type region 50P. In these embodiments, the channel regions in the n-type region 50N and the p-type region 50P may have different material compositions. The first semiconductor layer 51 and the second semiconductor layer 53 may be selectively removed from the n-type region 50N and the p-type region 50P by additional masking and etching techniques. For example, the channel region of the n-type region 50N can be a silicon channel region, while the channel region of the p-type region 50P can be a silicon-germanium channel region. Thus, in some embodiments, the first semiconductor layer 51 can include crystalline silicon-germanium, while the second semiconductor layer 53 can include crystalline silicon, and vice versa.

[0077] The multilayer stack 64 in the accompanying drawings, comprising three first semiconductor layers 51 and three second semiconductor layers 53, is for illustrative purposes only. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. The epitaxial growth method for each layer of the multilayer stack 64 may employ chemical vapor deposition, atomic layer deposition, vapor phase epitaxy, molecular beam epitaxy, or similar processes.

[0078] In various embodiments, the first semiconductor layer 51 may be composed of a first semiconductor material such as silicon, germanium, or the like, while the second semiconductor layer 53 may be composed of a second semiconductor material such as silicon, silicon carbide, or the like. The first semiconductor material and the second semiconductor material may be materials with high etch selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby patterning the second semiconductor layer 53 to form the channel region of the nanostructured field-effect transistor.

[0079] like Figure 3In some embodiments shown, fins 66 are formed in substrate 50, while nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 are formed in multilayer stack 64 and substrate 50, respectively, and the formation method may be etching trenches 58 in multilayer stack 64 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching, neutral beam etching, similar etching, or combinations thereof. Etching may be anisotropic. During the etching process, a hard mask 56 may be used to define the pattern of fins 66 and nanostructures 55. Hard mask 56 may include any suitable insulating material such as oxides, nitrides, oxynitrides, carbonitrides, or the like. In some embodiments (not shown), hard mask 56 may be a multilayer structure. The method of forming hard mask 56 on nanostructure 55 may employ acceptable processes such as thermal oxidation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, combinations thereof, or similar processes.

[0080] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, resulting in a smaller pattern spacing than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers are subsequently used to pattern the fins 66 and nanostructures 55.

[0081] Furthermore, the method of etching the multilayer stack 64 to form the nanostructure 55 can further define the first nanostructures 52A to 52C (collectively regarded as the first nanostructure 52) from the first semiconductor layer 51, and define the second nanostructures 54A to 54C (collectively regarded as the second nanostructure 54) from the second semiconductor layer 53.

[0082] The first nanostructure 52 and the second nanostructure 54 can be further considered together as nanostructure 55.

[0083] For the purpose of explanation, Figure 3 The fins 66 shown have substantially the same width. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P. Furthermore, although Figure 3The fins 66 and nanostructures 55 shown each have a consistent width. In other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, meaning that the width of each fin 66 and / or nanostructure 55 continuously increases in the direction toward the substrate 50. In these embodiments, the nanostructures 55 may each have different widths and be trapezoidal.

[0084] exist Figure 4 Shallow trench isolation regions 68 are formed adjacent to fins 66. The shallow trench isolation regions 68 can be formed by depositing an insulating material on the substrate 50, fins 66, and nanostructures 55, and between adjacent fins 66, to fill the trench 58. The insulating material can be an oxide such as silicon oxide, nitride, the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition, flowable chemical vapor deposition, similar methods, or a combination thereof. Other insulating materials formed by any acceptable process can also be used. In the described embodiment, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 55. Although the insulating material in the figures is a single layer, some embodiments may use multilayer insulating materials. For example, in some embodiments, a pad (not shown) may be formed first along the surfaces of the substrate 50, fins 66, and nanostructures 55. The aforementioned filling material can then be applied to the padding.

[0085] Next, a removal process is performed on the insulating material to remove excess insulating material from the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing, etch-back process, a combination thereof, or a similar process may be used. The planarization process exposes the nanostructure 55 so that the nanostructure 55 after the planarization process is completed is flush with the upper surface of the insulating material.

[0086] Next, the insulating material is recessed to form shallow trench isolation regions 68. The recessed insulating material causes the upper portion of the fin 66 to protrude from between adjacent shallow trench isolation regions 68. Furthermore, the shallow trench isolation regions 68 may have a flat surface as illustrated, a convex surface, a recessed surface (such as dishing), or a combination thereof. The upper surface of the shallow trench isolation regions 68 can be made flat, convex, and / or recessed by suitable etching. An acceptable etching process can be used, such as an etching process selective for the insulating material (where the etching rate of the insulating material is greater than the etching rate of the material between the fin 66 and the nanostructure 55), to recess the shallow trench isolation regions 68. For example, an oxide removal step using diluted hydrofluoric acid can be used.

[0087] exist Figure 4Suitable wells (not shown) can be formed in the fins 66 and / or nanostructures 55. In embodiments with different well morphologies, photoresist or other masks (not shown) can be used to achieve different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed on the fins 66 and nanostructures 55 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating technology, and the patterning method can use an acceptable photolithography technique. Once the photoresist is patterned, n-type impurities can be implanted in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, and the concentration in the implanted region can be about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 The photoresist can be removed after application, and the removal method can be an acceptable ashing process.

[0088] Before or after the implantation of the p-type region 50P, photoresist or other masks (not shown) can be formed on the fins 66 and nanostructures 55 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating technology, and the patterning method can use an acceptable photolithography technique. Once the photoresist is patterned, p-type impurities can be implanted in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the implantation of p-type impurities into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or the like, and the concentration implanted in the region can be about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 The photoresist can be removed after application, and the removal method can be an acceptable ashing process.

[0089] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, in-situ doping can be performed during the growth of the epitaxial fin to omit implantation, but in-situ doping and implantation doping can be used in combination.

[0090] exist Figure 5A and 5BIn this configuration, a dummy gate is formed on the nanostructure 55 and the fin 66, and along the sidewalls of the nanostructure 55 and the fin 66. To form the dummy gate, a dummy dielectric layer may first be formed on the fin 66 and / or the nanostructure 55. For example, the dummy dielectric layer may be silicon oxide, silicon nitride, a combination thereof, or the like, and its formation method may be deposition or thermal growth according to acceptable techniques. The dummy gate layer is formed on the dummy dielectric layer, and a masking layer is formed on the dummy gate layer. The dummy gate layer may be deposited on the dummy dielectric layer, and then the dummy gate layer may be planarized by methods such as chemical mechanical polishing. The masking layer may be deposited on the dummy gate layer. The dummy gate layer may be a conductive or non-conductive material, and may be selected from amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitrides, metal silicides, metal oxides, and metals. The deposition method for the dummy gate layer can be physical vapor deposition, chemical vapor deposition, sputtering deposition, or other techniques used for depositing selected materials. The composition of the dummy gate layer can be other materials that have high etch selectivity relative to the isolation region. For example, the masking layer may include silicon nitride, silicon oxynitride, or the like.

[0091] Next, an acceptable photolithography and etching technique can be used to pattern the mask layer to form mask 78. The pattern of mask 78 can then be transferred to a dummy gate layer and a dummy dielectric layer to form dummy gate 76 and dummy gate dielectric layer 70, respectively. Dummy gate 76 covers individual channel regions of fin 66. The pattern of mask 78 can be used to physically separate adjacent dummy gates 76. The length direction of dummy gate 76 can also be substantially perpendicular to the length direction of individual fin 66. It is worth noting that the dummy gate dielectric layer 70 in the figures only covers fin 66 and nanostructure 55 and is for illustrative purposes only. In some embodiments, the dummy gate dielectric layer 70 can be deposited such that the dummy gate dielectric layer 70 covers the shallow trench isolation region 68 and extends between the dummy gate 76 and the shallow trench isolation region 68.

[0092] exist Figure 6A and 6BIn this process, a gate spacer 81 is formed on the nanostructure 55 and the shallow trench isolation region 68, as well as on the exposed surfaces of the mask 78 (if present), the dummy gate 76, and the dummy gate dielectric layer 70. The gate spacer 81 can be formed by conformally forming one or more dielectric materials, followed by etching. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, and can be formed by deposition processes such as chemical vapor deposition, atomic layer deposition, or similar processes. Other insulating materials formed by any acceptable process may also be used. Any acceptable etching process such as dry etching, wet etching, similar etching, or combinations thereof can be performed to pattern the dielectric material. Etching may be anisotropic. A portion of the dielectric material may remain on the sidewalls of the dummy gate 76 during etching, thus forming the gate spacer 81. As detailed below, during etching, portions of the dielectric material may remain on the sidewalls of the semiconductor fins 66 and / or nanostructures 55, thus forming fin spacers 83 (see...). Figure 7C After etching, the fin spacers 83 and / or the gate spacers 81 may have flat sidewalls (as shown) or curved sidewalls (not shown).

[0093] Furthermore, the placement of lightly doped source / drain regions (not shown) can be performed. The placement of lightly doped source / drain regions can be performed before forming the gate spacer 81. In embodiments with different device configurations, similar to the placement described above, a mask, such as a photoresist, can be formed on the n-type region 50N, exposing the p-type region 50P, and impurities of a suitable morphology (e.g., p-type) can be placed into the exposed semiconductor fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The impurity concentration of the lightly doped source / drain regions can be approximately 10. 15 atoms / cm 3 Up to 10 19 atoms / cm 3 Annealing can be used to repair implant damage and revitalize the implants.

[0094] It is worth noting that the foregoing describes a typical process for forming spacers and lightly doped source / drain regions. Other processes and sequences can also be used. For example, fewer or more spacers can be used, different step sequences can be employed, and additional spacers can be formed and removed, and / or similar adjustments can be made. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0095] exist Figures 7A to 7CIn some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region may then be formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54, and extend into the substrate 50. Figure 7C As shown, the upper surface of the shallow trench isolation region 68 may be flush with the lower surface of the first recess 86. In other embodiments, the fins 66 may be etched so that the lower surface of the first recess 86 is higher or lower than the upper surface of the shallow trench isolation region 68. The first recess 86 may be formed by etching the fins 66, the nanostructure 55, and the substrate 50, using an anisotropic etching process such as reactive ion etching, neutral beam etching, or similar etching. During the etching process used to form the first recess 86, the gate spacer 81, the fin spacer 83, and the mask 78 mask portions of the fins 66, the nanostructure 55, and the substrate 50. Single or multiple etching processes may be used to etch each layer of the nanostructure 55 and / or the fins 66. A time-controlled etching process may be used to stop etching the first recess 86 after it reaches the desired depth.

[0096] Can be carried out as appropriate Figures 8A to 9B The process involves, for example, replacing the first nanostructure 52 with the sacrificial material 72 (which can also be considered as a one-time oxide interlayer). In this way, the sacrificial material 72 can also be considered as a nanostructure (such as a dielectric nanostructure).

[0097] exist Figure 8A and 8B In this process, the method for replacing the first nanostructure 52 can employ a suitable etching process, such as an isotropic etching process, to remove the first nanostructure 52 via etching through the first recess 86. The etching process can be selective in its application to the material of the first nanostructure 52, removing the first nanostructure 52 without significantly removing the second nanostructure 54 or the semiconductor fin 66. In one embodiment, the first nanostructure 52 comprises silicon germanium and the second nanostructure 54 comprises silicon or silicon carbide, and a dry etching process using tetramethylammonium hydroxide, ammonium hydroxide, or the like can be used to remove the first nanostructure 52.

[0098] A sacrificial material layer 71 is then deposited in the space left by the removal of the first nanostructure 52 and in the first recess 86. The deposition method of the sacrificial material layer 71 may be a compliant deposition process such as chemical vapor deposition, atomic layer deposition, or a similar process. The sacrificial material layer 71 may include an insulating material such as silicon oxide or the like, so the sacrificial material layer 71 may be selectively etched without etching the second nanostructure 54.

[0099] exist Figures 9A to 9DIn this process, the sacrificial material layer 71 can be etched to form the sacrificial material 72. The etching can be isotropic or anisotropic. For example, the etching method for the sacrificial material layer can be a wet etching process using diluted hydrofluoric acid or the like as an etchant. In some embodiments, etching can be performed to form recesses 87 from the sidewalls of the second nanostructure 54 within the sidewalls of the sacrificial material 72. Although Figure 9B and 9C The sidewalls of the sacrificial material 72 shown are straight, and the sidewalls may also be concave or convex (see...). Figure 9D and Figures 13E to 13H ).

[0100] Figure 9C and 9D yes Figure 9B An illustrative detail diagram of various units, including a second nanostructure 54, a fin 66, and a sacrificial material 72. As shown, the sacrificial material 72 may be recessed to a depth D1, which may be 5 nm to 10 nm (e.g., 6 nm to 7 nm), but the sacrificial material 72 (or the first nanostructure 52) may also be recessed to any suitable depth D1.

[0101] As mentioned above, Figure 9D The illustrated embodiments and Figure 9C Similarly, the difference lies in the fact that some units have adjusted shapes and / or sizes due to the actual manufacturing process steps. Furthermore, Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 17D ,and Figure 18D and Figure 9D This can be considered as a practical implementation. For example... Figure 9D As shown, after the etching process, the sidewalls of the sacrificial material 72 may have a concave shape, such that the concavity of the area of ​​the sacrificial material 72 along the second nanostructure 54 is smaller than the concavity of the middle area.

[0102] Replacing the first nanostructure 52 with the sacrificial material 72 offers several advantages. For example, one or more high-temperature processes can be performed in subsequent source / drain formation steps to activate the dopants in the source / drain regions. When the material of the first nanostructure 52 (such as silicon-germanium) is exposed to high temperatures, the roughness of the interface between the first nanostructure 52 and the second nanostructure 54 may increase, and germanium may mix with each other. This manufacturing defect can degrade the performance of the final transistor device. For example, when germanium diffuses into the second nanostructure 54, residual germanium may remain in the channel region of the final transistor device, negatively impacting the performance of the channel region. Replacing the first nanostructure 52 with an insulating material before high-temperature processes (such as source / drain annealing) can reduce manufacturing defects and improve device performance (such as increasing drive current, reducing capacitance, and improving short-channel effects).

[0103] As mentioned above, it can be done as appropriate. Figures 8A to 9B The process steps can be performed without performing the above-described process on the nanostructured field-effect transistors or on some nanostructured field-effect transistors. For example, some embodiments (not shown) retain the first nanostructure 52 at this process point without depositing the sacrificial material layer 71. Instead, an etching process is performed to recess the sidewalls of the first nanostructure 52. This etching process can be combined with... Figure 8A and 8B The etching process described above is similar (e.g., the process for removing the first nanostructure 52), except that the etching process stops once the desired indentation is achieved, rather than completely removing the first nanostructure 52. In some embodiments, the etching process is an isotropic etching process such as reactive ion etching, neutral beam etching, or a similar process. It is worth noting that the intermediate structure shown in the following figures contains sacrificial material 72. It should be understood that the corresponding shape and size of the first nanostructure 52 may be substantially the same as the shape and size of the sacrificial material 72, unless otherwise stated. In this way, the reference numerals used for the sacrificial material 72 (or a portion thereof) in the figures may be used instead for the first nanostructure 52 (or a portion thereof).

[0104] Figures 10A to 13H In this embodiment, a gap control process is used to form the inner spacer 90 within a first recess 86 on the sidewall of the sacrificial material 72 (or the first nanostructure 52, if present). The inner spacer 90 serves as an isolation structure between the subsequently formed source / drain regions and the gate structure. As detailed below, the source / drain regions will be formed in the first recess 86, and the sacrificial material 72 (or the first nanostructure 52) will be replaced by the corresponding gate structure. The inner spacer 90 can also be used to prevent subsequent etching processes (such as the etching process used to form the gate structure) from damaging the subsequently formed source / drain regions.

[0105] A gap-controlled process is used to form seamless or narrowly gapped inner spacers 90 to increase the reliability and improve the performance of the inner spacers 90. As detailed below, the inner spacers 90 can be formed by a deposition-etch-deposition process, wherein a first inner spacer layer is deposited on… Figures 9A to 9D In the structure shown, an etching process is performed, and one or more second inner spacer layers are deposited on the etched first inner spacer layer. The material of the inner spacer layers is selected to provide a sufficiently low effective dielectric constant and further provide the advantage of etch resistance in subsequent process steps (such as etch selectivity compared to certain other structures).

[0106] exist Figures 10A to 10DIn this process, a first inner spacer layer 90A is deposited along the exposed surface of the structure, for example, deposited along the exposed surface of the fin 66, the sidewalls of the sacrificial material 72, the sidewalls of the second nanostructure 54, the sidewalls of the gate spacer 81, and in the recesses of the upper surface of the mask 78 (if present). In various embodiments, the first inner spacer layer 90A may be a silicon-based low-dielectric-constant material, such as low-nitrogen-concentration silicon carbide or silicon carbonitride.

[0107] For example, the first inner spacer layer 90A has a silicon concentration of 25 to 35 atomic weights (e.g., 30 atomic weights), a carbon concentration of 5 to 20 atomic weights (e.g., 6 atomic weights), an oxygen concentration of 60 to 70 atomic weights (e.g., 64 atomic weights), and a nitrogen concentration of less than or equal to 10 atomic weights (e.g., 0 atomic weights).

[0108] In some embodiments, the deposition method for the first inner spacer layer 90A can be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or atomic layer deposition, using precursors including silane, dichlorosilane, hexachlorosilane, hydrogen, oxygen, the like, or combinations thereof. Furthermore, the deposition process temperature is at most between about 300°C and 700°C (e.g., at most about 550°C). Additionally, the dielectric constant of the first inner spacer layer 90A is less than about 4 (e.g., about 3.8). A dielectric constant below about 4 for the first inner spacer layer 90A is advantageous because the inner spacer 90 has a sufficiently low effective dielectric constant to improve the performance of the nanostructured field-effect transistor. In some embodiments, the deposition density of the first inner spacer layer 90A can be 2.00 g / cm³. 3 Up to 2.50 g / cm 3 (e.g., 2.23 g / cm) 3 The stress can be greater than about 0 GPa and at most about -0.05 GPa (such as compressive stress).

[0109] Forming the first inner spacer layer 90A described above offers several advantages. For example, a low dielectric constant ensures the inner spacer 90 (see...) Figures 13A to 13H The first inner spacer layer 90A has a low effective dielectric constant. In fact, a low nitrogen concentration and a high oxygen concentration (e.g., oxygen concentration greater than nitrogen concentration) are beneficial for the low dielectric constant value required for the first inner spacer layer 90A. Furthermore, the first inner spacer layer 90A can exhibit high etch selectivity relative to the sacrificial material 72 (e.g., silicon oxide). The aforementioned carbon concentration contributes to etch selectivity, providing the required etch resistance for the first inner spacer layer 90A during subsequent removal of the sacrificial material 72 (see [link to relevant documentation]). Figures 17A to 17D ).

[0110] Figure 10C and 10D yes Figure 10B An illustrative detail diagram of various units is shown, including a second nanostructure 54, a fin 66, a sacrificial material 72, and a first inner spacer layer 90A. As shown, the first inner spacer layer 90A can be compliantly deposited along the recessed sidewalls of the sacrificial material 72. The deposition thickness T1 of the first inner spacer layer 90A can be... to However, any suitable thickness T1 can be used to allow the first inner spacer layer 90A along the upper and lower surfaces of the second nanostructure 54 to connect during deposition. As shown, these portions may merge to form a gap 90M. The gap 90M begins at the outer sidewall of the first inner spacer layer 90A and extends toward (albeit partially toward) the inner sidewall of the first inner spacer layer 90A (e.g., toward the sacrificial material 72).

[0111] Specifically, Figure 10D In the actual embodiment shown, the sidewalls of the sacrificial material 72 are recessed, which may cause the inner sidewalls of the first inner spacer layer 90A to have a convex shape along the sidewalls of the sacrificial material 72. In addition, the outer sidewalls of the first inner spacer layer 90A may be disc-shaped in the region laterally adjacent to the recessed sacrificial material 72.

[0112] exist Figures 11A to 11D In the etching process, the first inner spacer layer 90A is etched to form a recess 87' in the slot 90M. Specifically, the critical dimension of the recess 87' formed by the etching process is smaller than that of the recess 87. In other words, the window used for the recess 87 associated with depth D2 is proportionally larger (e.g., wider or with a smaller angle to the vertical) compared to the window used for the recess 87 associated with depth D1. Furthermore, the slot 90M can be shortened. In some embodiments (not shown), etching can remove sufficient amount of the first inner spacer layer 90A to remove some or all of the slot 90M. The etching process can be isotropic or anisotropic, employing nitrogen trifluoride and / or any other suitable etchant.

[0113] Figure 11C and 11D yes Figure 11B The illustration details various units, including the second nanostructure 54, fin 66, sacrificial material 72, and a first inner spacer layer 90A (e.g., containing a recess 87'). In some embodiments, the depth D2 of the recess 87' may be... to Furthermore, the etching process can thin other portions of the first inner spacer layer 90A to a thickness T2, and the thickness T2 can be... to (Or approximately 50% to 60% of the thickness T1). It should be understood that the deeper portions of the first inner spacer layer 90A in the recess 87 (e.g., the portions between the second nanostructures 54 and adjacent to the sacrificial material 72) can be etched to a specific thickness (e.g., approximately 65% ​​to 75% of the thickness T1). For example, the depth D2 of the recess 87' can be greater than the thickness T2, such that the recess 87' extends between and beyond the sidewalls of the second nanostructures 54. As shown, the shape of the recess 87' can be substantially triangular, with the two sides of the triangle being portions of the outer sidewalls of the first inner spacer layer 90A.

[0114] Specifically, Figure 11D In the specific embodiment shown, the two sides of the triangle of recess 87' may be recessed and meet at a rounded point (located at or near the gap 90M). However, due to the effects or inconsistencies of the etching process, it should be understood that one or both sides of the meeting point may be convex, recessed, or substantially flat.

[0115] exist Figures 12A to 12D In this process, a second inner spacer layer 90B is formed over the first inner spacer layer 90A, within the recesses 87' adjacent to the sacrificial material 72 (or the first nanostructure 52), and between adjacent second nanostructures 54. As shown, the second inner spacer layer 90B has all the recesses 87' and no gaps. This is at least partly due to the fact that when the first inner spacer layer 90A is deposited, the window of the recess 87' is larger than the window of the recess 87 (or the critical dimension of the recess 87' is smaller than the critical dimension of the recess 87). In various embodiments, the second inner spacer layer 90B may be a silicon-based material such as silicon nitride, wherein the silicon to nitrogen ratio is between 0.75 and 0.85 (e.g., 0.816). In some embodiments, the second inner spacer layer 90B may be silicon oxycarbonate.

[0116] For example, the second inner spacer layer 90B may have a silicon concentration of 30 to 35 atomic weight percent (e.g., 32 atomic weight percent), a carbon concentration of 2 to 20 atomic weight percent (e.g., 5 atomic weight percent), an oxygen concentration of 30 to 50 atomic weight percent (e.g., 43 atomic weight percent), and a nitrogen concentration of 15 to 35 atomic weight percent (e.g., 20 atomic weight percent). It is noteworthy that the second inner spacer layer 90B may comprise another type of metal, such as boron instead of silicon, for example, containing boron oxycarbonate. In various embodiments, the first inner spacer layer 90A and the second inner spacer layer 90B may have similar silicon concentrations (or metalloid concentrations) and similar carbon concentrations, but the first inner spacer layer 90A may have a higher oxygen concentration while the second inner spacer layer 90B may have a higher nitrogen concentration.

[0117] In some embodiments, the deposition method for the second inner spacer layer 90B can be any suitable method such as atomic layer deposition (e.g., thermal atomic deposition), using precursors including hexachlorosilane, propylene, oxygen, ammonia, the like, or combinations thereof. In embodiments where the second inner spacer layer 90B is silicon nitride, the precursor may include hexachlorosilane, ammonia, and / or the like. Furthermore, the deposition process temperature may be at most between 500°C and 700°C (e.g., at most about 630°C). Additionally, the dielectric constant of the second inner spacer layer 90B is less than about 7, for example, 5.0 (e.g., silicon carbonitride) to 6.5 (e.g., silicon nitride). A dielectric constant of less than about 7 for the second inner spacer layer 90B (e.g., when combined with the first inner spacer layer 90A) ensures that the inner spacer 90 has a sufficiently low effective dielectric constant to improve the performance of the nanostructured field-effect transistor. In some embodiments, the density of the deposited second inner spacer layer 90B is 2.40 g / cm³. 3 Up to 2.85 g / cm 3 (e.g., 2.48g / cm) 3 Up to 2.85 g / cm 3 The stress is approximately 0.23 GPa to approximately 0.26 GPa (e.g., tensile stress).

[0118] Forming the second inner spacer layer 90B described above offers several advantages. For example, the second inner spacer layer 90B exhibits high etch resistance in subsequent processes, such as the process of etching the first inner spacer layer 90A and the second inner spacer layer 90B to form the inner spacer 90, and the process of forming the epitaxial source / drain regions (see...). Figures 14A to 14F The aforementioned nitrogen concentration contributes to etch resistance. Considering some of the above embodiments, the presence of carbon further enhances etch resistance. Furthermore, the dielectric constant of the second inner spacer layer 90B is low enough to ensure the inner spacer 90 (see...) Figures 13A to 13H It has a low effective dielectric constant. In some embodiments according to the above description, the second inner spacer layer 90B has a low nitrogen concentration and a high oxygen concentration (e.g., the oxygen concentration is greater than the nitrogen concentration), which contributes to the low dielectric constant value used in the second inner spacer layer 90B.

[0119] Figure 12C and 12D yes Figure 12B An illustrative detail diagram of various units is shown, including a second nanostructure 54, a fin 66, a sacrificial material 72, a first inner spacer layer 90A, and a second inner spacer layer 90B. As shown, the second inner spacer layer 90B can be compliantly deposited along the recessed sidewalls of the first inner spacer layer 90A (e.g., deposited in recess 87'). The deposition thickness T3 of the second inner spacer layer 90B can be [missing information]. to However, any suitable thickness T3 can be used to fill the recess 87'. As shown in the figure, due to the presence of the recess 87', a seamless second inner spacer layer 90B can be deposited. The material selection and process for forming the second inner spacer layer 90B also contribute to the seamless deposition.

[0120] Specifically, Figure 12D In a specific embodiment, the outer sidewall of the second inner spacer layer 90B may include a dishing, which is laterally adjacent to the recess 87'. For example, the depth D3 of the dishing is... to In this way, the discation does not need to extend into the recess 87', because the recess 87' can be filled with the second inner spacer 90B. In some embodiments (not shown), the discation can extend partially into the recess 87', as long as the portion of the recess 87' between the second nanostructures 54 is filled with the second inner spacer layer 90B.

[0121] In some embodiments (not shown), the second inner spacer layer 90B may consist of multiple compliant layers. For example, each of the multiple layers may comprise any material associated with the second inner spacer layer 90B and may be deposited by any process associated with the second inner spacer layer 90B. In some embodiments, a silicon carbonitride layer may be deposited first, followed by a silicon nitride layer. In other embodiments, a silicon nitride layer may be deposited first, followed by a silicon carbonitride layer. Multiple layers may be mixed as needed to give the second inner spacer layer 90B a substantially uniform composition.

[0122] exist Figures 13A to 13H In the etching process, the second inner spacer layer 90B and the first inner spacer layer 90A are etched to form the inner spacer 90. The etching method for the first inner spacer layer 90A and the second inner spacer layer 90B can be an isotropic etching process, such as reactive ion etching, neutral beam etching, or similar processes. The etching process can remove the first inner spacer layer 90A and the second inner spacer layer 90B from the sidewall of the second nanostructure 54, so that the retained portions of the first inner spacer layer 90A and the second inner spacer layer 90B are substantially flush with the sidewall of the second nanostructure 54. As described above, the etch resistance of the second inner spacer layer 90B can avoid or reduce dishing that may occur during the etching process. Specifically, the second inner spacer layer 90B (and the first inner spacer layer 90A) can be etched using a directional etching method, and the second inner spacer layer 90B (and the first inner spacer layer 90A) can be substantially left unetched in the lateral direction (e.g., between the second nanostructures 54). In various embodiments, a single etching process can be used to simultaneously etch the first inner spacer layer 90A and the second inner spacer layer 90B. However, any suitable combination of etching processes can be used.

[0123] Figure 13C and 13D yes Figure 13B An illustrative detail diagram of various units is shown, including a second nanostructure 54, fins 66, sacrificial material 72, and inner spacers 90. As shown, a first inner spacer layer 90A and a second inner spacer layer 90B are etched, causing the separated inner spacers 90 to be adjacent to the sacrificial material 72 and located between the second nanostructures 54. In some embodiments, the retained portions of the first inner spacer layer 90A may each be partially defined and physically contacted by one of the sacrificial material 72, one or more second nanostructures 54, and / or fins 66. Furthermore, the retained portions of the second inner spacer layer 90B may each be partially defined and physically contacted by the corresponding retained portions of the first inner spacer layer 90A. In this way, the outermost walls of the inner spacers 90 are substantially flush with the second nanostructures 54. As described above, Figure 13D The etching process described in the actual embodiments, and others Figures 13A to 13C and Figures 13E to 13H The etching process is similar.

[0124] Figures 13E to 13H In some embodiments, various units (such as the inner spacer 90) have other shapes. Although the outer walls of the inner spacer 90 in the figures are flush with the sidewalls of the second nanostructure 54 (see figure 54)... Figures 13B to 13D The outer sidewall of the inner spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54 (see...). Figure 13E and 13F In the example where the inner spacer 90 is recessed towards the outer wall, the amount of disking can be reduced because the composition of the inner spacer 90 (such as the second inner spacer layer 90B) is resistant to lateral etching. Furthermore, although the inner wall of the illustrated inner spacer 90 is straight (see...), Figure 13B and 13C The inner wall of the inner spacer 90 may be concave or convex (see...). Figures 13D to 13H For example, Figure 13E and 13F In the illustrated embodiment, the sidewalls of the sacrificial material 72 are recessed, the inner sidewalls of the inner spacer 90 are recessed inwards, and the outer sidewalls of the inner spacer 90 are recessed from the sidewalls of the second nanostructure 54. Other configurations are also possible. For example, Figure 13G and 13H In the embodiment shown, the sidewall of the sacrificial material 72 is recessed, the inner sidewall of the inner spacer 90 is recessed, and the outer sidewall of the inner spacer 90 is straight and flush with the sidewall of the second nanostructure 54.

[0125] exist Figures 14A to 14FIn this configuration, epitaxial source / drain regions 92 are formed in a first recess 86. In some embodiments, the epitaxial source / drain regions 92 may apply stress to the second nanostructure 54 in the n-type region 50N and / or the p-type region 50P, thereby improving performance. As shown, the epitaxial source / drain regions 92 are formed in the first recess 86 such that a dummy gate 76 is located between individual adjacent epitaxial source / drain regions 92. In some embodiments, gate spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gate 76, while inner spacers 90 are used to provide a suitable lateral distance between the epitaxial source / drain regions 92 and the sacrificial material 72, so that the epitaxial source / drain regions 92 are not shorted to the gate subsequently formed in the final nanostructure field-effect transistor.

[0126] The method of forming the epitaxial source / drain region 92 in the n-type region 50N, such as an n-type metal-oxide-semiconductor region, may involve masking the p-type region 50P, such as a p-type metal-oxide-semiconductor region. The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 within the n-type region 50N. The epitaxial source / drain region 92 may comprise any acceptable material suitable for an n-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 in the n-type region 50N may comprise a material to which tensile stress is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0127] The method of forming the epitaxial source / drain region 92 in the p-type region 50P, such as a p-type metal-oxide-semiconductor region, can be to mask the n-type region 50N, such as an n-type metal-oxide-semiconductor region. The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for a p-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 in the p-type region 50P can include a material to which compressive stress is applied to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like.

[0128] Dopant can be implanted into the epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 to form the source / drain region, which can be similar to the aforementioned process for forming lightly doped source / drain regions. Annealing is then performed. The impurity concentration of the epitaxial source / drain region can be between approximately 1 x 10⁻⁶. 19 atoms / cm 3 To approximately 1x10 21 atoms / cm 3 Between. The n-type and / or p-type impurities used in the source / drain regions can be any of the aforementioned impurities. In some embodiments, in-situ doping can be performed during the growth of the epitaxial source / drain regions 92.

[0129] Figure 14C and 14D yes Figure 14B An illustrative detail diagram of various units is shown, including a second nanostructure 54, a fin 66, a sacrificial material 72, an inner spacer 90, and an epitaxial source / drain region 92. As shown, after the epitaxial source / drain region 92 is initially formed along the sidewalls of the fin 66 and the second nanostructure 54, a portion of the epitaxial source / drain region 92 is formed along and merges with the outer sidewall of the inner spacer 90. Furthermore, the second inner spacer layer 90B can be completely defined by the epitaxial source / drain region 92 and the first inner spacer layer 90A. As described above, Figure 14D The actual implementation examples illustrate similarities to other Figures 14A to 14C , Figure 14E ,and Figure 14F The extended growth process.

[0130] The epitaxial process forming epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P results in the upper surface of the epitaxial source / drain regions 92 having sidewalls with crystal planes extending laterally outward beyond the nanostructure 55. In some embodiments, the crystal planes cause adjacent epitaxial source / drain regions 92 of the same nanostructure field-effect transistor to merge, such as... Figure 14E As shown. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as... Figure 14F As shown. In Figure 14C and 14D In the illustrated embodiment, fin spacers 83 may be formed on the upper surface of the shallow trench isolation region 68 to prevent epitaxial growth. In some other embodiments, fin spacers 83 may cover portions of the sidewalls of the nanostructure 55 to further prevent epitaxial growth. In some other embodiments, the spacer etching used to form the fin spacers 83 may be adjusted to remove spacer material, allowing the epitaxial growth region to extend to the surface of the shallow trench isolation region 68.

[0131] The epitaxial source / drain region 92 may include one or more half-semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. The epitaxial source / drain region 92 may employ any number of semiconductor material layers. The first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may each be composed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the dopant concentration of the first semiconductor material layer 92A is less than the dopant concentration of the second semiconductor material layer 92B, and greater than the dopant concentration of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0132] exist Figure 15A and 15B In the middle, the first interlayer dielectric layer 96 is deposited on... Figure 11A and 11B The structure shown. The first interlayer dielectric layer 96 may be composed of a dielectric material, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material may include phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer 94 is located between the first interlayer dielectric layer 96 and the epitaxial source / drain region 92, mask 78, and gate spacer 81. The contact etch stop layer 94 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and its etch rate is different from the etch rate of the material of the upper first interlayer dielectric layer 96.

[0133] After depositing the first interlayer dielectric layer 96, a planarization process, such as chemical mechanical polishing, can be performed to flush the upper surface of the first interlayer dielectric layer 96 with the upper surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and portions of the gate spacer 81 along the sidewalls of the mask 78. After the planarization process, the dummy gate 76, the gate spacer 81, and the upper surface of the first interlayer dielectric layer 96 are flush (in process variables). In summary, the upper surface of the dummy gate 76 is exposed from the first interlayer dielectric layer 96. In some embodiments, the mask 78 may be retained, and in this example, the planarization process flushes the upper surface of the first interlayer dielectric layer 96 with the upper surfaces of the mask 78 and the gate spacer 81.

[0134] exist Figure 16A and16B In the process, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form the second recess 98. A portion of the dummy gate dielectric layer 70 and a portion of the protective pad in the second recess 98 may also be removed. In some embodiments, the removal method for the dummy gate 76 and the dummy gate dielectric layer 70 may be an isotropic dry etching process. For example, the etching process may include a dry etching process in which the reactive gas selectively etches the dummy gate 76 at a rate greater than the rate at which the first interlayer dielectric layer 96 or the gate spacer 81 is etched. The second recess 98 exposes a portion of the nanostructure 55 and / or is located on a portion of the nanostructure 55, which serves as a channel region for the subsequently completed nanostructure field-effect transistor. The portion of the nanostructure 55 serving as the channel region is located between adjacent epitaxial source / drain regions 92. The dummy gate dielectric layer 70 may serve as an etch stop layer during the etching removal of the dummy gate 76. After the dummy gate 76 is removed, the dummy gate dielectric layer 70 may be removed.

[0135] exist Figures 17A to 17D In this process, sacrificial material 72 is removed to extend the second recess 98. Methods for removing sacrificial material 72 may include performing an isotropic etching process, such as wet etching or a similar process, using an etchant selective for sacrificial material 72, while the second nanostructure 54 remains relatively unetched relative to sacrificial material 72. As shown, extending the second recess 98 exposes the inner spacer 90's inward-facing sidewalls (such as the first inner spacer layer 90A). Sacrificial material 72 may be completely removed, or a residue 72' of sacrificial material may remain on the sidewalls of the inner spacer in the second recess 98 (see Figure 1). Figure 17D ).

[0136] In some embodiments, the shallow trench isolation region 68 may be etched when removing the sacrificial material 72, but etching parameters (such as time) may be controlled during the removal of the sacrificial material 72 to reduce the total loss in the shallow trench isolation region 68. In other embodiments, the shallow trench isolation region 68 may include a hard mask (not shown) on its upper surface to protect the underlying shallow trench isolation region 68 from the etching processes used for patterning and removing the sacrificial material 72. In these embodiments, the hard mask may include a nitride.

[0137] Figure 17C and 17D yes Figure 17BThe illustration details various units, including the second nanostructure 54, fin 66, inner spacer 90, epitaxial source / drain region 92, and a second recess 98 extending after the removal of sacrificial material 72. As shown, the etching process exposes the inward sidewalls of the inner spacer 90 (such as the first inner spacer layer 90A). Due to the high etch selectivity between the material of the sacrificial material 72 (such as silicon oxide) and the material of the first inner spacer layer 90A (such as silicon carbide), the exposed inner spacer 90 remains substantially unetched. In this way, the first inner spacer layer 90A protects the second inner spacer layer 90B (and the inner spacer 90 in general) from etching when the sacrificial material 72 is removed.

[0138] Specifically, Figure 17D In the actual embodiment shown, the residue 72' of the sacrificial material can be retained on the sidewall of the inner spacer 90, such as in the corner between the inner spacer 90 and the second nanostructure 54 (or fin 66). It is noteworthy that in the structure of this embodiment, the etched sacrificial material 72 (see...) Figures 9A to 9D This causes a concave sidewall (see) Figure 9D This creates a narrower corner between the inner spacer 90 and the second nanostructure 54. The etchant cannot reach this narrower corner to completely remove the sacrificial material 72. It should be understood that in some embodiments (not shown), the sidewalls of the sacrificial material are substantially flush with the inward sidewalls of the inner spacer 90 (see...). Figure 17B and 17C However, the etching process that removes the sacrificial material 72 still leaves a residue of the sacrificial material 72'.

[0139] exist Figures 18A to 18D In this process, a gate dielectric layer 100 and a gate 102 are formed as a replacement gate. The gate dielectric layer 100 is compliantly deposited in the second recess 98. The gate dielectric layer 100 may be formed on the upper surface and sidewalls of the substrate 50, the upper surface, sidewalls, and lower surface of the second nanostructure 54, and the inner sidewalls (if exposed) of the inner spacer 90. The gate dielectric layer 100 may also be deposited on the upper surface of the first interlayer dielectric layer 96, the contact etch stop layer 94, the gate spacer 81, and the shallow trench isolation region 68.

[0140] In some embodiments, the gate dielectric layer 100 includes one or more dielectric layers such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layer 100 may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a dielectric material with a high dielectric constant. In these embodiments, the dielectric constant of the gate dielectric layer 100 is greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 100 may include molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0141] Gate 102 can be deposited on gate dielectric layer 100 to fill the remaining portion of second recess 98. Gate 102 may include a metal material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although Figures 18A to 18D The gate 102 shown is a single layer. The gate 102 may include any number of pad layers, any number of work function adjustment layers, and filler material. The gate 102 formed by any combination of layers may be deposited between adjacent second nanostructures 54 in the n-type region 50N and the p-type region 50P, and between the second nanostructure 54A and the substrate 50.

[0142] Gate dielectric layers 100 in both the n-type region 50N and the p-type region 50P can be formed simultaneously, with the gate dielectric layers 100 in each region having the same material composition. Gates 102 in both the n-type region 50N and the p-type region 50P can also be formed simultaneously, with the gates 102 in each region having the same material composition. In some embodiments, the gate dielectric layers 100 in each region can be formed by separate processes, such that the gate dielectric layers 100 in each region are made of different materials and / or have different numbers of layers; and / or the gates 102 in each region can be formed by separate processes, such that the gates 102 in each region are made of different materials and / or have different numbers of layers. In the separate processes, various masking steps can be used to mask and expose suitable areas.

[0143] After filling the second recess 98, a planarization process such as chemical mechanical polishing can be performed to remove excess material from the gate dielectric layer 100 and gate 102 above the upper surface of the first interlayer dielectric layer 96. The remaining material of gate 102 and gate dielectric layer 100 can thus form the replacement gate structure of the final nanostructure field-effect transistor. Gate 102 and gate dielectric layer 100 can be considered together as a "gate structure".

[0144] Figure 18C and 18D yes Figure 18B The diagram illustrates various unit cells, including epitaxial source / drain regions 92, gate dielectric layer 100, gate 102, second nanostructure 54, and inner spacers 90. For example, the first inner spacer layer 90A of the inner spacers 90 may still include a portion of the gap 90M. Furthermore, as... Figure 18D As shown, residues of the sacrificial material 72 may remain on the inner spacer 90, for example, between the inner spacer 90 and the gate dielectric layer 100 and the gate 102. For instance, the sacrificial material 72 may not be completely removed, and the gate dielectric layer 100 may be formed on the retained sacrificial material 72. Since the sacrificial material 72 is an insulating material (such as silicon oxide), the retained residue does not significantly affect the electrical performance of the final device.

[0145] Figure 18C and 18D show Figure 18B An illustrative detail diagram of various units is shown, including a second nanostructure 54, a fin 66, an inner spacer 90, an epitaxial source / drain region 92, a residue of sacrificial material 72' (if present), a gate dielectric layer 100, and a gate 102. As shown, the gate dielectric layer 100 can be deposited along the inner sidewalls of the inner spacer 90 (such as the first inner spacer layer 90A) and the upper and lower surfaces of the second nanostructure 54 (and the upper surface of the fin 66). In this way, the inner spacer 90 can be defined by the epitaxial source / drain region 92, the second nanostructure 54, and the gate dielectric layer 100. Furthermore, the first inner spacer layer 90A can therefore be defined by these structures and the second inner spacer layer 90B. Furthermore, the second inner spacer layer 90B can be defined by the epitaxial source / drain region 92 and the first inner spacer layer 90A.

[0146] Specifically, Figure 18D In a practical embodiment, once the gate dielectric layer 100 and the gate 102 are deposited, the sacrificial material residue 72' can be combined with the inner spacer 90 to form a protruding inward sidewall. As shown, the inner spacer 90 can be defined by the epitaxial source / drain region 92, the second nanostructure 54, the gate dielectric layer 100, and any sacrificial material residue 72'.

[0147] exist Figures 19A to 19C In this process, the gate structure (containing the gate dielectric layer 100 and the corresponding upper gate 102) is recessed to directly form a portion recessed between the gate structure and the gate spacers 81 on both sides. The gate mask 104 includes one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like filling the recess, followed by a planarization process to remove excess dielectric material extending on the first interlayer dielectric layer 96. The subsequently formed gate contacts (such as those used in conjunction with...) Figures 21A to 21CThe gate contact 114 described below passes through the gate shield 104 to contact the upper surface of the recessed gate 102.

[0148] As described below, the second interlayer dielectric layer 106 is deposited on the first interlayer dielectric layer 96 and the gate mask 104. In some embodiments, the second interlayer dielectric layer 106 is a flowable film formed by flowable chemical vapor deposition. In some embodiments, the second interlayer dielectric layer 106 is composed of a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and its deposition method can be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0149] exist Figures 20A to 20C In this process, the second interlayer dielectric layer 106, the first interlayer dielectric layer 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a third recess 108, exposing the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching, employing anisotropic etching processes such as reactive ion etching, neutral beam etching, or similar etching. In some embodiments, the third recess 108 can be formed by etching through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 96 by a first etching process, etching through the gate mask 104 by a second etching process, and etching through the contact etch stop layer 94 by a third etching process. A patterned mask, such as photoresist, can be formed and patterned on the second interlayer dielectric layer 106 to shield portions of the second interlayer dielectric layer 106 from the first and second etching processes. In some embodiments, the etching process may be over-etching, so the third recess 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the recess 108 may be flush with (e.g., at the same height or at the same distance from the substrate) or lower than (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although in the various embodiments shown in FIG26B, the epitaxial source / drain region 92 and gate structure exposed by the third recess 108 are in the same cross-section, the epitaxial source / drain region 92 and gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting the subsequently formed contacts.

[0150] After forming the third recess 108, a silicide region 110 is formed on the epitaxial source / drain region 92. In some embodiments, the silicide region 110 may be formed by first depositing a metal (not shown) that can react with the semiconductor material (such as silicon, silicon-germanium, or germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region on the exposed portion of the epitaxial source / drain region 92, followed by a thermal annealing process to form the silicide region 110. The metal may be nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The unreacted portions of the deposited metal are then removed, and the removal method may be an etching process. Although the silicide region 110 is referred to as a silicide region, it may also be a germanide region or a silicon-germanium region (such as a region containing silicide and germanide). In one embodiment, the silicide region 110 includes titanium silicide, and its thickness is between about 2 nm and about 10 nm.

[0151] Then in Figures 21A to 21C In this embodiment, contacts 112 and 114 (which can also be considered as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to an underlying conductive structure (such as gate 102 and / or silicide region 110 in the described embodiment). Contact 114, electrically coupled to gate 102, can be considered a gate contact, while contact 112, electrically coupled to silicide region 110, can be considered a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material from the surface of the second interlayer dielectric layer 106.

[0152] The embodiments offer several advantages. Specifically, the disclosed embodiments involve an etching process after the deposition of the first inner spacer layer 90A and before the deposition of the second inner spacer layer 90B, resulting in the inner spacers 90 having no gaps or only small gaps. The etching process removes some or all of the gaps 90M in the first inner spacer layer 90A and allows for a shallower (e.g., proportionally wider) deposition window in the deposition process of the gapless or void-free second inner spacer layer 90B. Avoiding or reducing gaps can lower the effective dielectric constant. Furthermore, the composition of the first inner spacer layer 90A and the second inner spacer layer 90B is exemplary in controlling the effective dielectric constant (e.g., ensuring a low dielectric constant) and shape of the inner spacers 90. For the latter advantage, the first inner spacer layer 90A and the second inner spacer layer 90B exhibit high etch resistance and high etch selectivity relative to structures such as the sacrificial material 72 to avoid undesirably etching the inner spacers 90. This results in the inner spacer 90 not being dished out on its outward sidewalls. These embodiments produce nanostructured field-effect transistors with higher yields and functionality, as well as improved reliability and performance.

[0153] In one embodiment, a method of forming a semiconductor device includes forming a first nanostructure and a second nanostructure on a substrate, with the first nanostructure sandwiched between the substrate and the second nanostructure; etching a first sidewall of the first nanostructure such that the first sidewall is recessed from a second sidewall of the second nanostructure; depositing a first dielectric layer along the first sidewall, the second sidewall, and the substrate; etching the recess in the first dielectric layer, with the recess extending toward the first sidewall of the first nanostructure; depositing a second dielectric layer in the recess on the first dielectric layer; and removing the first dielectric layer and the second dielectric layer from the second sidewall and the substrate. In another embodiment, the method further includes forming source / drain regions on the substrate and the second sidewall of the second nanostructure, wherein the source / drain regions physically contact the first dielectric layer and the second dielectric layer. In another embodiment, the method further includes, after removing the first dielectric layer and the second dielectric layer from the second sidewall, etching the first nanostructure to form an opening between the substrate and the second nanostructure. In another embodiment, the step of etching the first nanostructure includes exposing the first dielectric layer located at the opening. In another embodiment, after etching the first nanostructure, a first portion of the first nanostructure physically contacts the substrate and the first dielectric layer, and a second portion of the first nanostructure physically contacts the second nanostructure and the first dielectric layer. In another embodiment, the first nanostructure comprises a first crystalline semiconductor material, wherein the second nanostructure comprises a second crystalline semiconductor material, and wherein the first crystalline semiconductor material is different from the second crystalline semiconductor material. In another embodiment, the first nanostructure comprises an oxide, and wherein the second nanostructure comprises a crystalline semiconductor material. In another embodiment, the step of forming the first nanostructure and the second nanostructure on the substrate includes: forming a silicon-germanium layer on the substrate; forming the second nanostructure on the silicon-germanium layer; forming a dummy gate structure on the second nanostructure; and replacing the silicon-germanium layer with the first nanostructure.

[0154] In one embodiment, the semiconductor device includes a first nanostructure and a second nanostructure located on a substrate; a source / drain region sandwiched between a first sidewall of the first nanostructure and a second sidewall of the second nanostructure; a gate dielectric layer sandwiched between an upper surface of the first nanostructure and a lower surface of the second nanostructure, with the upper surface of the first nanostructure facing the lower surface of the second nanostructure; a gate located between the first nanostructure and the second nanostructure in a cross-sectional view; and an inner spacer located between the first nanostructure, the second nanostructure, the source / drain region, and the gate dielectric layer in a cross-sectional view, wherein the inner spacer includes: a first inner spacer layer located between the first nanostructure, the second nanostructure, the source / drain region, and the gate dielectric layer; and a second inner spacer layer located between the source / drain region and the first inner spacer layer. In another embodiment, the first inner spacer layer comprises silicon carbide. In another embodiment, the second inner spacer layer comprises oxide carbonitride. In another embodiment, the semiconductor device further includes a first oxide material physically contacting the first nanostructure, the first inner spacer layer, and the gate dielectric layer; and a second oxide material physically contacting the second nanostructure, the first inner spacer layer, and the gate dielectric layer. In another embodiment, the second inner spacer layer, in a cross-sectional view, is entirely defined by the source / drain regions and the first inner spacer layer. In another embodiment, the first inner spacer layer includes a gap extending from the first inner spacer layer toward the gate dielectric layer and the gate. In another embodiment, the inner spacer layer does not have a gap.

[0155] In one embodiment, the semiconductor device includes a first nanostructure on a substrate; a second nanostructure on the first nanostructure; a gate and a gate dielectric layer between the first and second nanostructures; a first inner spacer layer between the first and second nanostructures, and the first inner spacer layer is located between the gate dielectric layers, wherein a first sidewall of the first inner spacer layer is flush with a sidewall of the first nanostructure, and a second sidewall of the first inner spacer layer is flush with a sidewall of the second nanostructure; a second inner spacer layer between the first and second nanostructures, wherein a third sidewall of the second inner spacer layer is flush with both the first and second sidewalls; and a source / drain region on the substrate, and the source / drain region is adjacent to the first nanostructure, the second nanostructure, the first inner spacer layer, and the second inner spacer layer. In another embodiment, the first inner spacer layer comprises silicon carbide. In another embodiment, the second inner spacer layer comprises oxide carbonitride. In another embodiment, the second inner spacer layer comprises boron oxide carbonitride. In another embodiment, the first inner spacer layer includes a gap, wherein a first end of the gap is located at the interface between the first inner spacer layer and the second inner spacer layer, and a second end of the gap is located in the substrate portion of the first inner spacer layer. In another embodiment, the first inner spacer layer is U-shaped in cross-sectional view, wherein the second inner spacer layer is located within the U-shape in cross-sectional view, and wherein the second inner spacer layer is triangular in cross-sectional view. In another embodiment, the semiconductor device further includes a first oxide material physically contacting the first nanostructure, the first inner spacer layer, and the gate dielectric layer; and a second oxide material physically contacting the second nanostructure, the first inner spacer layer, and the gate dielectric layer. In another embodiment, the first inner spacer layer does not have a gap.

[0156] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the concept and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the concept and scope of the present invention.

Claims

1. A semiconductor device, characterized in that... include: A first nanostructure and a second nanostructure are located on a substrate; A source / drain region is sandwiched between a first sidewall of the first nanostructure and a second sidewall of the second nanostructure; A gate dielectric layer is sandwiched between the upper surface of the first nanostructure and the lower surface of the second nanostructure, with the upper surface of the first nanostructure facing the lower surface of the second nanostructure. A gate is located between the first nanostructure and the second nanostructure in the cross-sectional view; as well as An inner spacer, located in a cross-sectional view between the first nanostructure, the second nanostructure, the source / drain region, and the gate dielectric layer, and the inner spacer comprises: A first inner spacer layer is located between the first nanostructure, the second nanostructure, the source / drain region, and the gate dielectric layer; as well as A second inner spacer layer is located between the source / drain region and the first inner spacer layer.

2. The semiconductor device as claimed in claim 1, characterized in that... Also includes: A first oxide material is in physical contact with the first nanostructure, the first inner spacer layer, and the gate dielectric layer; as well as A second oxide material is physically in contact with the second nanostructure, the first inner spacer layer, and the gate dielectric layer.

3. The semiconductor device as claimed in claim 1, characterized in that, In the cross-sectional view, the second inner spacer layer is completely defined by the source / drain region and the first inner spacer layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The first inner spacer layer includes a gap extending from the first inner spacer layer toward the gate dielectric layer and the gate.

5. The semiconductor device as claimed in claim 1, characterized in that, The inner spacer contains no gaps.

6. A semiconductor device, characterized in that... include: A first nanostructure is located on a substrate; A second nanostructure is located on the first nanostructure; A gate and a gate dielectric layer are located between the first nanostructure and the second nanostructure; A first inner spacer layer is located between the first nanostructure and the second nanostructure, and the first inner spacer layer is located between the gate dielectric layers. A first sidewall of the first inner spacer layer is flush with the sidewall of the first nanostructure, and a second sidewall of the first inner spacer layer is flush with the sidewall of the second nanostructure. A second inner spacer layer is located between the first nanostructure and the second nanostructure, and a third sidewall of the second inner spacer layer is flush with the first sidewall and the second sidewall; and A source / drain region is located on the substrate, and the source / drain region is adjacent to the first nanostructure, the second nanostructure, the first inner spacer layer, and the second inner spacer layer.

7. The semiconductor device as claimed in claim 6, characterized in that, The first inner spacer layer includes a slit, wherein a first end of the slit is located at the interface between the first inner spacer layer and the second inner spacer layer, and a second end of the slit is located in the matrix portion of the first inner spacer layer.

8. The semiconductor device as claimed in claim 6, characterized in that, The first inner spacer layer is U-shaped in the cross-sectional view, and the second inner spacer layer is located in the U-shape in the cross-sectional view, and the second inner spacer layer is triangular in the cross-sectional view.

9. The semiconductor device as claimed in claim 6, characterized in that... Also includes: A first oxide material is in physical contact with the first nanostructure, the first inner spacer layer, and the gate dielectric layer; as well as A second oxide material is physically in contact with the second nanostructure, the first inner spacer layer, and the gate dielectric layer.

10. The semiconductor device as claimed in claim 6, characterized in that, The first inner spacer layer has no gaps.

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