Semiconductor device

Abstract

A semiconductor device includes a stack of semiconductor layers and a gate structure. The stack of semiconductor layers is disposed over a substrate. The gate structure encloses the stack of semiconductor layers. In a cross-sectional side view, the gate structure includes at least a first portion, a second portion disposed over the first portion, and a third portion disposed over the second portion. The first portion, the second portion, and the third portion have first, second, and third lateral dimensions, respectively. A variation among the first, second, and third lateral dimensions is less than 1.4 nanometers.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor devices. Background Technology

[0002] The electronics industry's demand for smaller, faster electronic devices that can simultaneously support a multitude of increasingly complex and sophisticated functions is constantly growing. To meet these demands, the ongoing trend in the integrated circuit (IC) industry is to manufacture ICs that are low-cost, high-performance, and low-power. To date, these goals have been largely achieved by miniaturizing IC dimensions (e.g., reducing the minimum size of IC components), thereby increasing production efficiency and lowering associated costs. However, this miniaturization also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC devices and their performance require equally advanced IC manufacturing processes and technologies.

[0003] Multi-gate devices have been introduced to improve gate control. They have been observed to increase gate channel coupling, reduce off-state current, and / or reduce short-channel effects (SCE). One such multi-gate device is the gate-all-around (GAA) device, which includes a gate structure that can extend partially or completely around the channel region to provide access to the channel region at least on both sides. GAA devices enable significant scaling of IC technology, maintaining gate control and reducing SCE, while seamlessly integrating with traditional IC manufacturing processes. However, as GAA devices continue to shrink, challenges arise. For example, configuring the lateral dimensions of the metal gate structure in a GAA device can become more difficult, especially as device size shrinks. This can lead to a degraded device performance. Therefore, while existing IC structures and manufacturing techniques are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects. Utility Model Content

[0004] The purpose of this invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0005] This invention provides a semiconductor device, comprising: a stack of semiconductor layers disposed above a substrate; and a gate structure surrounding the stack of semiconductor layers; wherein, in a cross-sectional side view: the gate structure includes at least a first portion, a second portion disposed above the first portion, and a third portion disposed above the second portion; the first portion, the second portion, and the third portion respectively have a first lateral dimension, a second lateral dimension, and a third lateral dimension; and the variation between the first lateral dimension, the second lateral dimension, and the third lateral dimension is less than 1.4 nanometers.

[0006] According to one embodiment of the present invention, the first lateral dimension is smaller than the second lateral dimension or the third lateral dimension; or the second lateral dimension is smaller than the first lateral dimension or the third lateral dimension.

[0007] According to one embodiment of the present invention, in the cross-sectional side view, the ratio between the shortest lateral dimension and the longest lateral dimension among the first lateral dimension, the second lateral dimension and the third lateral dimension is between 0.91:1 and 1:1.

[0008] According to one embodiment of the present invention, it further includes: a first inner spacer disposed on the side of the first portion of the gate structure; a second inner spacer disposed on the side of the second portion of the gate structure; and a third inner spacer disposed on the side of the third portion of the gate structure; wherein the first inner spacer, the second inner spacer, and the third inner spacer have different lateral dimensions.

[0009] According to one embodiment of the present invention, the stacked semiconductor layers have the same first thickness.

[0010] According to one embodiment of the present invention, the difference between the first thicknesses is less than 5%.

[0011] According to one embodiment of the present invention, the gate structure includes a metal gate electrode and a gate dielectric layer.

[0012] According to one embodiment of the present invention, the first inner spacer, the second inner spacer and the third inner spacer have a convex shape.

[0013] According to one embodiment of the present invention, in the cross-sectional side view, the convex shape protrudes toward the gate dielectric layer of the gate structure.

[0014] According to one embodiment of the present invention, the stack of semiconductor layers includes 2 to 10 semiconductor layers. Attached Figure Description

[0015] The various embodiments of this utility model can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily enlarged or reduced.

[0016] Figure 1 This is a flowchart illustrating various methods for manufacturing semiconductor structures according to the present invention.

[0017] Figure 2 This is a top view of a semiconductor structure according to some embodiments of the present invention.

[0018] Figure 3 , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10 and Figures 11A to 12A According to some embodiments of this utility model, along various manufacturing stages Figure 2 A cross-sectional side view of the semiconductor structure along line A-A'.

[0019] Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figures 11B-12B These are some embodiments based on the present utility model. Figure 4A-9A and Figures 11A-12A An enlarged view of a portion of the semiconductor structure.

[0020] Figure 11C These are some embodiments of the present utility model. Figure 11A The semiconductor structure and along Figure 2 A side view of the cross section along line B-B'.

[0021] Figure 13 This is a block diagram of a tool for performing an etching process according to some embodiments of the present invention.

[0022] Figure 14A and Figure 14B This is a cross-sectional side view of a portion of a semiconductor structure according to some embodiments of the present invention.

[0023] Figure 15 These are diagrams related to etching processes according to some embodiments of the present invention.

[0024] Figure 16 and Figures 17A-17C This is a cross-sectional side view of a portion of a semiconductor structure according to some embodiments of the present invention.

[0025] Figure 18A This is a cross-sectional side view of a portion of a semiconductor structure according to some embodiments of the present invention.

[0026] Figure 18B This is a planar top view of a portion of a semiconductor structure according to some embodiments of the present invention.

[0027] Figure 19 This is a circuit diagram of a storage unit according to some embodiments of the present invention.

[0028] Figure 20 This is a block diagram of a semiconductor manufacturing apparatus according to some embodiments of the present invention.

[0029] The attached figures are labeled as follows:

[0030] 100: Method

[0031] 110: Step 120: Step 130: Step 200: Semiconductor Structure

[0032] 201: Isolation Component

[0033] 202: Semiconductor substrate

[0034] 202a: Top surface

[0035] 203: Fins

[0036] 204: Semiconductor layer

[0037] 204a: Core Layer

[0038] 205: Hybrid Layer

[0039] 206: Semiconductor layer

[0040] 206a: Core Layer

[0041] 207: Source / Drain Region

[0042] 208: Source / Drain Groove

[0043] 210: Dummy Gate Stack

[0044] 212: Gate spacer

[0045] 214: Opening

[0046] 216: Dielectric materials

[0047] 216a: Dielectric layer / Dielectric interlayer

[0048] 216b: Dielectric layer

[0049] 218: Bottom Cut

[0050] 220: Internal spacer

[0051] 222: First source / drain layer

[0052] 223: Epitaxial source / drain components

[0053] 224: Second source / drain layer

[0054] 225: Interlayer dielectric (ILD) layer 226: Opening

[0055] 228: Gate Trench

[0056] 230: Gate electrode

[0057] 232: Gate dielectric layer

[0058] 260: Dielectric materials

[0059] 300: Etching process

[0060] 330: Tools

[0061] 330A: Etching Chamber

[0062] 330B: Baking Chamber

[0063] 340: Wafer

[0064] 350: Byproducts

[0065] 350A: Byproduct

[0066] 350B: Byproduct

[0067] 350C: Byproduct

[0068] 360: Heater

[0069] 400: Etching agent particles

[0070] 410: Opening

[0071] 420: Lateral dimension

[0072] 421: Lateral dimension

[0073] 422: Lateral dimension

[0074] 500: Chart

[0075] 510: Curve

[0076] 550: Gate structure

[0077] 552: Gate Structure

[0078] 560: Horizontal dimension

[0079] 561: Lateral dimension

[0080] 562: Lateral dimension

[0081] 600: Angle

[0082] 610: Angle

[0083] 710A: Transistor

[0084] 800: SRAM cell

[0085] 900: Integrated Circuit Manufacturing System

[0086] 902: Entity

[0087] 904: Entity

[0088] 906: Entity

[0089] 908: Entity

[0090] 910: Entity

[0091] 912: Entity

[0092] 914: Entity

[0093] 916: Entity

[0094] 918: Network

[0095] T1: Thickness

[0096] T2: Thickness

[0097] T3: Thickness

[0098] T4: Thickness

[0099] T5: Thickness

[0100] T6: Thickness

[0101] T7: Spacing

[0102] ML: Multi-layer stacking

[0103] BL: Bitline

[0104] BLB: Complementary Bias Line

[0105] WL: Word Line

[0106] Vss: Voltage

[0107] Vcc: Voltage

[0108] SN1: First storage node

[0109] SNB1: Complementary First Storage Node

[0110] PU1: Pull-up transistor

[0111] PU2: Pull-up transistor

[0112] PD1: Pull-down transistor

[0113] PD2: Pull-down transistor

[0114] PG1: Transfer gate transistor

[0115] PG2: Transfer gate transistor

[0116] A-A': section line

[0117] B-B': Section line

[0118] X:X direction

[0119] Y: Y direction

[0120] Z:Z direction Detailed Implementation

[0121] Numerous embodiments or examples are disclosed below for different components of this invention. Reference values ​​and / or letters may be repeated in the various examples described herein. This repetition is for the purpose of brevity and clarity and does not in itself define a relationship between the various disclosed embodiments and / or configurations. Furthermore, specific examples of elements and configurations are described below to simplify this invention. Of course, these are merely examples and are not intended to be limiting. For example, if the following description refers to a first element forming above a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. Furthermore, descriptions of components in this invention forming on, connected to, and / or coupled to another component may include embodiments where these components are formed in direct contact, and may also include embodiments where additional components may be formed between the components such that the components are not in direct contact.

[0122] Furthermore, reference values ​​and / or letters may be repeated in various examples of the present invention. Such repetition is for the purpose of brevity and clarity, and not to indicate a relationship between the different embodiments and / or configurations discussed. Additionally, in the following description of the invention, the formation of a component on, connected to, and / or coupled to another component may include embodiments in which the components are formed in direct contact, and may also include embodiments in which additional components may be formed to insert the component, such that the components do not need to be in direct contact. Moreover, spatially relative terms such as “below,” “under,” “lower,” “above,” “higher,” etc., may be used to facilitate the description of one or more components or the relationship between one or more components or components in the figures. Spatially relative terms are used to include different orientations of the device in use or operation. Furthermore, when words such as “approximately,” “about,” etc., are used to describe a number or a range of numbers, the meaning of such words is to include numbers whose difference from the described number does not exceed ±10%, unless otherwise stated. For example, the phrase “approximately 5 nanometers” includes a size range from 4.5 nanometers to 5.5 nanometers.

[0123] Multi-gate devices (e.g., gate-all-around (GAA) devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). GAA devices can be significantly miniaturized while maintaining gate control and reducing SCEs. However, GAA devices may still face certain manufacturing challenges. For example, it may be difficult to flexibly configure the critical dimension (CD) of the metal gate structure of a GAA device. Generally, a GAA device may comprise a stack of metal gate structure segments, with the top metal gate structure segment having the smallest dimension and the bottom metal gate structure segment having the largest dimension. This profile may be a result of issues related to the etching process performed by laterally etching dummy oxide layers, resulting in etched dummy oxide layers with such a profile (e.g., the top dummy oxide layer is the shortest, and the bottom dummy oxide layer is the longest). The metal gate structure is then formed to replace the dummy oxide layer and thus inherits the profile of the dummy oxide layer. This invention relates to a method performed as part of GAA manufacturing to address the problems discussed above, such that the resulting metal gate structure can achieve a better profile, as discussed in more detail below.

[0124] Now for reference Figure 1The diagram illustrates a flowchart of an example method 100 for manufacturing a semiconductor device. In some embodiments, the semiconductor device is a GAA device, wherein its gate structure or a portion thereof is formed around all sides of the channel region (e.g., around a portion of the channel region). In some cases, the GAA device may also be referred to as a quad-gate device, wherein the channel region has four sides and the gate structure is formed on all four sides. The channel region of the GAA device may include one or more semiconductor layers, each of which may be one of many different shapes, such as wires (or nanowires), sheets (or nanosheets), rods (or nanobars), and / or other suitable shapes. In embodiments, the channel region of the GAA device may have multiple vertically spaced horizontal semiconductor layers (e.g., nanowires, nanosheets, or nanobars) (hereinafter collectively referred to as “nanochannels”), such that the GAA device is a stacked horizontal GAA device. The GAA device proposed herein can be a complementary metal-oxide-semiconductor (CMOS) GAA device, a p-type metal-oxide-semiconductor (pMOS) GAA device, or an n-type metal-oxide-semiconductor (nMOS) GAA device. Furthermore, the GAA device can have one or more channel regions associated with a single continuous gate structure or multiple gate structures. Those skilled in the art will recognize other examples of semiconductor devices that can benefit from the various forms of this invention. For example, other types of metal-oxide-semiconductor field-effect transistors (MOSFETs), such as planar MOSFETs, fin field-effect transistors (FinFETs), and other multi-gate field-effect transistors, can benefit from this invention. The GAA device and its manufacturing method proposed in this invention exhibit desired characteristics, such as reduced doping diffusion, reduced built-in stress, reduced device degradation, improved silicon performance, enhanced current drive, reduced short-channel effect (SCE), and reduced capacitance between adjacent conductive regions (e.g., between the source / drain region and adjacent SiGe residue).

[0125] Method 100 includes step 110, wherein a stack of first semiconductor layers and second semiconductor layers is formed. Each first semiconductor layer has a first material composition. Each second semiconductor layer has a second material composition different from the first material composition. The first semiconductor layers and the second semiconductor layers are interleaved in the stack.

[0126] Method 100 includes step 120, wherein the second semiconductor layer is replaced with a plurality of dielectric layers.

[0127] Method 100 includes step 130, wherein an etching process is performed on the dielectric layer. The etching is performed at a process pressure between about 600 milli-torrs and about 800 milli-torrs or at a process temperature between about 16 degrees Celsius and about 20 degrees Celsius.

[0128] In some embodiments, the etching process is performed in multiple cycles. Each cycle includes an etching step performed in an etching chamber and a baking step performed in a baking chamber. In some embodiments, the etching chamber and the baking chamber are integrated into the same / single tool. In some embodiments, the baking step is performed at a baking temperature in the range of about 120 degrees Celsius to about 130 degrees Celsius. In some embodiments, the etching step generates byproducts from the dielectric layer, and the baking step converts the byproducts into gaseous chemicals that can be removed from the baking chamber. In some embodiments, the etching step is performed using at least in part an etchant comprising HF or NH3, and the byproducts comprise (NH4)2SiF6(s).

[0129] In some embodiments, the etching process laterally etches the dielectric layer without substantially etching the first semiconductor layer.

[0130] It should be understood that method 100 may include steps performed before, during, and / or after steps 110-130. For example, method 100 may include the step of replacing the dielectric layer with a gate structure (e.g., a gate structure comprising a high-k gate dielectric and a metal gate electrode). For the sake of brevity, these steps are not discussed in detail herein.

[0131] refer to Figure 2 and Figure 3 The semiconductor structure 200 manufactured according to various embodiments of the present invention includes a semiconductor substrate 202 and a plurality of fins 203 protruding from the semiconductor substrate 202. The fins 203 are separated by an isolation member 201 and one or more dummy gate stacks 210 disposed above the fins 203.

[0132] In some embodiments, the semiconductor substrate 202 includes a semiconductor material, such as bulk silicon (Si). Optionally or additionally, the semiconductor substrate 202 may also include another elemental semiconductor, such as germanium (Ge) with a crystal structure. The semiconductor substrate 202 may also include compound semiconductors, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), etc. The semiconductor substrate 202 may also include a semiconductor-on-insulator substrate, such as silicon-on-insulator (SOI), silicon-germanium-on-insulator (SiGe-on-insulator (SGOI), or germanium-on-insulator (GOI) substrates.

[0133] A portion of the semiconductor substrate 202 may be doped and referred to as a doped portion. The doped portion may be doped with a p-type dopant such as boron (B) or boron fluoride (BF3), or with an n-type dopant such as phosphorus (P) or arsenic (As). The doped portion may also be doped with a combination of p-type and n-type dopant (e.g., to form a p-type well and an adjacent n-type well). The doped portion may be formed directly on the semiconductor substrate 202 as a p-well structure, an n-well structure, a double-well structure, or using a raised structure.

[0134] In some embodiments, semiconductor layers 204 and 206 (collectively referred to as "multilayer stack" or "ML") are formed over semiconductor substrate 202 in an interleaving or alternating manner and extend vertically from semiconductor substrate 202 (e.g., along...). Figure 3(in the Z direction). For example, semiconductor layer 204 is disposed above semiconductor substrate 202, semiconductor layer 206 is disposed above semiconductor layer 204, another semiconductor layer 204 is disposed above semiconductor layer 206, and so on. In the depicted embodiment, there are three semiconductor layers 206 and three semiconductor layers 204 alternating with each other. However, any suitable number of layers can be present in ML. For example, there can be 2 to 10 semiconductor layers 206 alternating with 2 to 10 semiconductor layers 204 in ML. The material composition of the semiconductor layers 206 and 204 is configured to allow them to have etch selectivity in subsequent etch processes. For example, in some embodiments, semiconductor layer 204 comprises silicon germanium (SiGe), while semiconductor layer 206 comprises silicon (Si). In some other embodiments, semiconductor layer 206 comprises SiGe, while semiconductor layer 204 comprises Si. In the depicted embodiment, each semiconductor layer 206 has substantially the same thickness (e.g., the difference between two semiconductor layers 206 is less than 5%), and these thicknesses are in Figure 3 Described as thickness T1, while each semiconductor layer 204 has substantially the same thickness (e.g., the difference between two semiconductor layers 204 is less than 5%), these thicknesses in Figure 3 The thickness is depicted as T2. T1 and T2 are approximately 2 nanometers (nm) to approximately 12 nm.

[0135] The stacked semiconductor layers 204 and 206 are then patterned into multiple fin structures, for example, patterned as follows: Figure 2 The fins 203 are arranged in an alternating manner. Each fin 203 includes a stack of semiconductor layers 204 and 206 disposed relative to each other. Each fin 203 extends longitudinally (e.g., vertically) in a horizontal direction (e.g., the Y direction) and is separated from each other (e.g., laterally) in different horizontal directions (e.g., the X direction), as shown below. Figure 2 As shown. It should be understood that the X and Y directions are perpendicular to each other, and the Z direction is perpendicular to the plane defined by the X and Y directions (or normal to it). The semiconductor substrate 202 can be aligned with its top surface parallel to the XY plane.

[0136] Fins 203 can be patterned using any suitable method. For example, one or more optical lithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fins. Generally, dual-patterning or multi-patterning processes combine optical lithography with self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins. The patterning step can utilize a variety of etching processes, which may include dry etching and wet etching. The area where the fins are formed will be used to form active devices through subsequent processes and is therefore referred to as the active region. For example, each fin 203 is formed in the active region. Figure 2 Both fins 203 protrude beyond the semiconductor substrate 202 (e.g., the doped portion).

[0137] Semiconductor structure 200 includes isolation component 201, which in some embodiments may include shallow trench isolation (STI) components. Isolation component 201 is formed on semiconductor substrate 202 and surrounds active regions. In some examples, the formation steps of isolation component 201 include etching trenches in the semiconductor substrate 202 between active regions and filling the trenches with one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. Any suitable method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), and / or combinations thereof, may be used to deposit isolation component 201. The isolation member 201 may have a multilayer structure, such as a thermally oxidized liner over the semiconductor substrate 202 and a fill layer (e.g., silicon nitride or silicon oxide) over the thermally oxidized liner. Alternatively, any other isolation member forming technique may be used to form the isolation member 201. Although not shown, in some embodiments, the fin 203 is located above the top surface of the isolation member 201 (e.g., protruding beyond the isolation member 201) and also above the top surface of the semiconductor substrate 202.

[0138] refer to Figure 2 and Figure 3 A dummy gate stack 210 is formed over a portion of each fin 203 and over the isolation member 201 between the fins 203. The dummy gate stacks 210 can be configured to extend longitudinally (e.g., vertically) parallel to each other; for example, each dummy gate stack 210 extends along the X direction, such as... Figure 2 As shown. In some embodiments, each dummy gate stack 210 wraps around the top and side surfaces of each fin 203. The dummy gate stack 210 may comprise polysilicon. In some embodiments, the dummy gate stack 210 further comprises one or more masking layers for patterning the dummy gate electrode layers. The dummy gate stack 210 may undergo a gate replacement process in subsequent processes to form a metal gate, such as a high-k metal gate, as discussed in more detail below. The dummy gate stack 210 may also undergo a second gate replacement process to form a dielectric-dominant gate that electrically isolates the semiconductor structure 200 from adjacent devices. The dummy gate stack 210 may be formed by steps including deposition, optical lithography patterning, and etching processes. The deposition process may include CVD, ALD, PVD, other suitable methods, and / or combinations thereof.

[0139] refer to Figure 3Gate spacers 212 are formed on the sidewalls of the dummy gate stack 210. Gate spacers 212 comprise one or more dielectric materials and may include silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon carbide oxycarbonate (SiOC), silicon oxynitride (SiON), silicon carbonitride oxycarbonate (SiOCN), carbon-doped oxide, nitrogen-doped oxide, porous oxide, or combinations thereof. Gate spacers 212 may comprise a single-layer or multi-layer structure. In some embodiments, each gate spacer 212 may have a thickness in the range of about 3 nm to about 10 nm (e.g., measured in the Y direction). The aforementioned thickness range may be necessary for device performance, particularly for advanced technology nodes. In some embodiments, gate spacers 212 may be formed by depositing a spacer layer (containing dielectric material) over the dummy gate stack 210, followed by an anisotropic etching process to remove a portion of the spacer layer from the top surface of the dummy gate. After the etching process, a portion of the spacer layer on the sidewall surface of the dummy gate stack 210 is substantially retained, becoming the gate spacer 212. In some embodiments, the anisotropic etching process is a dry (e.g., plasma) etching process. Alternatively, the formation step of the gate spacer 212 may also involve chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. In the active region, the gate spacer 212 is formed above the top layer of semiconductor layers 204 and 206. Therefore, the gate spacer 212 may also be interchangeably referred to as top spacer 212. In some examples, one or more material layers (not shown) may also be formed between the dummy gate stack 210 and the corresponding gate spacer 212. As an example, this one or more material layers may include an interface layer and / or a high-k dielectric layer (e.g., having a dielectric constant greater than that of silicon oxide, which has a dielectric constant of approximately 3.9).

[0140] refer to Figure 4A The process involves at least partially removing the exposed portion of fin 203 (i.e., the portion of fin 203 in the source / drain region 207 not covered by the dummy gate stack 210) to form a source / drain trench 208. Depending on the context, the source / drain region may refer individually or collectively to the source or drain. In the depicted embodiment, the etching process completely removes the ML in the source / drain region 207 of fin 203, thereby exposing the substrate portion of fin 203 in the source / drain region 207. Therefore, the source / drain trench 208 has sidewalls defined by the remaining portion of the ML and a bottom defined by the semiconductor substrate 202, which lies beneath the dummy gate stack 210.

[0141] The top surface 202a of the semiconductor substrate 202 is exposed to the source / drain recess 208. In some embodiments, the etching process removes some, but not all, of the ML, such that the source / drain recess 208 has a bottom defined by the semiconductor layer 204 or semiconductor layer 206 in the source / drain region 207. In some embodiments, the etching process may also remove some, but not all, of the substrate portion of the fin 203, such that the source / drain recess 208 extends below the topmost surface of the semiconductor substrate 202. In other words, the top surface 202a is located below the topmost surface of the semiconductor substrate 202. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may use etchants alternately to remove semiconductor layers 204 and 206 separately and alternately. In some embodiments, the parameters of the etching process are configured to selectively etch the ML while minimizing (or even not etching) the dummy gate stack 210 and the gate spacers 212 and / or the isolation components 201. In some embodiments, an optical lithography process, such as that described herein, is performed to form a patterned mask layer covering the dummy gate stack 210 and the gate spacers 212 and / or the isolation member 201, and the etching process uses the patterned mask.

[0142] Figure 4B yes Figure 4A An enlarged view of a portion (within the dashed rectangle) of the semiconductor structure 200. In some embodiments, the semiconductor structure 200 also includes a hybrid layer 205 (also referred to as "transmission layer 205") having a mixture of materials of semiconductor layers 204 and 206. In some embodiments, the hybrid layer 205 is formed by epitaxial growth of semiconductor layers 204 and 206. The ML may include the hybrid layer 205 and core layers 206a and 204a. Core layers 206a and 204a each comprise a relatively high concentration (e.g., greater than 90%) of the materials of semiconductor layers 204 and 206 (e.g., Si or SiGe). Each semiconductor layer 206 may include at least a portion of the core layer 206a and the hybrid layer 205. Each semiconductor layer 204 may include at least a portion of the core layer 204a and the hybrid layer 205.

[0143] In some embodiments, core layer 206a is adjacent to and above hybrid layer 205. In such hybrid layer 205, the concentration of the material (e.g., Si) of core layer 206a gradually decreases from about 90% to about 10% along the Z direction from top to bottom, while the concentration of the material (e.g., SiGe) of core layer 204a gradually increases from about 10% to about 90% along the Z direction from top to bottom. In such embodiments, the atomic percentage of Ge in hybrid layer 205 gradually increases from about 0.005% to about 20% along the Z direction from top to bottom. In some other embodiments, core layer 204a is adjacent to and above hybrid layer 205. In such hybrid layer 205, the concentration of the material (e.g., Si) of core layer 206a gradually increases from about 10% to about 90% along the Z direction from top to bottom, while the concentration of the material (e.g., SiGe) of core layer 204a gradually decreases from about 90% to about 10% along the Z direction from top to bottom. In such an embodiment, the atomic percentage of Ge in the hybrid layer 205 gradually decreases from about 20% to about 0.005% along the Z direction from top to bottom. In some embodiments, the concentration of the material (e.g., Si) of the semiconductor substrate 202 of the bottom hybrid layer 205 gradually increases from about 10% to about 90% along the Z direction from top to bottom, while the concentration of the material (e.g., SiGe) of the core layer 204a gradually decreases from about 90% to about 10% along the Z direction from top to bottom.

[0144] In the depicted embodiment, a core layer 206a adjoining only one of the hybrid layers 205 has a thickness T3 ranging from about 2 nm to about 12 nm; a core layer 206a connecting two hybrid layers 205 has a thickness T6 ranging from about 2 nm to about 12 nm; a core layer 204a connecting two hybrid layers 205 has a thickness T5 ranging from about 2 nm to about 12 nm; and each hybrid layer 205 has a substantially identical thickness (e.g., less than 5% difference) T4, ranging from about 0.1 nm to about 2 nm. T5 may be equal to T6. In some embodiments, T5 is different from T6.

[0145] In some embodiments, each of semiconductor layers 204 and 206 and the hybrid layer 205 has a uniform profile in each XY plane. For example, the concentration of the material (e.g., SiGe) of the core layer 204a is substantially the same across the XY plane spanning one hybrid layer 205. Therefore, the interface between the hybrid layer 205 and the adjacent core layer 204a or 206a extends along the XY plane, and the thickness of each core layer 206a or 204a is substantially the same at different locations in the XY plane. For example, the thickness of the core layer 206a or 204a near the sidewall of the core layer 206a or 204a is substantially the same as the thickness of the core layer 206a or 204a at its center (the portion directly below the dummy gate stack 210) (e.g., a difference of less than 5%). Similarly, the thickness of each hybrid layer 205 is substantially the same at different locations in the XY plane. For example, the thickness of the hybrid layer 205 near the sidewall of the hybrid layer 205 is substantially the same as the thickness of the hybrid layer 205 at the center (the portion directly below the dummy gate stack 210) (e.g., the difference is less than 5%).

[0146] refer to Figure 5A Semiconductor layer 204 (exposed by source / drain recess 208) is selectively removed from ML, thereby forming a suspended semiconductor layer 206 and an opening 214 between vertically (e.g., in the Z direction) adjacent semiconductor layers 206 (or semiconductor substrate 202, if applicable). Specifically, opening 214 is a through opening overlapping the core layer 204a and the hybrid layer 205, and spans between a pair of source / drain regions 207. Figure 5B yes Figure 5A An enlarged view of part of semiconductor structure 200 (within the dashed rectangle).

[0147] In the depicted embodiments, the etching process selectively etches the core layer 204a and the hybrid layer 205, while minimally etching (or even not etching) the core layer 206a, and (in some embodiments) minimally etching (or even not etching) the gate spacer 212. In some embodiments, the core layer 206a remains unetched. In some embodiments, the semiconductor layer 204 is completely removed. In the depicted embodiments, the core layer 204a and the hybrid layer 205 are completely removed, so the remaining semiconductor layer 206 comprises only the core layer 206a. In some other embodiments, the core layer 204a is completely removed, while the hybrid layer 205 is partially removed, so the remaining portions of the core layer 206a and the hybrid layer 205 together form the remaining semiconductor layer 206. For ease of description, the remaining semiconductor layer 206 hereinafter is referred to as the core layer 206a, regardless of whether the hybrid layer 205 is completely removed.

[0148] Various etching parameters can be adjusted to achieve selective etching of the core layer 204a and the hybrid layer 205, such as etchant composition, etching temperature, etchant solution concentration, etching time, etching pressure, source power, radio-frequency (RF) bias, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. For example, an etchant for etching the material of the core layer 204a (in the depicted embodiment, silicon germanium) at a higher rate than the material of the core layer 206a (i.e., the etchant has high etch selectivity relative to the material of the core layer 204a) is selected for the etching process. The hybrid layer 205 comprises a certain concentration of the material of the core layer 204a and can therefore be selectively removed together with the core layer 204a.

[0149] Etching processes may include dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, a dry etching process (e.g., reactive-ion etching (RIE)) uses a fluorine-containing gas (e.g., SF6) to selectively etch the core layer 204a and the hybrid layer 205. In some embodiments, the ratio of the fluorine-containing gas to the oxygen-containing gas (e.g., O2), the etching temperature, and / or the RF power may be adjusted to selectively etch silicon-germanium or silicon. In some embodiments, a wet etching process uses an etching solution comprising ammonium hydroxide (NH4OH) and water (H2O) to selectively etch the core layer 204a and the hybrid layer 205. In some embodiments, a chemical vapor deposition (CVD) process using hydrochloric acid (HCl) selectively etches the core layer 204a and the hybrid layer 205.

[0150] In the depicted embodiment, ML includes three vertically stacked suspended core layers 206a, which provide three channels through which current flows between corresponding epitaxial source / drain components during operation of the semiconductor structure 200. Therefore, the core layers 206a are hereinafter referred to as channel layers 206a. The channel layers 206a are separated from each other by openings 214. The channel layers 206a are also separated from the semiconductor substrate 202 by one of these openings 214. A spacing T7 is defined between the channel layers 206a along the Z-direction. The spacing T7 corresponds to the dimension of the opening 214 along the Z-direction. In the illustrated embodiment, the core layer 204a and the hybrid layer 205 are completely removed, so the spacing T7 is equal to (T5 + 2 * T4), which is the sum of the thicknesses of one core layer 204a and the two hybrid layers 205. In some other embodiments, the core layer 204a is completely removed, while the hybrid layer 205 is partially removed, so the spacing T7 is less than (T5 + 2 * T4). The core layer 204a and the removed hybrid layer 205 can be collectively referred to as non-channel layers. In some embodiments, the spacing of each opening 214 is substantially the same at different locations in the XY plane. For example, the spacing of the openings 214 near the edge (e.g., the portion directly below the gate spacer 212) is substantially the same as the spacing of the openings 214 at the center (e.g., the portion directly below the gate spacer 212) (e.g., less than 5% difference).

[0151] In some embodiments, the spacing T7 is in the range of about 2 nm to about 14 nm. In some embodiments, each channel layer 206a having a nanoscale size and which may be referred to as a “nanowire” (generally referring to a channel layer suspended in such a way that allows a metal gate entity to contact at least two sides of the channel layer, and in a GAA transistor) will allow a metal gate entity to contact at least four sides of the channel layer (i.e., around the channel layer). In such embodiments, the vertical stacking of the suspended channel layers may be referred to as a nanostructure, and Figure 5A and Figure 5B The described process can be referred to as a channel nanowire release process. In some embodiments, after removing the core layer 204a and the hybrid layer 205, an etching process is performed to modify the contour of the channel layer 206a to achieve the desired size and / or desired shape (e.g., cylindrical-shaped (e.g., nanowire), rectangular-shaped (e.g., nanobar), sheet-shaped (e.g., nanosheet)), etc.). This invention further considers embodiments in which the channel layer 206a (nanowire) has a sub-nanometer size according to the design requirements of the semiconductor structure 200.

[0152] refer to Figure 6A Dielectric material 216 is deposited into opening 214 and conformally deposited above source / drain region 207. Figure 6B yes Figure 6A An enlarged view of a portion (within the dashed rectangle) of the semiconductor structure 200. The deposition of the dielectric material can include any suitable method, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), or a combination thereof. In some embodiments, the deposition of the dielectric material includes an atomic layer deposition (ALD) process. The conformal deposition of the dielectric material 216 step can form a layer of dielectric material 216 with a thickness of about 2 nm to about 14 nm. In some embodiments, this thickness is about 2 nm to about 7 nm. In some embodiments, this thickness is about 2 nm to about 5 nm.

[0153] The dielectric material 216 may comprise any suitable material having an etch selectivity different from that of the channel layer 206a. In some embodiments, the dielectric material 216 comprises an oxide material. The dielectric material 216 may comprise at least one of silicon oxide (SiO2, SiO), silicon oxynitride (SiON), aluminum oxide (Al2O3), silicon nitride, SiOC, SiOCN, and combinations thereof. In some embodiments, the dielectric material 216 comprises a composition different from that of the semiconductor layer 204. In some embodiments, the dielectric material 216 comprises less than 0.001% (atomic percentage) of germanium (Ge) or is Ge-free. In some embodiments, the dielectric material 216 is SiGe-free. If the Ge content in the dielectric material 216 is too high (e.g., greater than 1% atomic percentage), subsequent processes may be affected by Ge residues, as described below.

[0154] In some embodiments, unlike semiconductor layers 204 and 206, channel layer 206a and adjacent dielectric material 216 have a clear boundary free of intermix sessions, which refer to mixtures of materials that may include channel layer 206a and dielectric material 216. Channel layer 206a remains substantially unchanged (e.g., less than 5% change) during the following processes, which will be described in further detail below.

[0155] refer to Figure 7AThe dielectric material 216 in the source / drain region 207 is removed, and the portion of the dielectric material 216 between adjacent channel layers 206a (or semiconductor substrate 202, if applicable) is etched through the exposed sidewall surface in the source / drain region 207 by a selective etching process to form undercuts 218 and dielectric layers 216a (or dielectric interposers 216a). Figure 7B yes Figure 7A An enlarged view of part of semiconductor structure 200 (within the dashed rectangle).

[0156] Selective etching can be any suitable process, such as wet etching or dry etching. The extent to which the dielectric material 216 is recessed (or the size of the removed portion) is determined by process conditions (e.g., the duration of exposure of the dielectric material 216 to etching chemicals). In the described embodiment, the duration is controlled such that the dielectric material 216 in the source / drain regions 207 is completely removed, and the sides of the dielectric material 216 between adjacent channel layers 206a (or semiconductor substrate 202, if applicable) are removed, while the central portion of the dielectric material 216 between adjacent channel layers 206a (or semiconductor substrate 202, if applicable) (e.g., dielectric layer 216a) remains substantially unchanged. Figure 7B As shown, the selective etching process produces an undercut 218 that extends the source / drain recess 208 into the region beneath the channel layer 206a and the gate spacer 212.

[0157] In some embodiments, the undercut 218 has as follows Figure 7B The illustrated convex shape. In some embodiments, dielectric layer 216a includes a tip portion extending toward the sidewalls of channel layer 206a (or semiconductor substrate 202, if applicable). In some embodiments, the tip portion extends to directly contact the entire top or bottom surface of channel layer 206a (or semiconductor substrate 202, if applicable). In such embodiments, dielectric layer 216a has sidewalls coplanar with the sidewalls of channel layer 206a.

[0158] Meanwhile, the channel layer 206a is only slightly affected during the selective etching process. For example, prior to the selective etching process, the sides of the channel layer 206a all have a thickness of T3 or T6 (see...). Figure 5BFollowing the selective etching process, the thickness of the side portion of channel layer 206a can vary from approximately 1% to 5% from T3 or T6. The etching selectivity between channel layer 206a and dielectric material 216 is achieved through the different material compositions between these layers. For example, dielectric material 216 can be etched away at a significantly faster rate than channel layer 206a (e.g., approximately 5 times or 10 times faster). Because... Figures 5A-5B The spacing of each opening 214 is substantially the same at different locations on the XY plane, and the channel layer 206a (or semiconductor substrate 202, where applicable) remains substantially unchanged (e.g., less than 5% variation), and the spacing of each undercut 218 along the Z direction is substantially the same as the thickness of each dielectric layer 216a (e.g., less than 5% difference), which is approximately the same as T7.

[0159] As described above, in some embodiments, the selective etching process can be a wet etching process. An etching technique and etchant can be selected to etch the dielectric material 216 without significantly etching the surrounding structure, such as the channel layer 206a. In embodiments, the channel layer 206a comprises Si and the dielectric material 216 comprises an oxide material (e.g., silicon oxide). In embodiments, a hydrofluoric acid (HF) solution, such as dilute hydrofluoric acid (DHF), can be used to selectively etch away the dielectric material 216. For example, the dielectric material 216 can be etched away at a significantly faster rate than the channel layer 206a (e.g., with a selectivity greater than 10). In this way, desired portions of the dielectric material 216 (e.g., the sides of the dielectric material 216 between adjacent channel layers 206a (or semiconductor substrate 202, if applicable)) are removed, while the channel layer 206a remains substantially unchanged. The etching duration is adjusted to control the size of the removed portions of the dielectric material 216. Optimal conditions can be achieved by further adjusting the etching temperature, dopant concentration, and other experimental parameters.

[0160] In some embodiments, selective etching processes may include dry, plasma-free etching processes performed using a suitable etching system, such as a gas chemical etching system available from Tokyo Electron Limited in Tokyo, Japan. In some examples, selective etching processes may include etching using a solution of standard clean 1 (SC-1), ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O), hydrofluoric acid (HF), buffered HF, and / or fluorine-based (F2) etching. In some examples, fluorine-based (F2) etching may include F2 remote plasma etching.

[0161] refer to Figure 8A A second dielectric material is deposited in the substrate 218. The deposition of the second dielectric material forms a spacer layer over the dummy gate stack 210, the gate spacer 212, and over the components defining the source / drain recess 208 (e.g., channel layer 206a, dielectric layer 216a, and semiconductor substrate 202), and includes methods such as CVD, PVD, ALD, high-density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition (MOCVD), remote plasma-enhanced CVD (RPCVD), PECVD, low-pressure chemical vapor deposition (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), electroplating, other suitable methods, or combinations thereof. The spacer layer partially (and in some embodiments, completely) fills the source / drain trench 208. The deposition process is configured to ensure the spacer layer fills the undercut 218. An etching process is then performed to selectively etch the spacer layer to form, as shown... Figures 8A-8B The inner spacer 220 is shown, wherein the channel layer 206a, the dummy gate stack 210, and the gate spacer 212 are etched to a minimum (or not etched at all). In some embodiments, the spacer layer is removed from the sidewalls of the gate spacer 212, the sidewalls of the channel layer 206a, the dummy gate stack 210, and the semiconductor substrate 202. The spacer layer (and therefore the inner spacer 220) comprises a material different from the material of the channel layer 206a and the gate spacer 212 to achieve desired etch selectivity during the etching process. In some embodiments, the spacer layer comprises a material different from the material of the dielectric layer 216a. In some embodiments, the spacer layer comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxynitride). In some embodiments, the spacer layer comprises a low-k dielectric material, such as those described herein. In some embodiments, a dopant (e.g., a p-type dopant, an n-type dopant, or a combination thereof) is introduced into the dielectric material such that the spacer layer comprises the doped dielectric material.

[0162] Figure 8B yes Figure 8AAn enlarged view of a portion (within the dashed rectangle) of the semiconductor structure 200. In the embodiment, the inner spacer 220 fills the undercut 218 and thus has the following characteristics: Figure 8B The convex shape is shown. In such an embodiment, dielectric layer 216a includes a pointed portion between inner spacer 220 and channel layer 206a (or semiconductor substrate 202, if applicable). In some embodiments, the pointed portion extends toward the sidewalls of ML but is not exposed to the source / drain recess 208. In such an embodiment, inner spacer 220 separates dielectric layer 216a from source / drain recess 208. In some other embodiments, although not depicted, the pointed portion extends to directly contact the entire top and / or bottom surface of channel layer 206a (or semiconductor substrate 202, if applicable). In such an embodiment, dielectric layer 216a is exposed to source / drain recess 208 and separates adjacent inner spacer 220 from adjacent channel layer 206a (or semiconductor substrate 202, if applicable). Dielectric layer 216a may have sidewalls coplanar with the sidewalls of channel layer 206a.

[0163] refer to Figures 9A-9B The epitaxial source / drain component 223 is formed in the source / drain groove 208. Figure 9B yes Figure 9A An enlarged view of a portion (within the dashed rectangle) of the semiconductor structure 200. In some embodiments, one source / drain component 223 is a source electrode, and the other source / drain component 223 is a drain electrode. A channel layer 206a extending from one source / drain component 223 to the other source / drain component 223 can form a channel of the semiconductor structure 200. Various processes, including etching and growth processes, can be used to grow the epitaxial source / drain components 223. Each epitaxial source / drain component 223 can comprise multiple layers, such as a first source / drain layer 222 and a second source / drain layer 224. In the depicted embodiment, the epitaxial source / drain component 223 has a top surface substantially aligned with the top surface of the topmost channel layer 206a. However, in other embodiments, the epitaxial source / drain component 223 may alternatively have a top surface extending higher than the top surface of the topmost channel layer 206a (e.g., in the Z direction). In the depicted embodiment, the epitaxial source / drain component 223 occupies the lower portion of the source / drain recess 208 (e.g., the portion defined by the inner spacer 220 and the channel layer 206a), leaving the upper portion of the source / drain recess 208 (e.g., the portion defined by the gate spacer 212) open. In some embodiments, the epitaxial source / drain components 223 may be merged together, for example, along the X direction, to provide a greater lateral width than individual epitaxial components.

[0164] The epitaxial source / drain component 223 may comprise any suitable semiconductor material. For example, the epitaxial source / drain component 223 in an n-type GAA device may comprise Si, SiC, SiP, SiAs, SiPC, or combinations thereof; while the epitaxial source / drain component 223 in a p-type GAA device may comprise Si, SiGe, Ge, SiGeC, or combinations thereof. The epitaxial source / drain component 223 may be in-situ or ex-situ doped. For example, an epitaxially grown Si source / drain component may be doped with carbon to form a silicon:carbon (Si:C) source / drain component, doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain component, or both carbon and phosphorus to form a silicon-carbon-phosphorus (SiCP) source / drain component; an epitaxially grown SiGe source / drain component may be doped with boron. One or more annealing processes may be performed to activate the dopants in the epitaxial source / drain component 223. Annealing processes can include rapid thermal annealing (RTA) and / or laser annealing.

[0165] The epitaxial source / drain component 223 can directly interface with the inner spacer 220 and the sidewalls of the channel layer 206a. During epitaxial growth, semiconductor material grows from the exposed top surface 202a of the semiconductor substrate 202 (e.g., the exposed top surface of the doped region) and from the exposed side surfaces of the channel layer 206a. Notably, during the epitaxial growth process, semiconductor material does not grow from the surfaces of the inner spacer 220 and the gate spacer 212.

[0166] Because the semiconductor layer 204 and the mixed layer 205 have been removed, the SiGe in ML can be neglected (e.g., less than 0.0001% of the total SiGe in the semiconductor layer 204) when the epitaxial source / drain component 223 is formed, reducing doping diffusion to undesirable regions and also reducing built-in stress (e.g., tensile stress and compressive stress) during the process.

[0167] refer to Figure 10An interlayer dielectric (ILD) layer 225 is formed over the epitaxial source / drain components 223 in the remaining space of the source / drain recess 208, and vertically over the isolation component 201. The ILD layer 225 may also be formed along the Y direction between adjacent dummy gate stacks 210, and along the X direction between the epitaxial source / drain components 223. The ILD layer 225 may include a dielectric material, such as a high-k material, a low-k material, or an extremely low-k material. For example, the ILD layer 225 may include SiO2, SiOC, SiON, or a combination thereof. The ILD layer 225 may comprise a single layer or multiple layers and can be formed using suitable techniques, such as CVD, ALD, and / or spin-on techniques. In some embodiments, a contact etch stop layer (CESL) is disposed between the ILD layer 225 and the isolation component 201, the epitaxial source / drain component 223, and the gate spacer 212. The CESL comprises a material different from that of the ILD layer 225, such as a dielectric material different from that of the ILD layer 225, to achieve etch selectivity. For example, when the ILD layer 225 comprises a low-k dielectric material, the CESL comprises silicon and nitrogen, such as silicon nitride or silicon oxynitride. After depositing the ILD layer 225 and / or the CESL, a chemical mechanical planarization (CMP) process and / or other planarization processes may be performed to remove excess portions of the ILD layer 225, thereby planarizing the top surface of the ILD layer 225 until the top (or top surface) of the dummy gate stack 210 is reached. Among other functions, the ILD layer 225 provides electrical isolation between the various components of the semiconductor structure 200.

[0168] ILD layer 225 may be part of a multilayer interconnect (MLI) component disposed above semiconductor substrate 202. The MLI component electrically couples various devices (e.g., GAA transistors, transistors, resistors, capacitors, and / or inductors of semiconductor structure 200) and / or elements (e.g., gate structures and / or epitaxial source / drain components of semiconductor structure 200) such that the various devices and / or elements can operate in a manner specified by the design requirements of semiconductor structure 200. The MLI component includes a combination of dielectric and conductive layers (e.g., metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect components, such as device-level contacts and / or vias, and / or horizontal interconnect components, such as wires. Vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the MLI component. During operation, interconnect components are configured to route signals and / or distribute signals (e.g., clock pulse signals, voltage signals, and / or ground signals) between devices and / or components of semiconductor structure 200 to devices and / or components.

[0169] refer to Figures 11A-11C The dummy gate stack 210 is selectively removed using any suitable optical lithography and etching process. In some embodiments, the optical lithography process includes forming a photoresist layer, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask element that exposes the area including the dummy gate stack 210. The dummy gate stack 210 is then selectively etched using the mask element. In some other embodiments, the gate spacer 212 may be used as a mask element or part thereof. For example, the dummy gate stack 210 may include polysilicon, the gate spacer 212 and the inner spacer 220 may include a dielectric material, and the channel layer 206a includes a semiconductor material. Thus, etching selectivity can be achieved by selecting suitable etching chemicals so that the dummy gate stack 210 can be removed without substantially affecting the components of the semiconductor structure 200. The removal of the dummy gate stack 210 creates a gate trench 228. The gate trench 228 exposes the top and side surfaces of the stack of channel layer 206a and dielectric layer 216a. In other words, the channel layer 206a and the dielectric layer 216a are exposed on at least two sides of the gate trench 228. In addition, the gate trench 228 also exposes the top surface of the isolation member 201.

[0170] refer to Figures 11A-11CAlternatively, a wet or dry etching process can be used to selectively remove the dielectric layer 216a through the gate trench 228. The etching chemicals are selected such that the dielectric layer 216a has a sufficiently different etch rate compared to the channel layer 206a, the inner spacer 220, and the gate spacer 212. In this way, the channel layer 206a, the inner spacer 220, and the gate spacer 212 remain substantially unchanged. This selective etching process may include one or more etching steps.

[0171] like Figures 11A-11C As shown, in this embodiment, the removal of dielectric layer 216a forms a suspended channel layer 206a and an opening 226 between vertically adjacent layers (e.g., in the Z direction), thereby exposing the top and bottom surfaces of the channel layer 206a. Each channel layer 206a is now circumferentially exposed in the XZ plane. Furthermore, a portion of the doped region of the semiconductor substrate 202 beneath the channel layer 206a is also exposed in the opening 226.

[0172] exist Figures 11A-11C In the example shown, the gate trench 228 and the opening 226 perpendicular to the gate trench 228 (e.g., along the Z direction) together form an opening with a vertical profile. In other words, the opening formed by the gate trench 228 and its corresponding opening 226 has vertical sidewalls. In some embodiments, such an opening with vertical sidewalls can be formed by multiple etching processes. For example, the etching chemical used in the etching process for removing the dummy gate stack 210 and thereby forming the gate trench 228 may include hydrogen bromide (HBr), which combines with chlorine (Cl2), tetrafluoromethane (CF4), oxygen, or combinations thereof. Furthermore, the etching process for selectively removing the dielectric layer 216a and thereby forming the opening 226 may have an initial etching chemical comprising hydrogen bromide (HBr) combined with chlorine (Cl2), oxygen, or combinations thereof. This initial etching chemical reaction is followed by a subsequent etching chemical reaction, which includes hydrogen bromide (HBr) combined with tetrafluoromethane (CF4), oxygen, or combinations thereof, resulting in a vertical profile of the opening formed by the gate trench 228 and its corresponding opening 226.

[0173] Figure 11B yes Figure 11A An enlarged view of a portion (within the dashed rectangle) of the semiconductor structure 200. In some embodiments, the removal process removes only some of the dielectric layer 216a, rather than all of it. A portion of the dielectric layer 216a may remain between the inner spacer 220 and the channel layer 206a (or the semiconductor substrate 202, if applicable). Such a remaining portion may be referred to as the "residual dielectric layer 216b".

[0174] In some embodiments, the remaining dielectric layer 216b does not contain SiGe. In conventional processes, non-channel layers containing SiGe are typically used. After the epitaxial source / drain components are formed, most of the non-channel layers are removed, but SiGe residue may remain between adjacent channel layers, resulting in undesirable capacitance between the SiGe residue and adjacent conductive components. In this invention, the semiconductor layer 204 and the mixed layer 205 have been removed, so the SiGe in ML is negligible (e.g., less than 0.0001% of the total SiGe in semiconductor layer 204). Therefore, the capacitance between SiGe and other conductive components (e.g., epitaxial source / drain components 223) is reduced or negligible.

[0175] In some embodiments, the etch selectivity of the dielectric layer 216a to the channel layer 206a can be higher than that of the semiconductor layer 204 to the channel layer 206a in conventional processes. In some embodiments, the etch selectivity of the dielectric layer 216a to the channel layer 206a is greater than 10 when the dielectric layer 216a is removed. If the etch selectivity of the dielectric layer 216a to the channel layer 206a is too low, the channel layer 206a may be etched, which may reduce the thickness and / or width of the channel layer 206a, potentially affecting the performance of the semiconductor structure 200 (e.g., more SCE, higher capacitance).

[0176] Figure 11C yes Figure 11A Semiconductor structure 200 along Figure 2 The cross-sectional view along line B-B'. In some embodiments, the channel layer 206a experiences no width loss or only a very small width loss during the removal of the dielectric layer 216a. This can be attributed to the etch selectivity of the dielectric layer 216a on the channel layer 206a, and / or the clear boundary between the channel layer 206a and the adjacent dielectric material 216 without any mixing portions, as previously described. In some embodiments, the width of the channel layer 206a along the X direction is equal to or less than 2% of the width along the X direction of the bottom of the fin 203 (e.g., the portion of the semiconductor substrate 202 that the fin 203 contacts). In other words, the width loss of the channel layer 206a during the process is negligible, which improves device performance and reduces capacitance.

[0177] refer to Figures 12A-12BA metal gate stack is formed. The metal gate stack includes a gate dielectric layer 232 and a gate electrode 230 disposed above the gate dielectric layer 232. For example, the metal gate stack may include a polysilicon gate electrode above a SiON gate dielectric layer. As another example, the metal gate stack may include a metal gate electrode located above a high-k dielectric layer. In some cases, a refractory metal layer may be interposed between the metal gate electrode (e.g., an aluminum gate electrode) and the high-k dielectric layer. As yet another example, the metal gate stack may include a silicide. The gate dielectric layer 232 is formed between the gate electrode 230 and the channel formed by the channel layer 206a.

[0178] In some embodiments, a gate dielectric layer 232 is conformally formed on the semiconductor structure 200. The gate dielectric layer 232 at least partially fills the gate trench 228. In some embodiments, a dielectric interface layer may be formed over the channel layer 206a prior to the formation of the gate dielectric layer 232. This dielectric interface layer improves the adhesion between the channel layer 206a and the gate dielectric layer 232. In the example described in this invention, such a dielectric interface layer is omitted. Instead, in the illustrated embodiment, the gate dielectric layer 232 is formed around the exposed surface of each channel layer 206a such that it wraps around the channel layer 206a 360 degrees. Additionally, the gate dielectric layer 232 also directly contacts the vertical sidewalls of the inner spacer 220, the sidewalls of the remaining dielectric layer 216b, and the vertical sidewalls of the gate spacer 212. The gate dielectric layer 232 may comprise a dielectric material having a dielectric constant greater than that of SiO2, which has a dielectric constant of approximately 3.9. For example, the gate dielectric layer 232 may include hafnium oxide (HfO2) with a dielectric constant in the range of about 18 to about 40. As various other examples, the gate dielectric layer 232 may include ZrO2, Y2O3, La2O5, Gd2O5, TiO2, Ta2O5, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, SrTiO, or combinations thereof. The gate dielectric layer 232 can be formed by any suitable process, such as CVD, PVD, ALD, or combinations thereof.

[0179] After forming the gate dielectric layer 232, a gate electrode 230 is formed above the gate dielectric layer 232 to fill the remaining space of the gate trench 228. The gate electrode 230 may comprise any suitable material, such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum aluminum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), nickel (Ni), platinum (Pt), or combinations thereof. In some embodiments, CMP is performed to expose the top surface of the ILD layer 225. The gate dielectric layer 232 and the gate electrode 230 together form a metal gate stack that engages multiple layers (e.g., multiple nanochannels) within the channel layer 206a.

[0180] Figure 12B yes Figure 12A An enlarged view of a portion of the semiconductor structure 200 (within the dashed rectangle). As previously described in this invention, the thickness of each channel layer 206a along the Z direction is substantially the same at different locations in the XY plane, and the channel layers 206a remain substantially unchanged throughout the process. Therefore, after the metal gate stack is formed, the thickness of each channel layer 206a along the Z direction remains substantially the same at different locations in the XY plane (e.g., the difference is less than 5%). If the thickness of each channel layer 206a along the Z direction is not substantially the same at different locations in the XY plane (e.g., the difference is less than 5%), for example, the thickness at the edge (e.g., closer to the epitaxial source / drain components) is greater than 10% of the thickness at the center (e.g., directly below the metal gate stack above ML), undesirable capacitance may increase. In conventional processes, non-channel layers, including SiGe, are typically removed after the formation of the epitaxial source / drain components and before the formation of the metal gate stack. The removal step of the non-channel layers includes multiple etching steps for removing the mixed layer. These multiple etching steps can lead to a reduction in the width of the channel layer (e.g., width along the x-direction), and the channel layer at the edges (e.g., closer to the epitaxial source / drain components) is thicker than the channel layer at the center (e.g., directly below the metal gate stack above the ML), negatively impacting device performance (e.g., increasing SCE) and adding undesirable capacitance. Furthermore, the SiGe in the ML of this invention is negligible (e.g., less than 0.0001% of the total SiGe in semiconductor layer 204), thus the amount of Ge oxide formed during the process is negligible, reducing the interface trap effect.

[0181] In some embodiments, such as Figure 12BAs shown, in each opening 226 between two adjacent channel layers 206a (or semiconductor substrate 202, where applicable) (referred to as "top channel layer 206a" and "bottom channel layer 206a"), at least one residual dielectric layer 216b (referred to as "top residual dielectric layer 216b" or "bottom residual dielectric layer 216b") directly contacts the top channel layer 206a or the bottom channel layer 206a. The top residual dielectric layer 216b and / or the bottom residual dielectric layer 216b are in the following positions: Figure 12B The cross-sectional view may have a triangle-like shape. In some embodiments, the sidewalls of the top residual dielectric layer 216b and / or the bottom residual dielectric layer 216b intersect with the top channel layer 206a and / or the bottom channel layer 206a, the adjacent inner spacer 220, and the adjacent gate dielectric layer 232, respectively. In some other embodiments, although not shown, in addition to intersecting with these interfaces, the top residual dielectric layer 216b and / or the bottom residual dielectric layer 216b extends to contact the adjacent epitaxial source / drain component 223. In such an embodiment, the adjacent inner spacer 220 is separated from the top channel layer 206a and / or the bottom channel layer 206a by the top residual dielectric layer 216b and / or the bottom residual dielectric layer 216b.

[0182] In some embodiments, the top residual dielectric layer 216b and / or the bottom residual dielectric layer 216b extend between one of the inner spacers 220 (the first inner spacer 220) and the gate dielectric layer 232. In some embodiments, the top residual dielectric layer 216b and the bottom residual dielectric layer 216b are separated by the first inner spacer 220 and the gate dielectric layer 232 of the metal gate stack. In some other embodiments, the top residual dielectric layer 216b extends and merges with the bottom residual dielectric layer 216b. In some embodiments, the top residual dielectric layer 216b extends to the top channel layer 206a. The top surface of the top residual dielectric layer 216b and the top surface of the gate dielectric layer 232 may be coplanar and may be in direct contact with the bottom surface of the top channel layer 206a. Similarly, the bottom residual dielectric layer 216b extends to the bottom channel layer 206a. The bottom surface of the bottom residual dielectric layer 216b and the bottom surface of the gate dielectric layer 232 can be coplanar and can be in direct contact with the top surface of the bottom channel layer 206a.

[0183] After forming the gate dielectric layer 232 and the gate electrode 230, a planarization process is performed to remove excess gate material from the semiconductor structure 200. For example, a CMP process is performed until the top surface of the ILD layer 225 is exposed, such that after the CMP process, the top surface of the metal gate stack is substantially planar with the top surface of the ILD layer 225. Therefore, the semiconductor structure 200 may include a GAA transistor having a metal gate stack surrounding a corresponding channel layer 206a, such that the metal gate stack is disposed between corresponding epitaxial source / drain components 223.

[0184] Manufacturing can continue to produce semiconductor structure 200. For example, various contacts can be formed to facilitate the operation of the GAA transistor. For example, one or more ILD layers, such as ILD layer 225 and / or CESL layers, can be formed over semiconductor substrate 202 (specifically, over ILD layer 225 and the metal gate stack). Contacts can then be formed in ILD layer 225 and / or in the ILD layers disposed above ILD layer 225. For example, a contact is electrically coupled and / or physically coupled to the metal gate stack, and another contact is electrically coupled and / or physically coupled to the source / drain region of the GAA transistor (specifically, epitaxial source / drain component 223). The contacts include conductive materials, such as metals. Metals include aluminum, aluminum alloys (e.g., aluminum / silicon / copper alloys), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, other suitable metals, or combinations thereof. Metal silicides may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, rubidium silicide, palladium silicide, or combinations thereof. In some embodiments, the ILD layer disposed above the ILD layer 225 and the contact (e.g., extending through ILD layer 225 and / or other ILD layers) is part of the aforementioned MLI component.

[0185] Other manufacturing processes can be applied to the semiconductor structure 200 and can be implemented before, during, or after the aforementioned processes. These include various process steps for forming interconnect structures from the front side of the semiconductor substrate 202 above the GAA transistors to electrically connect various circuit elements. The interconnect structure includes metal lines distributed across multiple metal layers (e.g., a first metal layer, a second metal layer, a third metal layer, etc., from bottom to top) to provide horizontal wiring and contact components (between the substrate and the first metal layer, and via components (between metal layers)) to provide vertical wiring. The semiconductor structure 200 also includes other elements, such as other conductive components (e.g., redistribution layers or RDLs), passivation layers to provide a sealing effect, and / or bonding structures to provide an interface between the semiconductor structure 200 and a circuit board (e.g., a printed circuit board) to be formed on the interconnect structure.

[0186] While not intended to be limiting, embodiments of this invention offer benefits to semiconductor processes and semiconductor devices. For example, by removing the non-channel layer, including the transition layer, prior to the formation of epitaxial source / drain components, SiGe residue becomes negligible before the formation of the epitaxial source / drain components, thereby reducing aberrant doping diffusion and built-in stress (e.g., tensile and compressive stress) in subsequent processes. Early removal of the transition layer can also reduce unintended capacitance and device degradation, avoid channel layer width loss, thereby improving device performance, reducing short-channel effect (SCE), and can lead to higher current drive and higher logic density.

[0187] However, certain improvements can still be made to the semiconductor structure 200 and its fabrication. For example, although the figures discussed above can represent different dielectric materials 216a in a stack (see Figure 200), the semiconductor structure 200 and its fabrication can still be improved. Figure 7A ) and gate structure (including metal gate electrode 230 and gate dielectric layer 232, see Figure 12A The examples shown are of the same dimensions in the stack for simplicity and may not actually represent the outline of the dielectric material 216a or the gate structure segment in the actual device. Often, the manufacturing process performed to form the semiconductor structure 200 can result in a tapered outline of the dielectric material 216a and the gate structure segment that eventually replaces the dielectric material 216a.

[0188] For example, the topmost dielectric material 216a and the corresponding topmost gate structure segment may have the shortest lateral dimension in the Y direction, the bottommost dielectric material 216a and the corresponding bottommost gate structure segment may have the longest lateral dimension in the Y direction, and the middle dielectric material 216a and the corresponding middle gate structure segment may have a lateral dimension between the shortest and longest in the Y direction. Such a distribution may not allow the device implementing the semiconductor structure 200 to achieve optimal performance and / or yield. To address this issue, various embodiments of the present invention also relate to lateral etching of the dielectric material 216 to form an undercut 218 (see...). Figure 7A Improvements to the etching process. For example, the etching process may include multiple etching-baking cycles, wherein each etching cycle is performed using etching parameters (e.g., etching temperature and / or pressure and / or baking time), which are specifically configured to adjust the profile of the dielectric material 216a in the stack, as discussed in more detail below.

[0189] Now for reference Figure 13Etching process 300 is performed as part of the fabrication of semiconductor structure 200. In some embodiments, etching process 300 may be performed to laterally etch dielectric material 216 to form undercut 218 (see [link]). Figure 7A The etching process 300 may include multiple etch-bake cycles performed using a tool 330 comprising an etch chamber 330A and a bake chamber 330B. The etching step in each cycle is performed in the etch chamber 330A, and the bake step in each cycle is performed in the bake chamber 330B.

[0190] For more details, please refer to the above. Figures 6A-6B The manufacturing steps are discussed later, but refer to the above. Figures 6A-6B Prior to the manufacturing steps discussed, one or more wafers 340 on which the semiconductor structure 200 is formed are placed in an etching chamber 330A. The wafer 340 thus includes dielectric material 216 formed in a vertically stacked manner, the dielectric material 216 being interleaved with the semiconductor layer 206 in the Z direction. In some embodiments, the dielectric material 216 comprises silicon dioxide (SiO2), which can be etched away using an etchant comprising hydrofluoric acid (HF) and / or ammonia (NH3). Thus, the etching step is performed at least in part by applying HF and / or NH3 as an etchant in the etching chamber 330A. According to various embodiments of the present invention, the etching step is performed at relatively low temperatures and relatively high pressures. In some embodiments, the temperature for performing the etching step is in the range of about 16 degrees Celsius to about 20 degrees Celsius, for example, at about 18 degrees Celsius. In some embodiments, the pressure for performing the etching step is in the range of about 600 milli-torrs to about 800 milli-torrs, for example, at about 700 milli-torrs. These process parameters are not randomly selected, but are specifically configured to optimize the lateral etching profile of the dielectric material 216, as will be discussed in more detail below.

[0191] Dielectric material 260 (e.g., SiO2) reacts with an etchant (e.g., HF and / or NH3) to form byproduct 350 on the surface of wafer 340. In some embodiments, byproduct 350 comprises ammonium fluorosilicate ((NH4)2SiF6(s)). Byproduct 350 is then removed in a baking step of etching process 300. For example, in each cycle of etching process 300, after the etching step is completed, one or more wafers 340 may be sent to baking chamber 330B of tool 330. Baking chamber includes one or more heaters 360, on which wafers 340 are placed. One or more heaters 360 generate heat, and the heat generated by heaters 360 may be controlled to configure the temperature inside baking chamber 330B.

[0192] In some embodiments, the baking step is performed at a baking temperature in the range of about 120 degrees Celsius to about 130 degrees Celsius, for example, at about 125 degrees Celsius. The baking step is also performed for a baking duration in the range of about 18 seconds to about 22 seconds, for example, about 20 seconds. It is understood that the above baking time is specifically configured to adjust the amount of byproducts remaining on the dielectric layers 216a in the stack (e.g., the top or middle of the dielectric layers 216a), which will help affect the etching of these dielectric layers 216a, as will be discussed in more detail below. The baking step converts the byproducts 350 into gaseous products, which can then be removed from the baking chamber 330B. At the end of each baking step, one or more wafers 340 can be returned to the etching chamber 330A for subsequent etching steps of the etching process 300.

[0193] Etching process 300 may include multiple etching and baking cycles until the desired profile of the lateral groove (e.g., undercut 218) is achieved. More specifically, the stacked dielectric layer 216a formed due to etching process 300 (see...) Figure 7A The dielectric layers 216a may have adjustable lateral dimensions in the Y direction. In some embodiments, the lateral dimensions of the dielectric layers 216a in the Y direction are adjusted so that they are substantially uniform with each other. For example, in some embodiments, the ratio between a shortest lateral dimension and a longest lateral dimension in the dielectric layers is in the range of about 0.91:1 to about 1:1 in a cross-sectional view, and the variation between the various lateral dimensions of the dielectric layers 216a is less than 1.4 nanometers.

[0194] The ability to configure the etch profile of dielectric layer 216a is at least partly attributable to the specific etch process parameters of this invention. For example, refer to Figure 14A and Figure 14B This illustrates a schematic cross-sectional view of a portion of a semiconductor structure 200. Figure 14A In this process, the semiconductor structure 200 is etched at relatively low pressure and relatively high temperature. Under these process conditions, the etchant (represented by etchant particles 400) may not penetrate deeply enough into the opening 410. In other words, the etchant particles 400 may be distributed more at or near the top layer of dielectric layer 216a than at the bottom layer. Therefore, the top layer of dielectric layer 216a may undergo more etching than the bottom layer, which can result in an etch profile of the semiconductor structure 200 where the top dielectric layer 216a has the smallest lateral dimension in the Y direction and the bottom dielectric layer 216a has the largest lateral dimension. If the difference between these lateral dimensions becomes too large, device performance and / or yield may be affected.

[0195] In contrast, at relatively low temperatures (e.g., between 16°C and 20°C) and / or relatively high process pressures (e.g., between 600 mTorr and 800 mTorr), the etchant particles 400 can be more uniformly distributed within the opening 410, even at the bottom of the opening 410. Furthermore, due to these process conditions, the etchant particles 400 are also able to remain at the bottom of the opening 410 for a longer period and react more readily with the etchant. Therefore, all dielectric layers 216a in the stack can undergo a more uniform amount of etching, resulting in an etch profile of the semiconductor structure 200 in which the top dielectric layer 216a, the middle dielectric layer 216a, and the bottom dielectric layer 216a have more consistent lateral dimensions.

[0196] For example, such as Figure 14B As shown, the top dielectric layer 216a, the middle dielectric layer 216a, and the bottom dielectric layer 216a have lateral dimensions 420, 421, and 422, respectively. Lateral dimensions 420-422 are measured across the narrowest portion of the corresponding dielectric layer 216a in the Y direction (because the undercut 218 may not have perfectly vertical sidewalls). In other words, lateral dimensions 420-422 can be considered as the smallest lateral dimension of the corresponding dielectric layer 216a in the Y direction. For the sake of uniformity, it is assumed that lateral dimension 421 is the shortest, lateral dimension 422 is the longest, and lateral dimension 420 lies between lateral dimensions 421 and 422. In such an embodiment, the ratio between lateral dimensions 421 and 422 is in the range of approximately 0.91:1 to approximately 1:1, and the amount of variation (in absolute value) between lateral dimensions 421 and 422 is less than 1.4 nanometers.

[0197] The greater uniformity in lateral dimensions between 420 and 422 is also partly attributed to byproduct 350 (see reference above), which was used as an etch stop layer in this paper. Figure 13 (See the discussion). For more details, see [link to relevant documentation]. Figure 15 Figure 500 illustrates various aspects of the etching process 300 considering the impact of byproducts 350, as discussed above. Figure 500 includes a horizontal axis (by... Figure 15 The X-axis (represented by) and the vertical axis (represented by) Figure 15 (Represented by the Y-axis in the diagram). Please note that... Figure 15 The X and Y axes in this diagram are intended to represent the two-dimensional representation of Figure 500 and should not be confused with the X and Y axes in the preceding figures. In any case, Figure 15 The X-axis in the diagram can represent time, for example, how much time has elapsed during the etching step in each etch-bake cycle of etching process 300. Figure 15 The Y-axis in the figure can represent the amount of etching, for example, the amount of dielectric layer 216 etched during the etching step. Thus, Figure 15Curve 510 in the figure represents the degree to which dielectric layer 216a is etched over time.

[0198] like Figure 15 As shown, in the early stages of the etching step, dielectric layer 216a is etched relatively quickly because there is nothing blocking its etching. Over time, byproducts 350 begin to form due to a chemical reaction between the etchant HF / NH3 and the material of dielectric layer 216a (e.g., SiO2). When byproducts 350 accumulate on dielectric layer 216a (e.g., in…),… Figure 14B When the etchant forms on the sidewalls of dielectric layer 216a, it begins to interfere with the chemical reaction between the etchant and dielectric layer 216a. As a result, the etching of dielectric layer 216a may begin to slow down. In the later stages of the etching step, a large amount of byproduct 350 may form on the sidewalls of dielectric layer 216a, which may lead to etch saturation, meaning that at this point, the etching of dielectric layer 216a is minimal (if any). In this way, byproduct 350 can act as an etch stop layer, because once the byproduct 350 reaches a sufficient thickness, it at least prevents or otherwise reduces the etching of dielectric layer 216a.

[0199] The etch-blocking properties of byproduct 350 also allow for flexible adjustment of the stacked profile of the resulting dielectric layer 216a. For example, now referring to... Figure 16 The diagram illustrates a schematic partial cross-sectional view of a portion of a semiconductor structure 200. The portion of semiconductor structure 200 shown includes an example stack of dielectric layers 216a interleaved with semiconductor layer 206a in the Z direction. Depending on various embodiments of the invention, certain process parameters can be adjusted to configure the formation of byproduct 350 (e.g., relative to its formation location and / or thickness in the Y direction). For example, at lower etching temperatures and / or higher etching pressures (e.g., for the etching steps of the etching process 300 described above), byproduct 350 is more likely to form on the top of the stack and less likely to form at the bottom of the stack.

[0200] exist Figure 16In the illustrated embodiment, byproduct 350A (formed on the side surface of the top dielectric layer 216a) has the maximum thickness in the Y direction, byproduct 350B (formed on the side surface of the middle dielectric layer 216a) has an intermediate thickness in the Y direction, and byproduct 350C (formed on the side surface of the bottom dielectric layer 216a) has the minimum thickness in the Y direction. Due to the thickness difference between byproducts 350A and 350C, byproduct 350A may have the most significant etch-blocking effect, byproduct 350B may have a moderate etch-blocking effect, and byproduct 350C may have the least significant etch-blocking effect. As described above, during the etching step of etching process 300, the general trend is that the etching of dielectric layer 216 is more significant at the top of the stack but less significant at the bottom of the stack, even if the etching process parameters are adjusted to allow the etchant particles to penetrate deeper to reach the dielectric layer 216a located at the bottom of the stack. Here, the fact that byproducts 350A-350C can help prevent the etching of the top dielectric layer 216a more than the etching of the bottom dielectric layer 216a can help compensate for the overall trend that the top dielectric layer 216a is etched more than the bottom dielectric layer 216a. As a result, the resulting dielectric layer 216a can have more uniform lateral dimensions. For example, in one embodiment where the etching temperature is in the range of about 16 degrees Celsius to about 20 degrees Celsius and the etching pressure is in the range of about 600 mTorr to about 800 mTorr, for the resulting semiconductor structure 200, in a cross-sectional side view, the ratio between the shortest of the lateral dimensions 420-422 and the longest of the lateral dimensions 420-422 is in the range of about 0.91:1 to about 1:1, and the variation between the shortest and longest dimensions of the lateral dimensions 420-422 is less than 1.4 nanometers.

[0201] Please note that the amount of baking time in each cycle of the etching process 300 can also be configured to adjust the profile of the dielectric layer 216a. This is because baking removes byproducts 350, and the length of the baking time affects the removal of byproducts 350, thereby affecting the etching of the dielectric layer 216a. In embodiments where the baking time is between approximately 18 seconds and approximately 22 seconds, such a baking duration helps to promote the uniformity of the lateral dimensions of the resulting dielectric layer 216a. Furthermore, such a relatively short baking duration helps to avoid unintentional damage to epitaxial layers (e.g., source / drain components).

[0202] It should be understood that Figure 16The examples shown are merely for illustrative purposes to facilitate the above discussion and may not represent the actual semiconductor structure 200 to precise scale. For example, in some embodiments, etching process parameters (e.g., temperature and / or pressure) can be adjusted such that very few (if any) byproducts 350C are formed on the sides of the bottom dielectric layer 216a, which would allow the bottom dielectric layer to be etched more thoroughly. In this embodiment, the bottom dielectric layer 216a may have the smallest lateral dimension 422 among the three lateral dimensions 420-422. In some other embodiments, the formation of byproducts 350A-350C may also be configured such that the middle layer of dielectric layer 216a may have the shortest lateral dimension 421 among the three lateral dimensions 420-422. The ability to achieve different profiles of the stacked dielectric layers 216a allows for greater design and / or manufacturing flexibility.

[0203] As referenced above Figure 12A As discussed, the final dielectric layer 216a will be replaced by a gate structure including a gate electrode 230 and a gate dielectric layer 232. Therefore, the gate structure of the semiconductor structure 200 can at least partially represent the outline and / or dimensions of the dielectric layer 216a. Since the outline of the dielectric layer 216 can be flexibly configured, it also means that the outline of the corresponding gate structure can also be flexibly configured. For example, now referring to… Figures 17A-17C The figure above illustrates a partial schematic cross-sectional view of a semiconductor structure 200 according to various embodiments. The illustrated portion of the semiconductor structure 200 includes a semiconductor substrate 202, source / drain components 223, inner spacers 220, an ILD 225, a gate electrode 230, a gate dielectric layer 232, gate spacers 212, etc., as shown in the figure above. Figure 1 As discussed in A, the illustrated portion of semiconductor structure 200 also includes a semiconductor layer stack 206a staggered in the Z direction with gate structures 550-552. Gate structures 550-552 may each include a corresponding gate dielectric layer 232 and a corresponding gate electrode 230. Figures 17A-17C In the different embodiments shown, the gate structures 550-552 may have different lateral dimensions.

[0204] For example, gate structures 550-552 each have lateral dimensions 560-562. Figure 17A In some embodiments, the process parameters of the etching process 300 can be configured (e.g., by adjusting the process temperature and / or pressure of the etching step and / or by adjusting the baking time of the baking step) so that the lateral dimensions 560-562 can be substantially identical to each other. Meanwhile, in Figure 17B In the embodiments described, the process parameters of the etching process 300 can be configured such that the lateral dimension 561 is smaller than the lateral dimension 560 and / or the lateral dimension 562. Figure 17CIn the embodiments described, the process parameters of the etching process 300 can be configured such that the lateral dimension 562 is smaller than the lateral dimension 561, wherein the lateral dimension 561 is smaller than the lateral dimension 560. Other suitable profiles of the gate structure are also conceivable, but for the sake of brevity, they are not specifically shown here. As described above, Figures 17A-17C Each gate structure profile shown may be useful or beneficial for a specific type of IC application. Therefore, this invention provides versatility in design and / or manufacture.

[0205] Note that due to the different lateral dimensions 560-562 of the gate structures 550-552, their corresponding adjacent inner spacers 220 can also have different lateral dimensions in the Y direction. This is because the overall size of each set of inner spacers 220 and its corresponding gate structures 560-562 is defined by the distance between the two source / drain components 223 located on opposite sides, and this distance does not substantially change. Therefore, longer gate structures are typically compensated for by shorter inner spacers, and vice versa.

[0206] Figure 18A and Figure 18B Various angles formed during the manufacturing process of the semiconductor structure 200 of this invention are illustrated. More specifically, Figure 18A This is a rough cross-sectional view of a portion of a semiconductor structure 200, including a dielectric layer 216a (which may include low-temperature oxide (LTOX) elements and elements formed by flowable chemical vapor deposition (FCVD)) and a semiconductor layer 206a. Figure 18A In the cross-sectional view, semiconductor layer 206a and dielectric layer 216a can define an angle 600. In some embodiments, angle 600 is in the range of approximately 105 degrees to approximately 115 degrees, for example, approximately 110 degrees. Such a value as angle 600 is significantly smaller than that of semiconductor structures formed by other techniques. For example, angle 600 is more like a right angle, while the corresponding angle of semiconductor structures formed by other techniques can be more like a curve or arc and can exceed 120 degrees.

[0207] at the same time, Figure 18B This is a planar top view of a portion of a semiconductor structure 200, including a dielectric 216a therein, an adjacent portion of a semiconductor layer 202, and an adjacent portion of a dummy gate stack 210 comprising polysilicon. Figure 18BIn the planar top view, semiconductor layer 202 and dielectric layer 216a can define an angle 610. In some embodiments, angle 610 is in the range of about 90 degrees to about 100 degrees, for example, about 95 degrees. Such a value as angle 610 is significantly smaller than that of semiconductor structures formed by other techniques. For example, angle 610 is more like a right angle, while the corresponding angle of a semiconductor structure formed by other techniques can be more like a curve or arc and can exceed 115 degrees. Sharper angles 600 and 610 can be unique physical characteristics of the semiconductor structure 200 formed using the manufacturing method of this invention.

[0208] Figure 19 An example type of memory in which semiconductor structure 200 can be implemented is illustrated. In this regard, Figure 19 A circuit diagram of an exemplary static random-access memory (SRAM) device is illustrated, for example, as a single-port SRAM cell (e.g., a 1-bit SRAM cell) 800. The single-port SRAM cell 800 includes pull-up transistors PU1 and PU2; pull-down transistors PD1 and PD2; and pass-gate transistors PG1 and PG2. As shown, transistors PU1 and PU2 are p-type transistors, and transistors PG1, PG2, PD1, and PD2 are n-type transistors. According to various embodiments of the present invention, transistors PG1, PG2, PD1, and PD2 are implemented using thinner spacers than transistors PU1 and PU2. Since the SRAM cell 800 in the illustrated embodiment includes six transistors, it can also be referred to as a 6T SRAM cell. In any case, transistor 710A can be used to implement transistors PG1, PG2, PD1, PD2, PU1, and / or PU2.

[0209] The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down gate transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form the first data latch. The gates of transistors PU2 and PD2 are coupled together and to the drains of transistors PU1 and PD1 to form the first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and to the drains of transistors PU2 and PD2 to form the complementary first storage node SNB1. The sources of pull-up transistors PU1 and PU2 are coupled to the power supply voltage Vcc (also known as Vdd), and the sources of pull-down transistors PD1 and PD2 are coupled to voltage Vss, which may be electrically grounded in some embodiments.

[0210] The first storage node SN1 of the first data latch is coupled to the bit line BL via a transfer gate transistor PG1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB via a transfer gate transistor PG2. The first storage node SN1 and the complementary first storage node SNB1 are complementary nodes that are constantly at opposite logic levels (logic high or logic low). The gates of the transfer gate transistors PG1 and PG2 are coupled to the word line WL. SRAM devices such as SRAM cell 800 can be implemented using planar transistor devices, FinFET devices, and / or GAA devices.

[0211] Figure 20 An integrated circuit manufacturing system 900 is illustrated, which can be used to manufacture a semiconductor structure 200 according to an embodiment of the present invention. The manufacturing system 900 includes multiple entities 902, 904, 906, 908, 910, 912, 914, 916…, N connected via a communication network 918. The network 918 can be a single network or various different networks, such as an internal network and the Internet, and can include both wired and wireless communication channels.

[0212] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a target product; entity 906 represents an engineer, such as a process engineer controlling processes and related formulations, or an equipment engineer monitoring or adjusting the conditions and configuration of process tools; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor process tool, such as an EUV tool for performing lithography to define gate spacers for SRAM devices; entity 912 represents a virtual metrology module associated with process tool 910; entity 914 represents an advanced process control module associated with process tool 910 and other other process tools; and entity 916 represents a sampling module associated with process tool 910.

[0213] Each entity can interact with other entities and can provide integrated circuit manufacturing, process control, and / or computing capabilities to and / or receive such capabilities from other entities. Each entity may also include one or more computer systems for performing calculations and automation. For example, the high-order process control module of entity 914 may include multiple computer hardware units with software instructions encoded therein. The computer hardware may include hard disks, flash drives, CD-ROMs, RAM memory, display devices (e.g., screens), and input / output devices (e.g., mice and keyboards). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0214] The integrated circuit manufacturing system 900 enables interaction between entities for the purpose of integrated circuit (IC) manufacturing, and advanced process control for IC manufacturing. In an embodiment, advanced process control includes adjusting process conditions, settings, and / or formulations of a process tool applicable to a relevant wafer based on metrological results.

[0215] In another embodiment, the metrological results are measured from a subset of processed wafers based on the optimal sampling rate determined by process quality and / or product quality. In yet another embodiment, the metrological results are measured from selected regions and points of the processed wafer subset based on the optimal sampling field / point determined by various characteristics of process quality and / or product quality.

[0216] One of the functions offered by the IC Manufacturing System 900 is to enable collaboration and information access in areas such as design, engineering and process, metrology, and advanced process control. Another capability offered by the IC Manufacturing System 900 is the integration of systems between equipment, such as metrology tools and process tools. This integration allows equipment to coordinate its activities. For example, integrating metrology tools and process tools allows manufacturing information to be more effectively incorporated into the manufacturing process or APC modules, and wafer data from online or field measurements can be obtained using metrology tools integrated into the relevant process tools.

[0217] In summary, this invention employs a unique manufacturing process to form the semiconductor structure as part of a GAA device. For example, this invention performs a lateral etching process on the dielectric layer (interlaced with the semiconductor layers in a vertical stack) in the GAA device, wherein the lateral etching process comprises multiple etch-bake cycles. Each etch cycle is performed at relatively low temperatures and relatively high pressures. The etch cycle generates byproducts, which can then be removed by a baking cycle. For example, the baking cycle applies heat to the GAA device, converting the byproducts into removable gaseous products. The etched dielectric layer is ultimately replaced by a high-k metal gate structure. This invention offers a variety of advantages. However, it should be understood that not all advantages are discussed herein, different embodiments may provide different advantages, and no particular advantage is required in any embodiment. One advantage is improved device performance. For example, if the lateral etching of the dielectric layer is not carefully configured, the dielectric layer in the stack may have very uneven lateral dimensions. This is because the lateral etching process typically etches more of the upper dielectric layer in the stack than the lower dielectric layer. The lack of uniformity can be inherited by the gate structure that will be formed to replace the dielectric layer, which can degrade device performance. Here, etching process parameters (e.g., low temperature and high pressure) are specifically configured to enhance the etching of the lower dielectric layer in the stack, which improves the uniformity of the lateral dimensions of the etched dielectric layer. Additionally, etching produces byproducts, which can be adjusted by process parameters to form more on the side surfaces of the upper dielectric layer in the stack. These byproducts can hinder or slow down the etching of the dielectric layer formed thereon. Thus, the etching of the upper dielectric layer may be further slowed down due to the presence of byproducts. As a result, the etched dielectric layer can have relatively uniform lateral dimensions, which ultimately translates into relatively uniform lateral dimensions of the gate structure. Therefore, device performance is improved. Other advantages may include compatibility with existing manufacturing processes, including FinFET and GAA processes, as well as ease of implementation and low cost.

[0218] One aspect of this invention relates to a method. According to this method, a stack of first and second semiconductor layers is formed. Each first semiconductor layer has a first material composition. Each second semiconductor layer has a second material composition different from the first material composition. The first and second semiconductor layers are interleaved in the stack. The second semiconductor layers are replaced by a plurality of dielectric layers. An etching process is performed on the dielectric layers. Etching is performed at a process pressure between about 600 mTorr and about 800 mTorr or at a process temperature between about 16 degrees Celsius and about 20 degrees Celsius.

[0219] Another aspect of this invention relates to a method. According to this method, a stack of first and second semiconductor layers is formed. Each first semiconductor layer has a first material composition. Each second semiconductor layer has a second material composition different from the first material composition. The first and second semiconductor layers are staggered in the stack. The second semiconductor layers are replaced by a plurality of dielectric layers. The dielectric layers are laterally etched such that each dielectric layer has a smaller lateral dimension than the first semiconductor layer in a cross-sectional side view. The etching is performed such that the ratio between a shortest lateral dimension and a longest lateral dimension in the dielectric layers is in the range of about 0.91:1 to about 1:1 in the cross-sectional view.

[0220] Another aspect of this invention relates to an apparatus. This apparatus includes a stack of semiconductor layers disposed above a substrate. This apparatus includes a gate structure surrounding each semiconductor layer stack. In a cross-sectional side view: the gate structure includes at least a first portion, a second portion disposed above the first portion, and a third portion disposed above the second portion; the first portion, the second portion, and the third portion each have a first lateral dimension, a second lateral dimension, and a third lateral dimension, respectively; and the variation between the first lateral dimension, the second lateral dimension, and the third lateral dimension is less than 1.4 nanometers.

[0221] The components of several embodiments are summarized above to facilitate a better understanding of the views expressed in the embodiments of this utility model by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this utility model to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this utility model, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this utility model.

Claims

1. A semiconductor device, characterized in that, include: A stack of multiple semiconductor layers is disposed above a substrate; as well as A gate structure, which surrounds the stack of semiconductor layers; In one of the sectional side views: The gate structure includes at least a first portion, a second portion disposed above the first portion, and a third portion disposed above the second portion; The first part, the second part, and the third part each have a first lateral dimension, a second lateral dimension, and a third lateral dimension, respectively; and The variation between the first lateral dimension, the second lateral dimension, and the third lateral dimension is less than 1.4 nanometers.

2. The semiconductor device as claimed in claim 1, characterized in that, The first lateral dimension is smaller than the second lateral dimension or the third lateral dimension; or The second lateral dimension is smaller than the first lateral dimension or the third lateral dimension.

3. The semiconductor device as claimed in claim 1, characterized in that, In this cross-sectional side view, the ratio between the shortest and longest of the first, second, and third lateral dimensions is between 0.91:1 and 1:

1.

4. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A first inner spacer is disposed on the side of the first portion of the gate structure; A second inner spacer is disposed on the side of the second portion of the gate structure; as well as A third inner spacer is disposed on the side of the third portion of the gate structure; The first inner spacer, the second inner spacer, and the third inner spacer have different lateral dimensions.

5. The semiconductor device as claimed in claim 4, characterized in that, The semiconductor layers in the stack have the same first thickness.

6. The semiconductor device as claimed in claim 5, characterized in that, The difference between each of the first thicknesses is less than 5%.

7. The semiconductor device as claimed in claim 5, characterized in that, The gate structure includes a metal gate electrode and a gate dielectric layer.

8. The semiconductor device as claimed in claim 7, characterized in that, The first inner spacer, the second inner spacer, and the third inner spacer have a convex shape.

9. The semiconductor device as claimed in claim 8, characterized in that, In this cross-sectional side view, the convex shape protrudes toward the gate dielectric layer of the gate structure.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The stack of semiconductor layers includes 2 to 10 semiconductor layers.

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