Semiconductor device

Abstract

A semiconductor device includes a plurality of semiconductor layers, a plurality of gate stacks, a plurality of fin isolation regions, and an isolation interface region. The gate stacks are on a portion of the semiconductor layers, the gate stacks having a gate length that is perpendicular to a length of the semiconductor layers. The fin isolation regions are present through the semiconductor layers, the fin isolation regions having a length direction that is perpendicular to the length of the semiconductor layers, where the length direction of the fin isolation regions is aligned with the gate length. The isolation interface region is between the fin isolation regions and at least one of the gate stacks.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Technological advancements in integrated circuit (IC) materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than its predecessors. Throughout IC development, functional density (e.g., the number of interconnects per wafer area) has generally increased, while geometric dimensions have decreased. This scaling down process typically benefits production efficiency and reduces associated costs.

[0003] Such scaling down also increases the complexity of processing and manufacturing ICs, requiring similar developments in IC processing and manufacturing to achieve these advancements. For example, Gate-All-Around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods for manufacturing them are under development.

[0004] The formation of a GAA transistor typically involves forming a strip (comprising alternating semiconductor materials) and a long gate stack, followed by forming an isolation region to cut the strip and long gate stack into shorter portions. These shorter portions can be used to form the channel layer and gate stack of the GAA transistor. Utility Model Content

[0005] Some embodiments of this disclosure provide a semiconductor device comprising: a plurality of semiconductor layers, a plurality of gate stacks, a plurality of fin isolation regions, and an isolation interface region. The gate stacks are located on a portion of the semiconductor layers and have a gate length perpendicular to the length of the semiconductor layers. The fin isolation regions extend through the semiconductor layers and have a length direction perpendicular to the length of the semiconductor layers, wherein the length direction of the fin isolation regions is aligned with the gate length, and wherein the ends of each fin isolation region have a profile with square corners. The isolation interface region is located between the fin isolation regions and at least one of the gate stacks.

[0006] Some embodiments of this disclosure provide a semiconductor device comprising: a plurality of semiconductor layers, a plurality of gate stacks, a plurality of fin isolation regions, and an isolation interface region. The gate stacks are located on a portion of the semiconductor layers and have a gate length perpendicular to the length of the semiconductor layers. The fin isolation regions extend through the semiconductor layers and have a length direction perpendicular to the length of the semiconductor layers, wherein the length direction of the fin isolation regions is aligned with the gate length. The isolation interface region is located between the fin isolation regions and at least one of the gate stacks.

[0007] Some embodiments of this disclosure provide a semiconductor device comprising: a plurality of semiconductor layers, a plurality of gate structures, a plurality of fin isolation regions, and an isolation interface region. The gate structures are located on a portion of the semiconductor layers and have a gate length perpendicular to the length of the semiconductor layers. The fin isolation regions extend through the semiconductor layers and have a length direction perpendicular to the length of the semiconductor layers, wherein the length direction of the fin isolation regions is aligned with the gate length. The isolation interface region is located between the fin isolation regions and at least one of the gate structures, wherein the isolation interface region includes a planar end face on a first sidewall abutting the fin isolation regions and a plurality of protrusions extending from a second sidewall into the gate structures. Attached Figure Description

[0008] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0009] Figures 1 to 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 11 , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 32A , Figure 32B , Figure 33A ,and Figure 33B The illustration shows a view of an intermediate stage in the formation of a transistor according to some embodiments;

[0010] Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A ,and Figure 18BThe illustration shows the formation of a continuous polysilicon on diffusion edge (CPODE) region by cutting a stack of dummy gates, according to some embodiments.

[0011] Figures 21 to 26 The diagram illustrates the formation of a diced metal gate region according to some embodiments;

[0012] Figures 27 to 31 The illustration shows the formation of a cut-metal gate (CMG) isolation interface according to some embodiments;

[0013] Figure 34 The diagram illustrates a process flow for forming a transistor according to some embodiments;

[0014] Figure 35 This is a top view illustrating a cut-metal gate (CMG) isolation interface according to some embodiments.

[0015] [Symbol Explanation]

[0016] 10: Wafer

[0017] 20:Substrate

[0018] 20': Substrate strip / Semiconductor strip

[0019] 22: Multi-layer stacking

[0020] 22': Multilayer stacking / Semiconductor stacking

[0021] 22A: Semiconductor layer / Sacrificial semiconductor layer / Layer

[0022] 22B: Semiconductor layer / nanostructure / layer

[0023] 23: Trench

[0024] 24: Semiconductor Strip

[0025] 26: STI Zone / Zone

[0026] 26T: Top surface

[0027] 28: Prominent fins / fin plates

[0028] 30: Dummy gate stack / gate stack

[0029] 32: Dummy gate dielectric

[0030] 34: Dummy gate electrode

[0031] 36: Hard mask layer / Hard mask

[0032] 38: Gate spacer / spacer

[0033] 41: Lateral groove

[0034] 42: Groove

[0035] 44: Internal spacers

[0036] 48: Epitaxial region / Source / Drain region

[0037] 50: Contact Etching Termination Layer / CESL

[0038] 52: Interlayer Dielectric / ILD

[0039] 58: Groove

[0040] 62: Gate Dielectric

[0041] 68: Gate electrode

[0042] 70: Replace gate stack / gate stack / gate structure

[0043] 70A, 70B: Gate stacking

[0044] 74: Gate Mask

[0045] 76:ILD

[0046] 78: Silicide Region

[0047] 80A, 80B: Contact socket / contact

[0048] 82A, 82B: Transistors

[0049] 88: Hard mask layer / Mask layer / Hard mask

[0050] 88A: Silicon nitride layer / hard mask

[0051] 88B: Silicon layer

[0052] 88C: Silicon nitride layer

[0053] 90: Mask

[0054] 90A: Bottom layer

[0055] 90B: Intermediate Layer

[0056] 90C: Top layer

[0057] 92: Trench

[0058] 110: CMG isolation zone / area / dielectric layer

[0059] 110A, 110B: Dielectric layers

[0060] 112: Fin isolation zone / CPODE isolation zone / area

[0061] 112A: Dielectric Liner

[0062] 112B: Dielectric layer

[0063] 113: CMG cutting CPODE area / CMG isolation interface / area

[0064] 114: Trench

[0065] 116: Hard mask / Hard mask opening

[0066] 117: Masking / Groove

[0067] 118: Opening

[0068] 120: Opening

[0069] 200: Process Flow

[0070] 202~234: Process

[0071] A1-A1: Cross section

[0072] BB: Cross-section

[0073] C1: Protrusion

[0074] E1: Square / Edge

[0075] P1: Flat sidewall / plane

[0076] S1: First sidewall

[0077] S2: Second sidewall

[0078] X: Direction

[0079] Y: direction

[0080] ZZ: Line Detailed Implementation

[0081] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0082] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “overlapping,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly.

[0083] This document provides a Gate-All-Around (GAA) transistor, a Cut-Metal Gate (CMG) isolation region, a Continuous Polysilicon on Diffusion Edge (CPODE) isolation region, and methods for forming the same. In some embodiments, the Cut-Metal Gate (CMG) isolation region is formed through the end of the Continuous Polysilicon on Diffusion Edge (CPODE) isolation region. In some embodiments, by positioning the Cut-Metal Gate (CMG) isolation region at the end of the Continuous Polysilicon on Diffusion Edge (CPODE) isolation region, the methods and structures described herein can remove device leakage (MD-to-MD device leakage) at the contacts of the source / drain regions. More specifically, etching steps, such as Cut Metal Gate (CMG) etching, can be used to remove leakage paths (MD-to-MD device leakage paths) between the contacts of the source and drain regions. These leakage paths may exist at the ends of the Continuous Polysilicon on Diffusion Edge (CPODE) isolation regions abutting the metal gate. In some embodiments, the leakage paths (MD-to-MD device leakage paths) between the contacts of the source and drain regions are caused by a metal gate (MG) refill process of a replacement gate process adjacent to the Continuous Polysilicon on Diffusion Edge (CPODE) isolation region. In some cases, leakage paths have been determined to exist at the edges of the CPODE region with rounded corners at the wiring ends. In some embodiments, leakage paths can be removed using a cut metal gate (CMG) dry etching process, which removes the leakage paths and can reshape the contour of the CPODE region edge from a rounded contour to a square contour. The methods and structures described herein can reduce device leakage.

[0084] In the illustrated embodiment, the formation of a GAA transistor is used as an example to explain the concepts of this disclosure. Other types of transistors, such as FinFETs, planar transistors, or similar transistors, may also employ the concepts of this disclosure. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made while remaining within the conceptual scope of the different embodiments will be readily understood by those skilled in the art. Throughout the various views and illustrative embodiments, the same element symbols are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0085] Figures 1 to 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 11 , Figure 19A , Figure 19B , Figure 20A ,and Figure 20B The illustration shows a view of an intermediate stage in the formation of a transistor according to some embodiments of the present disclosure.

[0086] refer to Figure 1 The image shows a perspective view of wafer 10. Wafer 10 includes a multilayer structure comprising a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, or the like, or other substrates and / or structures such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium-on-insulator, or the like. Substrate 20 may be doped as a p-type semiconductor, although in other embodiments it may be doped as an n-type semiconductor.

[0087] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes involving alternating materials. Individual process diagrams are shown below. Figure 34 Process 202 in the illustrated process flow 200. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0088] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or comprises SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is performed by epitaxial growth, and the corresponding deposition method may be vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or the like. According to some embodiments, the first layer 22A is formed with a range of approximately... With the agreement The initial thickness. However, any suitable thickness can be used while remaining within the scope of the embodiments.

[0089] Once the first layer 22A has been deposited over the substrate 20, the second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or contains a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon-germanium, the second layer 22B may be formed of silicon, and vice versa. It should be understood that any suitable combination of materials may also be used for the first layer 22A and the second layer 22B.

[0090] According to some embodiments, a second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, for example, the second layer 22A has a thickness ranging from about 4 nm to 7 nm, while the second layer 22B has a thickness ranging from about 8 nm to 12 nm.

[0091] Once the second layer 22B is formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired top layer of the multilayer stack 22 has been formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other, and the second layers 22B may have the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process, and is alternatively referred to throughout as the sacrificial layer 22A. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

[0092] According to some embodiments, several pad oxide layers and several hard mask layers (not shown) may be formed over the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0093] refer to Figure 2 A portion of the multilayer stack 22 and the underlying substrate 20 is patterned in multiple etching processes to form trenches 23. The trenches 23 extend into the substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as multilayer stack 22'. The underlying multilayer stack 22' leaves a portion of the substrate 20 untouched, hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layers 22A and 22B. Hereinafter, semiconductor layer 22A may be alternatively referred to as a sacrificial layer, and semiconductor layer 22B may be alternatively referred to as a nanostructure. The portion of multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0094] In the embodiments shown above, the transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine optical lithography with self-alignment processes, allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the device structure.

[0095] Figure 3 The diagram illustrates the formation of isolation zone 26, which is also referred to throughout the description as the Shallow Trench Isolation (STI) zone. Some process diagrams are shown below. Figure 34Process 206 in the illustrated process flow 200. STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, or the like. STI region 26 may also include a dielectric material above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, HDPCVD, or the like. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, may then be performed to flush the top surface of the dielectric material, with the remaining portion of the dielectric material constituting STI region 26.

[0096] Next, the STI region 26 is recessed, such that the top portion of the semiconductor strip 24 protrudes higher than the top surface 26T of the remaining portion of the STI region 26, thereby forming a protruding fin 28. The protruding fin 28 includes the top portion of the multilayer stack 22' and the substrate strip 20'. The recess of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 26 is performed by a wet etching process. Etching chemicals may include, for example, HF.

[0097] refer to Figure 4 A dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. Some process diagrams are as follows. Figure 34 Process 208 in the illustrated process flow 200. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, the dummy gate electrode 34 may be formed using polycrystalline silicon or amorphous silicon, or other materials such as amorphous carbon may be used.

[0098] Each of the dummy gate stacks 30 may also include one or more hard masking layers 36 above the dummy gate electrode 34. The hard masking layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stack 30 may span one or more protruding fins 28 and an STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a length direction perpendicular to the lengthwise direction of the protruding fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer above the dummy gate dielectric layer, depositing one or more hard masking layers, and then patterning the formed layers using multiple patterning processes.

[0099] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like, and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The formation process of the gate spacers 38 may include depositing one or more dielectric layers, followed by performing multiple anisotropic etching processes on the dielectric layers(s). The remaining portion of the dielectric layers(s) constitutes the gate spacers 38.

[0100] According to alternative embodiments, the following can be used: Figure 19A and Figure 19B The process shown forms one or more layers of gate spacers 38, the resulting layer of gate spacers 38 including a reference layer. Figures 19A to 21 The materials discussed. For example, the gate spacer 38 may be formed of SiOCNH or may include SiOCNH. Details of the formation process will be discussed in subsequent paragraphs.

[0101] Figure 5A and Figure 5B Illustration Figure 4 The cross-sectional view of the structure shown. Figure 5A Illustration Figure 4 The reference cross section A1-A1 cuts through the portion of the protruding fin 28 not covered by the gate stack 30 and gate spacers 38, and is perpendicular to the gate length direction. The fin spacers 38 on the sidewall of the protruding fin 28 are also illustrated. Figure 5B Illustration Figure 4 The reference cross section BB is parallel to the length direction of the protruding fin 28.

[0102] refer to Figure 6A and Figure 6BThe portion of the protruding fin 28 that does not directly bear the dummy gate stack 30 and gate spacer 38 is recessed by an etching process to form a groove 42. Some process illustrations are as follows. Figure 34 Process 210 in the process flow 200 shown. For example, a dry etching process can be performed using a mixture of C2F6, CF4, SO2, HBr, Cl2, and O2, a mixture of HBr, Cl2, O2, and CH2F2, or similar substances to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or may be lower than the bottom of the multilayer semiconductor stack 22' (e.g., ...). Figure 6B (As shown). Etching can be anisotropic, therefore the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown. Figure 6B As shown.

[0103] refer to Figure 7A and Figure 7B The sacrificial semiconductor layer 22A is laterally recessed to form a lateral groove 41, which is recessed from the edges of the individual overlying and underlying nanostructures 22B. Individual process illustrations are shown below. Figure 34 Process 212 in the illustrated process flow 200. The lateral recess of the sacrificial semiconductor layer 22A can be achieved by a wet etching process using an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon-germanium (SiGe)) than for the materials of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon-germanium and the nanostructure 22B is formed of silicon, an etchant such as hydrochloric acid (HCl) can be used to perform the wet etching process. The wet etching process can be performed using immersion processes, spraying processes, spin-on processes, or similar methods.

[0104] According to an alternative embodiment, the lateral recess of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0105] refer to Figure 8A and Figure 8B This forms internal spacers 44. Some process diagrams are as follows: Figure 34 Process 214 in the illustrated process flow 200. According to some embodiments, the formation of the internal spacer 44 includes depositing a conformal dielectric layer that extends to the lateral recess 41. Figure 7B Next, an etching process (also known as a spacer trimming process) is performed to trim the portion of the spacer layer outside the lateral groove 41, leaving a portion of the spacer layer inside the lateral groove 41. The remaining portion of the spacer layer is called the inner spacer 44.

[0106] Figure 9Aand Figure 9B The illustrations show a cross-sectional view and a perspective view of the source / drain region 48 formed in the groove 42 through epitaxial growth. Some process illustrations are as follows. Figure 34 Process 216 in the illustrated process flow 200. Multiple source / drain regions may individually or collectively refer to a source or drain, depending on the context. According to some embodiments, source / drain regions 48 may apply stress to the nanostructure 22B used as a channel for a corresponding GAA transistor, thereby improving performance.

[0107] According to some embodiments, the corresponding transistor is n-type, therefore the epitaxial source / drain region 48 is formed as n-type by doping with an n-type dopant. For example, silicon-phosphorus (SiP), silicon-carbon-phosphorus (SiCP), or the like can be grown to form the epitaxial source / drain region 48. According to alternative embodiments, the corresponding transistor is p-type, therefore the epitaxial source / drain region 48 is formed as p-type by doping with a p-type dopant. For example, silicon-boron (SiB), silicon-germanium-boron (SiGeB), or the like can be grown to form the epitaxial source / drain region 48. After filling the groove 42 with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally and can form a small facet. Further growth of the epitaxial region 48 can also cause adjacent epitaxial regions 48 to merge with each other, forming a gap.

[0108] Following the epitaxial process, the epitaxial region 48 may be further implanted with n-type or p-type impurities to form source and drain regions, which are represented by element symbol 48. According to an alternative embodiment of this disclosure, when the epitaxial region 48 is in situ doped with n-type or p-type impurities during epitaxialization, the implantation process is skipped, and the epitaxial region 48 also serves as the source / drain region.

[0109] Figure 10A and Figure 10B The figure shows a cross-sectional view of the structure after the formation of the Contact Etch Stop Layer (CESL) 50 and the Inter-Layer Dielectric (ILD) 52. Individual process illustrations are shown below. Figure 34 Process 218 in the process flow 200 shown. CESL 50 may be formed from silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 52 may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or any other suitable deposition method. ILD 52 may be formed from an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), silicon-free glass (USG), or the like.

[0110] CESL 50 and ILD 52 are planarized using a planarization process such as CMP or mechanical polishing. According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, such as... Figure 10A As shown. According to an alternative embodiment, the planarization process may expose and stop on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the ILD 52 are flush within the range of process variations.

[0111] Figure 10C The illustrations are based on some embodiments. Figure 10A and Figure 10B The diagram shows a top view of the structure. It includes a multi-layer stack 22', a substrate strip 20', and protruding fins 28 (see...). Figure 10A The gate stack 30, including the dummy gate electrode 34 (such as a polysilicon strip), has a length direction in the X direction, and the corresponding cross-sectional view is called the X-cut view. The gate stack 30 also has a length direction in the Y direction, and the corresponding cross-sectional view is called the Y-cut view. The source / drain region 48 is based on a multilayer stack 22' (such as...). Figure 5B and Figure 10B Some portions are formed (as shown). The edges of the source / drain regions may contact or be spaced apart from the gate spacer 38.

[0112] Figure 11 The illustration shows a top view of the formation of the fin isolation region 112. According to some embodiments, such as... Figure 11 As shown, the fin isolation region 112 is a continuous polysilicon on diffusion edge (CPODE) region, the formation of which involves etching the dummy gate stack 30, the multilayer stack 22', and the substrate strip 20'. Individual processes are also illustrated as follows. Figure 34 Process 220 in the process flow 200 shown. The detailed process for forming the fin isolation region 112 by cutting the dummy gate stack 30 is as follows... Figures 12A to 18B As shown.

[0113] Figure 12A and Figures 12B to 18A and Figure 18B The illustration shows the formation of the fin isolation region 112 according to some embodiments (using the CPODE process). In the following figures, figures with the letter A following the corresponding figure number are from... Figure 11 The Y-section (along the Y direction) is obtained from the figure, while the figure with the letter B after the corresponding figure number is obtained from... Figure 11 Obtained by X-cutting (along the X direction).

[0114] Figure 12A and Figure 12B Illustration Figure 10CThe structure was obtained by cutting the cross section Y and X, respectively. Figure 12A and Figure 12B Also corresponding to Figure 10A and Figure 10B .therefore, Figure 12A The diagram shows a multilayer stack 22' and a dummy gate stack 30 on the multilayer stack 22'. Figure 12B The diagram shows the source / drain region 48, the multilayer stack 22', the internal spacer 44, and the dummy gate stack 30.

[0115] refer to Figure 12A and Figure 12B A hard mask 116 is formed. The hard mask 116 may comprise a dielectric material, such as SiN, silicon, the like, or multiple layers thereof. An etch mask 117 (e.g., three layers of photoresist) is formed over the hard mask 116 and patterned thereon. Next, as... Figures 13A to 14B As shown, a hard mask 116 is etched to form an opening 118, through which the dummy gate electrode of the dummy gate stack 30 is exposed. Then, the hard mask 116 is used to etch through the underlying dummy gate electrode until the dummy gate dielectric of the dummy gate stack 30 is exposed, as shown. Figure 15A and Figure 15B As shown. The etching is anisotropic, such that the edge of the dummy gate electrode facing opening 118 is vertical and straight. In the etching process, the dummy gate dielectric can be used as an etch stop layer.

[0116] Next, for example, the dummy gate dielectric of the dummy gate stack is removed by an isotropic etching process, thereby exposing the multilayer stack 22'. The resulting structure is as follows: Figure 16A and Figure 16B As shown. Next, an etching process is performed to remove the exposed multilayer stack 22', followed by further etching of the underlying semiconductor material, such as semiconductor strip 20'. Figure 17A and Figure 17B As shown, an opening 120 is formed between adjacent STI zones 26. The opening 120 may extend to a level below the bottom surface of the STI zone 26 to reduce leakage.

[0117] Figure 18A and Figure 18B The diagram illustrates filling openings 118 and 120 to form a CPODE isolation region 112. According to some embodiments, the filling process may include depositing a dielectric liner 112A, followed by depositing a dielectric layer 112B on the dielectric liner 112A. According to some embodiments, the materials for the dielectric liner 112A and the dielectric layer 112B may be selected from SiN, SiO, SiON, SiOCN, SiCN, the like, or combinations thereof. A planarization process, such as a CMP process, may then be performed to form the fin isolation region 112, which is a CPODE isolation region, as shown below. Figure 11 As shown.

[0118] Next, the dummy gate electrodes and dummy gate dielectrics (and hard mask 36, if any) of the dummy gate stack 30 are removed in one or more etching processes to form a recess 58, such as... Figure 19A and Figure 19B As shown. Some process diagrams are as follows. Figure 34 Process 222 in the illustrated process flow 200. According to some embodiments, the dummy gate electrode and dummy gate dielectric are removed by (multiple) anisotropic dry etching processes. For example, (multiple) reactive gases can be used to perform the etching process, selectively etching the dummy gate electrode and dummy gate dielectric at a faster rate than etching ILD 52. Each recess 58 exposes and / or covers portions of the multilayer stack 22', including future channel regions in the subsequently completed transistor.

[0119] Next, the sacrificial layer 22A is removed to extend the grooves 58 between the nanostructures 22B. Some process diagrams are shown below. Figure 34 Process 224 in the illustrated process flow 200. The sacrificial layer 22A can be removed by performing an isotropic etching process, such as a wet etching process using an etchant selective for the material of the sacrificial layer 22A, while the nanostructure 22B, substrate 20, and STI region 26 remain relatively unetched compared to the sacrificial layer 22A. According to some embodiments, where the sacrificial layer 22A comprises, for example, SiGe, and the nanostructure 22B comprises, for example, Si or SiC, the sacrificial layer 22A can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0120] refer to Figure 20A and Figure 20B This forms the gate dielectric 62 and gate electrode 68, thereby forming the replacement gate stack 70. Some process diagrams are shown below. Figure 34 Process 226 in the illustrated process flow 200. According to some embodiments, each of the gate dielectrics 62 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer may be formed of or comprise silicon oxide, which may be deposited by a conformal deposition process such as ALD or CVD or by an oxidation process. According to some embodiments, the high-k dielectric layer comprises one or more dielectric layers. For example, the high-k dielectric layer(s) may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0121] A gate electrode 68 is also formed. During formation, a conductive layer is first formed on a high-k dielectric layer, and the remaining portion of the trench 58 is filled. The gate electrode 68 may include a metallic material such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, the gate electrode 68 may comprise any number of layers, any number of work function layers, and possible filler material. The gate dielectric 62 and the gate electrode 68 also fill the spaces between adjacent elements in the nanostructure 22B, and fill the space between the bottom element of the nanostructure 22B and the underlying substrate strip 20'. After filling the trench 58, a planarization process, such as CMP or mechanical polishing, is performed to remove excess material from the gate dielectric and gate electrode 68 above the top surface of the ILD 52. The gate electrode 68 and the gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting transistor.

[0122] After forming the gate stack 70, a cut-metal gate (CMG) region 110 can be formed, such as... Figures 21 to 26 As shown. Figure 21 The illustration shows a top view of the formation of the Cut-Metal Gate (CMG) region 110, which divides / separates the (metal) gate stack 70 into shorter portions. Individual process illustrations are shown below. Figure 34 Process 228 in the illustrated process flow 200. The CMG isolation region 110 is also referred to as the gate isolation region 110. According to some embodiments, the CMG isolation region 110 is formed by cutting and replacing the gate stack 70, such as... Figure 24 As shown.

[0123] Detailed processes for forming the CMG isolation zone 110 can be found from... Figures 22 to 26 The process shown is implemented as described. Figure 22 The diagram illustrates a cross-sectional view of the intermediate structure, where the gate stack 70 has been formed, including the gate dielectric 62 and the gate electrode 68, while the CMG isolation region 110 has not yet been formed. According to some embodiments, the hard mask layer 88 is deposited and may include a multilayer structure comprising multiple layers. According to some embodiments, the hard mask layer 88 includes a silicon nitride layer 88A, a silicon layer 88B, and a silicon nitride layer 88C. According to an alternative embodiment, a single-layer hard mask 88 is used, which may be formed of or contain silicon nitride.

[0124] Next, an etch mask 90 is formed, such as Figure 23As shown. The etch mask 90 may also have a single-layer structure (which may include a photoresist) or a two-layer structure including a bottom anti-reflective coating (BARC) and a photoresist. Alternatively, the etch mask 90 may have three layers, which may include a bottom layer, an intermediate layer above the bottom layer, and a top layer, the top layer being a patterned photoresist. Trench 92 is formed in the etch mask 90.

[0125] Next, an etch mask 90 is used to etch the mask layer 88, causing the trench 92 to extend into the hard mask layer 88. The etching can be anisotropic. According to some embodiments, the trench 92 extends to the top surface of the hard mask 88A. After the trench 92 is formed in the hard mask layer 88, the etch mask 90 can be removed.

[0126] Next, as... Figure 24 As shown, the gate stack 70 is etched to replace it. The etching of the gate stack 70 is anisotropic. According to some embodiments, the etching is performed until the STI region 26 is exposed. The trench 92 may or may not extend into the STI region 26. After the etching process, the hard mask layer 88 may or may not be removed. Thus, the gate stack 70 is divided into gate stacks 70A and 70B.

[0127] In subsequent processes, a dielectric layer 110 is deposited, such as... Figure 25 As shown. The dielectric layer 110 may have a multilayer structure (e.g., including dielectric layer 110A and dielectric layer 110B), or it may have a single-layer structure. The dielectric layer 110 and its sublayers may include SiO, SiN, SiCON, SiCN, SiON, SiCO, or the like.

[0128] After depositing the dielectric layer 110, a planarization process, such as CMP or mechanical polishing, is performed. The planarization process can be stopped on the top surface of the gate stack 70. Figure 26 As shown, the remaining portions of dielectric layers 110A and 110B are collectively referred to as CMG isolation region 110 in the following text.

[0129] Because the CMG isolation region 110 is separated from the fin isolation region 112, there may be regions that separate the CMG isolation region 110 from its adjacent fin isolation region 112. The length of the CMG isolation region 110 can be selected according to the circuit layout. According to some embodiments, when forming some CMG isolation regions 110, the gate spacers 38 on the opposite sides of the individual gate stacks 70 (or dummy gate stacks 30) are also etched, so that the CMG isolation regions 110 extend laterally (in the X direction) beyond the spacers 38. According to alternative embodiments, some or all of the CMG isolation regions 110 are limited by the opposing gate spacers 38. Some CMG isolation regions 110 may be cut into the gate spacers 38 and may extend laterally beyond the gate spacers 38 into the adjacent ILD region. The length of the CMG isolation region 110 may also be longer than shown.

[0130] Figure 21 The illustration further shows a top view of the formation of the cut-metal gate (CMG) cut-continuous polysilicon on diffusion edge (CPODE) region 113. The CMG cut-continuous CPODE region 113 can also be referred to as the CMG isolation interface 113 (also called the isolation interface region) between the gate structure 70 and the fin isolation region 112. Some process illustrations are shown below. Figure 34 Process 228 in the illustrated process flow 200. According to some embodiments, the CMG isolation region 110 is formed by cutting the interface between the gate replacement stack 70 and the fin isolation region 112, as shown below. Figure 21 and Figures 27 to 31 As shown. Figures 27 to 31 From Figure 11 and Figure 21 The side section view taken from the second line ZZ. Although Figure 21 The illustration shows a single CMG isolation interface 113 corresponding to a single interface between gate structure 70 and fin isolation region 112, but the methods and structures described herein are not limited to this example. For instance, a single CMG isolation interface 113 may extend across multiple gate structures and multiple fin isolation regions 112 at their interfaces. For example, a single CMG isolation region 110 may extend across up to 100 gate structures and up to 100 fin isolation regions 112 at its interface.

[0131] In some embodiments, a CMG isolation interface 113 is formed at the end of a Continuous Polysilicon on Diffusion edge (CPODE) isolation region 112 (also referred to as fin isolation region 112). In some embodiments, by positioning the CMG isolation interface 113 at the end of the Continuous Polysilicon on Diffusion edge (CPODE) isolation region (also referred to as fin isolation region 112), the methods and structures described herein can reduce or remove device leakage at the end of the Continuous Polysilicon on Diffusion edge (CPODE) isolation region (also referred to as fin isolation region 112). More specifically, device leakage paths can be formed at the end of the fin isolation region 112 during a metal-fill process for forming the replacement gate stack 70. These device leakage paths can extend to the contacts of the source / drain regions, which can lead to device leakage (e.g., gate contact to gate contact leakage (MD to MD device leakage) and / or gate contact to metal gate leakage (MD to MG device leakage)). Etching steps, such as cut-metal gate (CMG) etching, can be used to remove leakage paths (MD-to-MD device leakage paths) between contacts of the source and drain regions. These leakage paths may exist at the ends of the continuous polysilicon on diffusion edge (CPODE) isolation regions (also referred to as fin isolation regions 112) abutting the metal gate (gate structure 70). In some embodiments, a cut-metal gate (CMG) dry etching process for removing leakage paths can be used to remove the leakage paths, and the contour of the CPODE region edge can be trimmed from a rounded contour to a square contour. In some embodiments, the cut-metal gate (CMG) etching process for forming the CMG isolation interface 113 may be the same etching process for forming the CMG isolation region 110. In some embodiments, the cut-metal gate (CMG) etching process for forming the CMG isolation interface 113 may be an etching process performed separately from the etching process for forming the CMG isolation region 110.

[0132] Figure 27The diagram shows a cross-sectional view of the intermediate structure, where the gate stack 70 has been formed and includes the gate dielectric and gate electrode, while the CMG isolation interface 113 has not yet been formed. According to some embodiments, the hard mask layer 88 is deposited and may include a multilayer structure comprising multiple layers. According to some embodiments, the hard mask layer 88 includes a silicon nitride layer 88A, a silicon layer 88B, and a silicon nitride layer 88C. According to an alternative embodiment, a single-layer hard mask 88 is used, which may be formed of or contain silicon nitride.

[0133] Next, an etch mask 90 is formed, such as Figure 27 As shown. The etch mask 90 may also have a single-layer structure (which may include a photoresist) or a two-layer structure including a bottom anti-reflective coating (BARC) and a photoresist. Alternatively, the etch mask 90 may have three layers, which may include a bottom layer 90A, an intermediate layer 90B above the bottom layer 90A, and a top layer 90C, whereby the top layer 90C may be a patterned photoresist. Trench 117 is formed in the etch mask 90. ​​As previously described, the etching process for forming the CMG isolation interface 113 may be performed simultaneously with the etching process for forming the CMG isolation region 110. Therefore, the element symbol for the etch mask for forming the CMG isolation interface 113 may be the same as the element symbol for the etch mask for forming the CMG isolation region 110. In some embodiments, different etch masks may be used to form the CMG isolation interface 113 and the CMG isolation region 110.

[0134] Next, an etch mask 90 is used to etch the mask layer 88, causing the trench 117 to extend into the hard mask layer 88, providing the hard mask opening 116, such as Figure 28 The etching can be anisotropic. According to some embodiments, the trench extends through the hard mask 88A and terminates on the upper surface of the interface between the gate structure 70 and the fin isolation region 112. In some embodiments, the etch mask 90 may be removed after the trench 92 is formed in the hard mask layer 88.

[0135] Next, as... Figure 29As shown, the interface between the replacement gate stack 70 and the fin isolation region 110 is etched to form a trench 114 that separates the ends of the fin isolation region 112 from the gate structure 70. In some embodiments, etching the trench 114 at the interface between the fin isolation region 112 and the replacement gate structure 70 can remove leakage paths. For example, etching the trench 114 at the interface between the fin isolation region 112 and the replacement gate structure 70 can remove voids in the fin isolation region 112 that can be filled with metal from the refill process that forms the replacement gate stack 70. By removing metal-filled voids in the fin isolation region 112 by etching the trench 114 at the interface between the fin isolation region 112 and the replacement gate structure, the methods and structures described herein can remove leakage paths that could lead to device leakage, such as leakage to the contacts (MD) to the source / drain regions of the device. Applying the etching process to form the trench 114 can also trim the ends of the fin isolation region 112. For example, the end of the fin isolation region 112 may have curvature before the trench 114 is formed. The etching process that forms the trench 114 can trim the end of the fin isolation region 112, which removes the curvature, wherein after the trench 114 is formed, the end of the fin isolation region 112 may have a profile whose corners are closer to a square E1, such as... Figure 35 As depicted. Furthermore, the sidewalls of the fin isolation zone 112 may have a plane P1, such as... Figure 35 As depicted. In some embodiments, the angle of the square edge E1 can be in the range of 70 to 90 degrees.

[0136] In some embodiments, such as Figure 29 As shown, trench 114 can be etched at the interface between fin isolation region 112 and replacement gate structure 70 using an anisotropic etching process (such as dry etching). In some embodiments, the etching process for forming trench 114 includes two stages. According to some embodiments, the first stage of the two-stage etching process is performed until the STI region 26 is exposed. During the first stage, trench 114 may not extend into the STI region 26. In some embodiments, the first stage of the etching process may be a dry seven (7) cycle etching selectively on the material of isolation region 26 (e.g., silicon oxide (SiO2)). In some embodiments, a wet cleaning step may be performed after the first stage of the etching process.

[0137] In some embodiments, etching trench 114 further includes extending trench 114 into isolation region 26, such as Figure 30The trench 114 extending into the isolation region 26 may include a second stage of an etching process. In some embodiments, the second stage of the etching process includes five (5) cycles of etching. The second stage of the etching process may include hexafluorobutane (hexafluoro-1,3-butadiene) (C4F6). In some embodiments, a wet cleaning step may be performed after the second stage of the etching process. The hard mask layer 88 may or may not be removed after the etching process.

[0138] Although the formed groove 114 gives the cut portion of the fin isolation area 112 a flat sidewall P1 (as shown in the image) Figure 35 (as depicted), but trench 114 forms curved sidewalls in gate structure 70 (as shown). Figure 35 The difference in sidewall geometry between the fin isolation region 112 and the cut portion of the gate structure 70 is a result of the different etching rates of the different materials of the fin isolation region 112 and the gate structure 70 during the formation of the trench 114.

[0139] In subsequent processes, a dielectric layer is deposited to provide material for the CMG isolation interface 113, such as... Figure 31 As shown. In some embodiments, the dielectric layer may have a multilayer structure or a single-layer structure. The dielectric layer and its sublayers may include SiO, SiN, SiCON, SiCN, SiON, SiCO, or the like. It should be noted that the above materials are provided for illustrative purposes and are not intended to limit this disclosure. In some instances, the material used for the CMG isolation layer 113 may include hafnium oxide (HfO), silicon oxynitride (SiNOx), zirconium dioxide (ZrO2), or other high-k dielectric materials. After depositing the dielectric layer, a planarization process, such as a CMP process or a mechanical polishing process, is performed. The planarization process may be stopped on the top surface of the gate stack 70 and the fin isolation region 112. The remaining portion of the dielectric layer provides material for the CMG isolation interface 113, such as... Figure 31 As shown.

[0140] Figure 35 This is a top view illustrating an embodiment of an isolation interface region (also referred to as CMG isolation interface 113) between at least one of a plurality of fin isolation regions 112 and a plurality of gate structures 70, wherein the isolation interface region 113 includes a plane on a first sidewall S1 of the isolation interface region 113 and convex protrusions C1 extending into the plurality of gate structures 70 on a second sidewall S2 of the isolation interface region 113. As described above, trenches 114 are formed for the isolation interface region 112 (e.g., Figure 30 and Figure 31The etching process (shown) trims the ends of the fin isolation region 112, removing any curvature therein. After forming the trench 114, the ends of the fin isolation region 112 may have a profile with corners more closely resembling a square E1, such as... Figure 35 As depicted, the dielectric filler within the trench 114 forms an isolation interface region 113, which will have planar sidewalls (e.g., first sidewall S1) corresponding to the plane P1 of the trench 114. The opposing sidewalls (e.g., second sidewall S2) of the dielectric filler for the isolation interface region 113 fill the convex curvature formed in the gate structure 70 during the etching process that forms the trench 114, resulting in a protrusion C1.

[0141] exist Figure 31 After the process shown, execute Figure 32A , Figure 32B , Figure 33A ,and Figure 33B The remaining processes shown are used to complete the fabrication of transistors 82A and 82B.

[0142] Figure 32A Illustration Figure 21 The cross-section of the structure shown contains a CMG isolation region 110 to cut the long metal gate stack 70 into metal gate stacks 70A and 70B (partially). Next, as... Figure 32A and Figure 32B As shown, the gate stack 70 is recessed such that a groove (occupied by the CMG isolation region 110) is formed directly above the gate stack 70 and between the opposite portions of the gate spacer 38. Each of the grooves is filled with a gate mask 74 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like), followed by a planarization process to remove excess dielectric material extending above the ILD 52.

[0143] like Figure 32A and Figure 32B As further shown, ILD 76 is deposited above ILD 52 and gate mask 74. Individual process diagrams are as follows. Figure 34 Process 230 in the process flow 200 shown. An etch stop layer (not shown) may or may not be deposited prior to the formation of ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, or the like. ILD 76 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, or the like.

[0144] exist Figure 33A and Figure 33BIn this process, ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form recesses (occupied by contact sockets 80A and 80B), exposing the surfaces of the source / drain regions 48 and / or the gate stack 70. The recesses can be formed by etching using anisotropic etching processes (such as RIE, NBE, or similar).

[0145] After the groove is formed, a silicide region 78 is formed above the source / drain region 48. Some process diagrams are as follows. Figure 34 Process 232 in the process flow 200 shown. Next, a contact socket 80B is formed above the silicide region 78. Similarly, a contact 80A (also referred to as a gate contact socket) is formed in a recess and is above and in contact with the gate electrode 68. Individual process diagrams are as follows... Figure 34 Process 234 in the illustrated process flow 200. This forms transistors 82A and 82B. Although Figure 33B The illustrated contact sockets 80A and 80B are in the same cross-section, but in various embodiments, contact sockets 80A and 80B may be formed in different cross-sections to reduce the risk of short circuits between them.

[0146] The embodiments disclosed herein have several advantageous features. Continuous polysilicon on diffusion edge (CPODE) regions with rounded corner profiles at the terminals may suffer from device leakage. The ends of the CPODE regions may include leakage paths to contacts leading to the source / drain regions. In some embodiments, the methods and structures disclosed herein can remove leakage paths by cutting the ends of the CPODE regions.

[0147] According to some embodiments of the present disclosure, a method for forming a semiconductor device is described, the method comprising forming a plurality of semiconductor regions having a first length direction parallel to a first direction, and forming a plurality of gate stacks having a second length direction parallel to a second direction perpendicular to the first direction, wherein the plurality of gate stacks are on a first portion of the plurality of semiconductor regions.

[0148] The method may further include etching a plurality of semiconductor regions to form a first plurality of openings, wherein the first plurality of openings divide the plurality of semiconductor regions into a first shorter portion, and filling the first plurality of openings with a first dielectric material to form a fin isolation region. The method may further include forming an isolation interface region between the fin isolation region and a gate stack. In an embodiment, forming the isolation interface region between the fin isolation region and the gate stack includes forming a second plurality of openings at the interface between the fin isolation region and the gate stack, and filling the second plurality of openings with a second dielectric material. In an embodiment, the method further includes etching a plurality of gate stacks to form a third plurality of openings, wherein the third plurality of openings divide the plurality of gate stacks into a second shorter portion. In an embodiment, the method further includes filling the third plurality of openings with a third dielectric material. In an embodiment, the isolation interface region has a planar end face. In an embodiment, the isolation interface region includes a convex curvature protrusion extending toward the gate stack. In an embodiment, the isolation interface region includes a dielectric material selected from the group consisting of hafnium oxide, silicon oxynitride, zirconium dioxide, and combinations thereof.

[0149] According to some embodiments of this disclosure, a structure such as a semiconductor device is described, comprising a plurality of semiconductor layers, a plurality of gate stacks on a portion of the plurality of semiconductor layers, the plurality of gate stacks having a gate length perpendicular to the length of the semiconductor layers, and a plurality of fin isolation regions existing through the plurality of semiconductor layers, the plurality of fin isolation regions having a length direction perpendicular to the length of the semiconductor layers. The length direction of the plurality of fin isolation regions is aligned with the gate length. The structure further includes an isolation interface region between the plurality of fin isolation regions and at least one of the plurality of gate structures. In some embodiments, the structure further includes source / drain regions adjacent to the plurality of semiconductor layers. In some embodiments, the plurality of semiconductor layers are nanostructures. In some embodiments, the isolation interface comprises a first dielectric material, and the plurality of fin isolation regions comprise a second dielectric material. In some embodiments, the structure further includes a gate structure isolation region existing through the plurality of gate structures. In some embodiments, the gate structure isolation region includes a third dielectric material having the same composition as the first dielectric material. In some embodiments, the gate structure isolation region includes a third dielectric material having a different composition than the first dielectric material.

[0150] According to some embodiments of this disclosure, a structure such as a semiconductor device is described, comprising a plurality of semiconductor layers and a plurality of gate stacks. The plurality of gate stacks have gate lengths perpendicular to the lengths of the semiconductor layers. The structure may include a plurality of fin isolation regions existing through the plurality of semiconductor layers, the plurality of fin isolation regions having a length direction perpendicular to the lengths of the semiconductor layers. The plurality of fin isolation regions have a length direction aligned with the length of the gate. The device may include an isolation interface region between the plurality of fin isolation regions and at least one of the plurality of gate structures. The isolation interface region may include a plane abutting the plurality of fin isolation regions on a first sidewall and a protrusion extending from a second sidewall into the plurality of gate structures. In some embodiments, the structure includes source / drain regions adjacent to the plurality of semiconductor layers. In some embodiments, the plurality of semiconductor layers are nanostructures. In some embodiments, the isolation interface region includes a first dielectric material, and the plurality of fin isolation regions include a second dielectric material, wherein the first dielectric material is different from the second dielectric material. In some embodiments, a gate structure isolation region exists through the plurality of gate structures. In some embodiments, the gate structure isolation region includes a third dielectric material with the same composition as the first dielectric material.

[0151] According to some embodiments of this disclosure, a semiconductor device is described, comprising: a plurality of semiconductor layers, a plurality of gate stacks, a plurality of fin isolation regions, and an isolation interface region. The gate stacks are located on a portion of the semiconductor layers, and the gate stacks have a gate length perpendicular to the length of the semiconductor layers. The fin isolation regions exist through the semiconductor layers, and the fin isolation regions have a length direction perpendicular to the length of the semiconductor layers, wherein the length direction of the fin isolation regions is aligned with the gate length, and wherein the ends of each of the fin isolation regions have a profile with square corners. The isolation interface region is located between the fin isolation regions and at least one of the gate stacks. In some embodiments, the structure includes source / drain regions adjacent to the plurality of semiconductor layers.

[0152] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: Multiple semiconductor layers; Multiple gate stacks are stacked on a portion of the multiple semiconductor layers, the multiple gate stacks having a gate length perpendicular to a length of the multiple semiconductor layers; A plurality of fin isolation regions are present through the plurality of semiconductor layers, the plurality of fin isolation regions having a length direction perpendicular to the length of the plurality of semiconductor layers, wherein the length direction of the plurality of fin isolation regions is aligned with the gate length, and each of the plurality of fin isolation regions has an end having a profile, wherein a corner of the profile is square; and An isolation interface region is located between at least one of the plurality of fin isolation regions and the plurality of gate stacks.

2. The semiconductor device as claimed in claim 1, characterized in that, It further includes a plurality of source / drain regions adjacent to the plurality of semiconductor layers.

3. A semiconductor device, characterized in that, Include: Multiple semiconductor layers; Multiple gate stacks are stacked on a portion of the multiple semiconductor layers, the multiple gate stacks having a gate length perpendicular to a length of the multiple semiconductor layers; Multiple fin isolation regions exist through the multiple semiconductor layers, the multiple fin isolation regions having a length direction perpendicular to the length of the multiple semiconductor layers, wherein the length direction of the multiple fin isolation regions is aligned with the gate length; and An isolation interface region is located between at least one of the plurality of fin isolation regions and the plurality of gate stacks.

4. The semiconductor device as claimed in claim 3, characterized in that, It further includes a plurality of source / drain regions adjacent to the plurality of semiconductor layers.

5. The semiconductor device as claimed in claim 3, characterized in that, The plurality of semiconductor layers are multiple nanostructures.

6. The semiconductor device as claimed in claim 3, characterized in that, It further includes multiple gate structure isolation regions that exist through the multiple gate stacks.

7. A semiconductor device, characterized in that, Include: Multiple semiconductor layers; A plurality of gate structures on a portion of the plurality of semiconductor layers, the plurality of gate structures having a gate length perpendicular to a length of the plurality of semiconductor layers; Multiple fin isolation regions exist through the multiple semiconductor layers, the multiple fin isolation regions having a length direction perpendicular to the length of the multiple semiconductor layers, wherein the length direction of the multiple fin isolation regions is aligned with the gate length; and An isolation interface region is provided between at least one of the plurality of fin isolation regions and the plurality of gate structures, wherein the isolation interface region includes a planar end face on a first sidewall abutting the plurality of fin isolation regions, and a plurality of protrusions extending from a second sidewall into the plurality of gate structures.

8. The semiconductor device as claimed in claim 7, characterized in that, It further includes multiple source / drain regions on the plurality of semiconductor layers.

9. The semiconductor device as claimed in claim 7, characterized in that, The plurality of semiconductor layers are multiple nanostructures.

10. The semiconductor device as claimed in claim 7, characterized in that, It further includes multiple gate structure isolation regions that exist through the multiple gate structures.

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