Semiconductor structure

Abstract

A semiconductor structure. The semiconductor structure includes: a base fin over a substrate; first and second source / drain features over the base fin; a plurality of nanostructures extending between the first and second source / drain features along a first direction; and a gate structure surrounding each of the nanostructures. Each of the nanostructures has a shape of a bilaterally tapered spindle when viewed along the first direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generation after generation of ICs, each smaller and more complex than the last. In the evolution of ICs, functional density (i.e., the number of interconnects per die area) has generally increased, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. However, this shrinkage also increases the complexity of handling and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has evolved to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing the short-channel effect (SCE). A multi-gate device typically refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. Fin-like field-effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-efficiency and low-leakage applications. A FinFET has an elevated channel surrounded by gates on more than one side (e.g., gates surrounding the top and sidewalls of a "fin" of semiconductor material extending from the substrate). A GAA transistor has a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, the GAA transistor can also be called a surrounding gate transistor (SGT) or a multi-bridge-channel (MBC) transistor. The channel region of a GAA transistor can contain nanowires, nanosheets, or other nanostructures; therefore, GAA transistors can also be called nanowire transistors or nanosheet transistors. Fabricating GAA transistors is not without its challenges. Utility Model Content

[0004] In one exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate fin located above a substrate; a first source / drain feature and a second source / drain feature located above the substrate fin; a plurality of nanostructures extending along a first direction between the first source / drain feature and the second source / drain feature; and a gate structure surrounding each of the nanostructures. When viewed along the first direction, each of the nanostructures has a double-sided hammer shape.

[0005] In one exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes a first source / drain feature and a second source / drain feature; a plurality of nanostructures extending along a first direction between the first source / drain feature and the second source / drain feature; and a gate structure surrounding each of the nanostructures. The gate structure is spaced from the first source / drain feature by a first plurality of internal spacers, and the gate structure is spaced from the second source / drain feature by a second plurality of internal spacers. When viewed along the first direction, each of the nanostructures has a double-sided hammer shape.

[0006] In one exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate fin located above a substrate; a first source / drain feature and a second source / drain feature located above the substrate fin; a plurality of nanostructures extending along a first direction between the first source / drain feature and the second source / drain feature; and a bottom intermixed surface layer disposed above the top surface of the substrate fin. When viewed along the first direction, each of the nanostructures has a double-sided hammer shape. Attached Figure Description

[0007] This disclosure is best understood in conjunction with the accompanying drawings and the following detailed description. It is emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may be increased or decreased at will for clarity of discussion.

[0008] Figure 1 A flowchart illustrating a method for forming a semiconductor device according to one or more states of this disclosure is shown;

[0009] Figures 2 to 18 This illustrates one or more states according to this disclosure. Figure 1 Partial cross-sectional view of the work-in-progress (WIP) structure during the manufacturing process of the method;

[0010] Figure 19 , Figure 20 and Figure 21An enlarged cross-sectional view of the channel region of a semiconductor device along the gate width direction according to one or more states of the present disclosure is shown;

[0011] Figure 22 and Figure 23 An enlarged cross-sectional view of a channel region of a semiconductor device along the gate length direction according to one or more states of the present disclosure is shown.

[0012] [Symbol Explanation]

[0013] 100: Method

[0014] 102: Square

[0015] 104: Square

[0016] 106: Square

[0017] 108: Square

[0018] 110: Square

[0019] 112: Square

[0020] 114: Square

[0021] 116: Square

[0022] 118: Square

[0023] 120: Square

[0024] 122: Square

[0025] 124: Square

[0026] 126: Square

[0027] 128: Square

[0028] 200: WIP structure / semiconductor device

[0029] 202:Substrate

[0030] 202C: Channel Area

[0031] 202SD: Source / Drain Region

[0032] 204: Stacking

[0033] 206: Sacrifice Layer

[0034] 207: Intermixed Layer

[0035] 208: Channel Layer

[0036] 210: Hard mask layer

[0037] 212: Fin-like structure

[0038] 212B: Basement / Base Fins

[0039] 214: Isolation Features

[0040] 216: Dummy Dielectric Layer

[0041] 218: Dummy Gate Electrode

[0042] 220: Dummy gate stack

[0043] 222: Hard masking layer at the top of the gate

[0044] 223: First Hard Mask

[0045] 224: Second Hard Mask

[0046] 226: Gate spacer layer

[0047] 228: Source / Drain Trench

[0048] 230: Internal spacer groove

[0049] 232: Internal spacer material layer

[0050] 240: Characteristics of internal spacers

[0051] 242: Source / Drain Characteristics

[0052] 244: Contact Etching Stop Layer (CESL)

[0053] 246: Interlayer Dielectric (ILD) Layer

[0054] 247: Protective layer

[0055] 248: Gate Trench

[0056] 249: Openings between components

[0057] 250: Gate structure

[0058] 252: Gate dielectric layer

[0059] 254: Gate electrode

[0060] 300: Selective dry etching process

[0061] 400: Cleaning process

[0062] 500: Annealing process

[0063] 2070: Residual Intermixed Layer

[0064] 2080: Channel Components

[0065] 2080A: Channel Components

[0066] 2080B: Channel Components

[0067] 2080L: Petal section

[0068] 2080N: Neck section

[0069] 2100: Silicone Pad

[0070] 2200: Central protrusion

[0071] 2200A: Protrusion

[0072] 2300: Surface groove

[0073] 2400: Edge protrusion

[0074] A-A': Cross section

[0075] h1: Minimum height

[0076] h2: Mid-height

[0077] h3: Edge height

[0078] h4: End height

[0079] HL1: Height of the first petal

[0080] HL2: Second lobe height

[0081] HN1: First neck height

[0082] HN2: Second neck height

[0083] I-I': Cross section

[0084] L1: Channel length

[0085] L2: Groove length

[0086] W: Channel width Detailed Implementation

[0087] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0088] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientation depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly. Furthermore, when a number or a range of numbers is described using terms such as “about,” “approximately,” etc., unless otherwise stated, the term is intended to cover numbers within + / - 10% of the number described. For example, the term “about 5 nm” includes a size range of 4.5 nm to 5.5 nm.

[0089] This disclosure is generally about multi-gate transistors and methods of manufacturing them, and more specifically about the patterning of channel components of multi-gate transistors.

[0090] As described above, a GAA transistor has a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. A GAA transistor may contain more than one nanometer-sized channel components stacked together. In some techniques, the channel components are released after a sacrificial layer of different semiconductor compositions. In these techniques, the sacrificial layer and semiconductor layer released as channel components may undergo certain thermal cycles, such as at least one annealing process, to form source / drain characteristics. These thermal cycles may cause interdiffusion or mixing at the interface between the channel layer and the sacrificial layer. The mixed layer has a composition different from that of the channel layer or the sacrificial layer.

[0091] This disclosure provides an embodiment of a semiconductor device. The semiconductor device includes a plurality of channel components extending between two source / drain features. Each of the channel components is divided into a channel portion surrounded by a gate structure and a connection portion sandwiched between a gate spacer layer and an internal spacer feature or between two internal spacer features. According to this disclosure, the internal spacer feature includes an inner layer and an outer layer. The dielectric constant of the outer layer is greater than that of the inner layer. The outer and inner layers may contain silicon, carbon, oxygen, and nitrogen. The oxygen content of the outer layer is less than that of the inner layer, and the nitrogen content of the outer layer is greater than that of the inner layer. A portion of the outer layer facing the gate structure may be etched away together with the sacrificial layer, such that the gate structure contacts the inner layer. The channel component of this disclosure may not be straight. In some embodiments, the channel component may include a first ridge and an opposing second ridge located at the interface between the internal spacer feature and the gate structure. In some cases, the first and second ridges may extend partially between the internal spacer feature and the gate structure. For the outer layer, the internal spacer feature of this disclosure may have sufficient etch resistance to prevent damage to the source / drain features. A portion of the outer layer between the source / drain features and the gate structure can be removed. Since the dielectric constant of the inner layer is lower than that of the outer layer, removing the outer layer may reduce parasitic capacitance and improve device performance.

[0092] The various states disclosed herein will now be described in more detail with reference to the accompanying drawings. Figure 1 A flowchart of a method 100 for forming a semiconductor device from a WIP structure according to one or more embodiments of the present disclosure is shown. Method 100 is merely an example and is not intended to limit the present disclosure to what is expressly shown in method 100. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, eliminated, or moved for additional embodiments of these methods. For simplicity, not all steps are described in detail herein. Method 100 is described below with reference to partial cross-sectional views of WIP structures at different manufacturing stages according to embodiments of method 100.

[0093] refer to Figure 1 and Figure 2Method 100 includes block 102, in which a WIP structure 200 is provided. It should be noted that since the WIP structure 200 will be fabricated as a semiconductor device, it may also be referred to as a semiconductor device 200, depending on the context. The WIP structure 200 may include a substrate 202. Although not explicitly shown in the figures, the substrate 202 may include n-type and p-type well regions for fabricating transistors of different conductivity types. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Examples of III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. When present, each of the n-type and p-type wells is formed in the substrate 202 and includes a doping distribution. The n-type well may contain a doping distribution of n-type dopants (such as phosphorus (P) or arsenic (As)). The p-type well may contain a doping distribution of p-type dopants (such as boron (B)). The dopants in the n-type and p-type wells can be formed using ion implantation or thermal diffusion and can be considered part of the substrate 202. For the avoidance of doubt, the X, Y, and Z directions are perpendicular to each other.

[0094] like Figure 2 As shown, the WIP structure 200 also includes a stack 204 disposed on a substrate 202. The stack 204 includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206. The channel layers 208 and the sacrificial layers 206 may have different semiconductor compositions. In some embodiments, the channel layers 208 are formed of silicon (Si), and the sacrificial layers 206 are formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layers 206 allows for selective removal of the sacrificial layers 206 or their recessing without materially damaging the channel layers 208. In some embodiments, the sacrificial layers 206 and the channel layers 208 may be deposited using an epitaxial process. Suitable epitaxial processes include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Figure 2As shown, sacrificial layer 206 and channel layer 208 are deposited alternately one after another to form stack 204. It should be noted that the three (3) layers of sacrificial layer 206 and the three (3) layers of channel layer 208 are as follows... Figure 3 The alternating and vertical arrangement shown is for illustrative purposes only and is not intended to limit the specific contents listed in the claims. It is understood that any number of sacrificial layers and channel layers can be formed in the stack 204. The number of layers depends on the number of channel components required for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10. For patterning purposes, a hard mask layer 210 may be deposited over the stack 204. The hard mask layer 210 may be a single layer or multiple layers. In one example, the hard mask layer 210 comprises a silicon oxide layer and a silicon nitride layer.

[0095] refer to Figure 1 and Figure 3 Method 100 includes a block 104, wherein a fin-like structure 212 is formed from a stack 204. In some embodiments, the stack 204 and a portion of the substrate 202 are patterned to form the fin-like structure 212. Figure 3 As shown, the fin structure 212 extends perpendicularly from the substrate 202 along the Z-direction. The fin structure 212 includes a base portion 212B (or base fin 212B) formed by the substrate 202 and a stacked portion formed by the stack 204. The fin structure 212 can be patterned using suitable processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a lithography process. Spacers are formed next to the patterned material layer using a self-alignment process. The material layer is then removed, and the fin structure 212 can then be patterned using the remaining spacers or mandrels by etching the stack 204 and the substrate 202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0096] like Figure 3As shown, the operation at block 104 also includes forming an isolation feature 214 near and around the base portion of the fin structure 212. The isolation feature 214 is disposed between the fin structure 212 and another fin structure 212. The isolation feature 214 may also be referred to as a shallow trench isolation (STI) feature 214. In one example process, a dielectric layer is first deposited over the WIP structure 200, and the trench between the fin structure 212 and the adjacent fin structure is filled with a dielectric material. In some embodiments, the dielectric layer may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials. In various examples, the dielectric layer can be deposited using CVD processes, subatmospheric CVD (SACVD), flowable CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized using chemical mechanical polishing (CMP). The planarized dielectric layer is further recessed using dry etching, wet etching, and / or combinations thereof to form isolation features 214. Figure 3 As shown, the stacked portion of the fin-like structure 212 rises above the isolation feature 214. Although Figure 3 Although not explicitly shown, the hard mask layer 210 can also be removed during the formation of the isolation feature 214.

[0097] refer to Figure 1 , Figure 4 Figure 4 and Figure 5 Method 100 includes block 106, wherein a dummy gate stack 220 is formed over fin structure 212. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 220 serves as a reserved location for a functional gate structure. Other processes and configurations are also possible. In some embodiments, the dummy gate stack 220 is formed over isolation feature 214 and is at least partially disposed over fin structure 212. Figure 4 Figure 4 As shown, the dummy gate stack 220 extends longitudinally along the Y direction to surround the fin structure 212. The dummy gate stack 220 includes a dummy dielectric layer 216 and a dummy gate electrode 218. To illustrate how the dummy gate stack 220 is disposed above the fin structure 212, Figure 5The diagram provides a cross-sectional view along section A-A'. (Example) Figure 5 As shown, the portion of the fin structure 212 located below the dummy gate stack 220 is the channel region 202C. The channel region 202C and the dummy gate stack 220 also define the source / drain region 202SD, which does not vertically overlap with the dummy gate stack 220. The channel region 202C is disposed between the two source / drain regions 202SD. It should be noted that, due to... Figure 5 The cross-sectional view in the image is divided by fin structure 212, therefore the isolation feature 214 is not in the cross-sectional view. Figure 5 It is displayed in the middle.

[0098] In some embodiments, the dummy gate stack 220 is formed through various process steps such as layer deposition, patterning, etching, and other suitable processing steps. Exemplary layer deposition processes include low-pressure CVD (LPCVD), CVD, plasma-enhanced CVD (PECVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques, or combinations thereof. For example, the patterning process may include lithography (e.g., lithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching processes. In one example process, a dummy dielectric layer 216, a dummy electrode layer for a dummy gate electrode 218, and a gate top hard mask layer 222 are sequentially deposited over a WIP structure 200, including deposition over a fin structure 212. In some cases, the gate top hard mask layer 222 may be multilayered and may include a first hard mask 223 and a second hard mask 224 above the first hard mask 223. The first hard mask 223 may contain silicon oxide, and the second hard mask 224 may contain silicon nitride. Deposition can be performed using one of the exemplary layer deposition processes described above. The dummy dielectric layer 216 and the dummy electrode layer are then patterned using a lithography process to form a dummy gate stack 220. In some embodiments, the dummy dielectric layer 216 may contain silicon oxide, and the dummy gate electrode 218 may contain polycrystalline silicon.

[0099] After the dummy gate stack 220 is formed, a gate spacer layer 226 is formed along the sidewalls of the dummy gate stack 220. In some embodiments, the formation of the gate spacer layer 226 includes conformally depositing one or more dielectric layers over the WIP structure 200, and etching back the gate spacer layer 226 from the top surface of the WIP structure 200. In one example process, one or more dielectric layers are deposited using CVD, SACVD, or ALD, and the one or more dielectric layers are etched back in an anisotropic etching process to form the gate spacer layer 226. The gate spacer layer 226 may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, and / or combinations thereof.

[0100] refer to Figure 1 and Figure 6 Method 100 includes a block 108, wherein a source / drain trench 228 is formed in a fin structure 212. Figure 6 In the illustrated embodiment, the source / drain regions 202SD of the fin structure 212 not shielded by the gate top hard mask layer 222 and the gate spacer layer 226 are recessed to form source / drain trenches 228. The etching process at block 108 can be a dry etching process or a suitable etching process. For example, a dry etching process can be implemented using oxygen-containing gases, hydrogen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. Figure 6 As shown, the sidewalls of the sacrificial layer 206 and the channel layer 208 are exposed in the source / drain trench 228.

[0101] refer to Figure 1 and Figure 7Method 100 includes a block 110 in which an internal spacer recess 230 is formed. At block 110, a sacrificial layer 206 exposed in the source / drain trench 228 is selectively and partially recessed to form the internal spacer recess 230, while the exposed channel layer 208 is moderately etched. In embodiments where the channel layer 208 is substantially composed of silicon (Si) and the sacrificial layer 206 is substantially composed of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 may comprise a SiGe oxidation process followed by SiGe oxide removal. In this embodiment, the SiGe oxidation process may comprise the use of ozone (O3). In some other embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing of the sacrificial layer 206 is controlled by the duration of the etching process. The selective dry etching process may comprise the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Selective wet etching processes can include hydrogen fluoride (HF) or NH4OH etchants. For example... Figure 7 As shown, the channel layer 208 can be moderately etched at block 110, and the internal spacer recesses 230 can extend partially into the channel layer 208 along the Z direction. The depth (along the X direction) of each of the internal spacer recesses 230 is between approximately 2 nm and approximately 5 nm, and the height (along the Z direction) is between approximately 7 nm and approximately 12 nm. In other words, the height of each of the internal spacer recesses 230 is greater than its depth.

[0102] refer to Figure 1 , Figure 8 and Figure 9 Method 100 includes a block 112, wherein an internal spacer feature 240 is formed in an internal spacer recess 230. The operation at block 112 may include depositing an internal spacer material layer 232 (in... Figure 8 (as shown in the image) and the etched internal spacer material layer 232 to form the internal spacer feature 240 (in the image). Figure 9 (Shown in). In Figure 8 As shown, the internal spacer material layer 232 can be deposited using an ALD and may comprise silicon (Si), carbon (C), oxygen (O), and nitrogen. In some embodiments, the internal spacer material layer 232 may comprise silicon carbonitride. In some alternative embodiments, the internal spacer material layer 232 may comprise silicon carbonitride. (See reference...) Figure 9The deposited internal spacer material layer 232 is etched back to form internal spacer features 240. At block 112, the etch-back process removes the internal spacer material layer 232 on the channel layer 208, substrate 202, and gate spacer layer 226 to form internal spacer features 240 in the internal spacer recess 230. In some embodiments, the etch-back process at block 112 can be a dry etching process, which includes using oxygen-containing gas, hydrogen, nitrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas (e.g., CF3I), other suitable gases and / or plasma, and / or combinations thereof. As described above, the depth (along the X direction) of each of the internal spacer grooves 230 is between approximately 2 nm and approximately 5 nm, and the height (along the Z direction) is between approximately 7 nm and approximately 12 nm. Since each of the internal spacer features 240 is formed in the internal spacer grooves 230, each of the internal spacer features can also have a depth (along the X direction) between approximately 2 nm and approximately 5 nm and a height (along the Z direction) between approximately 7 nm and approximately 12 nm. In other words, the height (along the Z direction) of each of the internal spacer features 240 is greater than its depth (along the X direction).

[0103] refer to Figure 1 and Figure 10 Method 100 includes block 114, wherein source / drain features 242 are formed in source / drain trench 228. In some embodiments, the source / drain features 242 may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process may use gaseous and / or liquid precursors that interact with the composition of the substrate 202 and the channel layer 208. In some embodiments, the epitaxial growth process may include a process temperature between about 350°C and about 500°C. Depending on the conductivity type of the GAA transistor to be formed, the source / drain features 242 may be n-type or p-type source / drain features. Example n-type source / drain features may comprise Si, GaAs, GaAsP, SiP, or other suitable materials, and can be in-situ doped during the epitaxial process by introducing n-type dopants (such as phosphorus (P) or arsenic (As)), or out-of-situ doped using an implantation process (i.e., a junction implantation process). Example p-type source / drain features may comprise Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or other suitable materials, and can be in-situ doped during the epitaxial process by introducing p-type dopants, or out-of-situ doped using an implantation process (i.e., a junction implantation process).

[0104] refer to Figure 10 as well as Figure 19 A magnified view of the middle channel region 202C. Increased temperature may cause intermixing between the composition of the sacrificial layer 206 and the channel layer 208. The resulting intermixed layer 207 has a higher germanium content than the channel layer 208 but lower than the sacrificial layer 206. In terms of silicon content, the intermixed layer 207 contains more silicon than the sacrificial layer 206 but less than the channel layer 208. The increased germanium content of the intermixed layer 207 provides etch selectivity between the channel layer 208 and the sacrificial layer 206. That is, when the sacrificial layer 206 is selectively removed in a subsequent step, part or all of the intermixed layer 207 can also be removed. A similar intermixed layer 207 is also observed near the top surface of the substrate portion 212B. In some cases, the intermixed layer 207 does not have a uniform thickness along the length of the channel layer 208 and may have… Figure 10 and Figure 19 The wavy outline shown.

[0105] refer to Figure 1 and Figure 11 Method 100 includes block 116, in which a contact etch stop layer (CESL) 244 and an interlayer dielectric (ILD) layer 246 are deposited over a WIP structure 200. CESL 244 may comprise silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in this art, and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. Figure 11 As shown, CESL 244 can be deposited on the top surface of the source / drain feature 242 and along the sidewalls of the gate spacer layer 226. Although CESL 244 is also deposited above the gate spacer layer 226 and the top surface of the gate top hard mask layer 222, Figure 11Only a cross-sectional view is shown after the removal of the hard mask layer 222 on top of the gate. Block 116 also includes an ILD layer 246 deposited over CESL 244. In some embodiments, the ILD layer 246 comprises materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 246 can be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 246, the WIP structure 200 can be annealed to improve the integrity of the ILD layer 246. To remove excess material and expose the top surface of the dummy gate stack 220, a planarization process, such as chemical mechanical polishing (CMP), can be performed. Figure 11 As shown, the hard masking layer 222 on top of the gate is removed by a planarization process.

[0106] refer to Figure 1 and Figure 12 Method 100 includes block 118, wherein a protective layer 247 is deposited over ILD layer 246. To protect ILD layer 246 from damage during the gate replacement step, ILD layer 246 is selectively recessed to form a top recess, and the protective layer 247 is formed over the top recess. The protective layer 247 is formed of a material different from that of ILD layer 246. When ILD layer 246 contains silicon oxide, the protective layer 247 may contain silicon nitride, silicon carbonitride, silicon carbide, or silicon carbonitride. In one embodiment, the protective layer 247 may contain silicon nitride. Another planarization is performed to remove excess protective layer 247 and expose dummy gate stack 220. After planarization, the top surfaces of protective layer 247, CESL 244, gate spacer layer 226, and dummy gate stack 220 are coplanar.

[0107] refer to Figure 1 and Figure 13Method 100 includes block 120, in which a dummy gate stack 220 is removed. Exposing the dummy gate stack 220 at block 118 allows for removal of the dummy gate stack 220 at block 120. Removal of the dummy gate stack 220 may include one or more etching processes selectively applied to the material of the dummy gate stack 220. Removal of the dummy gate stack 220 results in the formation of a gate trench 248 over the channel region 202C. A gate structure 250 (described below) may then be formed in the gate trench 248. Removal of the dummy gate stack 220 may include one or more etching processes selectively applied to the material in the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof may be used to perform the removal of the dummy gate stack 220. After removal of the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 202C are exposed in the gate trench 248.

[0108] refer to Figure 1 and Figure 14 Method 100 includes block 122, wherein a sacrificial layer 206 in channel region 202C is selectively removed to release channel component 2080. After removing dummy gate stack 220, block 122 of method 100 may include the operation of selectively removing the sacrificial layer 206 between channel layers 208 in channel region 202C. Selective removal of sacrificial layer 206 releases channel layers 208 to form channel component 2080. The selective removal of sacrificial layer 206 may be implemented by a selective dry etching process 300. In some embodiments, selective dry etching process 300 includes using CF4, CF2Cl2, CCl4, BCl3, or HCl in gaseous or radical form. Selective dry etching process 300 is used to completely remove sacrificial layer 206. Since the composition of intermixed layer 207 is between the compositions of channel layer 208 and sacrificial layer 206, at least a portion of intermixed layer 207 may be removed to form residual intermixed layer 2070. In the depicted embodiment, residual intermixed layers 2070 may be present on the surfaces of the channel layer 208 and the base fin 212B that have been in contact with the sacrificial layer 206. Selective removal of the sacrificial layer 206 also forms intercomponent openings 249. Each of the intercomponent openings 249 is vertically disposed between the two residual intermixed layers 2070.

[0109] refer to Figure 1 and Figure 15Method 100 includes block 124, in which channel component 2080 is trimmed. Because the rough surface of the channel component and the presence of residual intermixed layer 2070 can affect device performance, the channel component 2080 released at block 122 undergoes a cleaning process 400 to selectively remove the residual intermixed layer 2070. In some embodiments, the cleaning process 400 includes wet etching using hydrogen fluoride (HF), ozone-deionized water (DIO3), ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), or mixtures thereof. The cleaning process 400 is used to remove or oxidize the residual intermixed layer 2070 and trim the channel component 2080. An aqueous solution of hydrogen fluoride (HF), fluorine radical etching, or a gas-phase reaction can be used in an oxide removal process to remove the oxidized residual intermixed layer 2070. Example fluorine radical etching may include: fluorine-containing gases such as NF3 (nitrogen trifluoride), SF6 (sulfur hexafluoride), CF4 (carbon tetrafluoride), OF2 (oxygen difluoride), HF (hydrogen fluoride), or mixtures thereof; and hydrogen-containing gases such as ammonia (NH3), hydrogen (H2), water (H2O), or combinations thereof. Example gas-phase reactions may include the use of hydrogen fluoride (HF), ammonia (NH3), alkylamines (C... x H y NH2) or combinations thereof. The cleaning process 400 and the oxide removal process also trim the channel component 2080. In some alternative embodiments, the operation at block 124 is omitted.

[0110] refer to Figure 1 , Figure 16 and Figure 17 Method 100 includes block 126, wherein a silicon pad 2100 is formed above channel component 2080. (See reference) Figure 16 The silicon pad 2100 is epitaxially deposited to achieve a smoother surface for the channel component 2080. In some embodiments, the silicon pad 2100 can be deposited using vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. In some cases, the silicon pad 2100 may have a thickness between about 0.3 nm and about 1.5 nm. The deposition of the silicon pad 2100 on the channel component 2080 (and the substrate fin 212B) can also be referred to as a silicon re-deposition process. To reduce defects, an annealing process 500 can be performed after the deposition of the silicon pad 2100, such as... Figure 17As shown. In some embodiments, in an environment containing nitrogen (N2), hydrogen (H2), or helium (He), the annealing process may include an annealing temperature between about 400°C and about 900°C. In some cases, the annealing process may include a process pressure between about 0.1 Torr and about 300 Torr. In some alternative embodiments, the operation at block 126 is omitted.

[0111] Annealing at block 126 can induce silicon atom surface migration to reduce surface roughness. Silicon atoms in silicon pad 2100 can migrate along the surface of channel component 2080 and the top surface of substrate fin 212B to achieve a smoother surface. Although surface planarization is performed during annealing process 500, the top surface of channel component 2080 and substrate fin 212B may still contain slightly wavy or concave surfaces. Figure 17 In the channel region 212C Figure 20 The image is magnified to schematically show an example outline of the channel component 2080 when viewed along the channel width direction (or the Y direction, which is perpendicular to the channel current direction (i.e., the X direction)). Figure 20 An example surface profile of a channel component 2080 is shown, wherein the top and bottom surfaces of each of the channel components 2080 include a central protrusion 2200 disposed between two edge protrusions 2400. Each of the two edge protrusions 2400 and the central protrusion 2200 defines a surface groove 2300. Each of the edge protrusions 2400 is configured to be adjacent to or disposed at the interface with the internal spacer feature 240. Figure 20 As shown, each of the channel components 2080 includes: a minimum height h1, wherein the channel component 2080 has the minimum height; and an edge height h3, which is defined between two opposing edge protrusions 2400. In some cases, the minimum height h1 is between about 2 nm and about 8 nm, and the edge height h3 is between about 3 nm and about 10 nm. The edge height h3 is greater than the minimum height h1. In some cases, the difference between the edge height h3 and the minimum height h1 is between 0 nm and about 6 nm. Each of the channel components 2080 also includes: an intermediate height h2, which is defined between the tips of two opposing intermediate protrusions 2200; and a terminal height h4, which is at the terminal surface of the channel component 2080. In some cases, the terminal height h4 is greater than the minimum height h1, and the edge height h3 is greater than the intermediate height h2. Along the gate length direction (i.e., Figure 20In the X direction), each of the channel components 2080 includes a channel length L1 and a groove length L2 from the edge protrusion 2400 and the position of the minimum height h1. In some embodiments, the channel length L1 is between about 5 nm and about 30 nm, and the groove length L2 is less than half of the channel length L1. The top surface of the base fin 212B may also include an intermediate protrusion 2200 disposed between the surface grooves 2300. Figure 20 In some embodiments illustrated, the top surface of the topmost channel member 2080 is substantially flat because it never interfaces with any sacrificial layer 206. In some alternative embodiments, the top and bottom surfaces of each of the channel members 2080 may include more than one protrusion similar to the intermediate protrusion, or may even have no protrusions at all. (See reference...) Figure 21 . Figure 21 The channel component 2080A in the middle includes a single intermediate protrusion 2200 on its top surface, but does not have an intermediate protrusion 2200 on its bottom surface. Figure 21 The channel component 2080B has a plurality of protrusions 2200A (such as between 2 and 5) on its top surface, but no intermediate protrusion 2200 on its bottom surface.

[0112] Figure 22 and Figure 23 It shows along Figure 17 An enlarged cross-sectional view of channel component 2080 at section I-I'. (See also...) Figure 22 and Figure 23 As shown, when viewed along the channel length direction (or the X direction, which is perpendicular to the channel width direction (i.e., the Y direction)), each of the channel components 2080 can have a shape similar to a double-sided maraca. That is, each of the channel components 2080 can include two lobe portions 2080L that enclose a narrower neck portion 2080N. Along the Y direction (i.e., the channel width direction), each of the channel components 2080 does not have a constant thickness. Each of the two lobe portions 2080L has a curvature of less than 2 nm. -1 The rounded end surface. Figure 22 and Figure 23In the bottom channel component 2080, each of the two lobe portions 2080L includes a first lobe height HL1, and the neck portion 2080N of the bottom channel component 2080 includes a first neck height HN1. Each of the two lobe portions 2080L of the intermediate channel component 2080 includes a second lobe height HL2, and the neck portion 2080N of the intermediate channel component 2080 includes a second neck height HN2. The first lobe height HL1 is greater than the first neck height HN1, and the second lobe height HL2 is greater than the second neck height HN2. The bottom channel component 2080 is thicker than the intermediate channel component 2080. In some embodiments, the first neck height HN1 is greater than the second neck height HN2, and the first lobe height HL1 is greater than the second lobe height HL2. The first lobe height HL1, the second lobe height HL2, the first neck height HN1, and the second neck height HN2 may be between about 1 nm and about 10 nm. Along the gate width direction, each of the channel components 2080 may have a channel width W, which may be between about 5 nm and about 90 nm.

[0113] refer to Figure 1 and Figure 18 Method 100 includes a block 128, wherein a (including forming to the inter-component opening 249) is formed above and around the channel component 2080. Figure 15 (As shown in the image) Gate structure 250. At block 128, gate structure 250 is formed above WIP structure 200 in gate trench 248 (in the image). Figure 14 The gate structure 250 is deposited within the channel region 202C, specifically in the inter-component opening 249 left after the removal of the sacrificial layer 206. In this regard, the gate structure 250 surrounds each of the channel components 2080 in the YZ plane. In some embodiments, the gate structure 250 includes a gate dielectric layer 252 and a gate electrode 254 formed over the gate dielectric layer 252. In one example process, the formation of the gate structure 250 may include the deposition of the gate dielectric layer 252, the deposition of the gate electrode 254, and a planarization process to remove excess material.

[0114] In some embodiments, gate dielectric layer 252 may comprise an intermediate layer and a high-k dielectric layer. The high-k gate dielectric used and described herein comprises a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermally oxidized silicon (~3.9)). The intermediate layer may comprise a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The intermediate layer may be deposited using chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. The high-k dielectric layer may comprise a high-k dielectric layer such as hafnium oxide. Alternatively, the high-k dielectric layer may comprise other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. High-k dielectric layers can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0115] The gate electrode 254 of the gate structure 250 may comprise a single layer or alternatively a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a pad layer, a wetting layer, an adhesion layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode 254 may comprise titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode 254 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, gate electrodes can be formed separately for n-type and p-type transistors, using different metal layers (e.g., metal layers for providing different n-type and p-type work functions). In various embodiments, planarization processes, such as CMP processes, can be performed to remove excess material from both the gate dielectric layer 252 and the gate electrode 254, thereby providing a substantially flat top surface of the gate structure 250. In some embodiments, due to the internal spacer feature 240 being exposed at the inter-component opening 249 (in... Figure 14 As shown in the diagram, the gate structure 250 fills the opening 249 between the components, so the gate structure 250 is in contact with the internal spacer feature 240.

[0116] It should be noted that the formation of the gate structure 250 does not substantially change the shape and outline of the channel component 2080. That is, Figure 17 and Figures 20 to 22 The description associated with channel component 2080 is generally applicable Figure 18 The channel component 2080 is shown in the figure. For example, the top and bottom surfaces of each of the channel components 2080 include a central protrusion 2200 disposed between two edge protrusions 2400. Each of the two edge protrusions 2400 and the central protrusion 2200 defines a surface groove 2300. Each of the edge protrusions 2400 is configured to be adjacent to or disposed at the interface with the internal spacer feature 240. In some alternative embodiments not shown in the figures, the top and bottom surfaces of each of the channel components 2080 may include two edge protrusions 2400 and more than one central protrusion 2200. The top surface of the base fin 212B may also include a central protrusion 2200 disposed between the surface grooves 2300. Figure 18In some embodiments shown, the top surface of the topmost channel component 2080 is substantially flat because the top surface of the topmost channel component 2080 never interfaces with any sacrificial layer 206.

[0117] In one exemplary embodiment, this disclosure relates to a method of manufacturing a semiconductor structure. The method includes: forming a fin-like structure over a substrate, the fin-like structure including a plurality of channel layers interleaved with a plurality of sacrificial layers; forming a dummy gate stack over the channel regions of the fin-like structure; forming a gate spacer layer along the sidewalls of the dummy gate stack; recessing source / drain regions to form source / drain trenches and exposing the sidewalls of the channel layers and sacrificial layers; selectively and partially etching the sacrificial layers to form internal spacer recesses; forming internal spacer features in the internal spacer recesses; forming source / drain features in the source / drain trenches; removing the dummy gate stack; selectively etching the sacrificial layers to release the channel layers in the channel regions as a plurality of channel components; cleaning the channel components; after cleaning, performing epitaxial deposition to form a semiconductor layer over the surface of the channel components; after epitaxial deposition, annealing the semiconductor layer; and forming a gate structure surrounding each of the channel components.

[0118] In some embodiments, the channel layer comprises silicon, and the sacrificial layer comprises silicon-germanium. In some embodiments, after the formation of the source / drain features, an intermix layer is formed at the interface between one of the channel layers and one of the sacrificial layers. The silicon content of the intermix layer is greater than the silicon content of the sacrificial layer, and the germanium content of the intermix layer is greater than the silicon-germanium content of the channel layer. In some embodiments, selective etching of the sacrificial layer etches the sacrificial layer faster than etching the intermix layer. In some embodiments, selective etching of the sacrificial layer comprises a dry etching process, and the dry etching process comprises using CF4, CF2Cl2, CCl4, BCl3, or HCl. In some cases, the cleaning comprises a wet etching process, and the wet etching process comprises hydrogen fluoride, ozone-deionized water, ammonium hydroxide, hydrogen peroxide, or mixtures thereof. In some cases, the method further comprises performing an oxide removal process on the channel components after the cleaning. The oxide removal process comprises using an aqueous solution of hydrogen fluoride, nitrogen trifluoride, sulfur hexafluoride, carbon tetrafluoride, oxygen difluoride, ammonia, hydrogen, water, alkylamine, or combinations thereof. In some embodiments, annealing is performed at a temperature between 400°C and 900°C in an environment containing nitrogen, hydrogen, or helium. In some embodiments, the semiconductor layer comprises silicon.

[0119] In another exemplary embodiment, this disclosure relates to a method of manufacturing a semiconductor structure. The method includes: forming a fin structure over a substrate, the fin structure including a base fin and a stack of multiple silicon layers interleaved with multiple silicon-germanium layers located above the base fin; forming a dummy gate stack over a channel region of the fin structure; forming a gate spacer layer along the sidewalls of the dummy gate stack; recessing the source / drain regions of the fin structure to form source / drain trenches; selectively and partially etching the silicon-germanium layer to form internal spacer recesses; forming internal spacer features in the internal spacer recesses; forming source / drain features in the source / drain trenches; removing the dummy gate stack; selectively etching the silicon-germanium layer to release silicon layers in the channel region as multiple channel components, each channel component including an intermingled surface layer; removing the intermingled surface layer from the channel components; after the removal, performing epitaxial deposition to form a silicon layer over the surface of the channel components; after the epitaxial deposition, annealing the silicon layer; and forming a gate structure surrounding each of the channel components.

[0120] In some embodiments, the silicon content of the intermixed surface layer is greater than the silicon content of the silicon-germanium layer, and the germanium content of the intermixed surface layer is greater than the silicon-germanium content of the silicon layer. In some embodiments, selective etching of the silicon-germanium layer includes a dry etching process, which includes the use of CF4, CF2Cl2, CCl4, BCl3, or HCl. In some embodiments, the removal includes a wet etching process, which includes hydrogen fluoride, ozone-deionized water, ammonium hydroxide, hydrogen peroxide, or mixtures thereof. In some embodiments, annealing includes a temperature between 400°C and 900°C in an environment containing nitrogen, hydrogen, or helium. In some embodiments, after the selective etching, a bottom intermixed surface layer is disposed above the top surface of the substrate fin. The germanium content of the bottom intermixed surface layer is greater than the silicon-germanium content of the substrate fin.

[0121] In another exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate fin located above a substrate; a first source / drain feature and a second source / drain feature located above the substrate fin; a plurality of nanostructures extending along a first direction between the first source / drain feature and the second source / drain feature; and a gate structure surrounding each of the nanostructures. When viewed along the first direction, each of the nanostructures has a double-sided hammer shape.

[0122] In some embodiments, the gate structure is spaced apart from the first source / drain feature by a first plurality of internal spacer features. The gate structure is spaced apart from the second source / drain feature by a second plurality of internal spacer features. In some embodiments, each of the nanostructures includes: a first bottom edge protrusion at the interface between the first source / drain feature and the first plurality of internal spacer features; and a second bottom edge protrusion at the interface between the second source / drain feature and the second plurality of internal spacer features. In some embodiments, each of the nanostructures includes: a middle bottom edge protrusion located along a first direction between the first bottom edge protrusion and the second bottom edge protrusion. In some embodiments, when viewed along a second direction perpendicular to the first direction, the top surface of the substrate fin below the nanostructure includes an upwardly extending middle protrusion.

[0123] In one exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes a first source / drain feature and a second source / drain feature; a plurality of nanostructures extending along a first direction between the first source / drain feature and the second source / drain feature; and a gate structure surrounding each of the nanostructures. The gate structure is spaced apart from the first source / drain feature by a first plurality of internal spacer features, and the gate structure is spaced apart from the second source / drain feature by a second plurality of internal spacer features. When viewed along the first direction, each of the nanostructures has a double-sided hammer shape. In some embodiments, each of the nanostructures includes: a first bottom edge protrusion located at the interface between the first source / drain feature and the first plurality of internal spacer features; and a second bottom edge protrusion located at the interface between the second source / drain feature and the second plurality of internal spacer features. In some embodiments, each of the nanostructures includes: a middle bottom edge protrusion located along the first direction between the first bottom edge protrusion and the second bottom edge protrusion.

[0124] In one exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate fin above a substrate; a first source / drain feature and a second source / drain feature above the substrate fin; a plurality of nanostructures extending along a first direction between the first source / drain feature and the second source / drain feature; and a bottom intermingled surface layer disposed above the top surface of the substrate fin. When viewed along the first direction, each of the nanostructures has a double-sided hammer shape. In some embodiments, when viewed along a second direction perpendicular to the first direction, the top surface of the substrate fin below the nanostructures includes an upwardly extending central protrusion.

[0125] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various modifications, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A base fin is positioned above a substrate; A first source / drain feature and a second source / drain feature are located above the substrate fin; Multiple nanostructures extend along a first direction between the first source / drain feature and the second source / drain feature; and A gate structure surrounds each of the plurality of nanostructures. When viewed along the first direction, each of the plurality of nanostructures has a shape resembling a double-sided sand hammer.

2. The semiconductor structure as described in claim 1, characterized in that, The gate structure is separated from the first source / drain feature by a plurality of internal spacers. The gate structure is separated from the second source / drain feature by a second plurality of internal spacers.

3. The semiconductor structure as described in claim 2, characterized in that, Each of the plurality of nanostructures includes: A first bottom edge protrusion is located at an interface between the first source / drain feature and the first plurality of internal spacer features, and A second bottom edge protrusion is located at an interface between the second source / drain feature and the second plurality of internal spacer features.

4. The semiconductor structure as described in claim 3, characterized in that, Each of the plurality of nanostructures includes: A central bottom edge protrusion is located between the first bottom edge protrusion and the second bottom edge protrusion along the first direction.

5. The semiconductor structure as described in claim 2, characterized in that, When viewed along a second direction perpendicular to the first direction, the top surface of the base fin beneath the plurality of nanostructures includes an upwardly extending central protrusion.

6. A semiconductor structure, characterized in that, include: A first source / drain characteristic and a second source / drain characteristic; Multiple nanostructures extend along a first direction between the first source / drain feature and the second source / drain feature; and A gate structure surrounds each of the plurality of nanostructures. The gate structure is separated from the first source / drain feature by a plurality of internal spacers. The gate structure is separated from the second source / drain feature by a second plurality of internal spacers. When viewed along the first direction, each of the plurality of nanostructures has a shape resembling a double-sided sand hammer.

7. The semiconductor structure as described in claim 6, characterized in that, Each of the plurality of nanostructures includes: A first bottom edge protrusion is located at an interface between the first source / drain feature and the first plurality of internal spacer features, and A second bottom edge protrusion is located at an interface between the second source / drain feature and the second plurality of internal spacer features.

8. The semiconductor structure as described in claim 7, characterized in that, Each of the plurality of nanostructures includes: A central bottom edge protrusion is located between the first bottom edge protrusion and the second bottom edge protrusion along the first direction.

9. A semiconductor structure, characterized in that, include: A base fin is positioned above a substrate; A first source / drain feature and a second source / drain feature are located above the substrate fin; Multiple nanostructures extend along a first direction between the first source / drain feature and the second source / drain feature; and A bottom intermixed surface layer is disposed above a top surface of the substrate fin; When viewed along the first direction, each of the plurality of nanostructures has a shape resembling a double-sided sand hammer.

10. The semiconductor structure as claimed in claim 9, characterized in that, When viewed along a second direction perpendicular to the first direction, the top surface of the base fin beneath the plurality of nanostructures includes an upwardly extending central protrusion.

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