Super junction semiconductor device terminal structure and super junction semiconductor device

Abstract

The utility model relates to a kind of terminal structure of super-junction semiconductor device and super-junction semiconductor device, including first conductive type substrate, first conductive type epitaxial layer, second conductive type terminal column, first field oxide layer and second field oxide layer, second conductive type terminal column is set in first conductive type epitaxial layer, multiple first field oxide layer is arranged and is set the front of the first conductive type epitaxial layer along first direction, second field oxide layer is set between adjacent two first field oxide layers, second field oxide layer and corresponding first field oxide layer are connected, first field oxide layer and second field oxide layer are made of different insulating materials, the utility model has the effect of relieving the electric field concentration of the front of first conductive type epitaxial layer below, smooth dispersion terminal area's surface electric field, optimize electric field distribution, to effectively suppress the early breakdown of terminal area, so that the actual breakdown voltage of device is more close to theoretical value, improve the reliability of device effect.

Description

Technical Field

[0001] This utility model relates to the technical field of semiconductor devices, and in particular to a terminal structure of a superjunction semiconductor device and the superjunction semiconductor device itself. Background Technology

[0002] Semiconductor devices are electronic devices whose conductivity lies between that of a good conductor and an insulator. They utilize the special electrical properties of semiconductor materials to perform specific functions and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. With the rapid development of emerging industries such as new energy, there is an increasing demand for high-power, high-voltage, and high-reliability power semiconductor devices. Among them, superjunction devices, as a new type of power device, are widely used in high-voltage and high-power power electronic equipment due to their advantages of low on-resistance and high breakdown voltage.

[0003] Superjunction semiconductor devices include a cell region and a termination region. The cell region and the termination region share a single epitaxial layer. The cell region employs alternating p-pillar and n-pillar structures, which can significantly optimize the device's conduction loss and breakdown voltage performance. The termination region also employs the same multiple p-pillars and N-pillars as the cell region, and a field oxide layer is placed above the epitaxial layer of the termination region.

[0004] Typically, field oxide layers are deposited on the surface of epitaxial layers using a single silicon oxide material. While these field oxide layers can provide some isolation and reduce the surface electric field to prevent premature breakdown, their breakdown resistance in actual superjunction semiconductor devices still needs improvement, resulting in poor reliability. Utility Model Content

[0005] In view of this, the purpose of this utility model is to provide a terminal structure and a superjunction semiconductor device to solve the technical problems of poor breakdown resistance and poor reliability in existing superjunction semiconductor devices.

[0006] This invention provides a termination structure for a superjunction semiconductor device, comprising: First conductivity type substrate; A first conductivity type epitaxial layer is disposed on the front side of a first conductivity type substrate; The second type of conductive terminal post is disposed within the first type of conductive epitaxial layer and extends from the front side to the back side of the first type of conductive epitaxial layer; The first field oxygen layer is provided in multiple forms, and the multiple first field oxygen layers are arranged along the first direction to form the front side of the first conductivity type epitaxial layer. A second field oxygen layer is provided between each two adjacent first field oxygen layers. The second field oxygen layer is connected to the corresponding first field oxygen layer. The first field oxygen layer and the second field oxygen layer are composed of different insulating materials.

[0007] Optionally, the insulating material of the first field oxygen layer includes silicon oxide, and the insulating material of the second field oxygen layer includes a high-k dielectric material.

[0008] Optionally, the width of the first field oxygen layer along the first direction is the same as the width of the second field oxygen layer along the first direction.

[0009] Optionally, it further includes a second conductivity type field limiting ring region, which is disposed on the front side of the first conductivity type epitaxial layer and within the first conductivity type epitaxial layer.

[0010] Optionally, multiple second-conductivity field-limiting ring regions are provided, and the multiple second-conductivity field-limiting ring regions are arranged at intervals along the first direction.

[0011] Optionally, it also includes a gate bus, the gate bus comprising: A polysilicon layer is disposed on the front side of the first conductivity type epitaxial layer and connected to the gate in the cell region; An insulating dielectric layer is disposed on the front side of the polycrystalline silicon layer; A first metal layer is disposed on the front side of the insulating dielectric layer. A first metal contact via is formed on the insulating dielectric layer at the location of the first metal layer. The first metal layer extends into the first metal contact via until it fills the first metal contact via.

[0012] Optionally, the insulating dielectric layer extends toward the first field oxygen layer and the second field oxygen layer until it covers the front surfaces of all the first field oxygen layer and the second field oxygen layer.

[0013] Optionally, it also includes: A first conductivity type cutoff ring is disposed on the front side of the first conductivity type epitaxial layer and located at the outer boundary of the terminal structure; A stop ring field plate is disposed on the front side of the first conductive type stop ring. The insulating dielectric layer extends toward the first conductive type stop ring until it covers the front side of the first conductive type stop ring. The insulating dielectric layer has a second metal contact through hole at the first conductive type stop ring. The stop ring field plate extends into the second metal contact through hole until it fills the second metal contact through hole.

[0014] This utility model also provides a superjunction semiconductor device, including a termination region and an active region. The termination region includes the termination structure of the superjunction semiconductor device, the termination structure surrounds the active region, a gate is disposed in the active region, a plurality of gates are connected in series, the gate bus is configured as a ring, the gate bus is disposed on the periphery of the active region and surrounds the active region, and the gates near the inner sidewall of the gate bus are connected to the gate bus.

[0015] Optionally, the active region and the terminal region share the first conductivity type substrate and the first conductivity type epitaxial layer, wherein the active region includes: At least two second conductivity type pillars are provided, extending from the front side to the back side of the first conductivity type epitaxial layer, and the gate is disposed between two adjacent second conductivity type pillars; The second conductivity type body region is disposed on the front side of the first conductivity type epitaxial layer and is located within the first conductivity type epitaxial layer; At least two first conductivity type source regions are provided, which are disposed on the front side of the second conductivity type body region and located within the second conductivity type body region. The first conductivity type source regions extend toward the corresponding gate and the second conductivity type pillar respectively.

[0016] The technical solution of this utility model has the following advantages: The superjunction semiconductor device termination structure provided by this invention changes the field oxide layer from a single field oxide layer to a composite field oxide layer structure consisting of alternating first and second field oxide layers, each composed of different insulating materials. By utilizing the difference in dielectric constants of different dielectric materials, the distribution of the electric field in the dielectric layer is adjusted, reducing the electric field concentration on the front side of the underlying first conductivity type epitaxial layer, smoothly dispersing the surface electric field in the termination region, and optimizing the electric field distribution. This effectively suppresses premature breakdown in the termination region, making the actual breakdown voltage of the device closer to the theoretical value and improving the reliability of the device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the overall structure of the superjunction semiconductor device of this utility model; Figure 2 is a schematic diagram of another embodiment of the superjunction semiconductor device of this utility model.

[0019] Explanation of reference numerals in the attached figures: 1. Substrate of first conductivity type; 2. Epitaxial layer of first conductivity type; 3. Termination pillar of second conductivity type; 4. First field oxide layer; 5. Second field oxide layer; 6. Field limiting ring region of second conductivity type; 7. Gate bus; 71. Polysilicon layer; 72. Insulating dielectric layer; 73. First metal layer; 8. Cut-off ring of first conductivity type; 9. Cut-off ring field plate; 10. Gate; 11. Pillar of second conductivity type; 12. Body region of second conductivity type; 13. Source region of first conductivity type; 14. Trench; 15. Gate oxide layer; 16. Shielding gate; 17. Front metal layer; 18. Back metal layer; 19. First metal contact via; 20. Second metal contact via; 21. Third metal contact via; 22. Termination region; 23. Active region. Detailed Implementation

[0020] The specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of this utility model. Based on the description of this utility model, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this utility model.

[0021] Unless otherwise explicitly specified and limited, the terms "setup," "installation," and "connection" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms based on the specific circumstances.

[0022] The terms “upper,” “lower,” “left,” “right,” “front,” “back,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are only for the convenience of description and simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0023] The terms “first,” “second,” “third,” etc., are used merely to distinguish elements with similar attributes, not to indicate or imply relative importance or a specific order.

[0024] The terms “include,” “comprising,” or any other variation thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0025] Example 1 Reference Figures 1-2 As shown, this utility model provides a terminal structure for a superjunction semiconductor device, including a first conductivity type substrate 1, a first conductivity type epitaxial layer 2, a second conductivity type terminal pillar 3, a first field oxide layer 4, and a second field oxide layer 5. In this embodiment, the top surface is set as the front surface and the bottom surface is set as the back surface. The first conductivity type substrate 1 is selected as N-type silicon as the substrate. The first conductivity type epitaxial layer 2 is disposed on the front surface of the first conductivity type substrate 1. The first conductivity type epitaxial layer 2 is grown by epitaxial process. The concentration of first conductivity type ions in the first conductivity type substrate 1 is greater than the concentration of first conductivity type ions in the first conductivity type epitaxial layer 2. At least two second conductivity type terminal pillars 3 are provided. The second conductivity type terminal pillars 3 extend from the front surface of the first conductivity type epitaxial layer 2 to the back surface of the first conductivity type epitaxial layer 2 until they are close to the first conductivity type substrate 1.

[0026] Both the first field oxide layer 4 and the second field oxide layer 5 are disposed on the front side of the first conductive epitaxial layer 2. Multiple first field oxide layers 4 are disposed, and the multiple first field oxide layers 4 are arranged along the first direction on the front side of the first conductive epitaxial layer 2. A gap is left between each two adjacent first field oxide layers 4. Similarly, multiple second field oxide layers 5 are disposed, and a second field oxide layer 5 is disposed between each two adjacent first field oxide layers 4, so that the multiple second field oxide layers 5 are also arranged along the first direction. The two sides of the second field oxide layer 5 are connected to the corresponding two adjacent first field oxide layers 4. The first field oxide layer 4 and the second field oxide layer 5 are both composed of different insulating materials.

[0027] By changing the field oxide layer from a single field oxide to a composite field oxide layer structure consisting of alternating first field oxide layer 4 and second field oxide layer 5, both of which are composed of different insulating materials, the electric field distribution in the dielectric layer is adjusted by utilizing the difference in dielectric constants of the different dielectric materials. This reduces the electric field concentration on the front side of the underlying first conductivity type epitaxial layer 2, smoothly disperses the surface electric field of the terminal region 22, and optimizes the electric field distribution. As a result, premature breakdown of the terminal region 22 is effectively suppressed, making the actual breakdown voltage of the device closer to the theoretical value and improving the reliability of the device.

[0028] Specifically, the insulating material of the first field oxide layer 4 includes silicon oxide, and the insulating material of the second field oxide layer 5 includes a high-k dielectric material. The high-k dielectric material includes, but is not limited to, one or more of Al2O3, TiO2, HfO2, and Si3N4. Silicon oxide has good interface characteristics with the silicon epitaxial layer, with a low interface state density but a low dielectric constant. The high-k dielectric material of the second field oxide layer 5 has a high dielectric constant and strong electric field modulation capability. The first field oxide layer 4 provides a stable interface, while the high-k dielectric material of the second field oxide layer 5 efficiently shares the voltage, achieving a synergistic effect. This reduces the electric field concentration on the front side of the first conductivity type epitaxial layer 2 below, smoothly disperses the surface electric field of the terminal region 22, optimizes the electric field distribution, and effectively suppresses the premature breakdown of the terminal region 22, making the actual breakdown voltage of the device closer to the theoretical value and improving the reliability of the device.

[0029] Furthermore, the first field oxide layer 4 and the second field oxide layer 5 are on the same plane on the side opposite to the first conductivity type epitaxial layer 2, ensuring overall smoothness. The width of the first field oxide layer 4 along the first direction and the width of the second field oxide layer 5 along the first direction are the same. Multiple first field oxide layers 4 are uniformly arranged along the first direction, and multiple second field oxide layers 5 are also uniformly arranged along the first direction. There is one second field oxide layer 5 between two adjacent first field oxide layers 4, and one first field oxide layer 4 between two adjacent second field oxide layers 5. This uniform width arrangement ensures that the modulation effect of the first field oxide layers 4 and the second field oxide layers 5 on the electric field presents a uniform and periodic distribution in the lateral dimension, which is beneficial for forming a stable lateral surface electric field distribution, thereby maximizing the breakdown voltage, ensuring the uniformity of the field oxide layer composed of the first field oxide layers 4 and the second field oxide layers 5, improving the breakdown resistance, and enhancing the reliability of the field oxide layer. In this embodiment, those skilled in the art can design the number of the first field oxide layers 4 and the second field oxide layers 5 according to the actual product size and performance requirements, and there is no single limitation.

[0030] As another implementation method, refer to Figure 1 As shown, the superjunction semiconductor termination structure also includes a second conductivity type field confinement ring region 6. The second conductivity type field confinement ring region 6 is disposed on the front side of the first conductivity type epitaxial layer 2 and within the first conductivity type epitaxial layer 2. The second conductivity type termination post 3 is disposed below the second conductivity type field confinement ring region 6, and its end facing the second conductivity type field confinement ring region 6 is connected to the second conductivity type field confinement ring region 6. By introducing the second conductivity type field confinement ring region 6, the width of the depletion region of the termination region 22 can be further expanded by forming a lateral PN junction, thus sharing the longitudinal electric field and achieving electric field optimization. This complements the function of the composite field oxygen layer modulating the surface electric field in combination with the first field oxygen layer 4 and the second field oxygen layer 5, forming a dual insurance mechanism of field confinement ring protection and surface composite field oxygen layer protection, significantly improving the overall withstand voltage capability of the termination structure.

[0031] As another implementation method, refer to Figure 2 As shown, multiple second conductivity type field-limiting ring regions 6 are provided, and the multiple second conductivity type field-limiting ring regions 6 are arranged at intervals along the first direction. Each second conductivity type terminal post 3 corresponds to a second conductivity type field-limiting ring region 6, and the top of the second conductivity type terminal post 3 is connected to the corresponding second conductivity type field-limiting ring region 6. Adjacent two second conductivity type field-limiting ring regions 6 are separated by a first conductivity type epitaxial layer 2. The multiple second conductivity type field-limiting ring regions 6 can gradually and smoothly reduce the electric field intensity at the edge of the terminal structure, forcing the electric field to extend gradually along the multiple second conductivity type field-limiting ring regions 6, avoiding electric field concentration, and more effectively suppressing edge breakdown.

[0032] As one specific implementation method, refer to Figure 1 and Figure 2 As shown, the terminal structure of the super semiconductor device also includes a gate bus 7, which is arranged in a ring shape and is located around the cell region and surrounds the cell region. The gate 10 in the active region 23 near the inner wall of the gate bus 7 is connected to the gate bus 7. The gate bus 7 includes a polysilicon layer 71, an insulating dielectric layer 72, and a first metal layer 73. The polysilicon layer 71 is disposed on the front side of the first conductivity type epitaxial layer 2 and is connected to the multiple gates 10 in the active region 23. The insulating dielectric layer 72 is disposed on the front side of the polysilicon layer 71, and the first metal layer 73 is disposed on the front side of the insulating dielectric layer 72. A first metal contact via 19 is formed on layer 72 at the first metal layer 73. The first metal layer 73 extends into the first metal contact via 19 until it is completely filled, so that the first metal layer 73 can be connected to the polysilicon layer 71 through the first metal contact via 19. This provides a stable, low-resistance common connection channel for the numerous gates 10 in the active region 23, and achieves a reliable electrical connection with the lower polysilicon layer 71 through the first metal contact via 19. This ensures that the gate signal can be transmitted uniformly and quickly to the gates 10 in all cells, reducing signal delay and loss.

[0033] In addition, the insulating dielectric layer 72 extends towards the first field oxygen layer 4 and the second field oxygen layer 5 until it covers the front surfaces of all the first field oxygen layers 4 and the second field oxygen layers 5. This insulating dielectric layer 72 can play a role in planarizing and protecting the composite field oxygen structure.

[0034] As another implementation method, refer to Figure 1 and Figure 2As shown, the termination structure of the superjunction semiconductor also includes a first conductivity type cutoff ring 8 and a cutoff ring field plate 9. The first conductivity type ion concentration of the first conductivity type cutoff ring 8 is greater than the first conductivity type ion concentration of the first conductivity type epitaxial layer 2. The first conductivity type cutoff ring 8 is disposed on the front side of the first conductivity type epitaxial layer 2 and located at the outer boundary of the termination structure. Specifically, the first conductivity type cutoff ring 8 is disposed within the second conductivity type field-limiting ring region 6, and the cutoff ring field plate 9 is disposed on the front side of the first conductivity type cutoff ring 8. The insulating dielectric layer 72 extends towards the first conductivity type cutoff ring 8 until it covers the front side of the first conductivity type cutoff ring 8. The cutoff ring field plate 9 is located on the front side of the first conductivity type cutoff ring 8. On the front side of the insulating dielectric layer 72, a second metal contact through-hole 20 is formed at the first conductive type cutoff ring 8. The cutoff ring field plate 9 extends into the second metal contact through-hole 20 until it is completely filled, so that the cutoff ring field plate 9 and the first conductive type cutoff ring 8 are in contact and connected. By setting the first conductive type cutoff ring 8 and the cutoff ring field plate 9, a physical boundary is set, which effectively suppresses the formation of the inversion layer and prevents premature failure caused by surface inversion. The cutoff ring field plate 9 is connected to the first conductive type cutoff ring 8 through the second metal contact through-hole 20, which can further modulate the electric field at the outermost edge of the terminal and ensure that the electric field is smoothly reduced to zero. It is the last key barrier for terminal protection.

[0035] Example 2 This embodiment provides a superjunction semiconductor device, which is configured as a MOSFET device or an IGBT device. In this embodiment, a MOSFET device is used as an example. The MOSS device includes an N-type MOSS device and a P-type MOSS device. For an N-type MOSS device, the first conductivity type is N-type and the second conductivity type is P-type; for a P-type MOSS device, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, an N-type MOSS device is used as an example.

[0036] Reference Figure 1-2 As shown, the superjunction semiconductor device includes a termination region 22 and an active region 23. The termination region 22 is provided with the termination structure of the superjunction semiconductor device in Embodiment 1. The active region 23 is provided with a gate 10. Multiple gates 10 are connected in series. The gate bus is arranged in a ring shape. The gate bus 7 is arranged on the periphery of the active region 23 and surrounds the active region 23. The gate 10 near the inner sidewall of the gate bus 7 is connected to the gate bus 7.

[0037] The active region 23 and the terminal region 22 share the first conductivity type substrate 1 and the first conductivity type epitaxial layer 2. Multiple gates 10 are disposed on the front side of the first conductivity type epitaxial layer 2. The active region 23 also includes a second conductivity type pillar 11, a second conductivity type body region 12, a first conductivity type source region 13, a front metal layer 17, and a back metal layer 18.

[0038] The second conductivity type body region 12 is disposed on the front side of the first conductivity type epitaxial layer 2 and located within the first conductivity type epitaxial layer 2. The width of the second conductivity type body region 12 and the width of the first conductivity type epitaxial layer 2 are the same. The first conductivity type source region 13 is disposed on the front side of the second conductivity type body region 12 and located within the second conductivity type body region 12. At least two first conductivity type source regions 13 are provided, and each gate 10 corresponds to two first conductivity type source regions 13. The gate 10 is located between two first conductivity type source regions 13. An insulating dielectric layer 72 is also disposed on the front side of the second conductivity type body region 12. A plurality of third metal contact vias 21 are formed in the insulating dielectric layer 72. The third metal contact vias 21 are connected to both the second conductivity type body region 12 and the first conductivity type source region 13. A front metal layer 17 is disposed on the second insulating dielectric layer 72. The front side of the substrate 17 is located at the third metal contact via 21 and extends into the third metal contact via 21 until it fills the third metal contact via 21. At this time, part of the front metal layer 17 in the third metal contact via 21 will contact the first conductivity type source region 13. The back side metal layer 18 is disposed on the back side of the first conductivity type substrate 1 and covers the entire back side of the first conductivity type substrate 1.

[0039] Furthermore, it also includes a trench 14 formed on the front side of the first conductivity type epitaxial layer 2. The trench 14 extends from the front side of the first conductivity type epitaxial layer 2 with the second conductivity type body region 12 to the back side of the first conductivity type epitaxial layer 2, until it extends into the first conductivity type epitaxial layer 2 on the back side of the second conductivity type body region 12. The gate 10 is located in the trench 14. Each trench 14 has a corresponding gate 10. A gate oxide layer 15 is disposed between the gate 10 and the inner wall of the trench 14. The gate 10 is separated from the inner wall of the trench 14 by the gate oxide layer 15. The thickness of the gate oxide layer 15 between the gate 10 and the inner bottom wall of the trench 14 is greater than the thickness of the gate oxide layer 15 between the gate 10 and the inner side wall of the trench 14. The thicker gate oxide layer 15 at the bottom can improve the gate oxide reliability of the device.

[0040] As another implementation, a shielding gate 16 is also provided in the trench 14. The shielding gate 16 is located below the gate 10, and the shielding gate 16 and the inner wall of the trench 14 are also separated by the gate oxide layer 15. There is a gap between the shielding gate 16 and the gate 10, which is also separated by the gate oxide layer 15. By providing the shielding gate 16, faster switching speed and lower switching loss can be achieved, further reducing the on-resistance and Miller capacitance, and improving the switching speed.

[0041] At least two second conductive type pillars 11 are provided. The second conductive type pillars 11 extend from the front side of the first conductive type epitaxial layer 2 with the second conductive type body region 12 to the back side of the first conductive type epitaxial layer 2, until they extend from the second conductive type body region 12 into the first conductive type epitaxial layer 2 below the second conductive type body region 12. The gate 10 is located between the two second conductive type pillars 11. The two first conductive type source regions 13 are located on both sides of the gate 10 in the direction towards the second conductive type pillars 11, and extend towards the second conductive type pillars 11 to contact them. The third metal contact via 21 is correspondingly provided with the second conductive type pillars 11, and the third metal contact via 21 will communicate with the second conductive type pillars 11, so that the front metal layer 17 located inside the third metal contact via 21 will contact the second conductive type pillars 11. By providing the second conductive type pillars 11, based on the charge balance technology, the thickness of the first conductive type epitaxial layer 2 is reduced under the same withstand voltage, thereby further reducing the on-resistance.

[0042] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0043] The above description is only a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model.

Claims

1. A termination structure for a superjunction semiconductor device, characterized in that, include: First conductivity type substrate; A first conductivity type epitaxial layer is disposed on the front side of a first conductivity type substrate; The second type of conductive terminal post is disposed within the first type of conductive epitaxial layer and extends from the front side to the back side of the first type of conductive epitaxial layer; The first field oxygen layer is provided in multiple forms, and the multiple first field oxygen layers are arranged along a first direction to form the front side of the first conductivity type epitaxial layer. A second field oxygen layer is provided between each two adjacent first field oxygen layers. The second field oxygen layer is connected to the corresponding first field oxygen layer. The first field oxygen layer and the second field oxygen layer are composed of different insulating materials.

2. The termination structure of the superjunction semiconductor device as described in claim 1, characterized in that, The insulating material of the first field oxygen layer includes silicon oxide, and the insulating material of the second field oxygen layer includes a high-k dielectric material.

3. The termination structure of the superjunction semiconductor device as described in claim 1, characterized in that, The width of the first field oxygen layer along the first direction is the same as the width of the second field oxygen layer along the first direction.

4. The termination structure of the superjunction semiconductor device as described in claim 1, characterized in that, It also includes a second conductivity type field limiting ring region, which is disposed on the front side of the first conductivity type epitaxial layer and within the first conductivity type epitaxial layer.

5. The termination structure of the superjunction semiconductor device as described in claim 4, characterized in that, Multiple second-conductivity field-limiting ring regions are provided, and the multiple second-conductivity field-limiting ring regions are arranged at intervals along the first direction.

6. The termination structure of the superjunction semiconductor device as described in claim 1, characterized in that, It also includes a gate bus, which comprises: A polysilicon layer is disposed on the front side of the first conductivity type epitaxial layer and connected to the gate in the cell region; An insulating dielectric layer is disposed on the front side of the polycrystalline silicon layer; A first metal layer is disposed on the front side of the insulating dielectric layer. A first metal contact via is formed on the insulating dielectric layer at the location of the first metal layer. The first metal layer extends into the first metal contact via until it fills the first metal contact via.

7. The termination structure of the superjunction semiconductor device as described in claim 6, characterized in that, The insulating dielectric layer extends toward the first field oxygen layer and the second field oxygen layer until it covers the front surfaces of all the first field oxygen layer and the second field oxygen layer.

8. The termination structure of the superjunction semiconductor device as described in claim 6, characterized in that, Also includes: A first conductivity type cutoff ring is disposed on the front side of the first conductivity type epitaxial layer and located at the outer boundary of the terminal structure; A stop ring field plate is disposed on the front side of the first conductive type stop ring. The insulating dielectric layer extends toward the first conductive type stop ring until it covers the front side of the first conductive type stop ring. The insulating dielectric layer has a second metal contact through hole at the first conductive type stop ring. The stop ring field plate extends into the second metal contact through hole until it fills the second metal contact through hole.

9. A superjunction semiconductor device, characterized in that, It includes a terminal region and an active region. The terminal region includes a terminal structure of the superjunction semiconductor device as described in any one of claims 6 to 7. The terminal structure surrounds the active region. A gate is disposed in the active region. A plurality of gates are connected in series. The gate bus is arranged in a ring shape. The gate bus is disposed on the periphery of the active region and surrounds the active region. The gate near the inner sidewall of the gate bus is connected to the gate bus.

10. The superjunction semiconductor device as described in claim 9, characterized in that, The active region and the terminal region share the first conductivity type substrate and the first conductivity type epitaxial layer, and the active region further includes: At least two second conductivity type pillars are provided, extending from the front side to the back side of the first conductivity type epitaxial layer, and the gate is disposed between two adjacent second conductivity type pillars; The second conductivity type body region is disposed on the front side of the first conductivity type epitaxial layer and is located within the first conductivity type epitaxial layer; At least two first conductivity type source regions are provided, which are disposed on the front side of the second conductivity type body region and located within the second conductivity type body region. The first conductivity type source regions extend toward the corresponding gate and the second conductivity type pillar respectively.

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