Panel level dual mos chip flip chip package structure
Patent Information
- Application Number
- CN202521404508.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-04
- Publication Date
- 2026-08-21
- Estimated Expiration
- 2035-07-04
AI Technical Summary
[0002]随着MOS功率器件在各行各业的应用范围逐渐扩大，产品在性能提升的同时封装尺寸小型化需求逐渐增大，产品性能提升伴随着芯片面积增大，故无法满足产品要求
[0013]本申请提供了一种Panel级双MOS芯片叠封封装结构，通过将两颗MOS芯片叠封封装结构，两颗芯片源极焊盘与源极焊盘分别通过其对应的源极引出区连接。栅极焊盘与芯片背面漏极焊盘通过对应的导电重布线层引出到外端实现具体功能，本申请可以缩小封装结构近一半的尺寸，集成度更高，双芯片比单芯片过流能力提升近1倍性能。
Smart Images
Figure CN224670190U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to a panel-level dual MOS chip stacked packaging structure. Background Technology
[0002] As the application of MOS power devices in various industries gradually expands, the demand for miniaturized packaging size is increasing while product performance is improving. However, the improvement in product performance is accompanied by an increase in chip area, which cannot meet the product requirements.
[0003] This solution is a new packaging structure developed based on Panel-level Fanout process technology, which improves performance while reducing the product's package size. Summary of the Invention
[0004] In order to fundamentally solve or alleviate the above-mentioned technical problems, this application provides a panel-level dual MOS chip stacked packaging structure, including: a first chip body and a second chip body;
[0005] The first chip body has a first gate pad and a first source pad on its front side; the second chip body has a first drain pad on its back side.
[0006] The second chip body has a second gate pad and a second source pad on its front side; the second chip body has a second drain pad on its back side.
[0007] The first gate pad is connected to the first gate lead-out region, the second gate pad is connected to the second gate lead-out region, the first source pad is connected to the first source lead-out region, and the second source pad is connected to the second source lead-out region.
[0008] A first conductive redistribution layer is provided between the first source lead-out region and the first source lead-out region, a second conductive redistribution layer is provided on the side of the first gate lead-out region away from the first chip body, and a third conductive redistribution layer is provided on the side of the second gate lead-out region away from the second chip body.
[0009] The second conductive redistribution layer and the third conductive redistribution layer are both spaced apart from the first conductive redistribution layer;
[0010] The first chip body has a fourth conductive redistribution layer on its drain pad, and the second chip body has an external pin on its drain pad.
[0011] The fourth conductive redistribution layer is connected to the external pin through the first conductive layer, and the third conductive redistribution layer is connected to the external pin through the second conductive layer.
[0012] In a preferred embodiment of this application, the first conductive redistribution layer, the second conductive redistribution layer, the third conductive redistribution layer, and the fourth conductive redistribution layer are all made of copper.
[0013] This application provides a panel-level dual MOS chip stacked package structure. By stacking two MOS chips, the source pads of the two chips are connected to each other through their corresponding source lead-out regions. The gate pad and the drain pad on the back of the chip are led out to the external end through corresponding conductive redistribution layers to achieve specific functions. This application can reduce the size of the package structure by nearly half, achieve higher integration, and improve the overcurrent capability of the dual-chip structure by nearly 100% compared to the single-chip structure. Attached Figure Description
[0014] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0015] Figure 1 This application provides a panel-level dual MOS chip stacked packaging structure. Detailed Implementation
[0016] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.
[0017] like Figure 1 As shown, this application provides a panel-level dual MOS chip stacked packaging structure, including: a first chip body 01 and a second chip body 02;
[0018] The first chip body 01 has a first gate pad 05 and a first source pad 03 on its front side; the second chip body 02 has a first drain pad on its back side.
[0019] The second chip body 02 has a second gate pad 06 and a second source pad 04 on its front side; and a second drain pad is provided on its back side.
[0020] The first gate pad 05 is connected to the first gate lead-out area 10, the second gate pad 06 is connected to the second gate lead-out area 09, the first source pad 03 is connected to the first source lead-out area 07, and the second source pad 04 is connected to the second source lead-out area 08.
[0021] A first conductive redistribution layer 11 is provided between the first source lead-out region 07 and the first source lead-out region 07. A second conductive redistribution layer 12 is provided on the side of the first gate lead-out region 10 away from the first chip body 01. A third conductive redistribution layer 13 is provided on the side of the second gate lead-out region 09 away from the second chip body 02.
[0022] The second conductive redistribution layer 12 and the third conductive redistribution layer 13 are both spaced apart from the first conductive redistribution layer 11;
[0023] The first chip body 01 has a fourth conductive redistribution layer 14 on its drain pad, and the second chip body 02 has an external pin 15 on its drain pad.
[0024] The fourth conductive redistribution layer 14 is connected to the external pin 15 through the first conductive layer 16, and the third conductive redistribution layer 13 is connected to the external pin 15 through the second conductive layer 17.
[0025] As a preferred embodiment of this application, the panel-level dual MOS chip stacked packaging structure described in claim 1 is characterized in that the first conductive redistribution layer 11, the second conductive redistribution layer 12, the third conductive redistribution layer 13 and the fourth conductive redistribution layer 14 are all made of copper.
[0026] like Figure 1 As shown, a molding compound 18 is wrapped around the entire first chip body 01 and the second chip body 02. The molding compound 18 is a material commonly used in the semiconductor field that is well known to those skilled in the art, and will not be described in detail here.
[0027] This application shortens the current conduction path, increases the electrical performance of the product, and reduces the product's package size by bonding the front sides of the two chips together.
[0028] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A panel-level dual MOS chip stacked packaging structure, characterized in that, include: First chip body and second chip body; The first chip body has a first gate pad and a first source pad on its front side; the second chip body has a first drain pad on its back side. The second chip body has a second gate pad and a second source pad on its front side; the second chip body has a second drain pad on its back side. The first gate pad is connected to the first gate lead-out region, the second gate pad is connected to the second gate lead-out region, the first source pad is connected to the first source lead-out region, and the second source pad is connected to the second source lead-out region. A first conductive redistribution layer is provided between the first source lead-out region and the first source lead-out region, a second conductive redistribution layer is provided on the side of the first gate lead-out region away from the first chip body, and a third conductive redistribution layer is provided on the side of the second gate lead-out region away from the second chip body. The second conductive redistribution layer and the third conductive redistribution layer are both spaced apart from the first conductive redistribution layer; The first chip body has a fourth conductive redistribution layer on its drain pad, and the second chip body has an external pin on its drain pad. The fourth conductive redistribution layer is connected to the external pin through the first conductive layer, and the third conductive redistribution layer is connected to the external pin through the second conductive layer.
2. The panel-level dual MOS chip stacked packaging structure as described in claim 1, characterized in that, The first conductive redistribution layer, the second conductive redistribution layer, the third conductive redistribution layer, and the fourth conductive redistribution layer are all made of metallic copper.