Semiconductor structure

Abstract

A semiconductor structure includes a substrate, an active region disposed on the substrate and including a channel region and a source / drain region, a gate structure disposed on the channel region of the active region and extending longitudinally along a first direction, a gate spacer disposed along a sidewall of the gate structure, and a source / drain feature disposed on the source / drain region of the active region. The channel region includes two sub-regions horizontally separated along the first direction by the gate structure.

Description

Technical Field

[0001] This utility model relates to a semiconductor technology, and more particularly to a semiconductor structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry is experiencing exponential growth. Technological advancements in IC materials and design have led to generation after generation of ICs, each generation smaller and more complex than the last. Throughout IC development, functional density (i.e., the number of interconnects per wafer area) has generally increased, while geometry (i.e., the smallest component (or line) that can be formed using manufacturing processes) has shrunk. This miniaturization typically brings numerous benefits due to increased production efficiency and reduced costs.

[0003] As integrated circuit (IC) technology moves toward smaller technology nodes, parasitic capacitance and leakage current (e.g., from the platform) can significantly impact the overall performance of IC components. While existing technologies are generally sufficient to achieve their intended purpose, they are not perfect in all aspects. Utility Model Content

[0004] The purpose of this invention is to propose a semiconductor structure to solve at least one of the above-mentioned problems.

[0005] In some embodiments, a semiconductor structure is provided, comprising: a substrate; an active region disposed on the substrate and including a channel region and a source / drain region; a gate structure disposed on the channel region of the active region and extending longitudinally along a first direction; a gate spacer disposed along one sidewall of the gate structure; and a source / drain feature disposed on the source / drain region of the active region. The channel region includes two sub-regions horizontally separated along the first direction by the gate structure.

[0006] According to one embodiment of the present invention, each of the two or more sub-regions has a first width along the first direction and is separated from each other by a first distance, and a first ratio of the first width to the first distance is 1 to 10.

[0007] According to one embodiment of the present invention, the active region is a first active region, the gate structure is a first gate structure, and the channel region is a first channel region.

[0008] According to one embodiment of the present invention, it further includes: a second active region and a third active region disposed above the substrate; a second gate structure extending longitudinally along the first direction and disposed above a second channel region of the second active region and a third channel region of the third active region; a fourth active region and a fifth active region disposed on the substrate; and a third gate structure extending longitudinally along the first direction and disposed on a fourth channel region of the fourth active region and a fifth channel region of the fifth active region.

[0009] According to one embodiment of the present invention, the second channel area and the third channel area each have a second width along the first direction and are separated from each other by a second distance; wherein the fourth channel area and the fifth channel area each have a third width along the first direction and are separated from each other by a third distance; and wherein a second ratio of the second width to the second distance and a third ratio of the third width to the third distance are different from the first ratio.

[0010] According to one embodiment of the present invention, the gate structure has a first portion disposed on two said sub-regions and a second portion disposed between the two said sub-regions.

[0011] According to one embodiment of the present invention, the second portion of the gate structure is in direct contact with an upper surface of a channel region located between the two sub-regions; wherein the first portion has a first width along a second direction perpendicular to the first direction; and wherein the second portion has a second width along the second direction that is greater than the first width.

[0012] According to one embodiment of the present invention, the source / drain feature includes a first epitaxial layer disposed above the source / drain region and a second epitaxial layer disposed above the first epitaxial layer, wherein the first epitaxial layer includes a dopant of a first concentration; and wherein the second epitaxial layer includes the dopant of a second concentration greater than the first concentration.

[0013] According to one embodiment of the present invention, the second epitaxial layer includes a first portion disposed on an upper surface of the first epitaxial layer and a second portion disposed along a sidewall of the first epitaxial layer.

[0014] According to one embodiment of the present invention, the first part has a first thickness and the second part has a second thickness; and wherein a ratio of the first thickness to the second thickness is equal to or greater than 2. Attached Figure Description

[0015] Figure 1 A flowchart illustrating a method for forming one or more types of semiconductor structures according to this disclosure is shown.

[0016] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18A and Figure 18B The illustration depicts one or more forms according to this disclosure. Figure 1 A partial cross-sectional schematic diagram of an exemplary semiconductor structure during each manufacturing stage of the method.

[0017] Figure 19 A partial planar schematic diagram of an exemplary semiconductor structure of one or more types according to this disclosure is shown.

[0018] Figure 20A and Figure 20B This illustrates one or more forms according to this disclosure, respectively along... Figure 19 The diagram shows a partial cross-sectional view of the semiconductor structure taken by the CC and DD lines.

[0019] Figure 21 A flowchart illustrating a method for forming one or more types of semiconductor structures according to this disclosure is shown.

[0020] Figure 22 , Figure 26 , Figure 31 and Figure 35 This illustrates one or more forms according to this disclosure. Figure 21 A partial planar schematic diagram of an exemplary semiconductor structure during each manufacturing stage of the method.

[0021] Figure 23 , Figure 24 , Figure 25 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 32 , Figure 33 , Figure 34 , Figure 36 , Figure 37A , Figure 37B and Figure 38 This illustrates one or more forms according to this disclosure. Figure 21A partial cross-sectional schematic diagram of the semiconductor structure during each manufacturing stage of the method.

[0022] Figure 39 A partial planar schematic diagram of an exemplary semiconductor structure of one or more types according to this disclosure is illustrated.

[0023] The attached figures are labeled as follows:

[0024] 100,400: Method

[0025] 102,104,106,108,110,112,114,116,118,120,122,402,404,406,408,410,412,414,416,418: Step Block

[0026] 200, 500: Working components; semiconductor structures; semiconductor devices

[0027] 202: Base

[0028] 204: Semiconductor layer stacking

[0029] 206: Sacrifice Layer

[0030] 208: Channel Layer

[0031] 212: Fin-shaped structure; active region

[0032] 212a, 212b: Active regions

[0033] 212B: Fin matrix structure

[0034] 212C: Passage Area

[0035] 212C-1, 212C-2: Subregions

[0036] 212SD: Source / Drain Region

[0037] 214: Isolation feature; Shallow Trench Isolation (STI) feature

[0038] 214a: Upper surface

[0039] 214b, 556b: Lower surface

[0040] 216: Virtual Dielectric Layer

[0041] 218: Dummy Electrode Layer

[0042] 220: Dummy Gate Stack

[0043] 222: Hard mask layer on top of gate

[0044] 223: Silicon oxide layer

[0045] 224: Silicon nitride layer

[0046] 226: Gate spacer layer

[0047] 228: Source / Drain Trench

[0048] 230: Inner spacer groove

[0049] 234: Inner Spacing Feature Component

[0050] 235a, 235b, 239a, 239b: Outline

[0051] 236: First epitaxial layer

[0052] 237,241: Gaps

[0053] 238: Second epitaxial layer

[0054] 240, 340, 540: Source / Drain Feature Components

[0055] 242: Contact Etching Stop Layer (CESL)

[0056] 244: Interlayer Dielectric (ILD) Layer

[0057] 245, 260: Dielectric layer

[0058] 246: Gate Trench

[0059] 250: Gate structure

[0060] 251, 551: Source / Drain Contact

[0061] 251a: Convex profile

[0062] 252: Silicide layer

[0063] 254n, 254p: Combined with active region

[0064] 300, 600: Semiconductor Structure

[0065] 305, 605: Zone 1

[0066] 315, 615: Second Zone

[0067] 325, 625: Third Zone

[0068] 550: Gate structure

[0069] 550a: Joint

[0070] 550b: Regular Department

[0071] 556,556': Groove

[0072] 558: Hard mask layer

[0073] 2080: Channel component

[0074] D1, D2, D3: Distance

[0075] T1, T2, T3: Thickness

[0076] W1, W2, W3, W4, W5, W6, W7: Width

[0077] Wt: Total channel width Detailed Implementation

[0078] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure provides specific examples of the various components and their arrangements to simplify the present invention. Of course, these are merely illustrative examples and are not intended to define the present invention. For example, if the following disclosure describes forming a first feature above or above a second feature, it indicates that it includes embodiments where the first and second feature are in direct contact, and also includes embodiments where additional feature components may be formed between the first and second feature components, so that the first and second feature components may not be in direct contact.

[0079] Additionally, reference numerals and / or text are repeated in various examples in this embodiment. This repetition is for simplification and clarity, not to specify the relationships between the different embodiments and / or configurations discussed. Furthermore, in subsequent embodiments, the formation of a feature component located on, connected to, and / or coupled to another feature component may include embodiments where the feature components are formed in direct contact, and may also include embodiments where additional feature components are sandwiched between the feature components, such that the feature components are not in direct contact. Furthermore, spatially related terms, such as “down,” “up,” “horizontal,” “vertical,” “above,” “above,” “below,” “below,” “upward,” “downward,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.), are used to facilitate the description of the relationship between one feature component and another in this embodiment. Spatially related terms are intended to cover different orientations of the device having feature components. Moreover, when using “about,” “approximately,” etc., to describe numbers or ranges of numbers, unless otherwise stated, the term covers numbers within + / - 10% of the described number. For example, the term "approximately 5nm" covers a size range from 4.5nm to 5.5nm.

[0080] As integrated circuit (IC) technology advances towards smaller technology nodes, multi-gate devices are being introduced to improve gate control by increasing gate channel coupling, reducing off-state current, and mitigating the short-channel effect (SCE). Multi-gate devices typically refer to devices with a gate structure or a portion thereof disposed on more than one side of the channel region. Fin-like field-effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising alternatives for high-efficiency and low-leakage applications. A FinFET has a raised channel surrounded by a gate on more than one side (e.g., the gate surrounds the top and sidewalls of a semiconductor material "fin" extending from the substrate). A GAA transistor has a gate structure that can partially or completely extend around the channel region to provide access to both or more sides of the channel region. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives alternative names to gate-wound (GAA) transistors, such as nanosheet transistors or nanowire transistors. Parasitic capacitance and leakage current affect the overall performance of multi-gate devices. Loss of isolation features during manufacturing can lead to deep gate structures and parasitic capacitance. While existing technologies are generally sufficient to achieve their intended purpose, they are not perfect in all aspects.

[0081] This embodiment provides various embodiments of semiconductor structures. Specifically, the semiconductor structure includes a multi-gate device, such as a gate fully wound (GAA) transistor or a fin field-effect transistor (FinFET). The semiconductor structure includes an active region or a combined active region, including a channel region and a source / drain region, a gate structure disposed above the channel region, and a source / drain feature disposed on the source / drain region. The channel region may include two or more channel layer stacks. The gate structure surrounds the channel layer and is disposed between adjacent channel layer stacks. The source / drain feature is connected to the two or more channel layer stacks and may include multiple epitaxial layers. In some embodiments, the combined active region includes two or more fin structures, and the source / drain feature is a merged source / drain feature disposed on two or more substrate fin structures of the two or more fin structures. In other embodiments, the source / drain feature is disposed on a single fin substrate structure of the active region. By surrounding two or more channel layers with a gate structure and connecting them to common source / drain features, while having a relatively large total channel width, gate control of the channel layer can be improved, short-channel effect and sheet-width load effect can be reduced, and process tolerance for gate replacement and metal gate patterning can be increased.

[0082] The various forms of this disclosure will now be described in more detail with reference to the accompanying drawings. Accordingly, Figure 1 A flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure is shown. Figure 21 A flowchart illustrating a method 400 for forming another semiconductor structure according to an embodiment of the present disclosure is provided. Methods 100 and 400 are merely examples and do not limit the present disclosure to the content expressly described in methods 100 and 400. Other steps may be provided before, during, and after the aforementioned methods 100 and / or 400, and certain steps may be replaced, omitted, or moved to suit other embodiments of the method. For simplicity, not all steps are described in detail herein. The following is accompanied by... Figure 2-18B Explanation of method 100, which is based on Figure 1 The following is a partial cross-sectional schematic diagram of the working part 200 at different manufacturing stages of an embodiment of method 100. (The following text is in conjunction with...) Figure 22-38 Explanation of method 400, which is based on Figure 21 The embodiments of method 400 are shown in partial plan view / cross-sectional view of alternative working parts 500 at different manufacturing stages. Since the working part 200 (or 500) will be fabricated as a semiconductor structure or semiconductor device, the working part 200 (or 500) may be referred to herein as semiconductor structure 200 (or 500) or semiconductor device 200 (or 500) as the context requires. Figures 19-20BA partial plan view / cross-sectional view of an exemplary semiconductor structure 300 according to one or more types of this disclosure is shown. Figure 39 A partial planar schematic diagram of an exemplary semiconductor structure 600 according to one or more types of this disclosure is shown. For the avoidance of ambiguity, Figure 2-20B In Figures 22-39, the X, Y, and Z directions are perpendicular to each other and are used consistently throughout this disclosure. Throughout this disclosure, unless otherwise stated, similar reference numerals denote the same characteristic parts. That is, the material properties and comparisons of various numbered parts related to the method or figures should be applied to the same numbered parts related to different methods or different figures.

[0083] Furthermore, the semiconductor structures disclosed herein may include various other devices and features, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, SRAM, and / or other types of logic circuits, etc., but are simplified for better understanding of the inventive concept of this disclosure. In some embodiments, exemplary devices include a plurality of interconnectable semiconductor devices (e.g., transistors), including n-gate fully wound (GAA) transistors, p-gate fully wound (GAA) transistors, p-field-effect transistors (PFETs), n-field-effect transistors (NFETs), etc.

[0084] Please refer to Figure 1 and Figure 2 Method 100 includes step block 102, in which a working component 200 is provided. For example... Figure 2As shown, the working component 200 includes a substrate 202 and an alternating semiconductor layer stack 204 formed over the working component 200. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 202 may include various doping configurations according to design requirements known in the art. In embodiments where the semiconductor device is p-type, an n-type doping profile distribution (i.e., an n-doped profile distribution or an n-well) may be formed on the substrate 202. In some embodiments, the n-type dopant used to form the n-type well region may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is n-type, a p-type doping profile distribution (i.e., a p-doped profile distribution or a p-well) may be formed on the substrate 202. In some embodiments, the p-type dopant used to form the p-type well region may include boron (B) or gallium (Ga). Suitable doping may include ion implantation dopant and / or diffusion processes. The substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 202 may optionally include an epitaxial layer, which may be strained to enhance performance, and may include silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structures and / or have other suitable reinforcing features.

[0085] In some embodiments, the semiconductor layer stack 204 above the substrate 202 includes a channel layer 208 composed of a first semiconductor and a sacrificial layer 206 composed of a second semiconductor interleaved therewith. Alternatively, the sacrificial layer 206 is interleaved with the channel layer 208. In some embodiments, the sacrificial layer 206 comprises silicon-germanium (SiGe) or germanium-tin (GeSn), while the channel layer 208 comprises silicon (Si). It should be noted that, as... Figure 2 As shown, three (3) sacrificial layers 206 and three (3) channel layers 208 are arranged alternately, which is for illustrative purposes only and is not intended to limit the scope beyond the specific description in the claims. It is understood that any number of epitaxial layers can be formed in the semiconductor layer stack 204.

[0086] The sacrificial layer 206 and channel layer 208 in the semiconductor layer stack 204 can be deposited using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and channel layer 208 are substantially doped (i.e., have an external dopant concentration from approximately 0 atoms / cm³ to 1 × 10¹⁷ atoms / cm³), wherein, for example, no deliberate doping is performed during the epitaxial growth process of the semiconductor layer stack 204.

[0087] Please refer to Figure 1 and Figure 3 Method 100 includes step block 104, wherein a fin structure 212 (also referred to as active region 212) is formed from a semiconductor layer stack 204 and a substrate 202. To pattern the semiconductor layer stack 204, a hard mask layer may be deposited on the semiconductor layer stack 204 to form an etch mask layer. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include an oxide pad layer and a nitride pad layer disposed above the oxide pad layer. The fin structure 212 may be patterned from the semiconductor layer stack 204 and the substrate 202 using optical lithography and etching processes. Optical lithography processes may include photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), and other suitable processes. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. Figure 3 As shown, the etching process at step block 104 forms a trench extending vertically through a portion of the semiconductor layer stack 204 and the substrate 202. The trench defines a fin structure 212. In some embodiments, a dual patterning process or a multiple patterning process may be used to define the fin structure, for example, with a spacing smaller than that achievable using a single direct optical lithography process. For example, in one embodiment, a material layer is formed on the substrate and patterned using an optical lithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can be used to etch a portion of the semiconductor layer stack 204 and the substrate 202 to pattern the fin structure 212. Figure 3 As shown, the fin-shaped structure 212, including the sacrificial layer 206 and the channel layer 208, extends vertically along the Z direction and longitudinally along the X direction. Figure 3As shown, the fin structure 212 includes a fin substrate structure 212B patterned from a substrate 202. A patterned semiconductor layer stack 204, including a sacrificial layer 206 and a channel layer 208, is directly disposed on the fin substrate structure 212B.

[0088] The isolation feature component 214 is adjacent to the fin-shaped structure 212. Figure 3 In some embodiments shown, isolation feature 214 is disposed on the sidewall of fin substrate structure 212B. In some embodiments, isolation feature 214 may be formed within a trench to isolate fin structure 212 from adjacent fin structures 212. Isolation feature 214 may also be referred to as shallow trench isolation (STI) feature 214. For example, in some embodiments, a dielectric layer is first deposited over substrate 202 and the trench is filled with this dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited using chemical vapor deposition (CVD), subatmospheric CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. Subsequently, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. Dry etching, wet etching, and / or combinations thereof further recess or pull back the planarized dielectric layer to form... Figure 3 The shallow trench isolation (STI) feature 214 is shown. The fin structure 212 rises above the shallow trench isolation (STI) feature 214 after being recessed, while the fin base structure 212B is embedded or buried within the isolation feature 214.

[0089] Please refer to Figure 1 , Figure 4 and Figure 5 Method 100 includes step block 106, wherein a dummy gate stack 220 is formed on channel region 212C of fin structure 212. Figure 5 For along Figure 4 A partial cross-sectional schematic diagram of the working component 200 as captured by line A-A'. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 220 (e.g.) Figure 4 and 5(As shown) This serves as a placeholder for various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 5 In some embodiments shown, a dummy gate stack 220 is formed on a fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 5 As shown, the channel region 212C is disposed between the two source / drain regions 212SD along the X direction.

[0090] Fabrication of the dummy gate stack 220 may include film deposition and patterning of the dummy gate stack 220. Please refer to... Figure 4 A dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 may be deposited over the working component 200 in a blanket manner. In some embodiments, the dummy dielectric layer 216 is formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an oxygen plasma oxidation process, or other suitable processes. In some embodiments, the dummy dielectric layer 216 may include silicon oxide. Subsequently, a dummy electrode layer 218 may be deposited over the dummy dielectric layer 216 using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or other suitable processes. In some embodiments, the dummy electrode layer 218 may include polysilicon. For patterning purposes, a gate top hard mask layer 222 may be deposited on the dummy electrode layer 218 using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or other suitable processes. Subsequently, the hard mask layer 222 on top of the gate, the dummy electrode layer 218, and the dummy dielectric layer 216 can be patterned to form a dummy gate stack 220, such as... Figure 5 As shown. For example, the patterning process may include lithography (such as optical lithography or electron beam lithography) and etching processes. The lithography process also includes photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable optical lithography techniques and / or combinations thereof. The optical lithography process forms a patterned photoresist layer. Then, in the etching process, the patterned photoresist layer is used as an etching mask to pattern the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. The etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 located above the silicon oxide layer 223. Figure 5As shown, the patterned dummy gate stack 220 is positioned only above the channel region 212C and not above the source / drain region 212SD.

[0091] Please refer to Figure 1 and Figure 6 Method 100 includes step block 108, wherein a gate spacer layer 226 is deposited over a working member 200 (including over a dummy gate stack 220). In some embodiments, the gate spacer layer 226 is conformally deposited over the working member 200, including on the upper surface and sidewalls of the dummy gate stack 220. For ease of description of a film layer having a substantially uniform thickness in different regions, the term "conformally" may be used herein. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon carbide, silicon carbide, or silicon carbonitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using, for example, chemical vapor deposition (CVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), or other suitable processes.

[0092] Please refer to Figure 1 and Figure 7 Method 100 includes step block 110, in which the source / drain regions 212SD of the anisotropically recessed fin structure 212 are formed to create a source / drain trench 228. Anisotropic etching may include dry etching or a suitable etching process to etch the source / drain regions 212SD and a portion of the substrate 202 beneath them. The resulting source / drain trench 228 extends vertically through the depth of the semiconductor layer stack 204 and locally extends into the substrate 202. Examples of dry etching processes for step block 110 may employ oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, C4F8 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof. Figure 7 As shown, the source / drain region 212SD of the recessed fin structure 212 exposes the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends below the stack 204 into the substrate 202, the source / drain trench 228 includes a lower surface and lower sidewalls defined within the substrate 202.

[0093] Please refer to Figure 1 , Figure 8 and Figure 9Method 100 includes step block 112, in which an inner spacer feature 234 is formed. Although not explicitly shown, the operational steps of step block 112 may include selectively and locally removing the sacrificial layer 206 to form the inner spacer recess 230 (shown in…). Figure 8 ), depositing internal spacer material above the working part 200, and etching back internal spacer material to form internal spacer feature 234 within the internal spacer groove 230 (shown in Figure 9 Please refer to... Figure 8 Selective and localized recesses are created in the sacrificial layer 206 exposed within the source / drain trench 228 to form an inner spacer recess 230, while the exposed portions of the gate spacer layer 226, the substrate 202, and the channel layer 208 are substantially unetched. In embodiments where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), selective wet etching or selective dry etching can be used to selectively recess the sacrificial layer 206. Exemplary selective dry etching processes may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Exemplary selective wet etching processes may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0094] After the inner spacer recess 230 is formed, an inner spacer material is deposited over the working component 200, including over the inner spacer recess 230. The inner spacer material may include metal oxides, silicon oxide, silicon carbonitride, silicon nitride, silicon oxynitride, silicon carbonitride-rich, or other dielectric materials. Metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, hafnium oxide, or other suitable metal oxides. Although not explicitly shown, the inner spacer material may be a single layer or multiple layers. In some embodiments, CVD, PECVD, SACVD, ALD, or other suitable methods may be used to deposit the inner spacer material. The inner spacer material is deposited within the inner spacer recess 230 and over the sidewalls of the channel layer 208 exposed within the source / drain trench 228. Please refer to... Figure 9 Next, the deposited inner spacer material is etched back to remove it from the sidewalls of the channel layer 208, forming an inner spacer feature 234 within the inner spacer recess 230. In step block 112, the inner spacer material may also be removed from the upper surface and / or sidewalls of the gate top hard mask layer 222 and the gate spacer layer 226. Figure 9 As shown, each inner spacer feature 234 is in direct contact with the recessed sacrificial layer 206 and is vertically disposed (along the Z direction) between two adjacent channel layers 208.

[0095] Although not explicitly shown, method 100 may include a cleaning process to clean the surface of the workpiece 200 prior to the formation of any epitaxial layer. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, a wet cleaning process may include removing oxides using Standard Cleaner 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), Standard Cleaner 2 (RCA SC-2, a mixture of deionized (DI) water, hydrochloric acid, and hydrogen peroxide), SPM (a mixture of sulfur peroxide), and / or hydrofluoric acid. A dry cleaning process may include helium (He) and hydrogen (H2) treatment. Hydrogen treatment can convert silicon on the surface into silane (SiH4), which can be extracted and removed.

[0096] Please refer to Figure 1 and Figures 10-13B Method 100 includes step block 114, wherein source / drain feature 240 is formed over source / drain region 212SD.

[0097] Please refer to Figures 10-11B The operation at step block 114 includes forming a first epitaxial layer 236 over the source / drain region 212SD. In some embodiments, the first epitaxial layer 236 can be epitaxially and selectively grown from the exposed sidewalls of the channel layer 208 and the exposed surface of the fin substrate structure 212B. Suitable epitaxial processes for step block 114 include vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process at step block 114 can use gaseous precursors that interact with the composition of the channel layer 208 and the fin substrate structure 212B. This allows the first epitaxial layer 236 to overgrow and merge over the inner spacer feature 234 and substantially fill the source / drain trench 228. In some embodiments, the first epitaxial layer 236 is doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the first epitaxial layer 236 is doped by an ion implantation process after the deposition process.

[0098] In some embodiments, when a p-type device (e.g., a transistor) is required, the first epitaxial layer 236 comprises silicon germanium (SiGe) and is doped with a p-type dopant, such as boron (B). In some embodiments, the first epitaxial layer 236 comprises a germanium (Ge) content between about 10% and 30%. This range of germanium (Ge) content is not unimportant. When the germanium content is greater than about 30%, the lattice mismatch between silicon and germanium can cause excessive defects at the interface between the first epitaxial layer 236 and the channel layer 208, which can lead to increased resistance or device failure. When the germanium content is less than about 10%, the channel layer 208 will not have sufficient strain to improve hole mobility. The concentration of the p-type dopant in the first epitaxial layer 236 can be about 2 × 10⁻⁶. 20 atoms / cm 3 Up to 1×10 21 atoms / cm 3 between.

[0099] In some embodiments, when an n-type device (e.g., a transistor) is required, the first epitaxial layer 236 comprises silicon, which is in-situ doped with an n-type dopant, such as arsenic (As), phosphorus (P), antimony (Sb), or a combination thereof. In some embodiments, the first epitaxial layer 236 is doped with phosphorus (P). The concentration of the n-type dopant in the first epitaxial layer 236 may be between about 1 × 10²¹ atoms / cm³ and 5 × 10²¹ atoms / cm³.

[0100] The type and amount of dopant affect the conductivity of this region, the lattice mismatch (e.g., stress) between the first epitaxial layer 236 and the channel layer 208 and the fin substrate structure 212B, as well as the epitaxial growth rate and facet formation. If the dopant concentration is too low, it cannot provide enough carriers to form the semiconductor device 200, while if the dopant concentration is too high, it will increase the lattice mismatch with the underlying film and other potential problems.

[0101] Figure 11A Show along Figure 10A partial cross-sectional view of the working component 200 taken by line B-B'. In some embodiments, two fin structures 212 are arranged adjacently, and the first epitaxial layers 236 corresponding to the fin substrate structure 212B are merged together during epitaxial growth. In the illustrated embodiment, the upper surface of the first epitaxial layer 236 is located below the upper surface of the topmost channel layer 208. The merged first epitaxial layer 236 may include an upper surface having a curved or non-linear profile 235a and a lower surface having a curved or non-linear profile 235b. In some embodiments, the curved or non-linear profile 235a is a concave profile. In some embodiments, the curved or non-linear profile 235b is a concave profile. Although not shown, it should be understood that more than two (e.g., three, four) first epitaxial layers 236 of fin structures 212 adjacent to each other may be merged together.

[0102] The channel layer has a width W1 along the Y direction as shown, which is approximately 5 nm to 50 nm. The distance D1 along the Y direction between two channel layers 208 in adjacent fin structures 212 can be approximately 5 nm to 20 nm. The ratio of width W1 to distance D1 can be in the range of approximately 1 to approximately 10. If the width W1 / distance D1 is too large (e.g., greater than 10), the width W1 may be too large, and the benefits of short-channel effect and drain-induced barrier lowering (DIBL) of semiconductor device 200 may be reduced or insignificant. If the width W1 / distance D1 is too small (e.g., less than 1), the width W1 may be too small, and the drive current in the channel layer 208 may be too small.

[0103] Figure 11B Show along Figure 10 Other partial cross-sectional schematic diagrams of the working part 200, taken by line B-B'. In the above embodiment, with Figure 11A The differences in the illustrated embodiments include: the merging of the two first epitaxial layers 236 may leave a gap 237 between them. This may be because the first epitaxial layers 236 are formed epitaxially and selectively from the corresponding exposed sidewalls of the channel layer 208 and the exposed surface of the fin matrix structure 212B. In some embodiments, the gap 237 has one or two openings leading to the external environment along the X direction. In some other embodiments, the gap 237 does not have openings leading to the external environment and is surrounded by the first epitaxial layers 236.

[0104] Please refer to Figures 12-13BThe operational steps of step block 114 include forming a second epitaxial layer 238 over the first epitaxial layer 236. In some embodiments, the second epitaxial layer 238 may be formed epitaxially and selectively from the first epitaxial layer 236. Suitable epitaxial processes include vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process may use a gaseous precursor that interacts with the composition of the first epitaxial layer 236. In some embodiments, the second epitaxial layer 238 is grown from a seed crystal including the surface of the first epitaxial layer 236. In some embodiments, the second epitaxial layer 238 is doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the second epitaxial layer 238 is doped by an ion implantation process following the deposition process. According to this embodiment, the volume of the second epitaxial layer 238 is smaller than the volume of the first epitaxial layer 236.

[0105] In some embodiments, when a p-type device (e.g., a transistor) is required, the second epitaxial layer 238 comprises silicon germanium (SiGe) and is doped with a p-type dopant, such as boron (B). In some embodiments, the Ge content of the second epitaxial layer 238 is greater than the germanium (Ge) content of the first epitaxial layer 236. In some embodiments, the germanium (Ge) content of the second epitaxial layer 238 is approximately between 25% and 65%. The concentration of the p-type dopant in the second epitaxial layer 238 is approximately 5 × 10⁻⁶. 20 atoms / cm 3 Up to 2×10 21 atoms / cm 3 between.

[0106] In some embodiments, when an n-type device (e.g., a transistor) is required, the second epitaxial layer 238 comprises silicon, which is in-situ doped with an n-type dopant, such as arsenic (As), phosphorus (P), antimony (Sb), or a combination thereof. In some embodiments, the second epitaxial layer 238 is doped with phosphorus (P). In some embodiments, the second epitaxial layer 238 comprises Si, GaAs, GaAsP, SiP, or other suitable materials. The concentration of the n-type dopant in the second epitaxial layer 238 is approximately 2 × 10⁻⁶. 21 atoms / cm 3 Up to 1×10 22 atoms / cm 3 between.

[0107] The type and amount of dopant affect the conductivity of the region, the lattice mismatch (e.g., stress) between the first epitaxial layer 236 and the second epitaxial layer 238, and the epitaxial growth rate and facet formation. If the dopant concentration is too low, it cannot provide enough carriers to form the semiconductor device 200; if the dopant concentration is too high, it will increase lattice mismatch with the underlying film and other potential problems. The dopant concentration in the second epitaxial layer 238 can be greater than that in the first epitaxial layer 236. Increasing the dopant concentration can provide the semiconductor device 200 with appropriate functionality while also reducing the resistance of the source / drain features 240.

[0108] Figure 13A Show along Figure 12 The diagram shows a partial cross-sectional view of the working component 200 taken along line B-B'. The second epitaxial layer 238 can grow from all exposed surfaces of the first epitaxial layer 236, thus growing along the contour of the first epitaxial layer 236. In some embodiments, the second epitaxial layer 238 has a curved or non-linear contour 239a and a lower surface having a curved or non-linear contour 239b. In some embodiments, the curved or non-linear contour 239a is a concave contour. In some embodiments, the curved or non-linear contour 239b is a concave contour. The working component 200 may include a gap 241 between the lower surface of the second epitaxial layer 238 and the isolation feature 214 below it. In some embodiments, the second epitaxial layer 238 includes a first portion disposed above the upper surface of the first epitaxial layer 236 and a second portion disposed along the sidewall of the first epitaxial layer 236. The first portion may provide a landing place for the source / drain contacts and / or subsequently formed silicide layer. The lower surface of the first part is located below the upper surface of the topmost channel layer 208. The first part may have a thickness T1 in the vertical direction, while the second part may have a thickness T2 in the horizontal direction. The thickness T1 may be approximately 5 nm to 20 nm. The thickness T2 may be controlled to be equal to or less than approximately 5 nm to prevent the source / drain feature 240 from merging with the epitaxial layer of an adjacent semiconductor device (e.g., as described below). Figure 19The third region 325 in the diagram. In some examples, the thickness T2 is approximately 1 nm to 5 nm. In some embodiments, the ratio of thickness T1 to thickness T2 is approximately equal to or greater than 2. If the ratio is too small, the second epitaxial layer 238 will be too thin to provide a location for the source / drain junction and / or the subsequently formed silicide layer. In the illustrated embodiment, the second epitaxial layer 238 also includes a third portion disposed below the first epitaxial layer 236 and having a thickness T3, which falls between the thickness T1 and the thickness T2. The different thicknesses are caused by the controlled growth of the second epitaxial layer 238 in different directions. For example, selective growth, radial growth, deposition, and etching can be used to form the second epitaxial layer 238.

[0109] Figure 13B Show along Figure 12 Other partial cross-sectional schematic diagrams of the working part 200, taken by line B-B'. In the above embodiment, with Figure 13A The differences shown in the example include: the merging of the two first epitaxial layers 236 may leave gaps 237 between them, such as... Figure 11B As shown. The second epitaxial layer 238 is formed locally (e.g. Figure 13B The top gap 237) or completely (as in Figure 13B Fill the bottom gap 237) in the middle.

[0110] Please refer to Figure 1 and Figures 14-15 Method 100 includes step block 116, in which dummy gate stack 220 is removed. Step block 116 may include depositing a contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 over the source / drain feature 240, and removing the dummy gate stack 220. Please refer to... Figure 14A contact etch stop layer (CESL) 242 is deposited on the working component 200, including on the source / drain feature component 240. The contact etch stop layer (CESL) 242 may include silicon nitride or aluminum nitride. In some embodiments, the contact etch stop layer (CESL) 242 may be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD). Then, an interlayer dielectric (ILD) layer 244 is deposited on the contact etch stop layer (CESL) 242. In some embodiments, the material of the interlayer dielectric (ILD) layer 244 includes, for example, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric (ILD) layer 244 may be deposited using chemical vapor deposition (CVD), flow-through chemical vapor deposition (FCVD), spin coating, or suitable deposition techniques. After depositing the interlayer dielectric (ILD) layer 244, the working component 200 may be planarized using a planarization process to expose the dummy gate stack 220. For example, the planarization process may include chemical mechanical planarization. The planarization (CMP) process exposes the dummy gate stack 220, allowing for its removal. Removal of the dummy gate stack 220 may include one or more etching processes selectively targeting the material of the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove the dummy gate stack 220, which are selective in targeting the dummy gate stack 220. After removal of the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed.

[0111] Please refer to Figure 1 and Figure 15 Method 100 includes step block 118, in which a plurality of channel layers 208 are released as channel members 2080. After removing the dummy gate stack 220, a sacrificial layer 206 located between the channel layers 208 in the channel region 212C is selectively removed. The selective removal of the sacrificial layer 206 forms a gate trench 246. The selective removal of the sacrificial layer 206 releases the channel layers 208 (e.g., Figure 14 (as shown), to form as Figure 15The channel component 2080 is shown. Selective removal of the sacrificial layer 206 can be achieved through selective dry etching, selective wet etching, or other selective etching processes. Examples of selective dry etching processes may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Examples of selective wet etching processes may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0112] Please refer to Figure 1 and Figure 16 Method 100 includes step block 120, in which a gate structure 250 is formed to surround each channel member 2080 released as a channel member 2080. After the channel members 2080 are released, the gate structure 250 is formed to cover each channel member 2080. Although not explicitly shown, the gate structure 250 includes: an interface layer in contact with the channel member 2080 and the substrate 202 in the channel region 212C, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The interface layer may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer may also comprise other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), europium zirconium oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), lanthanum zirconium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, and / or other suitable methods.

[0113] The gate electrode layer of gate structure 250 may include a single-layer or multi-layer structure, such as various bonds, substrates, wetting layers, adhesive layers, metal alloys, or metal silicides of a metal layer (work function metal layer) having a selected work function to enhance device performance. For example, the gate electrode layer may include titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), tantalum (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode layer may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or other suitable processes. In various embodiments, a chemical mechanical polishing (CMP) process can be performed to remove excess metal, thereby providing a substantially flat upper surface of the gate structure. The gate structure includes a portion between channel members 2080 in the channel region 212C.

[0114] Please refer to Figure 1 and Figures 17-18B Method 100 includes step block 122, wherein a source / drain contact 251 is formed over the source / drain feature 240. For simplicity, in Figure 17-18B In this diagram, the contact etch stop layer (CESL) 242 and the interlayer dielectric (ILD) layer 244 are shown as a combined dielectric layer 245. In some embodiments, an opening is formed within the dielectric layer 245 on the source / drain feature 240. The opening can be fabricated by patterning a hard mask or photoresist mask to define the opening and etching the dielectric layer 245 through this opening. Patterning can also be achieved or replaced by other suitable methods, such as maskless lithography, electron beam writing, ion beam writing, and molecular imprinting. Removal processes used to form the opening can include plasma etching, reactive ion etching (RIE), dry etching, wet etching, another suitable removal process, or a combination thereof.

[0115] Then, a contact filler metal or a combination of metals (e.g., copper, tungsten) is formed in the opening and connected to the source / drain feature 240. Various deposition processes can be applied to deposit the material forming the source / drain contact 251. For example, copper deposition may include physical vapor deposition (PVD) to form a seed layer and electroplating on the copper seed layer to form a copper bulk. In some embodiments, a silicide layer 252 may be formed on the source / drain feature 240 (e.g., on the second epitaxial layer 238) before filling the contact opening with conductive material to further reduce contact resistance. The silicide layer 252 may be located above the first epitaxial layer 236 and may be spaced apart from the first epitaxial layer 236 by the second epitaxial layer 238. In some embodiments, the above process may convert a portion of the second epitaxial layer 238 into the silicide layer 252. The silicide layer 252 comprises silicon and a metal, such as titanium silicide, tantalum silicide, nickel silicide, or cobalt silicide. The silicide layer 252 can be formed using a process called self-aligned silicide (or salicide). This process includes metal deposition, annealing to react the metal with silicon, and etching to remove unreacted metal. Contact openings are filled to form source / drain contacts 251, as shown below. Figures 17-18B As shown.

[0116] like Figures 17-18B As shown, the source / drain contact 251 is situated on the upper surface of the source / drain feature 240, which is disposed above two or more fin substrate structures 212B. This allows the source / drain contact 251 to be properly positioned on the source / drain feature 240 and at a suitable interface between the features, thereby reducing contact resistance. The lower surface of the source / drain contact 251 may have a convex profile 251a on the concave profile 239a of the source / drain feature 240.

[0117] Semiconductor device 200 may undergo further process steps to form various features and regions known in the art. For example, subsequent process steps may form additional interlayer dielectric (ILD) layers, additional contacts / vias / wiring, and multilayer interconnect features (e.g., metal layers and interlayer dielectric layers) on substrate 202 to connect various features to form a functional circuit, which may include one or more devices, including semiconductor device 200. In a further example, multilayer interconnects may include vertical interconnects (e.g., vias or contacts) and horizontal interconnects (e.g., metal lines). Various interconnect features may be made of various conductive materials, including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form a copper-associated multilayer interconnect structure.

[0118] Figure 19A partial plan view of an exemplary semiconductor structure 300 according to one or more embodiments of the present disclosure is shown. In some embodiments, the semiconductor structure 300 includes a first region 305, a second region 315, and a third region 325. The third region 325 may include a semiconductor device 200. The first region 305 and the second region 315 may include, for example, Figure 20A and Figure 20B The gate fully wound (GAA) device shown illustrates the following: Figure 19 A schematic diagram of a partial cross-section taken from lines C-C' and D-D'.

[0119] The first region 305, the second region 315, and the third region 325 may each include one or more n-type active regions 212a forming an n-type transistor and one or more p-type active regions 212b forming a p-type transistor. Depending on the context, the n-type active regions 212a and p-type active regions 212b may be referred to individually or collectively as active regions 212 or fin structures 212. In each of the first region 305, the second region 315, and the third region 325, a gate structure 250 is disposed above the active region, and a gate spacer layer 226 is disposed along the sidewall of the gate structure 250. Each active region 212 and the corresponding gate structure 250 disposed thereon form a transistor (e.g., a gate fully wound (GAA) device). The gate fully wound (GAA) devices in the first region 305 and the second region 315 differ from the working component 200 in that each source / drain feature 340 is disposed on a single fin substrate structure 212B, and the dimensional differences will be described below.

[0120] In the first region 305, each active region 212 may have a width W2, approximately 5 nm to 50 nm, and the distance D2 between two adjacent active regions 212 may be approximately 25 nm to 100 nm, or approximately 25 nm to 50 nm. In some embodiments, the width W2 is approximately the same as the width W1. In the second region 315, each active region 212 may have a width W3, approximately 20 nm to 200 nm, and the distance D3 between two adjacent active regions 212 may be approximately 25 nm to 50 nm. In some embodiments, the width W3 is greater than the width W2 and greater than the width W1. In the third region 325, each active region 212 may have the width W1 as described above, and the distance between two adjacent active regions 212 is the distance D1 as described above. The distance D1 is less than the distances D2 and D3, such that the source / drain feature 240 is a merged source / drain feature as described above. The merged source / drain feature 240 may have a width W4. In some embodiments, the total width W5 of the n-type active region 212a (or p-type active region 212b) and the spacing between them, as shown in the figure, can be approximately the same as the width W3. Width W5 can be equal to or less than width W4. The ratios of width W1 to distance D1, width W2 to distance D2, and width W3 to distance D3 can be different. In some embodiments, the ratio of width W1 to distance D1 is greater than the ratio of width W2 to distance D2. In some embodiments, the ratio of width W3 to distance D3 is greater than the ratio of width W1 to distance D1 and also greater than the ratio of width W2 to distance D2. Dimensions such as width W1, width W2, width W3, width W4, width W5, distance D1, distance D2, and distance D3 are all along the Y direction. Adjacent n-type active regions 212a (or p-type active regions 212b) and the space between them can collectively form a combined active region 254n (or combined active region 254p), as shown by the dashed rectangle. In some embodiments, the combined active region 254n (or combined active region 254p) may include two or more (e.g., three, four) n-type active regions 212a (or p-type active regions 212b), which include source / drain features 240 merged together. The combined active regions 254n (or combined active regions 254p) and the corresponding gate structures 250 in the third region 325 may form a transistor. The distance between adjacent combined active regions may be the distance D3 as described above.

[0121] Despite having a source / drain bonding feature 240, the bonding active region 254n (or bonding active region 254p) has a total channel width Wt, which is greater than the channel width W1 of each active region 212 in the third region 325 (e.g., for...). Figure 19The combined active region 254n (Wt = 2 × W1) in the first region 305 has a channel width W2 greater than that of each active region 212 in the first region 305. The gate structure 250 is disposed between adjacent active regions 212 in the combined active region 254n (or combined active region 254p) and surrounds each of its channel layers, thus increasing the gate structure's control over the channel layers in the combined active region 254n (or combined active region 254p) and also increasing the process tolerance of the metal gate replacement process (e.g., metal gate patterning process) in steps 116-120. In some embodiments, during operation, the devices in the first region 305 have relatively small currents, while the devices in the second region 315 and the third region 325 have relatively large currents, which may be due to differences in channel widths (e.g., width W3 > width W2 and total channel width Wt > width W2). In some embodiments, the short-channel effect and drain-induced barrier reduction (DIBL) of the devices in the first region 305 and the third region 325 are smaller compared to the devices in the second region 315, which may be due to the difference in channel width (e.g., width W2 < width W3). The first region 305, the second region 315, and the third region 325 may be designed for different device purposes.

[0122] Figure 21 Method 400 is an example method for forming another semiconductor structure 500. Method 400 is derived from... Figure 1 Step 112 of method 100 continues. Please refer to... Figures 21-25 Method 400 includes step block 402, wherein source / drain feature 540 is formed in the source / drain recess of working member 500. Figure 22 A partial planar schematic diagram of the working component 500 in step block 402 is shown.

[0123] Figures 23-25 Show along Figure 22 A partial cross-sectional view of the working component 500, taken from the D-D', E-E', and C-C' lines. The operation steps in step block 402 are similar to those described in step block 114 of method 100. The source / drain feature component 540 includes a first epitaxial layer 236 and a second epitaxial layer 238 similar to those described above. Compared to Figures 12-13B The differences between the illustrated working components 200 and 500 may include the following: The individual source / drain features 540 of the working component 500 may be disposed on a single fin substrate structure 212B. The source / drain features 540 may include a relatively flat upper surface (e.g., without a concave profile formed by the merged source / drain features). As described above, the channel layer 208 may have a width W5 and the source / drain features 540 may have a width W4.

[0124] Please refer to Figure 21 and Figures 26-28 Method 400 includes step block 404, wherein trench 556 is formed within dummy gate stack 220 and fin structure 212. Channel region 212C (e.g. Figure 23 As shown, sub-regions (e.g., sub-region 212C-1 and sub-region 212C-2) can be formed by dividing the area through trench 556. Figure 26 A partial planar schematic diagram of the working component 500 in step block 404 is shown. Figure 27-28 Show along Figure 26 A partial cross-sectional view taken by lines E-E' and C-C' in the diagram. Forming trench 556 may include forming a hard mask layer 558 over the working component 500, patterning the hard mask layer 558 to form an opening, and using the patterned hard mask layer 558 as an etch mask to etch the dummy gate stack 220 and the fin structure 212. The hard mask layer 558 may be removed after forming trench 556.

[0125] In one embodiment, the working component 200 undergoes optical lithography and etching processes to form a trench 556. A portion of the dummy gate stack 220 and a portion of the fin structure 212 are removed to form the trench 556. The etching process may include wet etching, dry etching, or a combination thereof. The etching process may use one or more etchants. In an example process, a hard mask layer 558 and a photoresist layer (not shown) are deposited over the working component 500. The photoresist layer is then exposed to patterned radiation transmitted through or reflected from the photomask, baked in a post-exposure baking process, developed in a developer, and then cleaned to form a patterned photoresist layer. The hard mask layer 558 is then etched using the patterned photoresist layer as an etching mask to form the patterned hard mask layer 558, as shown below. Figures 27-28 As shown. Then, using the patterned hard mask layer 558 as an etching mask, the dummy gate stack 220 and fin structure 212 are etched. The etching process can be a dry etching process, including the use of argon (Ar), fluorine-containing etchants (e.g., SF6, NF3, CH2F2, CHF3, C4F8 and / or C2F6), oxygen-containing etchants, chlorine-containing etchants (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing etchants (e.g., HBr and / or CHBr3), iodine-containing etchants, oxygen, hydrogen, other suitable gases, or combinations thereof.

[0126] In some embodiments, trench 556 has tapered sidewalls. For example, the width of the bottom of trench 556 may be smaller than the width of the top of trench 556 along the Y direction and / or along the X direction. Therefore, the width of the channel layer 208 along the Y direction of each sub-region (e.g., sub-regions 212C-1 and 212C-2) can gradually increase from top to bottom. In this embodiment, trench 556 extends through the dummy electrode layer 218, the dummy dielectric layer 216, and downwards into the fin structure 212, such as... Figures 27-28 As shown. The trench 556 may extend through at least one channel layer 208 and at least one sacrificial layer 206. In some embodiments, the trench 556 extends through the channel layer 208 and the sacrificial layer 206. In the illustrated example, the trench 556 further extends to the fin substrate structure 212B. In some embodiments, the lower surface 556b of the trench 556 is lower than the lower surface of the topmost sacrificial layer 206. The lower surface 556b is lower than the upper surface 214a of the isolation feature member 214 and higher than the lower surface 214b of the isolation feature member 214.

[0127] In the illustrated embodiment, the dummy gate stack 220 has a width W6 along the X direction, which is approximately 5 nm to 20 nm. The trench 556 has a width W7 along the X direction, which is approximately 15 nm to 30 nm. Figure 26 As shown, the width W7 is greater than the width W6. In the above embodiment, a portion of the gate spacer layer 226 and / or a portion of the inner spacer feature 234 is removed to form the trench 556. The trench 556 does not extend through the gate spacer layer 226 or the inner spacer feature 234 in the X direction. In other words, a portion of the gate spacer layer 226 and a portion of the inner spacer feature 234 remain between the trench 556 and the adjacent source / drain feature 540, as shown. Figure 28 As shown in the diagram, the width W7 is approximately the same as the width W6. In the above embodiment, when forming the trench 556, the gate spacer layer 226 and / or the inner spacer feature 234 are not removed.

[0128] In some embodiments, such as Figure 26 and Figure 27 As shown in the bottom active region 212, a trench 556 is formed within the active region 212, and the top of the channel region 212C of the active region 212 is divided into two sub-regions 212-1 and 212-2 (also referred to as sub-fin structures 212-1 and 212-2). The sub-regions include a semiconductor layer stack disposed above the same fin substrate structure 212B. In some other embodiments, more than one (e.g., two, three) trenches 556 are formed in the channel region 212C. For example, in... Figure 26In the top active region 212, three trenches 556 are formed, thus dividing the top of the channel region 212C of the active region 212 into four sub-regions. The number of sub-regions in the active region 212 is for illustrative purposes only and should not be construed as limiting the scope of this disclosure. The sub-regions may have a width W1 as described above, and the trenches 556 may have a width of a distance D1 as described above. The distance between the active regions 212 may be D3 as described above.

[0129] Please refer to Figure 21 and Figure 29 Method 400 includes step block 406, in which a dielectric layer 260 is deposited over the working component 500 using an appropriate deposition technique (e.g., atomic layer deposition (ALD), physical vapor deposition (PVD) process, or chemical vapor deposition (CVD) process). Figure 29 A partial cross-sectional schematic diagram of the working component 500 in step block 406 is shown. A dielectric layer 260 may be deposited on the lower surface 556b and sidewalls of trench 556, and on the upper surface of the dummy gate stack 220. The deposition may be compliant. The dielectric layer 260 may have a thickness of approximately 0.5 nm to 2 nm. In some embodiments, the dielectric layer 260 comprises an oxide layer, such as a silicon oxide layer (SiO2). The dielectric layer 260 may be used to control the subsequent chemical mechanical polishing (CMP) process described below.

[0130] Please refer to Figure 21 and Figure 30 Method 400 includes step block 408, in which polycrystalline semiconductor material 262 is deposited over working component 500 using an appropriate deposition technique (e.g., atomic layer deposition (ALD), physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process). Figure 30 A partial cross-sectional schematic diagram of the working component 500 in step block 408 is shown. The crystalline semiconductor material 262 includes polycrystalline silicon.

[0131] Please refer to Figure 21 and Figures 31-32 Method 400 includes step block 410, in which a chemical mechanical polishing (CMP) process is performed to remove a portion of the polycrystalline semiconductor material 262 and a portion of the dielectric layer 260 and expose the upper surface of the dummy gate stack 220. Figure 31 This is a partial planar schematic diagram of the working component 500 in step block 410, and Figure 32 Then it is along Figure 31 A partial cross-sectional view taken by the E-E' line. The chemical mechanical polishing (CMP) process removes the polycrystalline semiconductor material 262 and dielectric layer 260 from the upper surface of the dummy gate stack 220. The top of the dummy electrode layer 218 can also be removed in the chemical mechanical polishing (CMP) process.

[0132] Please refer to Figure 21 and Figure 33 Method 400 includes step block 412, in which polycrystalline semiconductor material 262, dielectric layer 260 and dummy gate stack 220 are removed. Figure 33 A partial cross-sectional schematic diagram of the working component 500 in step block 412 is shown. The operation steps of step block 412 are similar to those of step block 116 of method 100 described above. The difference includes that the polycrystalline semiconductor material 262 and dielectric layer 260 are also removed in step block 412. The removal of polycrystalline semiconductor material 262 and dielectric layer 260 may include one or more etching processes that selectively target the polycrystalline semiconductor material 262 and / or dielectric layer 260. For example, selective wet etching, selective dry etching, or a combination thereof that selectively targets the polycrystalline semiconductor material 262 and / or dielectric layer 260 may be used for removal. After removing the polycrystalline semiconductor material 262, dielectric layer 260, and dummy gate stack 220, the sidewalls of the channel layer 208 and sacrificial layer 206 in the sub-regions (e.g., sub-regions 212C-1 and 212C-2) are exposed. A groove 556' having a width similar to that of groove 556 along the Y direction is formed between adjacent sub-regions (e.g., sub-regions 212C-1 and 212C-2). Groove 556' includes the bottom of groove 556. The lower surface 556b of groove 556' is exposed.

[0133] Please refer to Figure 21 and Figure 34 Method 400 includes step block 414, in which multiple channel layers 208 are released as channel components 2080. Figure 34 This is a partial cross-sectional view of the working component 500 in step block 414. The operation steps of step block 414 are similar to those of step block 118 of method 100 described above. The difference includes that the channel member 2080 is formed by stacking in various sub-regions (e.g., sub-regions 212C-1 and 212C-2). The channel member 2080 has a width W1 along the Y direction as described above, adjacent stacks are spaced apart from each other by a distance D1 as described above, and the width W1 / distance D1 can be as described above.

[0134] Please refer to Figure 21 and Figures 35-37B Method 400 includes step block 416, wherein a gate structure 550 is formed to surround each channel member 2080. Figure 35 This is a partial cross-sectional view of the working component 500 at step block 416. Figures 36-37B respectively along Figure 35A partial cross-sectional view taken by the E-E', C-C', and F-F' lines in the diagram. The operation steps of step block 416 can be similar to the operation steps of step block 120 of method 100 as described above, and the gate structure 550 is similar to the gate structure 250. The difference includes that the gate structure 550 is formed within a trench 556' between adjacent sub-regions (e.g., sub-regions 212C-1 and 212C-2). The gate structure 550 is formed on the lower surface 556b. From a top view, the gate structure 550 may include a junction 550a disposed between adjacent sub-regions of the active region 212 and a regular portion 550b elsewhere. The junction 550a may have a width similar to that of the trench 556 or 556'. In the illustrated embodiment, the width W7 of the junction 550a is greater than the width W6 of the regular portion 550b. Please refer to Figures 37A-37B As shown, the thickness (along the X direction) of the gate spacer layer 226 and the inner spacer feature 234 disposed along the sidewall of the junction 550a is less than the corresponding thickness of the gate spacer layer 226 and the inner spacer feature 234 disposed along the sidewall of the junction 550a. In some embodiments not shown, the junction 550a and the regular portion 550b have the same width along the X direction. In the above embodiments, the thickness of the gate spacer layer 226 and the inner spacer feature 234 disposed along the sidewall of the junction 550a and the regular portion 550b is the same.

[0135] By dividing the top of the channel region 212C of the fin structure 212 into two or more sub-regions, the width of each channel member 2080 along the Y direction can be reduced, thereby improving the control of the channel member 2080 by the gate structure 550. The source / drain features 540 are each connected to the channel member 2080 of the two or more sub-regions, and there is no need to form merged source / drain features as in the operating member 200.

[0136] Please refer to Figure 1 and Figure 38 Method 400 includes step block 418, in which a source / drain contact 551 is formed onto a source / drain feature 540. The operational steps may be similar to those in step block 122 of method 100 as described above, and the source / drain contact 551 may be similar to the source / drain contact 251 as described above. The differences include that the source / drain contact 551 is located above the upper surface of the source / drain feature 540, and that the lower surface of the source / drain contact 551 does not have a convex profile.

[0137] Figure 39A partial planar schematic diagram of an exemplary semiconductor structure 600 according to one or more embodiments of the present disclosure is shown. In some embodiments, the semiconductor structure 600 includes a first region 605, a second region 615, and a third region 625. The first region 605 and the second region 615 are respectively connected to... Figure 19-20B The first region 305 and the second region 315 are similar. The third region 625 may include the semiconductor device 500 described above. In some embodiments, the first region 605, the second region 615, and the third region 625 each include an n-type active region 212a and a p-type active region 212b. Each of the n-type active region 212a and the p-type active region 212b, and the corresponding gate structure 550 disposed thereon, forms a transistor. Each active region 212 of the third region 625 includes a sub-region of the channel region 212C (e.g., sub-region 212C-1 and sub-region 212C-2). The number of sub-regions in the active region is for illustrative purposes only and should not be construed as limiting the scope of this disclosure.

[0138] In the third region 625, the total channel width Wt of the active regions 212a or 212b (e.g., for) Figure 39 The active region 212b in the first region 605 (Wt = 2 × W1) is greater than the channel width W2 of the active regions 212a / 212b in the second region 605. Furthermore, the gate structure 550 is disposed between adjacent sub-regions (e.g., sub-regions 212C-1 and 212C-2) in the active regions 212a / 212b and surrounds their respective channel layers. This increases the control of the gate structure 550 over the channel layers in the active regions 212a / 212b and also increases the process tolerance of the metal gate replacement process (e.g., metal gate patterning process) in steps 412-416. In some embodiments, during operation, the devices in the first region 605 have relatively small currents, while the devices in the second region 615 and the third region 625 have relatively large currents, which may be due to differences in channel widths (e.g., width W3 > width W2, and total channel width Wt > width W2). In some embodiments, the short-channel effect and drain-induced barrier reduction (DIBL) of the devices in the first region 605 and the third region 625 are smaller compared to the devices in the second region 615, which may be due to the difference in channel width (e.g., width W2 < width W3). The first region 605, the second region 615, and the third region 625 may be designed for different device purposes.

[0139] As can be understood by those skilled in the art, although Figure 2-Figure 20B Sections 22-39 illustrate a gate fully wound (GAA) device as an example. Other examples of semiconductor devices may benefit from the types of this disclosure, such as fin field-effect transistor (FinFET) devices.

[0140] While not limiting, one or more embodiments of this disclosure provide numerous benefits to semiconductor devices. For example, this disclosure reduces short-channel effects, wafer-width loading effects, and drain-induced barrier reduction (DIBL) by connecting two or more channel regions to the common source / drain feature disclosed herein, which increases control over the metal gate structure. Process tolerance for metal gate substitution can also be increased. Therefore, the overall performance of the semiconductor device can be improved.

[0141] In one exemplary embodiment, a method for forming a semiconductor structure is provided. The method includes: providing a working component. The working component includes: a fin-shaped structure having a fin substrate and a semiconductor layer stack located on the fin substrate; a dummy gate structure disposed on the semiconductor layer stack; and a source / drain feature connected to a channel layer of the semiconductor layer stack. The semiconductor layer stack includes a plurality of channel layers interleaved with a plurality of sacrificial layers. The method further includes: forming a trench within the dummy gate structure and the fin-shaped structure; depositing a dielectric layer within the trench; depositing a polycrystalline semiconductor material on the dielectric layer; performing a planarization process on the working component; and replacing the dielectric layer, the polycrystalline semiconductor material, the dummy gate structure, and the sacrificial layers with a metal gate structure.

[0142] In some embodiments, the dummy gate structure extends longitudinally along a direction, and a trench divides a top of the fin structure into two segments. The trench has a first width of about 5 nm to 20 nm along the direction, and each of the two segments has a second width of about 5 nm to 50 nm in the direction. In some embodiments, forming the trench includes: forming a hard mask on the dummy gate structure; patterning the hard mask to form an opening within the hard mask; and using the patterned hard mask as an etching mask to etch the dummy gate structure and the fin structure to form the trench. In some embodiments, the trench extends through a semiconductor layer stack and extends to the fin substrate. In some embodiments, depositing a dielectric layer includes: depositing a dielectric layer on a lower surface and a plurality of sidewalls of the trench and on an upper surface of the dummy gate structure. In some embodiments, performing a planarization process includes: removing the dielectric layer located on the upper surface of the dummy gate structure. In some embodiments, the source / drain feature includes: a first epitaxial layer disposed on a fin substrate; and a second epitaxial layer disposed on the first epitaxial layer, the second epitaxial layer having a first portion disposed on an upper surface of the first epitaxial layer and a second portion disposed along a sidewall of the first epitaxial layer, the first portion having a first thickness and the second portion having a second thickness less than the first thickness. In some embodiments, the method further includes forming a silicide layer on the second epitaxial layer and forming a source / drain contact on the silicide layer.

[0143] In another exemplary embodiment, a method for forming a semiconductor structure is provided. The method includes: providing a working component, the working component including a substrate and a fin-shaped structure protruding from the substrate. The fin-shaped structure extends longitudinally along a first direction. The method further includes: forming a dummy gate structure on the fin-shaped structure and extending longitudinally along a second direction perpendicular to the first direction; forming a gate spacer along a sidewall of the dummy gate structure; forming a source / drain trench within the fin-shaped structure and adjacent to the gate spacer; forming a source / drain feature within the source / drain trench; forming a trench within the dummy gate structure and the fin-shaped structure; filling the trench with a dielectric layer and a polycrystalline semiconductor material; performing a planarization process on the working component; and replacing the dielectric layer, the polycrystalline semiconductor material, and the dummy gate structure with a metal gate structure.

[0144] In some embodiments, forming source / drain features within a source / drain trench includes: forming a first epitaxial layer within the source / drain trench; and forming a second epitaxial layer on the first epitaxial layer. The second epitaxial layer has a first portion located on an upper surface of the first epitaxial layer and a second portion along a sidewall of the first epitaxial layer, wherein the first portion has a first thickness and the second portion has a second thickness less than the first thickness. In some embodiments, forming the trench removes a portion of the gate spacer, a portion of the dummy gate structure, and a portion of the fin structure. In some embodiments, the working component further includes an isolation feature disposed on the substrate and adjacent to the fin structure, wherein a lower surface of the trench is located below an upper surface of the isolation feature. In some embodiments, filling the trench with a dielectric layer and a polycrystalline semiconductor material includes: conformally depositing a dielectric layer within the trench and on the upper surface of the dummy gate structure; and filling the trench with a polycrystalline semiconductor material. In some embodiments, forming a trench includes: forming a hard mask layer on a dummy gate structure; patterning the hard mask layer to form an opening within the hard mask layer; and using the patterned hard mask layer as an etch mask to etch the dummy gate structure and the fin structure.

[0145] In another exemplary embodiment, a semiconductor structure is provided. The semiconductor structure includes: a substrate; an active region disposed on the substrate, including a channel region and a source / drain region; a gate structure disposed on the channel region of the active region and extending longitudinally along a first direction; a gate spacer disposed along one sidewall of the gate structure; and a source / drain feature member disposed on the source / drain region of the active region. The channel region includes two sub-regions horizontally separated along the first direction by the gate structure.

[0146] In some embodiments, each sub-region has a first width along a first direction and is spaced apart by a first distance, and a first ratio of the first width to the first distance is approximately 1 to 10. In some embodiments, the active region is a first active region, the gate structure is a first gate structure, and the channel region is a first channel region, and the semiconductor structure further includes: a second active region and a third active region disposed above a substrate; a second gate structure extending longitudinally along the first direction and disposed above a second channel region of the second active region and a third channel region of the third active region; a fourth active region and a fifth active region disposed on the substrate; and a third gate structure extending longitudinally along the first direction and disposed on a fourth channel region of the fourth active region and a fifth channel region of the fifth active region. Each of the second and third channel regions has a second width along the first direction and is spaced apart by a second distance, and each of the fourth and fifth channel regions has a third width along the first direction and is spaced apart by a third distance, and a second ratio of the second width to the second distance and a third ratio of the third width to the third distance are different from the first ratio. In some embodiments, the gate structure has a first portion disposed on two sub-regions and a second portion disposed between the two sub-regions, the second portion of the gate structure being in direct contact with the upper surface of a channel region located between the two sub-regions. The first portion has a first width along a second direction perpendicular to the first direction, and the second portion has a second width greater than the first width along the second direction. In some embodiments, the source / drain feature includes a first epitaxial layer disposed above the source / drain region and a second epitaxial layer disposed above the first epitaxial layer, the first epitaxial layer including a first concentration of dopant, and the second epitaxial layer including a second concentration of dopant greater than the first concentration. In some embodiments, the second epitaxial layer includes a first portion disposed on an upper surface of the first epitaxial layer and a second portion disposed along a sidewall of the first epitaxial layer, the first portion having a first thickness and the second portion having a second thickness, the ratio of the first thickness to the second thickness being approximately equal to or greater than 2.

[0147] Details of the device of this utility model will be described in the accompanying drawings. The foregoing has outlined the characteristic components of several embodiments of this utility model, enabling those skilled in the art to more readily understand its form. Those skilled in the art will understand that this utility model can be readily used as a basis for modifications or designs to other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Those skilled in the art will also understand that equivalent structures as described above do not depart from the spirit and scope of this utility model, and that modifications, substitutions, and refinements can be made without departing from its spirit and scope.

Claims

1. A semiconductor structure, characterized in that, include: One base; An active region is disposed on the substrate and includes a channel region and a source / drain region; A gate structure is disposed on the channel region of the active region and extends longitudinally along a first direction; A gate spacer is disposed along one sidewall of the gate structure; and A source / drain feature is disposed on the source / drain region of the active region. The channel region includes two sub-regions that are horizontally separated along the first direction by the gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, Each of the two or more sub-regions has a first width along the first direction and is separated from each other by a first distance, and a first ratio of the first width to the first distance is 1 to 10.

3. The semiconductor structure as described in claim 2, characterized in that, The active region is the first active region, the gate structure is the first gate structure, and the channel region is the first channel region.

4. The semiconductor structure as described in claim 3, characterized in that, Also includes: A second active region and a third active region are disposed above the substrate; A second gate structure extends longitudinally along the first direction and is disposed above a second channel region of the second active region and a third channel region of the third active region; A fourth active region and a fifth active region are disposed on the substrate; as well as A third gate structure extends longitudinally along the first direction and is disposed on a fourth channel region of the fourth active region and a fifth channel region of the fifth active region.

5. The semiconductor structure as described in claim 4, characterized in that, The second channel area and the third channel area each have a second width along the first direction and are separated from each other by a second distance; The fourth and fifth channel areas each have a third width along the first direction and are separated from each other by a third distance; and The second ratio of the second width to the second distance and the third ratio of the third width to the third distance are different from the first ratio.

6. The semiconductor structure as described in claim 1 or 2, characterized in that, The gate structure has a first portion disposed on the two sub-regions and a second portion disposed between the two sub-regions.

7. The semiconductor structure as described in claim 6, characterized in that, The second part of the gate structure is in direct contact with an upper surface of the channel region located between the two sub-regions; The first part has a first width along a second direction perpendicular to the first direction; and The second part has a second width along the second direction that is greater than the first width.

8. The semiconductor structure as described in claim 1 or 2, characterized in that, The source / drain feature includes a first epitaxial layer disposed above the source / drain region and a second epitaxial layer disposed above the first epitaxial layer. The first epitaxial layer includes a dopant of a first concentration; and The second epitaxial layer includes a dopant with a second concentration greater than the first concentration.

9. The semiconductor structure as described in claim 8, characterized in that, The second epitaxial layer includes a first part disposed on an upper surface of the first epitaxial layer and a second part disposed along a side wall of the first epitaxial layer.

10. The semiconductor structure as described in claim 9, characterized in that, The first part has a first thickness, and the second part has a second thickness; and The ratio of the first thickness to the second thickness is equal to or greater than 2.

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