Integrated circuit layout

Abstract

An integrated circuit layout includes a gap arranged for the integrated circuit layout, the gap including a plurality of rows extending along a first direction, each row of the plurality of rows having a uniform row height along a second direction perpendicular to the first direction. The integrated circuit layout further includes one or more first cell regions arranged in the gap, one of the first cell regions being disposed within a corresponding one of the plurality of rows; one or more second cell regions arranged in the gap, one of the second cell regions being disposed within two corresponding adjacent rows of the plurality of rows; and one or more third cell regions arranged in the gap, one of the third cell regions being disposed partially across three corresponding adjacent rows of the plurality of rows.

Description

Technical Field

[0001] This utility model relates to an integrated circuit layout. Background Technology

[0002] Generally, electronic design automation (EDA) tools assist semiconductor designers in transforming a purely behavioral description of a circuit into a complete, manufacturable circuit layout. This process typically converts the behavioral description into a functional description, then decomposes it into multiple Boolean functions and maps them to corresponding cell rows using a standard cell library. Once mapping is complete, synthesis is performed to convert the structural design into a solid layout, a clock tree is built to synchronize structural components, and the design is optimized post-layout. Utility Model Content

[0003] This utility model provides an integrated circuit layout. The integrated circuit layout includes: gaps arranged for the integrated circuit layout, including a plurality of rows extending along a first direction, each of the plurality of rows having a uniform row height along a second direction perpendicular to the first direction; one or more first cell regions arranged in the gaps, one of the one or more first cell regions being placed in a corresponding row of the plurality of rows; one or more second cell regions arranged in the gaps, one of the one or more second cell regions being placed in two corresponding adjacent rows of the plurality of rows; and one or more third cell regions arranged in the gaps, one of the one or more third cell regions being placed to partially span three corresponding adjacent rows of the plurality of rows.

[0004] This invention provides an integrated circuit layout. The integrated circuit layout includes: gaps arranged for the integrated circuit layout, comprising a plurality of rows extending along a first direction, each of the plurality of rows having a uniform row height along a second direction perpendicular to the first direction; and one or more first cell regions arranged in the gaps, one of the one or more first cell regions partially spanning three corresponding adjacent rows of the plurality of rows, wherein the one first cell region includes: a first sub-region including a first channel of a first doping type, the first channel extending across the first cell region along the first direction and having a first channel width along the second direction; and a second sub-region including a second channel of a second doping type opposite to the first doping type, the second channel also extending across the first cell region along the first direction and having a second channel width along the second direction equal to the width of the first channel. Attached Figure Description

[0005] Figure 1 A schematic diagram illustrating a portion of an example integrated circuit layout according to some embodiments is shown.

[0006] Figure 2 Illustrations based on some embodiments Figure 1 A schematic diagram of the integrated circuit portion at a specific metallization level.

[0007] Figure 3 The illustrations are based on some embodiments and include Figure 1 A schematic diagram of the first cell region in a multi-cell layout of an integrated circuit.

[0008] Figure 4 The illustrations are based on some embodiments and include Figure 1 A schematic diagram of the second cell region in a multi-cell region layout of an integrated circuit.

[0009] Figure 5 The illustrations are based on some embodiments and include Figure 1 A schematic diagram of the third cell region in a multi-cell layout of an integrated circuit.

[0010] Figure 6 The illustration includes, according to an embodiment, Figure 1 An example layout of multiple cell regions in an integrated circuit layout.

[0011] Figure 7 The illustration includes, according to another embodiment, Figure 1 Another example layout of multiple cell regions in an integrated circuit layout.

[0012] Figure 8 The illustration is based on yet another embodiment and includes Figure 1 Another layout of multiple cell regions in integrated circuit layout.

[0013] Figure 9 A flowchart illustrating an exemplary method for generating an integrated circuit layout comprising multiple cell regions according to some embodiments is provided.

[0014] Figure 10 A schematic diagram illustrating a portion of a netlist according to some embodiments is shown.

[0015] Figure 11 A block diagram illustrating an example information handling system (IHS) according to some embodiments is shown.

[0016] Figure 12 It is a chart that illustrates the different trends or requirements of different integrated circuit applications.

[0017] Figure 13 The illustration is based on yet another embodiment and includes Figure 1 Further layout of multiple cell regions in integrated circuit layout.

[0018] Figure 14 It is a chart that illustrates the different trends or effectiveness of different technical methods.

[0019] Figure 15 This is a table illustrating the uses and recommendations for the mixed threshold voltage (Vt) of nanosheets. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features form direct contact, and may also include embodiments where an additional feature may be formed between the first and second features, such that the first and second features do not form direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances throughout this disclosure. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to cover not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0022] In practice, some integrated circuits (ICs) prioritize performance, while others prioritize power / area. Therefore, various design trade-offs are typically made to design an IC that consumes low power and occupies a small area without sacrificing performance (e.g., a balance-oriented circuit). When designing ICs, a larger active region (OD) width may result in higher speed, energy consumption, and leakage current, while a smaller OD width may result in lower speed, energy consumption, and leakage current. Furthermore, adjusting the OD width is more efficient than adjusting the number of gates (POs) in achieving a balanced or acceptable level of speed, energy consumption, and leakage current.

[0023] This disclosure provides various embodiments of integrated circuit layout. According to some embodiments, the integrated circuit layout includes spaces arranged for the layout, the spaces comprising a plurality of rows extending along a first direction. Each of the plurality of rows has a uniform row height along a second direction perpendicular to the first direction and is defined by a first power line (e.g., Vdd) and a second power line (e.g., Vss), both extending along the first direction and adjacent to each other along the second direction. The integrated circuit layout further includes: one or more first cell regions arranged in the spaces, one of the first cell regions being placed within a corresponding row of the plurality of rows; one or more second cell regions arranged in the spaces, one of the second cell regions being placed within two corresponding adjacent rows of the plurality of rows; and one or more third cell regions arranged in the spaces, one of the third cell regions partially spanning three corresponding adjacent rows of the plurality of rows. Thus, the cell regions of the integrated circuit layout may have a configuration of merging channels or merging active regions.

[0024] According to some embodiments, the first cell region includes: a first sub-region including a first channel of a first doping type that spans the first cell region along a first direction, the first channel having a first channel width along a second direction; and a second sub-region directly adjacent to the first sub-region along the second direction, and including a second channel of a second doping type opposite to the first doping type that spans the first cell region along the first direction, the second channel having a second channel width equal to the first channel width along the second direction.

[0025] According to some embodiments, the second cell region includes: a third sub-region including a third channel of a first doping type, the third channel spanning the second cell region along a first direction and having a third channel width along a second direction; a fourth sub-region including a fourth channel of the first doping type, the fourth channel spanning the second cell region along the first direction and having a fourth channel width equal to the third channel width along the second direction; and a fifth sub-region disposed between the third and fourth sub-regions along the second direction, including a fifth channel of the second doping type, the fifth channel spanning the second cell region along the first direction and having a fifth channel width greater than either the third channel width or the fourth channel width along the second direction. The fifth channel width of the second cell region is greater than the width of the first channel of the first cell region along the second direction.

[0026] According to some embodiments, the third cell region includes: a sixth sub-region including a sixth channel of a first doping type, the sixth channel spanning the third cell region along a first direction and having a sixth channel width along a second direction; and a seventh sub-region including a seventh channel of a second doping type, the seventh channel also spanning the third cell region along the first direction and having a seventh channel width along the second direction equal to the sixth channel width. The sixth channel width of the third cell region is greater than the width of the first channel of the first cell region along the second direction. In some embodiments, the third cell region completely spans the first corresponding row of three corresponding adjacent rows and partially spans the second and third corresponding rows located on either side of the first corresponding row along the second direction.

[0027] Integrated circuit layouts employing merged active region configurations can offer a variety of advantages. Merged active region configurations can lead to optimized and / or balanced power consumption, performance, and area considerations in the design of various integrated circuit applications, such as System-on-Chip (SoC), Graphics Processing Unit (GPU), embedded CPU (e-CPU), physical CPU (pCPU), and High-Performance Computing (HPC), resulting in overall improvements in performance, power efficiency, and area efficiency.

[0028] Figure 1 The illustrations depict a portion of an example integrated circuit or integrated circuit layout 100 designed according to some embodiments of the systems and methods of this disclosure. Not all elements illustrated are necessary; however, some embodiments of this disclosure may include elements not shown in the illustrations. Figure 1 Additional elements shown herein. Variations in the arrangement and type of elements may be made without departing from the scope of this disclosure. Additional, different, or fewer elements may be included.

[0029] Reference Figure 1 The integrated circuit layout 100 includes a plurality of uniform cell rows 110, 112, and 114, etc., arranged (e.g., layout) along a first direction (X direction) and in relation to gaps, grids, or planar diagrams 102 arranged for the design of the integrated circuit layout 100. In some embodiments, each uniform cell row 110-114 of the integrated circuit layout 100 may have a uniform (or identical) row height H0 along a second direction (Y direction) perpendicular to the first direction. In some embodiments, the uniform row height H0 is in the range of 100 nm to 140 nm, while in other embodiments, the uniform row height H0 is in another range of 140 nm to 190 nm.

[0030] like Figure 1As shown, the integrated circuit layout 100 may include a plurality of contiguous cell areas or a plurality of cell areas, such as 103A, 103B, and 103C, and each of the plurality of cell areas is composed of one or more unified cell rows that extend within or across the gap 102 in a first direction. For example, the contiguous cell area 103A is composed (or extended) of a single cell row 112 that extends within or across the gap 102 in the first direction. The contiguous cell area 103B is composed (or extended) of two cell rows 110 and 112, both of which extend within or across the gap 102 in the first direction. The contiguous cell area 103C is composed (or extended) of three corresponding adjacent rows among a plurality of rows, for example, the entire cell row 112, a portion of the cell row 110, and a portion of the cell row 114, all of which extend within or across the gap 102 in the first direction. The contiguous cell area 103A has a first cell area pitch P1 in the first direction and a first cell area height H1 in the second direction, where H1 = H0. The contiguous cell area 103B has a second cell area pitch P2 in the first direction and a second cell area height H2 in the second direction, where H2 = 2xH0. The contiguous cell area 103C has a third cell area pitch P3 in the first direction and a third cell area height H3 in the second direction, where H3 is in the range of H0 < H3 < 3xH0. In some embodiments, H3 is in the range of H0 < H3 < 2xH0, while in other embodiments, H3 is in another range of 2xH0 < H3 < 3xH0. Details regarding the configuration and arrangement of the contiguous cell areas will be explained later in reference to Figure 3 , 4 and 5.

[0031] Figure 2 FIG. shows a schematic diagram of a portion of an integrated circuit layout 100 at a certain metallization level (e.g., the M1 level) according to some embodiments. In some embodiments, each unified cell row is bounded on its respective sides in a second direction (Y direction) perpendicular to the first direction (X direction) by a first metal rail and a second metal rail. The first metal rail may be a Vdd power rail configured to provide Vdd to each cell placed in the cell row, and the second metal rail may be a Vss power rail configured to provide Vss to each cell placed in the cell row.

[0032] As Figure 2As shown, adjacent cell rows along the second direction may be combined, adjacent, or otherwise share the same Vdd or Vss power rail. For example, cell row 110 may share the same Vss power rail with cell row 112. Since the Vdd / Vss power rails can extend along the corresponding uniform cell row, it is understood that in some embodiments, such as Figure 2 As shown, some Vdd / Vss power rails may completely span gap 102 along the X direction (e.g., the Vss power rail shared by cell rows 110 and 112), while in other embodiments, other Vdd / Vss power rails may partially span gap 102 along the X direction (not shown). In some embodiments, such as Figure 2 As shown, one or more of the multiple cell regions (e.g., 103A, 103B, and 103C) in the gaps 102 of the integrated circuit layout 100 are configured to create nanosheet transistors. Detailed information about nanosheet transistors is omitted here.

[0033] In some embodiments, such as Figure 2 As shown, one or more consecutive cell regions, such as 103A, 103B, and 103C, in the gaps 102 of the integrated circuit layout 100 correspond to one or more circuit modules. These consecutive cell regions can be arranged based on the identified circuit modules of the integrated circuit. For example, a circuit module can be identified or selected based on whether it was previously designated (e.g., user-designated) as a performance-oriented circuit module. In another example, a circuit module can be identified based on whether it was previously designated as a power-oriented circuit module.

[0034] The circuit module discussed herein can refer to a group of circuit elements configured to perform a specific function. For example, an integrated circuit may include a central processing unit (CPU), a graphics processing unit (GPU), input / output (I / O) interfaces, and memory. Thus, each of a plurality of circuit modules can perform a specific function (e.g., calculation, receiving instructions, etc.), collectively forming a CPU. An integrated circuit or system may arrange such contiguous cell regions based on at least one identified timing constraint, identified performance constraint, or identified power constraint, which may be shared by cells configured in contiguous cell regions. It is understood that these cells do not necessarily correspond to the same circuit module. In some embodiments, such shared timing / performance / power constraints may be specified by the design or identified by performing one or more simulations of the integrated circuit's circuit design using a circuit simulator (e.g., SPICE (Simulation Program with Integrated Circuit Emphasis)).

[0035] Figure 3 The illustration is based on some embodiments. Figure 1 A schematic diagram of the first cell region (e.g., 103A) among the multiple cell regions included in the integrated circuit layout 100. (See diagram below.) Figure 1 As shown, a first cell region 103A is arranged in a gap 102 containing multiple uniform cell rows (e.g., 110, 112, and 114). Each of the multiple uniform cell rows (e.g., 110) extends along a first direction (X direction) in the gap 102 and has a uniform row height H0 along a second direction (Y direction) perpendicular to the first direction. The first cell region 103A is placed within a corresponding uniform cell row (e.g., 112) of the multiple uniform cell rows (e.g., 110, 112, and 114), and the first cell region 103A has a first cell region height H1 along the second direction, which is equal to the uniform row height H0. Figure 3 As shown, the upper and lower boundaries of the first cell region 103A are defined by a first power line and a second power line in the second direction, respectively, which extend along the first direction and are adjacent to each other. In some embodiments, the first power line may be a Vdd power line and the second power line may be a Vss power line.

[0036] like Figure 3 As shown, in some embodiments, the first cell region 103A includes a first sub-region 302 of type PMOS and a second sub-region 304 of type NMOS adjacent to the first sub-region 302 along a second direction. The first sub-region 302 includes a p-type first channel 312 extending across the first cell region 103A along a first direction. The first channel 312 has a first channel width C1 along the second direction and is formed in an n-type first well 313. The second sub-region 304 includes an n-type second channel 314 extending across the first cell region 103A along the first direction. The second channel 314 has a second channel width C2 along the second direction and is formed in a p-type second well 315. In some embodiments, the second channel width C2 and the first channel width C1 are the same, while in other embodiments, the second channel width C2 and the first channel width C1 are different. In some embodiments, the first cell region 103A includes one or more gate (PO) structures or gates 322, all of which extend along a second direction, are spaced apart from each other, and span the first channel 312 and the second channel 314. In some embodiments, the leftmost gate structure 322L and the rightmost gate structure 322R are dummy gates, both of which define the first cell region spacing P1 of the first cell region 103A along a first direction.

[0037] Figure 4 The illustrations are based on some embodiments. Figure 1A schematic diagram of the second cell region (e.g., 103B) within multiple cell regions included in the integrated circuit layout 100. (See diagram below.) Figure 1 As shown, the second cell region 103B is arranged in a gap 102 containing multiple uniform cell rows (e.g., 110, 112, and 114). Each uniform cell row (e.g., 110) extends in the gap 102 along a first direction (X direction) and has a uniform row height H0 along a second direction perpendicular to the first direction (Y direction). The second cell region 103B is placed within two corresponding adjacent rows (e.g., 110 and 112) of the multiple rows (e.g., 110 and 112), and the second cell region 103B has a second cell region height H2 along the second direction, which is equal to twice the uniform row height H0, i.e., H2 = 2 x H0. Figure 4 As shown, the upper and lower boundaries of the second cell region 103B are defined by two corresponding power lines in the second direction.

[0038] like Figure 4 As shown, in some embodiments, the second cell region 103B includes: a first sub-region 402 including a first channel 412 of a first type of doping, extending across the second cell region 103B along a first direction, the first channel 412 being formed in a first well 413 of a second type of doping opposite to the first type of doping; a second sub-region 404 including a second channel 414 of a first type of doping, extending across the second cell region 103B along the first direction, the second channel 414 being formed in a second well 415 of the second type of doping; and a third sub-region 406 including a third channel 416 of the second type of doping, extending across the second cell region 103B along the first direction, the third channel 416 being formed in a third well 417 of the first type of doping. The third sub-region 406 is positioned between and adjacent to the first sub-region 402 and the second sub-region 404 along a second direction. In some embodiments, the first type of doping is p-type and the second type of doping is n-type, while in other embodiments, the first type of doping is n-type and the second type of doping is p-type. Therefore, the second cell region 103B can be of type PNP or type NPN.

[0039] In some embodiments, the first channel 412 of the second cell region 103B has a first channel width C3 extending along a second direction, the second channel 414 of the second cell region 103B has a second channel width C4 extending along a second direction, and the third channel 416 of the second cell region 103B has a third channel width C5 extending along a second direction. In some embodiments, the first channel width C3 and the second channel width C4 of the second cell region 103B are the same, while in other embodiments, the first channel width C3 and the second channel width C4 of the second cell region 103B are different. In some embodiments, the third channel width C5 of the second cell region 103B is greater than either the first channel width C3 or the second channel width C4 of the second cell region 103B. In some embodiments, the third channel width C5 of the second cell region 103B is less than the sum of the first channel width C3 and the second channel width C4 of the second cell region 103B. In some embodiments, the second cell region 103B includes one or more gate (PO) structures or gates 422, all of which extend along a second direction, are spaced apart from each other, and span the first channel 412, the second channel 414, and the third channel 416. In some embodiments, the leftmost gate structure 422L and the rightmost gate structure 422R are dummy gates, both of which define the second cell region spacing P2 of the second cell region 103B along a first direction.

[0040] Figure 5 Illustrations based on some embodiments Figure 1 A schematic diagram of the third cell region (e.g., 103C) among multiple cell regions included in the integrated circuit layout 100. (See diagram below.) Figure 1 As shown, the third cell region 103C is arranged in a gap 102 comprising multiple uniform cell rows (e.g., 110, 112, and 114). Each of the multiple uniform cell rows (e.g., 110) extends along a first direction (X direction) in the gap 102 and has a uniform row height H0 along a second direction perpendicular to the first direction (Y direction). Figure 5 As shown, compared to the arrangement of the first cell region 103A, the third cell region 103C is partially placed along the second direction in or across three adjacent rows (e.g., 110, 112, and 114). For example, the third cell region 103C is partially placed along the second direction in or across a portion of cell row 110, a portion of cell row 112, and a portion of cell row 114.

[0041] like Figure 5As shown, in some embodiments, the third cell region 103C includes a first sub-region 502 of PMOS type and a second sub-region 504 of NMOS type adjacent to the first sub-region 502 along a second direction. The first sub-region 502 of the third cell region 103C includes a p-type first channel 512 spanning the third cell region 103C along a first direction. The first channel 512 of the third cell region 103C has a first channel width C6 along a second direction and is formed in an n-type first well 513 of the third cell region 103C. The second sub-region 504 of the third cell region 103C includes an n-type second channel 514 spanning the third cell region 103C along a first direction. The second channel 514 of the third cell region 103C has a second channel width C7 along a second direction and is formed in a p-type second well 515 of the third cell region 103C. In some embodiments, the second channel width C7 and the first channel width C6 of the third cell region 103C are the same, while in other embodiments, the second channel width C7 and the first channel width C6 of the third cell region 103C are different. The third cell region 103C includes one or more gate (PO) structures or gates 522, all of which extend along a second direction, are separated from each other, and span the first channel 512 and the second channel 514 of the third cell region 103C. In some embodiments, the leftmost gate structure 522L and the rightmost gate structure 522R are dummy gates, both of which define the third cell region spacing P3 of the third cell region 103C along a first direction.

[0042] In some embodiments, either the first channel width C6 or the second channel width C7 of the third cell region 103C is greater than either the first channel width C1 or the second channel width C2 of the first cell region 103A along the second direction. In some embodiments, the third cell region height H3 of the third cell region 103C is greater than the first cell region height H1 of the first cell region 103A along the second direction. In some embodiments, the third cell region height H3 of the third cell region 103C is greater than the second cell region height H2 of the second cell region 103B along the second direction, while in other embodiments, the third cell region height H3 of the third cell region 103C is less than the second cell region height H2 of the second cell region 103B along the second direction.

[0043] Figure 6 The illustration includes, according to the embodiment. Figure 1 An example integrated circuit layout 600 comprising multiple cell regions in an integrated circuit layout. In some embodiments, the integrated circuit layout 600 includes gaps 102 arranged for the integrated circuit layout 600. In some embodiments, the gaps 102 are configured to create nanosheet transistors. In some embodiments, as Figure 1As shown, the gap 102 includes multiple rows (e.g., 110, 112, and 114) extending along a first direction (X direction), each of the multiple rows (e.g., 110) having a uniform row height H0 along a second direction (Y direction) perpendicular to the first direction. The integrated circuit layout 600 further includes multiple (e.g., six) PN-type first cell regions 103A, such as 103A(1), 103A(2), 103A(3), 103A(4), 103A(5), and 103A(6), arranged in the gap 102, with one of the multiple first cell regions 103A placed in one of the multiple rows (e.g., ...). Figure 1 One of the corresponding rows (e.g., 110, 112, and 114) in the data. Figure 1 Within 112). Although the display gap 102 contains six first cell regions 103A, the number of first cell regions 103A is not limited to six and can be any integer.

[0044] like Figure 3 As shown, in some embodiments, the first cell region 103A includes a first sub-region 302, which includes a first channel 312 (e.g., p-type) extending across the first cell region 103A along a first direction, the first channel having a first channel width C1 along a second direction; and a second sub-region 304, which is directly adjacent to the first sub-region 302 along the second direction, and includes a second channel 314 (e.g., n-type) extending across the first cell region 103A along the first direction, the second channel having a second channel width C2 along the second direction. The first cell region height H1 of the first cell region 103A is equal to a uniform row height H0 along the second direction. Furthermore, as... Figure 6 As shown, in some embodiments, a plurality of first cell regions 103A are arranged adjacent to each other along a first direction and a second direction, and are aligned with each other along the first direction and the second direction, and each of the plurality of first cell regions 103A includes a first sub-region 302 and a second sub-region 304. For example, a first cell region 103A(1) of the plurality of first cell regions 103A is directly adjacent to another first cell region 103A(2) of the plurality of first cell regions 103A along the first direction, and a first cell region 103A(1) is directly adjacent to yet another first cell region 103A(4) of the plurality of first cell regions 103A along the second direction.

[0045] Figure 7 The illustration is based on other embodiments included in Figure 1Another example layout 700 of multiple cell regions in an integrated circuit layout. In some embodiments, the integrated circuit layout 700 includes gaps 102 arranged for the integrated circuit layout 700. In some embodiments, the gaps 102 are configured to create nano-sheet transistors. In some embodiments, such as Figure 1 As shown, the gap 102 includes a plurality of rows (e.g., 110, 112, and 114) extending along a first direction (X direction), each of the plurality of rows (e.g., 110) having a uniform row height H0 along a second direction (Y direction) perpendicular to the first direction. The integrated circuit layout 700 further includes one or more first cell regions 103A (e.g., PN type), each placed within a corresponding row (e.g., 110) of the plurality of rows, and one or more second cell regions (e.g., PNP type), each placed within two corresponding adjacent rows (e.g., 110 and 112) of the plurality of rows.

[0046] like Figure 3 As shown, in some embodiments, the first cell region 103A includes a first sub-region 302, which includes a first channel 312 (e.g., p-type) extending across the first cell region 103A along a first direction, the first channel having a first channel width C1 along a second direction; and a second sub-region 304, which is directly adjacent to the first sub-region 302 along the second direction, and includes a second channel 314 (e.g., n-type) extending across the first cell region 103A along the first direction, the second channel having a second channel width C2 along the second direction. The first cell region height H1 of the first cell region 103A is equal to a uniform row height H0 along the second direction.

[0047] like Figure 4 As shown, in some embodiments, the second cell region 103B includes a first sub-region 402, which includes a first channel 412 having a first type of doping and extending across the second cell region 103B along a first direction, the first channel 412 being formed in a first well 413 having a second type of doping opposite to the first type of doping; a second sub-region 404, which includes a second channel 414 having a first type of doping and extending across the second cell region 103B along the first direction, the second channel 414 being formed in a second well 415 having the second type of doping; and a third sub-region 406, which includes a third channel 416 having a second type of doping and extending across the second cell region 103B along the first direction, the third channel 416 being formed in a third well 417 having the first type of doping. The third sub-region 406 is positioned between and adjacent to the first sub-region 402 and the second sub-region 404 along a second direction.

[0048] In some embodiments, such as Figure 7As shown, a first cell region 103A (e.g., 103A(1)) is laterally separated from a second cell region 103B by a first distance D1 along a first direction, while another first cell region 103A (e.g., 103(6)) is directly adjacent to the second cell region 103B along a second direction. The first distance D1 is within the range of the width of the gate structure 422 to five times the width of the gate structure 422.

[0049] Figure 8 The illustration is based on yet another embodiment contained in Figure 1 Another example of an integrated circuit layout 800 is a plurality of cell regions in an integrated circuit layout. In some embodiments, the integrated circuit layout 800 includes gaps 102 arranged for the integrated circuit layout 800. In some embodiments, the gaps 102 are configured to create nanosheet transistors. In some embodiments, as Figure 1 As shown, the gap 102 includes a plurality of rows (e.g., 110, 112, and 114) extending along a first direction (X direction), each of the plurality of rows (e.g., 110) having a uniform row height H0 along a second direction (Y direction) perpendicular to the first direction. The integrated circuit layout 800 further includes one or more first cell regions 103A (e.g., PN type), each first cell region 103A being placed within a corresponding row (e.g., 110) of the plurality of rows, and one or more third cell regions (e.g., PN type), each third cell region being partially placed within or across three corresponding adjacent rows (e.g., 110, 112, and 114) of the plurality of rows.

[0050] like Figure 3 As shown, in some embodiments, the first cell region 103A includes a first sub-region 302, which includes a first channel 312 (e.g., p-type) extending across the first cell region 103A along a first direction, the first channel having a first channel width C1 along a second direction; and a second sub-region 304, which is directly adjacent to the first sub-region 302 along the second direction, and includes a second channel 314 (e.g., n-type) extending across the first cell region 103A along the first direction, the second channel having a second channel width C2 along the second direction. The first cell region height H1 of the first cell region 103A is equal to a uniform row height H0 along the second direction.

[0051] like Figure 5As shown, in some embodiments, the third cell region 103C includes a PMOS-type first sub-region 502 and an NMOS-type second sub-region 504 adjacent to the first sub-region 502 along a second direction. The first sub-region 502 of the third cell region 103C includes a p-type first channel 512 extending across the third cell region 103C along a first direction. The first channel 512 of the third cell region 103C has a first channel width C6 along a second direction and is formed in an n-type first well 513 of the third cell region 103C. The second sub-region 504 of the third cell region 103C includes an n-type second channel 514 extending across the third cell region 103C along a first direction. The second channel 514 of the third cell region 103C has a second channel width C7 along a second direction and is formed in a p-type second well 515 of the third cell region 103C. The third cell region 103C includes one or more gate (PO) structures or gates 522, all of which extend along a second direction, are separated from each other, and span the first channel 512 and the second channel 514 of the third cell region 103C.

[0052] like Figure 8 As shown, in some embodiments, one of the first cell regions 103A (e.g., 103A(1)) is laterally separated from one of the third cell regions 103C along a first direction (X direction) by a second distance D2. The second distance D2 is in the range of one to five times the width of the gate structure 522. In some embodiments, such as Figure 8 As shown, one of the third cell regions 103C is separated from another first cell region 103A (not shown) in the vertical direction by a third distance D3 along the second direction (Y direction). The third distance D3 is in the range of one to five times the width of the gate structure 522.

[0053] Figure 9 This diagram illustrates an example method 900 for generating an integrated circuit layout comprising one or more cell regions (e.g., 103A, 103B, and / or 103C) with different active region (OD) configurations, according to some embodiments. In some embodiments, method 900 may be collectively referred to as EDA. The operation of method 900 is performed by... Figure 11 The various elements shown are executed. For discussion purposes, the following embodiments of method 900 will be combined with... Figure 11 The illustrated method 900 embodiment is merely an example. Therefore, it will be understood that any of the various operations may be omitted, reordered, and / or added while remaining within the scope of this disclosure.

[0054] According to some embodiments, method 900 begins with the provision of an "input netlist" 902 and "design constraints" 904. The input netlist 902 may be a functionally equivalent logic gate-level circuit description provided through a synthesis process. The synthesis process forms a functionally equivalent logic gate-level circuit description by matching one or more behaviors and / or functions with (standard) cells from a set of cell libraries. The behaviors and / or functions are specified based on various signals or stimuli applied to the overall design input of the integrated circuit (e.g., integrated circuit layout 100) and may be written in a suitable language, such as a hardware description language (HDL). The input netlist 902 can be accessed via an input / output interface 1128 (in... Figure 11 The input netlist 902 can be uploaded to the processing unit 1110, for example, by a user creating a file during EDA execution. Alternatively, the input netlist 902 can be uploaded and / or stored on memory 1122 or mass storage device 1124, or the input netlist 902 can be uploaded from a remote user via network interface 1140. Figure 11 (In these cases, the central processing unit 1120 should access or interface with the input netlist 902 during EDA execution).

[0055] The user also provides a design constraint 904 to limit the overall physical layout design of the input netlist 902. In some embodiments, the design constraint 904 can be input via input / output interface 1128, downloaded via network interface 1140, or similarly (in... Figure 11 (In the middle). Design constraints 904 can specify timing, process parameters and other appropriate constraints, which must be met once the input netlist 902 is physically formed into an integrated circuit.

[0056] According to some embodiments, method 900 proceeds to operation 906 to "identify circuit modules". Based on input netlist 902 and / or design constraints 904, the disclosed system can identify, recognize, or otherwise determine one or more circuit modules specified by the user, for example, those composed of one or more cell regions (e.g., 103A, 103B, and / or 103C) with different active area (OD) configurations. For example, the system might identify a first circuit module in response to input netlist 902 specifying that the first circuit module is a power-oriented circuit module that should be composed of a first cell region (e.g., 103A). For example, the system might identify a second circuit module in response to input netlist 902 specifying that the second circuit module is a performance-oriented circuit module that should be composed of a third cell region (e.g., 103C).

[0057] Alternatively, or additionally, the system can identify a circuit module that should consist of a first cell region (e.g., 103A) or a second cell region (e.g., 103B), or a first cell region (e.g., 103A) or a third cell region (e.g., 103C), or a first cell region (e.g., 103A), a second cell region (e.g., 103B), or a third cell region (e.g., 103C), by determining at least one timing constraint, performance constraint, or power constraint corresponding to the circuit module. The system can access, communicate, or otherwise interface with design constraint 904 to determine such timing / performance / power constraints. In some embodiments, the system can identify one or more circuit modules that should not consist of only high or low cells based on input netlist 902. Continuing with the above examples, the system may identify a third circuit module in response to input netlist 902 specifying that the third circuit module has a more flexible configuration.

[0058] Method 900 proceeds to operation 908 to "arrange cell regions," according to some embodiments. In response to identifying one or more circuit modules that should be composed of first, second, or third cell regions (e.g., in operation 906), the system can arrange corresponding cell regions (e.g., 103A, 103B, and / or 103C) with different active region (OD) configurations. The characteristics of the cell regions (e.g., 103A, 103B, and / or 103C) have been respectively... Figure 3-5 As described in the text.

[0059] Method 900 proceeds to operation 910 for "place and route," according to some embodiments. In response to arranging corresponding cell regions (e.g., 103A, 103B, and / or 103C) with different active area (OD) configurations for various circuit modules, the system can place and route cells to produce the actual physical design of the overall integrated circuit. Operation 910 is configured to form the physical design by selecting cells from a cell library and placing them into individual cell rows. The placement of each cell in a cell row, and the placement of each cell row relative to other cell rows, may be guided by a cost function to minimize the routing length and cell area requirements of the resulting integrated circuit. This placement can be performed automatically by operation 910, or it can be performed partially by a manual process, whereby a user can manually insert one or more cells into a cell row.

[0060] Method 900 then proceeds to operation 912 to determine whether the actual physical design of the overall integrated circuit "meets design requirements," according to some embodiments. In response to generating the actual physical design of the overall integrated circuit (in operation 910), the system can check, monitor, or otherwise determine whether it meets the design requirements. Various requirements can be checked, such as the timing quality of the actual physical design of the overall integrated circuit, the power quality of the actual physical design of the overall integrated circuit, the presence of local congestion problems, etc., by performing one or more simulations using a circuit simulator (e.g., a Simulation Program with Integrated Circuit Emphasis (SPICE)).

[0061] If all design requirements are met, method 900 proceeds to operation 914, "Making the tooling". On the other hand, if not all design requirements are met, method 900 proceeds to operation 916, "Finding the root cause".

[0062] The system may perform operation 916 to identify the reasons why the design requirements were not met in judgment operation 912. Various reasons may lead to failure. Based on one or more of these reasons, method 900 may proceed to respective operations to re-execute the operation. For example, when the reason is due to an incorrect arrangement of cell rows, method 900 may proceed to an operation (e.g., operation 904) to re-evaluate the specified limitations therein. When the reason is due to the infeasibility of synthesizing a functionally equivalent logic gate-level circuit description, method 900 may proceed to an operation (e.g., operation 904) to re-evaluate the specified limitations therein. When the reason is due to the infeasibility of generating an actual physical design, method 900 may proceed to an operation (e.g., operation 910) to reposition and / or rewire.

[0063] The system can execute manufacturing tool 914 to generate, for example, a photomask, which can be used for actual manufacturing physical design. The physical design can be sent to manufacturing tool 914 via local area network / wide area network 1116.

[0064] Figure 10 A schematic diagram illustrating a portion of a netlist according to some embodiments is shown. For example... Figure 10 As shown, the netlist portion (during composition) 1000 can be one of the aforementioned windows, including, for example, such as Figure 1 and Figure 3-5 The “first cell region” 103A, the “second cell region” 103B, and the “third cell region” 103C are shown respectively.

[0065] Reference Figure 1 and Figure 3A first cell region 103A (e.g., PN type) is arranged in a gap 102 comprising multiple uniform cell rows (e.g., 110, 112, and 114), placed within a corresponding uniform cell row (e.g., 112), and having a first cell region height H1 equal to the uniform row height H0 along a second direction. The first cell region 103A includes a first sub-region 302 of PMOS type and a second sub-region 304 of NMOS type adjacent to the first sub-region 302 along the second direction. The first sub-region 302 includes a p-type first channel 312 extending across the first cell region 103A along a first direction. The first channel 312 has a first channel width C1 along the second direction and is formed in an n-type first well 313. The second sub-region 304 includes an n-type second channel 314 extending across the first cell region 103A along the first direction. The second channel 314 has a second channel width C2 along the second direction, and the second channel 314 is formed in the p-type second well 315.

[0066] Reference Figure 1 and Figure 4 The second cell region 103B (e.g., PNP type) is arranged in the gap 102 comprising multiple uniform cell rows (e.g., 110, 112 and 114), placed in two corresponding adjacent rows (e.g. 110 and 112) of the multiple rows, and has a second cell region height H2 along the second direction that is equal to twice the uniform row height H0, i.e., H2 = 2xH0. The second cell region 103B includes a first sub-region 402, which includes a first channel 412 of a first type of doping extending across the second cell region 103B along a first direction, the first channel 412 being formed in a first well 413 of a second type of doping opposite to the first type of doping; a second sub-region 404, which includes a second channel 414 of a first type of doping extending across the second cell region 103B along the first direction, the second channel 414 being formed in a second well 415 of the second type of doping; and a third sub-region 406, which includes a third channel 416 of the second type of doping extending across the second cell region 103B along the first direction, the third channel 416 being formed in a third well 417 of the first type of doping. The third sub-region 406 is placed between and adjacent to the first sub-region 402 and the second sub-region 404 along a second direction. In some embodiments, the first channel 412 of the second cell region 103B has a first channel width C3 extending along the second direction, the second channel 414 of the second cell region 103B has a second channel width C4 extending along the second direction, and the third channel 416 of the second cell region 103B has a third channel width C5 extending along the second direction.

[0067] Reference Figure 1 and Figure 5The third cell region 103C (e.g., PPNN type) is arranged in a gap 102 comprising multiple uniform cell rows (e.g., 110, 112, and 114), partially placed within or across three corresponding adjacent rows (e.g., 110, 112, and 114) of the multiple rows, and includes a first sub-region 502 of type PMOS, and a second sub-region 504 of type NMOS adjacent to the first sub-region 502 along a second direction. The first sub-region 502 of the third cell region 103C includes a p-type first channel 512 extending across the third cell region 103C along a first direction. The first channel 512 of the third cell region 103C has a first channel width C6 along a second direction and is formed in an n-type first well 513 of the third cell region 103C. The second sub-region 504 of the third cell region 103C includes an n-type second channel 514 extending across the third cell region 103C along a first direction. The second channel 514 of the third cell region 103C has a second channel width C7 along the second direction and is formed in the p-type second well 515 of the third cell region 103C. In some embodiments, either the first channel width C6 or the second channel width C7 of the third cell region 103C is greater than either the first channel width C1 or the second channel width C2 of the first cell region 103A along the second direction.

[0068] Figure 11 A block diagram of an example information processing system (IHS) according to some embodiments of the present invention is shown. IHS 1100 may be a computer platform for implementing any or all programs discussed herein for designing integrated circuits. IHS 1100 may include a processing unit 1110, such as a desktop computer, workstation, laptop computer, or a dedicated unit customized for a particular application. IHS 1100 may be equipped with a display 1114 and one or more input / output (I / O) elements 1112, such as a mouse, keyboard, or printer. Processing unit 1110 may include a central processing unit (CPU) 1120, memory 1122, mass storage device 1124, video adapter 1126, and input / output interface 1128 connected to bus 1130.

[0069] Bus 1130 can be one or more of several bus architectures of any type, including a memory bus or memory controller, a peripheral bus, or a video bus. CPU 1120 can include any type of electronic data processor, and memory 1122 can include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).

[0070] Mass storage device 1124 may include any type of storage device configured to store data, programs, and other information, and make the data, programs, and other information accessible via bus 1130. Mass storage device 1124 may include, for example, one or more hard disk drives, disk drives, optical disk drives, or similar devices.

[0071] Video adapter 1126 and input / output interface 1128 provide interfaces to couple external input and output devices to processing unit 1110. For example... Figure 11 As shown, examples of input and output devices include a display 1114 coupled to the video adapter 1126 and input / output elements 1112 coupled to the input / output interface 1128, such as a mouse, keyboard, printer, and similar devices. Other devices may be coupled to the processing unit 1110, and additional or fewer interface cards may be used. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing unit 1110 may also include a network interface 1140, which may be a wired and / or wireless connection to a local area network (LAN) or wide area network (WAN) 1116.

[0072] It should be noted that the IHS1100 may include other components / devices. For example, the IHS1100 may include a power supply, cables, a motherboard, removable storage media, a housing, and the like. These other components / devices, though not shown, are considered part of the IHS1100.

[0073] In some embodiments of this invention, electronic design automation (EDA) is program code executed by CPU 1120 to analyze user files to obtain the layout of integrated circuits (e.g., the integrated circuit layout of HIS1100 discussed above). Furthermore, during EDA execution, the EDA can analyze the functional elements of the layout, as known to those skilled in the art. The program code can be accessed by CPU 1120 via bus 1130 from memory 1122, mass storage device 1124, or a similar device, or remotely via network interface 1140.

[0074] Figure 12 Chart 1200 illustrates different trends or requirements for various integrated circuit applications. For example... Figure 12 As shown, different integrated circuit applications (such as SoC, GPU, eCPU, pCPU, and HPC) have different trends or requirements for core area and speed. Figure 13 The illustration is based on yet another embodiment. Figure 1 Further integrated circuit layout 1300, comprising multiple cell regions within the integrated circuit layout. For example... Figure 13As shown, different combinations of multiple cell regions (e.g., first cell region 103A, second cell region 103B, and third cell region 103C) with different active region heights can be used depending on factors such as different trends or requirements of the core area and speed in integrated circuit applications. The integrated circuit layout 1300 employing the merged active region configuration of this application offers various advantages. The merged active region configuration can bring optimized and / or balanced power, performance, and area considerations during the design process of various IC applications, resulting in overall improved performance, power efficiency, and area efficiency.

[0075] Figure 14 The chart illustrates the different trends or efficiencies of various technical approaches using, for example, hybrid (or adjustable) critical voltage (Vt) devices, combined active region devices, and devices that adjust the size of the active region. Figure 14 In the middle, line L1 represents the PN merging active region design ( Figure 13 In 103A), line L2 represents the NPN merging active region design ( Figure 13 In 103B), line L3 represents the PPNN merging active region design ( Figure 13 103C in the text). W19 indicates the active region size (19 nanometers). SVT (Standard Critical Voltage), LVTLL (Low Critical Voltage with Low Leakage), LVT (Low Critical Voltage), ULVTLL (Ultra-Low Critical Voltage with Low Leakage), ULVT (Ultra-Low Critical Voltage), and ELVT (Extremely Low Critical Voltage) represent different critical voltage (VT) types. TTG / 0.75V / 25C indicates the PVT (Process, Voltage, Temperature) angle. (Refer to...) Figure 14 For digital design, different techniques (such as those described above) can be used to optimize power and speed performance to meet the different requirements of various applications. For example, SoCs require relatively low power and speed, while HPCs require relatively high speed but have no power concerns; therefore, their optimization trends differ. The different VT types used in semiconductor devices (such as LVTLL) affect their performance (e.g., leakage current and speed). Figure 15 A table illustrating the usage of the hybrid threshold voltage (Vt) for nanosheet transistors is provided. Nanosheet transistors allow for better gate control of the channel, reducing leakage current and improving performance. Figure 15 In this architecture, there are two cell height designs: Type A and Type B. The critical path 800CP is an internal path used for velocity limiting and power distribution. For example... Figure 15 In the table shown, the label "UL" indicates the type of ultra-low threshold voltage (ULVT) transistor, the label "ULLL" indicates the type of ultra-low threshold voltage (ULVTLL) transistor with low leakage current, and the label "L" indicates the type of low threshold voltage (LVT) transistor.

[0076] Reference Figure 14 and Figure 15 In semiconductor design, different hybrid threshold voltages (Vt) are used to optimize performance and power consumption. The hybrid Vt approach allows for optimizing the trade-off between performance and power efficiency by applying different threshold voltages to different parts of the circuit. Nanochip transistors can be designed to support multiple threshold voltage options to meet a variety of application requirements. For example, SVT transistors offer a balance between speed and power consumption. ULVT transistors have very low threshold voltages, turning on at lower voltages, and are typically used in speed-critical performance paths. ULVTLL transistors are designed with ultra-low threshold voltages and incorporate additional techniques to minimize leakage, providing similar high performance to ULVT transistors while incorporating design optimizations to reduce leakage, better balancing speed and power efficiency. LVT transistors have low threshold voltages, offering a trade-off between the high-speed operation of ULVT transistors and the lower leakage of SVT transistors. Therefore, using different VT types allows for good control over the speed and power performance of semiconductor devices, enabling designers to optimize their circuits for a wide range of applications and needs.

[0077] In one aspect of this disclosure, an integrated circuit layout is provided. The integrated circuit layout includes: gaps arranged for the integrated circuit layout, comprising a plurality of rows extending along a first direction, each of the plurality of rows having a uniform row height along a second direction perpendicular to the first direction; one or more first cell regions arranged in the gaps, one of the one or more first cell regions being placed within a corresponding row of the plurality of rows; one or more second cell regions arranged in the gaps, one of the one or more second cell regions being placed within two corresponding adjacent rows of the plurality of rows; and one or more third cell regions arranged in the gaps, one of the one or more third cell regions being positioned to partially span three corresponding adjacent rows of the plurality of rows.

[0078] In a related embodiment, each of the plurality of rows is defined by a first power line of Vdd and a second power line of Vss, the first power line and the second power line extending along the first direction and adjacent to each other along the second direction.

[0079] In a related embodiment, the first cell region includes: a first sub-region including a first channel of a first doping type, the first channel extending across the first cell region along a first direction, the first channel having a first channel width along a second direction; and a second sub-region directly adjacent to the first sub-region along the second direction, and including a second channel of a second doping type opposite to the first doping type, the second channel extending across the first cell region along the first direction, the second channel having a second channel width equal to the first channel width along the second direction.

[0080] In a related embodiment, the second cell region includes: a third sub-region including a third channel of the first doping type, the third channel extending across the second cell region along the first direction and having a third channel width along the second direction; a fourth sub-region including a fourth channel of the first doping type, the fourth channel extending across the second cell region along the first direction and having a fourth channel width equal to the width of the third channel along the second direction; and a fifth sub-region disposed between the third sub-region and the fourth sub-region along the second direction, including a fifth channel of the second doping type, the fifth channel extending across the second cell region along the first direction and having a fifth channel width along the second direction greater than either the width of the third channel or the width of the fourth channel, wherein the fifth channel width of the second cell region is greater than the first channel width of the first cell region along the second direction.

[0081] In a related embodiment, the third cell region includes: a sixth sub-region including a sixth channel of the first doping type, the sixth channel extending across the third cell region along the first direction and having a sixth channel width along the second direction; and a seventh sub-region including a seventh channel of the second doping type, the seventh channel also extending across the third cell region along the first direction and having a seventh channel width along the second direction equal to the width of the sixth channel, wherein the sixth channel width of the third cell region is greater than the first channel width of the first cell region along the second direction.

[0082] In a related embodiment, the third cell region completely spans the first corresponding row of the three corresponding adjacent rows, and partially spans the second and third corresponding rows of the three corresponding adjacent rows on both sides of the first corresponding row along the second direction.

[0083] In a related embodiment, one of the one or more first cell regions is directly adjacent to and aligned with another of the one or more first cell regions along the first direction.

[0084] In a related embodiment, one of the one or more first cell regions is directly adjacent to and aligned with another of the one or more first cell regions along the second direction.

[0085] In a related embodiment, the second cell region is spaced apart from either the first cell region or the third cell region along the first direction.

[0086] In a related embodiment, the third cell region is spaced apart from either the first cell region or the second cell region along the first direction.

[0087] In a related embodiment, the integrated circuit layout is arranged for a nanosheet transistor, and the nanosheet transistor includes: a plurality of nanosheets stacked on top of each other; a gate structure surrounding each of the plurality of nanosheets; a first source / drain feature located on a first side of the gate structure; and a second source / drain feature located on a second side of the gate structure.

[0088] In one aspect of this disclosure, an integrated circuit layout is provided. The integrated circuit layout includes: gaps arranged for the integrated circuit layout, comprising a plurality of rows extending along a first direction, each of the plurality of rows having a uniform row height along a second direction perpendicular to the first direction; and one or more first cell regions arranged in the gaps, one of the one or more first cell regions being placed partially across three corresponding adjacent rows of the plurality of rows, wherein the one first cell region includes: a first sub-region including a first channel of a first doping type extending across the first cell region along the first direction and having a first channel width along the second direction; and a second sub-region including a second channel of a second doping type opposite to the first doping type, the second channel also extending across the first cell region along the first direction and having a second channel width along the second direction equal to the first channel width.

[0089] In related embodiments, the integrated circuit layout further includes: one or more second cell regions arranged in the gap, one of the second cell regions being placed in a corresponding row of the plurality of rows; and one or more third cell regions arranged in the gap, one of the third cell regions being placed in two corresponding adjacent rows of the plurality of rows.

[0090] In a related embodiment, the one or more second cell regions include: a third sub-region including a third channel of the first doping type, the third channel extending across the second cell region along the first direction, the third channel having a third channel width along the second direction; and a fourth sub-region directly adjacent to the third sub-region along the second direction, and including a fourth channel of the second doping type, the fourth channel extending across the second cell region along the first direction, the fourth channel having a fourth channel width along the second direction equal to the width of the third channel.

[0091] In a related embodiment, the first channel width of the first cell region is greater than the second channel width of the first binary cell region along the second direction.

[0092] In a related embodiment, the first cell region is spaced apart from any one of the second cell region and the third cell region along the first direction.

[0093] In one aspect of this disclosure, a method for generating an integrated circuit layout is provided. The method includes: receiving an integrated circuit design; identifying a first circuit module of the integrated circuit from the design based on a user specification or a first common feature; and arranging at least one first cell region based on the identified first circuit module, the at least one first cell region relating to gaps arranged for the integrated circuit design, the gaps comprising a plurality of rows extending along a first direction, each of the plurality of rows having a uniform row height along a second direction perpendicular to the first direction, the at least one first cell region being placed partially across three corresponding adjacent rows of the plurality of rows, wherein the at least one first cell region comprises: a first sub-region including a first channel of a first doping type extending across the first cell region along the first direction and having a first channel width along the second direction; and a second sub-region including a second channel of a second doping type opposite to the first doping type, the second channel also extending across the first cell region along the first direction and having a first channel width along the second direction.

[0094] In related embodiments, the method further includes: placing at least one first cell into the at least one first cell region.

[0095] In a related embodiment, the method further includes: identifying a second circuit module of the integrated circuit from the design of the integrated circuit based on the user specification or second common feature; arranging at least one second cell region related to the gap based on the identified second circuit module, wherein the at least one second cell region comprises: a third sub-region including a third channel of the first doping type extending across the second cell region along the first direction, the third channel having a second channel width along the second direction; and a fourth sub-region directly adjacent to the third sub-region along the second direction and including a fourth channel of the second doping type extending across the second cell region along the first direction, the fourth channel having a second channel width along the second direction, wherein, along the second direction, the first channel width of the first cell region is greater than the second channel width of the second cell region.

[0096] In a related embodiment, the method further includes: placing at least one second cell into the at least one second cell region, wherein the at least one second cell region is spaced apart from the at least one first cell region along the first direction.

[0097] In one aspect of this disclosure, an integrated circuit layout is provided. The integrated circuit layout includes a cell region comprising a plurality of cell rows extending along a first direction, each of the plurality of cell rows having a uniform row height along a second direction perpendicular to the first direction. The cell region comprises: a first region including a plurality of p-type first channels that span the cell region along the first direction and are separated from each other along the second direction, each of the plurality of first channels having a first channel height along the second direction; and a second region directly adjacent to the first region along the second direction and including a plurality of n-type second channels that span the cell region along the first direction and are separated from each other along the second direction. Each of the plurality of second channels has a second channel height along the second direction that is different from the first channel height.

[0098] In another aspect of this disclosure, an integrated circuit layout is provided. The integrated circuit layout includes gaps arranged for the layout and cell regions arranged within the gaps. Each cell region includes a plurality of cell rows extending along a first direction, each cell row having a uniform row height along a second direction perpendicular to the first direction. The cell region comprises: a first region including a plurality of first channels that completely span the cell region along the first direction and are separated from each other along the second direction, each of the plurality of first channels having a first channel height along the second direction; and a second region directly adjacent to the first region along the second direction, and including a plurality of second channels that partially span the cell region along the first direction and are separated from each other along the second direction. Each of the plurality of second channels has a second channel height along the second direction that is different from the height of the first channels.

[0099] In another aspect of this disclosure, an integrated circuit layout is provided. The integrated circuit layout includes gaps arranged for the integrated circuit layout; a first cell region arranged in the gaps, comprising a first plurality of cell rows extending along a first direction, each cell row having a uniform row height along a second direction perpendicular to the first direction; and a second cell region arranged in the gaps, comprising a second plurality of cell rows extending along the first direction, each cell row having a uniform row height along the second direction. The first cell region comprises: a first region including a plurality of p-type first channels extending along the first direction and separated from each other along the second direction, each of the plurality of first channels having a first channel height along the second direction; and a second region directly adjacent to the first region along the second direction, and including a plurality of n-type second channels extending along the first direction and separated from each other along the second direction, each of the plurality of second channels having a second channel height along the second direction greater than the first channel height.

[0100] The features of the above embodiments are conducive to the understanding of various aspects of this disclosure by those skilled in the art. Those skilled in the art should understand that other processes and structures can be designed and modified based on this disclosure to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this disclosure, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit layout, characterized in that, include: The gaps arranged for the layout of the integrated circuit include a plurality of rows extending along a first direction, each of the plurality of rows having a uniform row height along a second direction perpendicular to the first direction; One or more first cell regions are arranged in the gap, and one of the one or more first cell regions is placed in a corresponding row of the plurality of rows; One or more second cell regions are arranged in the gap, and one of the one or more second cell regions is placed in two corresponding adjacent rows of the plurality of rows; as well as One or more third cell regions are arranged in the gaps, and one of the one or more third cell regions is positioned to partially span three corresponding adjacent rows of the plurality of rows.

2. The integrated circuit layout according to claim 1, characterized in that, Each of the plurality of rows is defined by a first power line of Vdd and a second power line of Vss, the first power line and the second power line extending along the first direction and adjacent to each other along the second direction.

3. The integrated circuit layout according to claim 1, characterized in that, The first cell region includes: A first sub-region includes a first channel of a first doping type, the first channel extending across the first cell region along a first direction, and the first channel having a first channel width along a second direction; and The second sub-region is directly adjacent to the first sub-region along the second direction and includes a second channel of a second doping type opposite to the first doping type. The second channel extends across the first cell region along the first direction and has a second channel width along the second direction equal to the width of the first channel.

4. The integrated circuit layout according to claim 1, characterized in that, The second cell region includes: The third sub-region includes a third channel of the first doping type, the third channel extending across the one second cell region along the first direction, and the third channel having a third channel width along the second direction; A fourth sub-region includes a fourth channel of the first doping type, the fourth channel extending across the one second cell region along the first direction, and the fourth channel having a fourth channel width along the second direction equal to the width of the third channel; and A fifth sub-region, positioned along the second direction between the third and fourth sub-regions, includes a fifth channel of a second doping type, the fifth channel extending across the one second cell region along the first direction, and the fifth channel having a width along the second direction greater than either the width of the third channel or the width of the fourth channel. The fifth channel width of the second cell region is greater than the first channel width of the first cell region along the second direction.

5. The integrated circuit layout according to claim 1, characterized in that, The third cell region includes: A sixth sub-region includes a sixth channel of a first doping type, the sixth channel extending across the third cell region along the first direction, and the sixth channel having a sixth channel width along the second direction; and The seventh sub-region includes a seventh channel of the second doping type, which also extends across the third cell region along the first direction, and the seventh channel has a width equal to the width of the sixth channel along the second direction. The sixth channel width of the third cell region is greater than the first channel width of the first cell region along the second direction.

6. The integrated circuit layout according to claim 1, characterized in that, The third cell region completely spans the first corresponding row of the three corresponding adjacent rows, and partially spans the second and third corresponding rows of the three corresponding adjacent rows on both sides of the first corresponding row along the second direction.

7. The integrated circuit layout according to claim 1, characterized in that, In the one or more first cell regions, one first cell region is directly adjacent to and aligned with another first cell region in the one or more first cell regions along the first direction.

8. The integrated circuit layout according to claim 1, characterized in that, The second cell region is spaced apart from either the first cell region or the third cell region along the first direction.

9. The integrated circuit layout according to claim 1, characterized in that, The integrated circuit layout is arranged for nanochip transistors, and the nanochip transistors include: Multiple nanosheets are stacked on top of each other; A gate structure that surrounds each of the plurality of nanosheets; A first source / drain feature is located on a first side of the gate structure; and The second source / drain feature is located on the second side of the gate structure.

10. An integrated circuit layout, characterized in that, include: The gaps arranged for the layout of the integrated circuit include a plurality of rows extending along a first direction, each of the plurality of rows having a uniform row height along a second direction perpendicular to the first direction; as well as One or more first cell regions are arranged in the gaps, one of the one or more first cell regions being placed partially across three corresponding adjacent rows of the plurality of rows, wherein the one first cell region comprises: The first sub-region includes a first channel of a first doping type, the first channel extending across the first cell region along the first direction, and the first channel having a first channel width along the second direction; as well as The second sub-region includes a second channel of a second doping type opposite to the first doping type, the second channel also extending across the first cell region along the first direction, and the second channel having a second channel width along the second direction equal to the width of the first channel.

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