A topcon cell structure

Abstract

The utility model discloses a kind of TOPCon battery structure, it is related to solar cell technical field, including first electrode layer, first silicon nitride dielectric layer, passivation layer, P-type diffusion layer, silicon substrate, oxidation dielectric layer, polysilicon layer, second silicon nitride dielectric layer and second electrode layer which are sequentially laminated, the silicon substrate front and back are respectively pyramid-shaped suede structure and polishing surface structure, the suede structure is divided into grid line area and non-grid line area, the pyramid size of the non-grid line area is greater than the pyramid size of grid line area. The TOPCon battery structure, in the front non-grid line position area, secondary texturing is carried out, increase the pyramid size size of non-grid line area, by reducing front reflectivity, improve light absorption effect, while small suede structure is retained in the front grid line position area, reduce the contact resistance at the front grid line, improve the conversion efficiency of battery.

Description

Technical Field

[0001] This utility model relates to the field of solar cell technology, specifically a TOPCon battery structure. Background Technology

[0002] TOPCon is a novel solar cell technology based on N-type silicon wafers, short for tunneling oxide passivated contact solar cell. It is considered one of the main directions for next-generation high-efficiency solar cells, offering higher photoelectric conversion efficiency and long-term performance stability. TOPCon cells reduce recombination losses and improve efficiency by adding a tunneling oxide layer and a thin layer of polycrystalline silicon to the silicon wafer surface. They are also compatible with existing PERC production lines and have promising development prospects.

[0003] For example, Chinese patent CN222233645U, entitled "A TOPCon Battery Structure," includes a silicon substrate. The front side of the silicon substrate, from the outside to the inside, is provided with front gate lines, an anti-reflection film layer, an aluminum oxide layer, and a boron diffused emitter layer. The back side of the silicon substrate, from the inside to the outside, is provided with a tunneling oxide layer, a doped polycrystalline silicon layer, a silicon nitride layer, and a back gate line. An ultrathin silicon oxide layer, with a thickness of 0.8 nm to 2.0 nm, is disposed within the doped polycrystalline silicon layer. This TOPCon battery structure effectively increases the doping concentration of the poly layer, thereby improving the back passivation effect and back contact. Simultaneously, the ultrathin silicon oxide layer structure acts as a barrier against phosphorus atoms, preventing phosphorus atom diffusion without affecting the passage of charge carriers.

[0004] While the TOPCon battery structure in the aforementioned patent is practical and convenient, it also has its shortcomings. The TOPCon battery structure selects a pyramid textured surface of a certain size on the front side to increase light absorption on the front side of the battery. However, when the pyramid size is too small, the contact resistance of the silver paste on the front side will be low, and the reflectivity of the textured surface will be too high. This makes it impossible to balance the light absorption effect and the contact resistance at the grid line, resulting in a loss of both the light absorption effect and the contact resistance. Utility Model Content

[0005] The purpose of this invention is to provide a TOPCon battery structure to address the shortcomings of the prior art.

[0006] To achieve the above objectives, this utility model provides the following technical solution: The TOPCon battery structure includes a first electrode layer, a first silicon nitride dielectric layer, a passivation layer, a P-type diffusion layer, a silicon substrate, an oxide dielectric layer, a polycrystalline silicon layer, a second silicon nitride dielectric layer, and a second electrode layer, which are stacked sequentially. The front and back sides of the silicon substrate are a pyramid-shaped textured surface structure and a polished surface structure, respectively. The textured surface structure is divided into a grid line region and a non-grid line region. The pyramid size of the non-grid line region is larger than the pyramid size of the grid line region.

[0007] Furthermore, the oxide dielectric layer is a silicon oxide film layer, and the thickness of the oxide dielectric layer is 20-40 nm.

[0008] Furthermore, the P-type diffusion layer is a boron diffusion layer, and the P-type diffusion layer forms a PN junction with the silicon substrate. The thickness of the P-type diffusion layer is 80-130 nm.

[0009] Furthermore, the passivation layer is an alumina dielectric layer with a thickness of 3-8 nm.

[0010] Furthermore, the thickness of the first silicon nitride dielectric layer is 60-90 nm and the refractive index is 2.0-2.10, and the thickness of the second silicon nitride dielectric layer is 70-90 nm and the refractive index is 2.05-2.15.

[0011] Furthermore, both the first electrode layer and the second electrode layer are silver electrodes.

[0012] Furthermore, the silicon substrate is an N-type single-crystal silicon wafer.

[0013] Furthermore, the polycrystalline silicon layer is a phosphorus-doped polycrystalline silicon film, and the thickness of the polycrystalline silicon layer is 80-130 nm.

[0014] Compared with the prior art, the beneficial effects provided by this utility model are as follows: The TOPCon battery structure performs secondary texturing in the non-grid area on the front side, which increases the size of the pyramid in the non-grid area and improves the light absorption effect by reducing the front reflectivity. At the same time, it retains a small texturing structure in the grid area on the front side, which reduces the contact resistance at the grid and improves the conversion efficiency of the battery. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings.

[0016] Figure 1This is a schematic diagram of the TOPCon battery structure provided in an embodiment of the present invention;

[0017] Figure 2 A process flow diagram for the fabrication of the TOPCon battery structure provided in this embodiment of the present invention.

[0018] Explanation of reference numerals in the attached figures: 1. First electrode layer; 2. First silicon nitride dielectric layer; 3. Passivation layer; 4. P-type diffusion layer; 5. Silicon substrate; 6. Oxide dielectric layer; 7. Polycrystalline silicon layer; 8. Second silicon nitride dielectric layer; 9. Gate line region; 10. Non-gate line region; 11. Textured surface structure; 12. Polished surface structure; 13. Second electrode layer. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solution of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings.

[0020] Please see Figure 1-2 The present invention provides a technical solution: the TOPCon battery structure includes a first electrode layer 1, a first silicon nitride dielectric layer 2, a passivation layer 3, a P-type diffusion layer 4, a silicon substrate 5, an oxide dielectric layer 6, a polycrystalline silicon layer 7, a second silicon nitride dielectric layer 8, and a second electrode layer 13, which are stacked sequentially. The front and back sides of the silicon substrate 5 have a pyramid-shaped textured structure 11 and a polished structure 12, respectively. The textured structure 11 is divided into a grid line region 9 and a non-grid line region 10. The pyramid size of the non-grid line region 10 is larger than that of the grid line region 9. Specifically, after texturing, a mask layer is deposited on the front surface of the silicon wafer, and a laser is used to modify the front non-grid line region 10. After a second texturing process, a large textured structure 11 is obtained for the non-grid line region 10. By reducing the front reflectivity, the light absorption effect is improved. The small textured structure 11 for the grid line region 9 on the front surface reduces the contact resistance at the front grid line and improves the conversion efficiency of the battery.

[0021] In this embodiment, the oxide dielectric layer 6 is a silicon oxide film layer with a thickness of 20-40 nm.

[0022] In this embodiment, the P-type diffusion layer 4 is a boron diffusion layer, and the P-type diffusion layer 4 forms a PN junction with the silicon substrate 5. The thickness of the P-type diffusion layer 4 is 80-130nm.

[0023] In this embodiment, the passivation layer 3 is an aluminum oxide dielectric layer with a thickness of 3-8 nm.

[0024] In this embodiment, the thickness of the first silicon nitride dielectric layer 2 is 60-90 nm and the refractive index is 2.0-2.10, and the thickness of the second silicon nitride dielectric layer 8 is 70-90 nm and the refractive index is 2.05-2.15.

[0025] In this embodiment, both the first electrode layer and the second electrode layer 13 are silver electrodes. Specifically, the first electrode layer 1 penetrates the first silicon nitride dielectric layer 2 and the passivation layer 3 and is in contact with the P-type diffusion layer 4, and the second electrode layer 13 penetrates the second silicon nitride dielectric layer 8 and the polycrystalline silicon layer 7 and is in contact with the polycrystalline silicon layer 7.

[0026] In this embodiment, the silicon substrate 5 is an N-type monocrystalline silicon wafer.

[0027] In this embodiment, the polycrystalline silicon layer 7 is a phosphorus-doped polycrystalline silicon film with a thickness of 80-130 nm. Specifically, it can transport electrons to the electrode.

[0028] The fabrication method of the TOPCon battery structure in this embodiment includes the following steps:

[0029] S1. Texturing: Using an N-type monocrystalline silicon wafer as the silicon substrate 5, acid and alkali chemicals are used to texturize both sides of the monocrystalline silicon wafer to form a pyramid structure on the surface of the monocrystalline silicon wafer.

[0030] S2, Deposition Mask: A 20-40nm silicon oxide film is deposited on the surface using PECVD at a temperature of 450℃, a time of 100s, a power of 15000W, and a SiH4 / N2O flow rate of 1600 / 7100sccm.

[0031] S3, Laser: Laser energy: 30-60W, spot size: 60-120um, using laser to modify the non-grid area on the front side with 10 lasers;

[0032] S4. Secondary texturing: Using chemicals such as alkaline solution, additives, and pure water, the pyramids of the non-gate area 10 of the silicon wafer are further etched to increase the size of the pyramids in the non-gate area 10. The size is controlled by the etching conditions.

[0033] S5. Boron diffusion and oxidation: Boron diffusion is performed on the front surface of the silicon wafer. The boron source is BCl3 and the diffusion sheet resistance is 300-400Ω / sq. BSG is formed on the surface of the N-type single crystal silicon wafer with a thickness of 100-150nm.

[0034] S6. Alkaline polishing: After removing the back BSG, the back surface of the silicon wafer is polished and cleaned using a tank-type machine. The reaction solution is alkali (KOH or NaOH) and the cleaning is carried out at 50-70℃ for 100-200s to obtain a back surface with a reflectivity greater than 40% and a base greater than 8um.

[0035] S9, PE-poly and annealing: The back side is deposited with tunneling oxide and doped amorphous silicon using PECVD. The ultrathin oxide layer is 1-1.8nm thick, the doped amorphous silicon layer is 80-130nm thick, and the sheet resistance is 30-80Ω / sq. After annealing at 650-950℃, the doped amorphous silicon is crystallized into a phosphorus-doped polycrystalline silicon film.

[0036] S10, Remove polysilicon wrapping: Chain etching and acid washing of the front side of the silicon wafer, followed by RCA cleaning (alkali and additives) to remove the polysilicon wrapping on the edge and front side, and HF acid bath to remove the BSG layer on the front side.

[0037] S11, ALD: A layer of aluminum oxide dielectric layer (Al2O3 thin film) with a thickness of 3-8nm is deposited on the front surface using ALD;

[0038] S12, Coating: Silicon nitride layers are deposited on the front and back sides. The first silicon nitride dielectric layer 2 (front silicon nitride film) has a thickness of 60-90nm and a refractive index of 2.0-2.10; the second silicon nitride dielectric layer 8 (back silicon nitride film) has a thickness of 70-90nm and a refractive index of 2.05-2.15.

[0039] S13, Screen printing: Silver paste is printed on the front and the back.

[0040] Working principle: The TOPCON battery structure provided by this invention is prepared using the above-mentioned method. In the prior art, when the size of the pyramid textured surface on the front of the TOPCon battery structure is small, the contact resistance of the silver paste on the front will be low, and the reflectivity of the textured surface will be large, resulting in a loss of both light absorption and contact resistance. In this invention, after texturing, a mask layer is deposited on the front surface of the silicon wafer, and a laser is used to modify the non-grid area 10 on the front. After secondary texturing, a large textured surface structure 11 is obtained in the non-grid area 10. By reducing the front reflectivity, the light absorption effect is improved. The small textured surface structure 11 in the grid area 9 on the front surface reduces the contact resistance at the grid line and improves the conversion efficiency of the battery.

[0041] The foregoing description only illustrates certain exemplary embodiments of the present invention. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A TOPCon battery structure, characterized in that, The structure includes a first electrode layer (1), a first silicon nitride dielectric layer (2), a passivation layer (3), a P-type diffusion layer (4), a silicon substrate (5), an oxide dielectric layer (6), a polysilicon layer (7), a second silicon nitride dielectric layer (8), and a second electrode layer (13) stacked sequentially. The front and back sides of the silicon substrate (5) are a pyramid-shaped textured structure (11) and a polished structure (12), respectively. The textured structure (11) is divided into a gate line region (9) and a non-gate line region (10). The pyramid size of the non-gate line region (10) is larger than that of the gate line region (9).

2. The TOPCon battery structure according to claim 1, characterized in that, The oxide medium layer (6) is a silicon oxide film layer, and the thickness of the oxide medium layer (6) is 20-40 nm.

3. The TOPCon battery structure according to claim 1, characterized in that, The P-type diffusion layer (4) is a boron diffusion layer. The P-type diffusion layer (4) forms a PN junction with the silicon substrate (5). The thickness of the P-type diffusion layer (4) is 80-130 nm.

4. The TOPCon battery structure according to claim 1, characterized in that, The passivation layer (3) is an alumina dielectric layer with a thickness of 3-8 nm.

5. A TOPCon battery structure according to claim 1, characterized in that, The thickness of the first silicon nitride dielectric layer (2) is 60-90 nm and the refractive index is 2.0-2.

10. The thickness of the second silicon nitride dielectric layer (8) is 70-90 nm and the refractive index is 2.05-2.

15.

6. A TOPCon battery structure according to claim 1, characterized in that, Both the first electrode layer (1) and the second electrode layer (13) are silver electrodes.

7. A TOPCon battery structure according to claim 1, characterized in that, The silicon substrate (5) is an N-type monocrystalline silicon wafer.

8. A TOPCon battery structure according to claim 1, characterized in that, The polycrystalline silicon layer (7) is a phosphorus-doped polycrystalline silicon film, and the thickness of the polycrystalline silicon layer (7) is 80-130 nm.

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