Semiconductor structure

Abstract

A semiconductor structure is provided, including: a plurality of pixel segments arranged in a substrate, each pixel segment having a plurality of sides; and a first pixel segment of the plurality of pixel segments, the first pixel segment including: a photodetector; and a vertical transfer gate (VTG) structure disposed over the photodetector, the VTG structure having a laterally extending body portion, and a plurality of wall segments connected to end regions of the body portion, the plurality of wall segments extending vertically into the substrate and laterally to a vicinity of the sides of the pixel segment.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure. Background Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using lithography to pattern each material layer to form circuit elements and components on it.

[0003] The semiconductor industry is continuously shrinking the minimum feature size to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), allowing more components to be integrated into specific areas. However, as the minimum feature size shrinks, more problems also arise that need to be solved. Utility Model Content

[0004] According to some embodiments, a semiconductor structure includes a plurality of pixel segments and a first pixel segment of the pixel segments. The plurality of pixel segments are arranged in a substrate, and each pixel segment has a plurality of sides. The first pixel segment includes a photodetector and a Vertical Transfer Gate (VTG) structure. The VTG structure is disposed above the photodetector and has a laterally extending body portion and a plurality of wall segments connected to the body portion and extending vertically into different end regions of the substrate. A first wall segment of the wall segments extends laterally by a first side of the first pixel segment by a first distance, and a second wall segment of the wall segments extends laterally by a second side of the first pixel segment by a second distance. The first distance is greater than half the length of the first side, and the second distance is greater than half the length of the second side.

[0005] According to some embodiments, a semiconductor structure includes a plurality of pixel segments and a first pixel segment of the pixel segments. The plurality of pixel segments are arranged in a substrate, and each pixel segment has a plurality of sides. The first pixel segment includes a photodetector and a vertical transmission gate structure. The vertical transmission gate structure is disposed above the photodetector and includes a body portion and two or more wall segments extending vertically into the substrate below the body portion. The two or more wall segments have different depths. The first wall segment of the two or more wall segments extends laterally by a first side of the first pixel segment by a first distance. The second wall segment of the two or more wall segments extends laterally by a second side of the first pixel segment by a second distance. The first distance is greater than half the length of the first side, and the second distance is greater than half the length of the second side.

[0006] According to some embodiments, a semiconductor structure includes a plurality of pixel segments and a first pixel segment of the pixel segments. The plurality of pixel segments are arranged in a substrate, and each pixel segment has a plurality of sides. The first pixel segment includes a photodetector and a vertical transmission gate structure. The vertical transmission gate structure is disposed above the photodetector. The vertical transmission gate structure includes a body portion and four wall segments below the body portion. The first wall segments of the four wall segments extend laterally by a first distance adjacent to a first side of the first pixel segment. The second wall segments of the four wall segments extend laterally by a second distance adjacent to a second side of the first pixel segment. The first distance is greater than half the length of the first side, and the second distance is greater than half the length of the second side. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of discussion.

[0008] Figure 1A To illustrate a plan or layout diagram of a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) according to certain embodiments;

[0009] Figure 1B A schematic cross-sectional view illustrating a pixel segment of a complementary metal-oxide-semiconductor image sensor according to certain embodiments;

[0010] Figure 2A A schematic top view illustrating a portion of the pixel structure of an image sensor comprising multiple sub-pixel segments according to certain embodiments;

[0011] Figure 2B To illustrate the path according to certain embodiments Figure 1A A schematic cross-sectional view of a sub-pixel segment of an embodiment of the cutting line A-A';

[0012] Figure 3A A schematic top view illustrating a portion of a pixel structure according to certain embodiments, the pixel structure comprising a plurality of pixel segments arranged in a substrate;

[0013] Figure 3B To illustrate the path according to certain embodiments Figure 3A A schematic cross-sectional view of an example sub-pixel segment of the cutting line B-B';

[0014] Figure 3C To illustrate the path according to certain embodiments Figure 3A A schematic cross-sectional view of a sub-pixel segment of another embodiment of the cutting line B-B';

[0015] Figure 3D To illustrate the path according to certain embodiments Figure 3A A schematic cross-sectional view of a sub-pixel segment of another embodiment of the cutting line B-B';

[0016] Figure 4A A schematic top view illustrating that the pixel structure comprises multiple pixel segments arranged in a substrate;

[0017] Figure 4B To illustrate along some implementation methods Figure 4A A schematic cross-sectional view of a sub-pixel segment of an embodiment of the cutting line C-C';

[0018] Figure 4C To illustrate the path according to some implementation methods Figure 4A Another embodiment of the cutting line C-C' is a sub-pixel segment;

[0019] Figure 5A A schematic top view is provided to illustrate a portion of a pixel structure according to some embodiments, the pixel structure comprising multiple pixel segments arranged in a substrate;

[0020] Figure 5B To illustrate, according to some implementation methods, the following is depicted along... Figure 5A A schematic cross-sectional view of a sub-pixel segment of an embodiment of the cutting line D-D';

[0021] Figure 5C To illustrate, according to some implementation methods, the following is depicted along... Figure 5A A schematic cross-sectional view of a sub-pixel segment of another embodiment of the cutting line D-D';

[0022] Figure 5D To illustrate, according to some implementation methods, the following is depicted along... Figure 5A A schematic cross-sectional view of a sub-pixel segment of another embodiment of the cutting line D-D';

[0023] Figures 6A to 6I A schematic top view is provided to illustrate a portion of a pixel structure according to some embodiments, the pixel structure comprising multiple pixel segments arranged in a substrate;

[0024] Figure 7A To illustrate the quantum efficiency of an imaging element in converting incident photons of light into electrons versus the wavelength of light (in nanometers) according to some embodiments;

[0025] Figures 7B to 7F A schematic cross-sectional view illustrating pixel segments according to embodiments of some implementation methods;

[0026] Figure 8A A schematic diagram illustrating an embodiment layout of multiple pixel segments in a semiconductor imaging element according to some implementations;

[0027] Figure 8B A schematic cross-sectional view illustrating example pixel segments according to some implementation methods;

[0028] Figure 8C A schematic cross-sectional view illustrating example pixel segments according to some implementation methods;

[0029] Figure 9 A flowchart illustrating an embodiment of a method for manufacturing a semiconductor device having a vertical transmission gate according to some implementations;

[0030] Figures 10A to 10H This is a schematic cross-sectional view illustrating different stages of the manufacturing process of a semiconductor device according to some embodiments.

[0031] [Symbol Explanation]

[0032] 100: Example of a complementary metal-oxide-semiconductor image sensor

[0033] 102: Pixel segment

[0034] 102U: Unit Pixel

[0035] 104: Optical isolation area

[0036] 106: Physically isolated area

[0037] 108: Electrode sheet

[0038] 110: Black level correction area

[0039] 112: Photodiode layer

[0040] 114: Semiconductor substrate

[0041] 116: First Surface

[0042] 118: Second Surface

[0043] 120: Color Filter

[0044] 122: Miniature Lens

[0045] 124: Substrate Dielectric Layer

[0046] 126: First isolation structure

[0047] 128: Second isolation structure

[0048] 130: Dielectric materials

[0049] 132: Transmission Gate

[0050] 134: Third isolation structure

[0051] 200: Pixel Structure

[0052] 202: Sub-pixel segment

[0053] 203: Pixel segment

[0054] 203-1, 203-2, 203-3, 203-4: Side

[0055] 204: Gate polymerization region

[0056] 205: Gate oxide

[0057] 206: Light Detector

[0058] 208: Substrate

[0059] 210: Floating diffusion region

[0060] 212: Contact point

[0061] 214: Shallow trench isolation features

[0062] 216: Vertical transmission gate structure

[0063] 218: Ontology Department

[0064] 220: Wall Section

[0065] 300: Pixel Structure

[0066] 302-1, 302-2, 302-3, 302-4: Pixel segments

[0067] 303-1, 303-2, 303-3, 303-4: Side

[0068] 304: Shallow trench isolation features

[0069] 306: Vertical transmission gate structure

[0070] 306-1, 306-2, 306-3, 306-4: Wall Sections

[0071] 308: Light Detector

[0072] 309: Vertical transmission gate structure

[0073] 310: Gate polymerization region

[0074] 312: Gate oxide

[0075] 314: Substrate

[0076] 318: Ontology Department

[0077] 320: Wall Section

[0078] 330: Wall Section

[0079] 400: Pixel Structure

[0080] 402-1, 402-2, 402-3, 402-4: Pixel segments

[0081] 403-1, 403-2, 403-3, 403-4: Side

[0082] 406: Vertical transmission gate structure

[0083] 406-1, 406-2, 406-3, 406-4: Wall Sections

[0084] 408: Light Detector

[0085] 409: Vertical transmission gate structure

[0086] 410: Gate polymerization region

[0087] 412: Gate oxide

[0088] 414: Substrate

[0089] 418: Ontology Department

[0090] 420: Wall Section

[0091] 430: Wall Section

[0092] 500: Pixel Structure

[0093] 502-1, 502-2, 502-3, 502-4: Pixel segments

[0094] 503-1, 503-2, 503-3, 503-4: Side

[0095] 504: Shallow trench isolation features

[0096] 506: Vertical transmission gate structure

[0097] 506-1, 506-2, 506-3, 506-4: Wall Sections

[0098] 508: Light Detector

[0099] 509: Vertical transmission gate structure

[0100] 510: Gate polymerization region

[0101] 512: Gate oxide

[0102] 514: Substrate

[0103] 518:Ontology Department

[0104] 520: Wall Section

[0105] 530: Wall Section

[0106] 602-1, 602-2, 602-3, 602-4: Pixel segments

[0107] 604: Shallow trench isolation features

[0108] 606: Vertical transmission gate structure

[0109] 606-1, 606-2, 606-3, 606-4: Wall Sections

[0110] 702: First Image

[0111] 704: Second Figure

[0112] 706: Third Figure

[0113] 710: Vertical transmission gate structure

[0114] 712:Wall

[0115] 714: Wall Depth

[0116] 720: Vertical transmission gate structure

[0117] 722:Wall

[0118] 724: Wall Depth

[0119] 730: Vertical transmission gate structure

[0120] 732:Wall

[0121] 734: Wall Depth

[0122] 740: Vertical transmission gate structure

[0123] 742:Wall

[0124] 744: Wall Depth

[0125] 750: Vertical transmission gate structure

[0126] 752:Wall

[0127] 754: Wall Depth

[0128] 802: Area 1

[0129] 804: Second Zone

[0130] 806: Third Area

[0131] 808: Fourth Area

[0132] 810: Fifth District

[0133] 820: Vertical transmission gate structure

[0134] 822: Green pixel segment

[0135] 824: Red pixel segment

[0136] 826: Transparent pixel segment

[0137] 828: Ontology Department

[0138] 830, 832, 834, 836: Wall sections

[0139] 840: Vertical transmission gate structure

[0140] 842: Green pixel segment

[0141] 844: Red pixel segment

[0142] 846: Transparent pixel segment

[0143] 848:Ontology Department

[0144] 850, 852, 854, 856: Wall sections

[0145] 900: Methods 910, 920, 930, 932, 934, 940, 950, 952, 954, 956, 958, 959, 960: Block 1002: Substrate

[0146] 1004: Pixel shallow trench isolation area

[0147] 1006: Pixel sensor area

[0148] 1008: Photoresist

[0149] 1010: Open

[0150] 1012: Vertical trench

[0151] 1014: Gate oxide layer

[0152] 1016: Gate polymerization layer

[0153] 1018: Optical Obscuration

[0154] 1020: Gate Aggregation Region

[0155] A-A': Cutting line

[0156] B-B': Cutting line

[0157] C-C': Cutting line

[0158] D-D': Cutting line

[0159] L-L': Cutting line Detailed Implementation

[0160] The following disclosure provides many different implementations, or embodiments, to carry out different features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify the content of this disclosure. Of course, these are merely embodiments and are not intended to be limiting.

[0161] For the sake of brevity, technologies related to semiconductor device manufacturing may not be described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into a more comprehensive procedure or process with additional functionality not described in detail herein. In particular, various processes in semiconductor device manufacturing are well-known; therefore, for the sake of brevity, many routine processes will only be briefly mentioned herein, or omitted entirely without providing details of well-known processes. Those skilled in the art will readily recognize, upon a full reading of this disclosure, that the structures disclosed herein can be employed using various different technologies and incorporated into a wide variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures contain varying numbers of elements, and a single element shown in the accompanying drawings may represent multiple elements.

[0162] In addition to the directions depicted in the diagram, spatially relative terms also include different orientations of the elements during use or operation. The device may be in other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly. When using spatially relative terms (as listed above) to describe the first element relative to the second element, the first element may be directly on the other element, or there may be intermediate elements or layers present.

[0163] Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is for the sake of brevity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0164] It should be noted that the terms "an embodiment," "an embodiment," "an exemplary embodiment," "exemplary," and "example" used in these claims indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment does not necessarily include specific features, structures, or characteristics. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described as being related to a particular embodiment, whether or not it is explicitly described, the influence of the relationship between that feature, structure, or characteristic and other embodiments falls within the knowledge scope of those skilled in the art.

[0165] It should be understood that the vocabulary or terms used herein are for descriptive and not limiting purposes, and therefore the terms or vocabulary in these claims should be interpreted by those skilled in the art based on the teachings herein.

[0166] The following disclosure provides many different implementations, or embodiments, to carry out different features of the disclosed subject matter. To simplify this disclosure, specific embodiments of elements and arrangements are described below. Of course, these are merely embodiments and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, or embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Throughout this description, unless otherwise stated, like reference numerals in the different figures refer to like or similar elements formed using the same or similar materials and in the same or similar methods.

[0167] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or parts, and these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another element, component, region, layer, or segment. Unless the context clearly indicates otherwise, the use of terms such as “first,” “second,” and “third” herein does not indicate order or sequence.

[0168] As used in this article, the terms “approximately,” “substantially,” “largely,” and “about” are used to describe and explain minute variations. When used with an event or situation, these terms can refer to an event or situation occurring precisely, or approximately. For example, when used with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the “average,” such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two values ​​can be considered “approximately” the same or equal. For example, "approximately" parallel can refer to an angle variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "approximately" perpendicular can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0169] Semiconductor image sensors are used to sense incoming visible or invisible radiation, such as visible light and infrared radiation. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) are used in a variety of applications, such as digital still cameras, mobile phones, tablet computers, and goggles. These image sensors utilize pixel arrays to absorb (e.g., sense) input radiation and convert it into electronic signals.

[0170] A backside-illuminated (BSI) image sensor is an image sensor element. A BSI image sensor includes pixel segments having an array of pixels or radiation-sensing regions formed on a substrate (e.g., a semiconductor substrate). The terms "radiation-sensing region" and "pixel" may be used interchangeably in this disclosure. Pixels are configured to convert photons of incident radiation into electronic signals. These electronic signals are then distributed to processing elements attached to the BSI image sensor. Pixel segments include pixel segment structures that provide optical isolation between adjacent pixels. Furthermore, pixel segments may include color filters. The material of the color filter can be selected such that light of a desired wavelength passes through the color filter, while light of other wavelengths is absorbed by the color filter.

[0171] The aim is to improve image sensor elements. According to some embodiments of this disclosure, a vertical transfer gate (VTG) surround design structure with multiple transfer gate walls is proposed to capture more electrons in the radiation sensing region, thereby reducing image sensor hysteresis. According to some embodiments of this disclosure, a full-circumference vertical transfer gate design structure is proposed, which has multiple transfer gate walls arranged deeper in the radiation sensing region to capture more electrons in the radiation sensing region, thereby reducing image sensor hysteresis.

[0172] Figure 1A This is a plan or layout diagram illustrating an example complementary metal-oxide-semiconductor (CMOS) image sensor 100 according to some embodiments. The example CMOS image sensor 100 includes pixel segments 102 in which a plurality of unit pixels are arranged in a matrix, and an optical isolation region 104 surrounding the pixel segments 102. Furthermore, the optical isolation region 104 is surrounded by a physical isolation region 106. In some embodiments, the example CMOS image sensor 100 includes a plurality of electrode pads 108 for wiring to external circuitry. The example CMOS image sensor 100 further includes one or more black level calibration (BLC) regions 110 that block incident light and provide a reference dark voltage current.

[0173] Figure 1B The pixel segment 102 of an example complementary metal-oxide-semiconductor image sensor 100 according to some embodiments is shown along... Figure 1AA cross-sectional view of the cutting line L-L'. Pixel segment 102 includes a plurality of unit pixels 102U, each unit pixel 102U including a photodiode layer 112 formed in a semiconductor substrate 114 (e.g., a Si substrate) having a first surface 116 and an opposing second surface 118, a color filter 120 disposed on the second surface 118 and substantially aligned with the photodiode layer 112, and a microlens 122 disposed on and aligned with the color filter 120. In some embodiments, a liner dielectric layer 124 is disposed between the color filter 120 and the microlens 122. The example complementary metal-oxide-semiconductor image sensor 100 also includes a first isolation structure 126 to laterally separate adjacent color filters 120. The example complementary metal-oxide-semiconductor (CMOS) image sensor 100 includes a second isolation structure 128, which is a deep trench isolation structure filled with one or more dielectric materials 130, disposed in a semiconductor substrate 114 to laterally separate adjacent photodiode layers 112. Furthermore, the example CMOS image sensor 100 also includes a transmission gate 132 coupled to and aligned with the photodiode layers 112 disposed on a first surface 116 of the semiconductor substrate 114. In some embodiments, a third isolation structure 134 (which is a doped region implanted, for example, with boron) is disposed between and aligned with the second isolation structure 128 and the first surface 116, and functions as an electrical isolation structure. In some embodiments, each unit pixel 102U has a square or rectangular shape in a plan view and is surrounded by the first isolation structure 126, the second isolation structure 128, and the third isolation structure 134.

[0174] Figure 2A This is a schematic top view of a portion of a pixel structure 200 (e.g., unit pixel 102U) of an image sensor comprising a plurality of sub-pixel segments 202 according to some embodiments of the present disclosure. The pixel structure 200 comprises a plurality of pixel segments 203 arranged in a substrate. When viewed from top, each pixel segment 203 has a plurality of sides. In this embodiment, each pixel segment 203 has four sides (side 203-1, side 203-2, side 203-3, and side 203-4). The sub-pixel segments 202 and pixel segments 203 of this embodiment include gate aggregation regions 204 for vertical transmission gates, disposed above and around a photodetector 206 in the substrate. The sub-pixel segments 202 also include floating diffusion (FD) regions 210 and contact points 212, and may include shallow trench isolation features 214.

[0175] Figure 2B It describes along Figure 2AAn exemplary cross-sectional view of the subpixel segment 202 along the cutting line A-A'. In this embodiment, the subpixel segment 202 includes a gate aggregation region 204 and a gate oxide 205 for a vertical transmission gate disposed above and around a photodetector 206 in the substrate 208. The subpixel segment 202 also includes a shallow trench isolation feature 214.

[0176] The vertical transmission gate structure 216 includes a gate polymerization region 204 and a gate oxide 205, which is disposed above the photodetector 206 in the pixel segment 203. The vertical transmission gate structure 216 has a laterally extending body portion 218 and a plurality of wall segments 220 connected to an end region of the body portion 218, the end region extending vertically to the substrate 208 and laterally to the side of the pixel segment 203.

[0177] The substrate 208 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, or a similar substrate, which may be doped (e.g., having p-type or n-type dopants) or undoped. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate may comprise silicon.

[0178] Figure 3A This is a schematic top view of a portion of a pixel structure 300 according to some embodiments of the present disclosure, the pixel structure 300 comprising a plurality of pixel segments (e.g., pixel segment 302-1, pixel segment 302-2, pixel segment 302-3, pixel segment 302-4) disposed in a substrate. Each pixel segment has a plurality of sides (side 303-1, side 303-2, side 303-3, side 303-4), four in this embodiment. In this embodiment, each pixel segment is isolated from neighboring pixel segments among the plurality of pixel segments by an isolation layer (e.g., shallow trench isolation feature 304) at the boundary between the pixel segment and neighboring pixel segments.

[0179] The vertical transmission gate structure 306 includes a gate polymerization region (shown) and a gate oxide (not shown), disposed above and around a photodetector 308 in a pixel segment (e.g., pixel segment 302-1). The vertical transmission gate structure 306 has a plurality of wall segments (wall segments 306-1, 306-2, 306-3, and 306-4) that extend vertically into the substrate and laterally to the sides (sides 303-1, 303-2, 303-3, and 303-4) of the pixel segment (e.g., pixel segment 302-1). In this embodiment, each wall segment extends by a distance greater than half the length of the corresponding side adjacent to it. For example, wall segment 306-1 extends by a distance greater than half the length of side segment 303-1.

[0180] Figure 3B It describes along Figure 3A An exemplary cross-sectional view of a sub-pixel segment in pixel segment 302-1 along the cut line B-B'. In this embodiment, the sub-pixel segment includes a vertical transmission gate structure 309 comprising a gate aggregation region 310 and a gate oxide 312, which serve as vertical transmission gates configured above and around a photodetector 308 in a pixel segment (e.g., pixel segment 302-1, pixel segment 302-2, pixel segment 302-3, or pixel segment 302-4) within a substrate 314. The sub-pixel segment also includes a shallow trench isolation feature 304.

[0181] The vertical transmission gate structure 309 has a laterally extending body portion 318 and a plurality of wall segments 320 connected at the end regions of the body portion 318. These wall segments 320 extend vertically into the substrate 314 and laterally to adjacent sides (e.g., side 303-1, side 303-2, side 303-3, or side 303-4) of pixel segments (e.g., pixel segments 302-1, 302-2, 302-3, or 302-4). The plurality of wall segments 320 are disposed within portions of the pixel segments, which are isolated from adjacent pixel segments by an isolation layer (e.g., shallow trench isolation feature 304).

[0182] Figure 3C It describes along Figure 3AA schematic cross-sectional view of another example sub-pixel segment in pixel segment 302-1 with cut line B-B'. In this embodiment, the sub-pixel segment includes a vertical transmission gate structure 309 comprising a gate aggregation region 310 and a gate oxide 312, which serve as a vertical transmission gate configured above and around a photodetector 308 in a pixel segment (e.g., pixel segment 302-1, pixel segment 302-2, pixel segment 302-3, or pixel segment 302-4) in the substrate 314. The sub-pixel segment also includes a shallow trench isolation feature 304.

[0183] The vertical transmission gate structure 309 has a laterally extending body portion 318 and a plurality of wall segments 330 connected to the end regions of the body portion 318. The wall segments 330 extend vertically into the substrate 314 and laterally to adjacent sides (e.g., side 303-1, side 303-2, side 303-3, or side 303-4) of pixel segments (e.g., pixel segments 302-1, 302-2, 302-3, or 302-4). The plurality of wall segments 330 are disposed within portions of the pixel segments, which are isolated from adjacent pixel segments by an isolation layer (e.g., shallow trench isolation feature 304).

[0184] Figure 3C Example sub-pixel segments are similar to Figure 3B The example sub-pixel segments differ in length from the wall segments. Figure 3B In one embodiment, the length of the wall segment 320 is longer than Figure 3C In this embodiment, the length of the wall segment 330 is specified. The length of the wall segment can be adjusted for light in a specific wavelength band that the sub-pixel area is configured to detect. For example, if the sub-pixel segment is configured to detect red light, the length of the wall segment can be within a first predetermined length range; if the sub-pixel segment is configured to detect green light, the length of the wall segment can be within a second predetermined length range; if the sub-pixel segment is configured to detect blue light, the length of the wall segment can be within a third predetermined length range; if the sub-pixel segment is configured to detect clear light (e.g., white light), the length of the wall segment can be within a fourth predetermined length range; if the sub-pixel segment is configured to detect infrared light, the length of the wall segment can be within a fifth predetermined length range, and so on.

[0185] Figure 3D It describes along Figure 3AA schematic cross-sectional view of another example sub-pixel segment in pixel segment 302-1 with cut line B-B'. In this embodiment, the sub-pixel segment includes a vertical transmission gate structure 309 comprising a gate aggregation region 310 and a gate oxide 312, which serve as a vertical transmission gate configured above and around a photodetector 308 in a pixel segment (e.g., pixel segment 302-1, pixel segment 302-2, pixel segment 302-3, or pixel segment 302-4) in the substrate 314. The sub-pixel segment also includes a shallow trench isolation feature 304.

[0186] The vertical transmission gate structure 309 has a laterally extending body portion 318 and a plurality of wall segments 320 and 330 connected at the end regions of the body portion 318. The wall segments 320 and 330 extend vertically to the substrate 314 and laterally to adjacent sides (e.g., side 303-1, side 303-2, side 303-3, or side 303-4) of pixel segments (e.g., pixel segments 302-1, 302-2, 302-3, or 302-4). The plurality of wall segments 320 and 330 are disposed within portions of the pixel segments, which are isolated from adjacent pixel segments by an isolation layer (e.g., shallow trench isolation feature 304).

[0187] Figure 3D Example sub-pixel segments are similar to Figure 3B and Figure 3C The example sub-pixel segments differ in length from the wall segments. Figure 3D In this embodiment, the length of wall segment 320 is longer than the length of wall segment 330. The length of the wall segment can be adjusted for light in a specific wavelength band that the sub-pixel segment is configured to detect. For example, if the sub-pixel segment is configured to detect red light, the length of the wall segment can be within a first predetermined length range; if the sub-pixel segment is configured to detect green light, the length of the wall segment can be within a second predetermined length range; if the sub-pixel segment is configured to detect blue light, the length of the wall segment can be within a third predetermined length range; if the sub-pixel segment is configured to detect clear light, the length of the wall segment can be within a fourth predetermined length range; if the sub-pixel segment is configured to detect infrared light, the length of the wall segment can be within a fifth predetermined length range, and so on.

[0188] Figure 4AThis is a schematic top view of a portion of a pixel structure 400 according to some embodiments of the present disclosure, the pixel structure 400 comprising a plurality of pixel segments (e.g., pixel segment 402-1, pixel segment 402-2, pixel segment 402-3, pixel segment 402-4) arranged in a substrate 414. Each pixel segment has a plurality of sides (side 403-1, side 403-2, side 403-3, side 403-4), four in this embodiment. In this embodiment, each pixel segment is separated from neighboring pixel segments among the plurality of pixel segments, but at the boundaries between pixel segments and neighboring pixel segments, there is no isolation layer separating them from neighboring pixel segments.

[0189] The vertical transmission gate structure 406 includes a gate polymerization region (shown) and a gate oxide (not shown), disposed above and around a photodetector 408 in a pixel segment (e.g., pixel segment 402-1). The vertical transmission gate structure 406 has a plurality of wall segments (wall segments 406-1, 406-2, 406-3, and 406-4) extending vertically to the substrate 414 and laterally to the vicinity of the sides of the pixel segment (e.g., sides 403-1, 403-2, 403-3, and 403-4) of the pixel segment (e.g., pixel segment 402-1). In this embodiment, each wall segment extends a distance greater than half the length of the corresponding side adjacent to that wall segment. For example, wall segment 406-1 extends a distance greater than half the length of side segment 403-1.

[0190] Figure 4B It describes along Figure 4A An exemplary cross-sectional view of a sub-pixel segment in pixel segment 402-1 with cut line C-C'. In this embodiment, the sub-pixel segment includes a vertical transmission gate structure 409, which includes a gate aggregation region 410 and a gate oxide 412 for providing a vertical transmission gate above and around a photodetector 408 in a pixel segment (e.g., pixel segment 402-1, 402-2, 402-3, or 402-4) in substrate 414.

[0191] The vertical transmission gate structure 409 has a laterally extending body portion 418 and a plurality of wall segments 420 connected to the end regions of the body portion 418. The wall segments 420 extend vertically to the substrate 414 and laterally to adjacent sides (e.g., side 403-1, side 403-2, side 403-3, or side 403-4) of pixel segments (e.g., pixel segment 402-1, pixel segment 402-2, pixel segment 402-3, or pixel segment 402-4). The plurality of wall segments 420 are disposed within a portion of the pixel segments and are not isolated from adjacent pixel segments by an isolation layer at the boundary between the pixel segments and adjacent pixel segments.

[0192] Figure 4C It describes along Figure 4A A schematic cross-sectional view of another example sub-pixel segment in pixel segment 402-1 with cut line C-C'. In this embodiment, the sub-pixel segment includes a vertical transmission gate structure 409, which includes a gate polymerization region 410 and a gate oxide 412 for use as a vertical transmission gate disposed above and around a photodetector 408 in a pixel segment (e.g., pixel segment 402-1, pixel segment 402-2, pixel segment 402-3, or pixel segment 402-4) in the substrate 414.

[0193] The vertical transmission gate structure 409 has a laterally extending body portion 418 and a plurality of wall segments 420 and 430 connected to the end regions of the body portion 418. The wall segments 420 and 430 extend vertically to the substrate 414 and laterally to adjacent sides (e.g., side 403-1, side 403-2, side 403-3, or side 403-4) of pixel segments (e.g., pixel segments 402-1, 402-2, 402-3, or 402-4). The plurality of wall segments 420 and 430 are disposed within a portion of the pixel segments and are not isolated from adjacent pixel segments by an isolation layer at the boundary between the pixel segments and adjacent pixel segments.

[0194] Figure 4C Example sub-pixel segments are similar to Figure 4B The example sub-pixel segments differ in length from the wall segments. Figure 4B In this embodiment, the length of wall segment 420 is longer than the length of wall segment 430. The length of the wall segment can be adjusted for light in a specific wavelength band that the sub-pixel segment is configured to detect. For example, if the sub-pixel segment is configured to detect red light, the length of the wall segment can be within a first predetermined length range; if the sub-pixel segment is configured to detect green light, the length of the wall segment can be within a second predetermined length range; if the sub-pixel segment is configured to detect blue light, the length of the wall segment can be within a third predetermined length range; if the sub-pixel segment is configured to detect clear light, the length of the wall segment can be within a fourth predetermined length range; if the sub-pixel segment is configured to detect infrared light, the length of the wall segment can be within a fifth predetermined length range, and so on.

[0195] Figure 5AThis is a schematic top view of a portion of a pixel structure 500 according to some embodiments of the present disclosure, the pixel structure 500 comprising a plurality of pixel segments (e.g., pixel segment 502-1, pixel segment 502-2, pixel segment 502-3, pixel segment 502-4) arranged in a substrate. Each pixel segment has a plurality of sides (side 503-1, side 503-2, side 503-3, side 503-4), four in this embodiment. In this embodiment, each pixel segment is isolated from neighboring pixel segments among the plurality of pixel segments, wherein some pixel segments are isolated from first neighboring pixel segments by an isolation layer at the boundary between the pixel segment and a first neighboring pixel segment, and are not isolated from second neighboring pixel segments by an isolation layer at the boundary between the pixel segment and a second neighboring pixel segment.

[0196] The vertical transmission gate structure 506 includes a gate polymerization region (shown) and a gate oxide (not shown), disposed above and around a photodetector 508 in a pixel segment (e.g., pixel segment 502-1). The vertical transmission gate structure 506 has a plurality of wall segments (wall segment 506-1, wall segment 506-2, wall segment 506-3, wall segment 506-4) that extend vertically to the substrate and laterally to the vicinity of the sides (sides 503-1, 503-2, 503-3, 503-4) of the pixel segment (e.g., pixel segment 502-1). In this embodiment, each wall segment extends a distance greater than half the length of the corresponding side adjacent to that wall segment. For example, wall segment 506-1 extends a distance greater than half the length of side segment 503-1.

[0197] Figure 5B It describes along Figure 5A A schematic cross-sectional view of an example sub-pixel segment in pixel segment 502-1 of the cut line D-D'. In this embodiment, the sub-pixel segment includes a vertical transmission gate structure 509, which includes a gate polymerization region 510 and a gate oxide 512 for use as a vertical transmission gate disposed above and around a photodetector 508 in a pixel segment (e.g., pixel segment 502-1, pixel segment 502-2, pixel segment 502-3, or pixel segment 502-4) in the substrate 514.

[0198] The vertical transmission gate structure 509 has a laterally extending body portion 518 and a plurality of wall segments 520 connected at end regions of the body portion 518. The body portion 518 extends vertically to a substrate 514 and laterally extends to the sides (e.g., side 503-1, side 503-2, side 503-3, or side 503-4) of adjacent pixel segments (e.g., pixel segment 502-1, pixel segment 502-2, pixel segment 502-3, or pixel segment 502-4). The plurality of wall segments 520 are disposed on a portion of the pixel segments, wherein a first wall segment of the plurality of wall segments 520 is isolated from the first adjacent pixel segment by a bit-separation layer (e.g., shallow trench isolation feature 504) at the boundary between the pixel segment and the first adjacent pixel segment, and a second wall segment of the plurality of wall segments 520 is not isolated from the second adjacent pixel segment by a bit-separation layer at the boundary between the pixel segment and the second adjacent pixel segment.

[0199] Figure 5C It describes along Figure 5A A schematic cross-sectional view of another example sub-pixel segment in pixel segment 502-1 of the cut line D-D'. In this embodiment, the sub-pixel segment includes a vertical transmission gate structure 509, which includes a gate polymerization region 510 and a gate oxide 512 for use as a vertical transmission gate disposed above and around a photodetector 508 in a pixel segment (e.g., pixel segment 502-1, pixel segment 502-2, pixel segment 502-3, or pixel segment 502-4) in the substrate 514.

[0200] The vertical transmission gate structure 509 has a laterally extending body portion 518 and a plurality of wall segments 520 and 530 connected at the end regions of the body portion 518. The wall segments 520 and 530 extend vertically to the substrate 514 and laterally to the adjacent side (e.g., side 503-1, side 503-2, side 503-3, or side 503-4) of the pixel segments (e.g., pixel segments 502-1, 502-2, 502-3, or 502-4). Multiple wall segments 520, 530 are disposed in a portion of a pixel segment, wherein the first wall segment 520 is isolated from the first neighboring pixel segment by a bit-separation layer (e.g., shallow trench isolation feature 504) at the boundary between the pixel segment and the first neighboring pixel segment, while the second wall segment 530 is not isolated from the second neighboring pixel segment by a bit-separation layer at the boundary between the pixel segment and the second neighboring pixel segment.

[0201] Figure 5C Example sub-pixel segments are similar to Figure 5B The example sub-pixel segments differ in length from the wall segments. Figure 5BIn this embodiment, the length of wall segment 420 is longer than the length of wall segment 430. The length of the wall segment can be adjusted for light in a specific wavelength band that the sub-pixel segment is configured to detect. For example, if the sub-pixel segment is configured to detect red light, the length of the wall segment can be within a first predetermined length range; if the sub-pixel segment is configured to detect green light, the length of the wall segment can be within a second predetermined length range; if the sub-pixel segment is configured to detect blue light, the length of the wall segment can be within a third predetermined length range; if the sub-pixel segment is configured to detect clear light, the length of the wall segment can be within a fourth predetermined length range; if the sub-pixel segment is configured to detect infrared light, the length of the wall segment can be within a fifth predetermined length range, and so on.

[0202] Figure 5D It describes along Figure 5A A schematic cross-sectional view of another example sub-pixel segment in pixel segment 502-1 with cut line D-D'. In this embodiment, the sub-pixel segment includes a vertical transmission gate structure 509, which includes a gate polymerization region 510 and a gate oxide 512 for use as a vertical transmission gate disposed above and around a photodetector 508 in a pixel segment (e.g., pixel segment 502-1, pixel segment 502-2, pixel segment 502-3, or pixel segment 502-4) in the substrate 514.

[0203] The vertical transmission gate structure 509 has a laterally extending body portion 518 and a plurality of wall segments 520 and 530 connected to the end regions of the body portion 518. The plurality of wall segments 520 and 530 extend vertically to the substrate 514 and laterally to the adjacent sides of the side portions (e.g., side portions 503-1, side portions 503-2, side portions 503-3, or side portions 503-4) of the pixel segments (e.g., pixel segments 502-1, 502-2, 502-3, or 502-4). Multiple wall segments 520 and 530 are disposed in a portion of a pixel segment, wherein the first wall segment 520 is not isolated from the first neighboring pixel segment by a bit isolation layer at the boundary between the pixel segment and the first neighboring pixel segment, and the second wall segment 530 is isolated from the second neighboring pixel segment by a bit isolation layer at the boundary between the pixel segment and the second neighboring pixel segment (e.g., shallow trench isolation feature 504).

[0204] Figure 5D Example sub-pixel segments are similar to Figure 5B The example sub-pixel segments differ in length from the wall segments. Figure 5BIn this embodiment, the length of wall segment 420 is longer than the length of wall segment 430. The length of the wall segment can be adjusted for light in a specific wavelength band that the sub-pixel segment is configured to detect. For example, if the sub-pixel segment is configured to detect red light, the length of the wall segment can be within a first predetermined length range; if the sub-pixel segment is configured to detect green light, the length of the wall segment can be within a second predetermined length range; if the sub-pixel segment is configured to detect blue light, the length of the wall segment can be within a third predetermined length range; if the sub-pixel segment is configured to detect clear light, the length of the wall segment can be within a fourth predetermined length range; if the sub-pixel segment is configured to detect infrared light, the length of the wall segment can be within a fifth predetermined length range, and so on.

[0205] Figures 6A to 6I This is a schematic top view of a portion of a pixel structure according to some embodiments of the present disclosure, the pixel structure comprising a plurality of pixel segments (e.g., pixel segment 602-1, pixel segment 602-2, pixel segment 602-3, pixel segment 602-4) arranged in a substrate. Figure 6A , Figure 6D and Figure 6G In this embodiment, each pixel segment is isolated from neighboring pixel segments in a plurality of pixel segments at the boundary between the pixel segment and neighboring pixel segments by an isolation layer (e.g., shallow trench isolation feature 604). These pixel segments are completely isolated from neighboring pixel segments of the plurality of pixel segments by the isolation layer.

[0206] exist Figure 6B , Figure 6E and Figure 6H In this embodiment, the isolation layer at the boundary between pixel segments and neighboring pixel segments does not isolate the pixel segments. These pixel segments are not isolated from their neighboring pixel segments.

[0207] exist Figure 6C , Figure 6F and Figure 6I In this embodiment, each pixel segment is separated from neighboring pixel segments of a plurality of pixel segments. Some of these pixel segments are isolated from the first neighboring pixel segment by an isolation layer at the boundary between the pixel segment and the first neighboring pixel segment, and are not isolated from the second neighboring pixel segment by an isolation layer (e.g., shallow trench isolation feature 604) at the boundary between the pixel segment and the second neighboring pixel segment. These pixel segments are partially isolated from the neighboring pixel segments of the plurality of pixel segments by the isolation layer.

[0208] exist Figures 2A to 2B , Figures 3A to 3D , Figures 4A to 4C and Figures 5A to 5DIn some embodiments, the semiconductor structure includes multiple pixel segments. In these embodiments, each pixel segment includes a vertical transmission gate structure comprising multiple vertically extending wall segments, and each vertical transmission gate structure forms a closed shape when viewed from a top view around its pixel segment. In these embodiments, each pixel segment includes four sides and four corners, and the vertical transmission gate structure with multiple vertically extending wall segments includes four wall segments extending laterally along the four sides of the pixel segment, each of the four wall segments extending substantially along one side of the pixel segment and connected to two of the four wall segments adjacent to each of the four corners.

[0209] exist Figure 6A , Figure 6B and Figure 6C In some embodiments, the semiconductor structure includes multiple pixel segments. In these embodiments, each pixel segment includes a vertical transmission gate structure 606, which includes multiple vertically extending wall segments (e.g., wall segments 606-1, 606-2, 606-3, and 606-4), and each vertical transmission gate structure 606 forms an open shape in a top view around its pixel segment, wherein one corner of the pixel segment is open and not surrounded by the vertical transmission gate structure 606. One corner of the vertical transmission gate structure 606 is open. In these embodiments, each pixel segment includes four sides and four corners, and the vertical transmission gate structure 606 having its multiple vertically extending wall segments includes four wall segments extending laterally along the four sides of the pixel segment, each of the four wall segments extending substantially along one side of the pixel segment and connected to two of the four wall segments adjacent to three of the four corners. In this embodiment, wall segments 606-1 and 606-2 are connected at the first corner, wall segments 606-3 and 606-4 are connected at the second corner, and wall segments 606-4 and 606-1 are connected at the third corner. Wall segments 606-2 and 606-3 adjacent to the fourth corner are not connected.

[0210] exist Figure 6D , Figure 6E and Figure 6FIn some embodiments, the semiconductor structure includes multiple pixel segments. In these embodiments, each pixel segment includes a vertical transmission gate structure 606, which includes multiple vertically extending wall segments (e.g., wall segment 606-1, wall segment 606-2, wall segment 606-3, wall segment 606-4), and each vertical transmission gate structure 606 forms an open shape when viewed from a top view around its pixel segment, wherein one corner and approximately half of the side of the pixel segment are open and not surrounded by the vertical transmission gate structure 606. The vertical transmission gate structure 606 is open at one corner and approximately half of the pixel segment. In these embodiments, each pixel segment includes four sides and four corners. The vertical transmission gate structure 606, having multiple vertically extending wall segments, includes four wall segments extending laterally along the four sides of the pixel segment. Three of the four wall segments extend substantially the entire length of one side of the pixel segment, one of the four wall segments extends substantially about half the length of one side of the pixel segment, and two of the four wall segments are adjacent to three of the four corners. In this embodiment, wall segments 606-1 and 606-4 extend substantially the entire length of one side of the pixel segment, and wall segments 606-2 and 606-3 extend substantially about half the length of one side of the pixel segment. Wall segments 606-1 and 606-2 are connected at the first corner, wall segments 606-3 and 606-4 are connected at the second corner, and wall segments 606-4 and 606-1 are connected at the third corner. Wall segments 606-2 and 606-3, which are adjacent to the fourth corner, are not connected.

[0211] exist Figure 6G , Figure 6H and Figure 6IIn some embodiments, the semiconductor structure includes multiple pixel segments. In these embodiments, each pixel segment includes a vertical transmission gate structure 606, which includes multiple vertically extending wall segments (e.g., wall segment 606-1, wall segment 606-4), and each vertical transmission gate structure 606 forms an open shape in a top view around its pixel segment, wherein two sides of the pixel segment are surrounded by the vertical transmission gate structure 606. The vertical transmission gate structure 606 is open on both sides of the pixel segment. In these embodiments, each pixel segment includes four sides and four corners, and the vertical transmission gate structure 606 with multiple vertically extending wall segments includes two wall segments extending along two of the four sides of the pixel segment, these two wall segments extending substantially along one side of the pixel segment for its entire length, and adjacently connected to one of the two corners. In this embodiment, wall segments 606-1 and 606-4 extend approximately along one side of the pixel segment, and wall segments 606-1 and 606-4 are connected at one corner. The wall segments adjacent to the other three corners are not connected.

[0212] Figure 7A This is a comparison graph of the quantum efficiency of an imaging element in converting incident photons of light into electrons with the wavelength of light (in nanometers). The graph shows that the quantum efficiency (QE) of blue light in the first wavelength band (e.g., about 450 nm) is peaked in the second wavelength band (e.g., about 625 nm) in the second wavelength band (e.g., about 625 nm) in the third ...).

[0213] Figures 7B to 7F These are schematic cross-sectional views illustrating example pixel segments. These embodiments provide embodiment configurations of vertical transmission gate wall depth in sub-pixel segments to maximize electron capture of imaging elements configured to sense light in a specific optical band.

[0214] exist Figure 7B In one embodiment, the pixel segment is configured for sensing light in the near-infrared band. The vertical transmission gate structure 710 includes a wall 712 having a wall depth 714 of about 6.0 μm to about 20 μm to optimize the vertical transmission gate structure for collecting electrons from a photoelectric tester configured to sense light in the near-infrared band.

[0215] exist Figure 7C In one embodiment, the pixel segment is configured for sensing light in the transparent band. The vertical transmission gate structure 720 includes a wall 722 having a wall depth 724 of about 3.0 μm to about 10 μm to optimize the vertical transmission gate structure for collecting electrons from a photodetector configured to sense light in a clear wavelength band.

[0216] exist Figure 7D In one embodiment, the pixel segment is configured for sensing light in the red band. The vertical transmission gate structure 730 includes a wall 732 having a wall depth 734 of about 3.0 μm to about 6.0 μm to optimize the vertical transmission gate structure for collecting electrons from a photodetector configured to sense light in the red band.

[0217] exist Figure 7E In one embodiment, the pixel segment is configured for sensing light in the green band. The vertical transmission gate structure 740 includes a wall 742 having a wall depth 744 of about 1.0 μm to about 3.0 μm to optimize the vertical transmission gate structure for collecting electrons from a photodetector configured to sense light in the green band.

[0218] exist Figure 7F In one embodiment, the pixel segment is configured for sensing light in the blue band. The vertical transmission gate structure 750 includes a wall 752 having a wall depth 754 of about 0.5 μm to about 1.5 μm to optimize the vertical transmission gate structure for collecting electrons from a photodetector configured to sense light in the blue band.

[0219] Figure 8A This is a schematic diagram illustrating an embodiment of the layout of multiple pixel segments in a semiconductor imaging element. In this embodiment, a first region 802 is configured to sense red light, a second region 804 is configured to sense green light, a third region 806 is configured to sense clear light, a fourth region 808 is configured to sense gray light, and a fifth region 810 is configured to sense clear light.

[0220] Figure 8B This is a schematic cross-sectional view illustrating an example pixel segment. In this embodiment, a vertical transmission gate structure 820 is provided, which can collect electrons from green pixel segment 822, red pixel segment 824, and transparent pixel segment 826. The vertical transmission gate structure 820 includes a body portion 828 and a plurality of vertically extending wall segments (wall segments 830, 832, 834, and 836). Wall segments 830 and 832 can sense electrons in green pixel segment 822, wall segments 832 and 834 can sense electrons in red pixel segment 824, and wall segments 834 and 836 can sense electrons in transparent pixel segment 826. In this embodiment, the depth of all wall segments 830, 832, 834, and 836 is 6 μm. The wall segment with this depth can be optimized for the red pixel segment 824 and the transparent pixel segment 826, but cannot be optimized for the green pixel segment 822.

[0221] Figure 8CThis is a schematic cross-sectional view illustrating an example pixel segment. In this embodiment, a vertical transmission gate structure 840 is provided that can collect electrons from a green pixel segment 842, a red pixel segment 844, and a transparent pixel segment 846. In this embodiment, the vertical transmission gate structure spans four pixels, with each of the green pixel segment 842 and the red pixel segment 844 comprising one pixel, and the transparent pixel segment 846 comprising two pixels. The vertical transmission gate structure 840 includes a body portion 848 and a plurality of vertically extending wall segments (wall segments 850, 852, 854, and 856). Wall segments 850 and 852 can sense electrons in the green pixel segment 842, wall segments 852 and 854 can sense electrons in the red pixel segment 844, and wall segments 854 and 856 can sense electrons in the transparent pixel segment 846. In this embodiment, all wall segments 850, 852, 854, and 856 have different depths. In some implementations, the depth of wall segment 850 is approximately 1 μm, the depth of wall segment 852 is approximately 3 μm, the depth of wall segment 854 is approximately 6 μm, and the depth of wall segment 856 is approximately 6 μm. These wall segments with these depths can be optimized for green pixel segment 842 (optimal depth approximately 1 μm to approximately 3 μm), red pixel segment 844 (optimal depth approximately 3 μm to approximately 6 μm), and transparent pixel segment 846 (optimal depth approximately 3 μm to approximately 10 μm).

[0222] Figure 9 This is a flowchart of an embodiment method 900 for manufacturing a semiconductor device having a vertical transmission gate, according to some embodiments. For illustrative purposes, reference will be made to... Figures 10A to 10H describe Figure 9 The operation shown in the figure, Figures 10A to 10H Cross-sectional views of a semiconductor device at different stages of its manufacturing process, according to some embodiments, are shown. Operations may be performed in different sequences or not, depending on the specific application. It should be noted that method 900 may not produce a complete semiconductor device. Therefore, it is understood that additional processes may be provided before, during, and after the method, and some other processes may only be briefly described herein. In some figures, certain reference numerals for the elements or features illustrated therein may be omitted to avoid obscuring other elements or features; this is for convenience in depicting the figures.

[0223] Method 900 is merely an embodiment and is not intended to limit the scope of this disclosure beyond the express recitation of the claims. Additional steps may be provided before, during, and after embodiment method 900, and some of these steps may be moved, replaced, or omitted for additional embodiments of embodiment method 900. Additional features may be added to the semiconductor element depicted in the drawings, and in other embodiments of the semiconductor element, certain features described below may be replaced, modified, or eliminated.

[0224] It is understood that parts of a semiconductor element can be manufactured using typical semiconductor technology processes; therefore, only some processes are briefly described herein. Furthermore, the exemplary semiconductor element may include various other elements and features, such as other types of elements, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic elements, but simplifications have been made for better understanding of the concepts disclosed herein. In some embodiments, the exemplary element includes multiple semiconductor elements (e.g., transistors), including P-channel field-effect transistors (PFETs), N-channel field-effect transistors (NFETs), etc., which may be interconnected. Additionally, it should be noted that the operation of method 900, including any descriptions given with reference to the accompanying drawings, is exemplary only and is not intended to limit anything beyond the specific descriptions in the following claims.

[0225] In block 910, method 900 includes providing a substrate. (See reference...) Figure 10A In one embodiment of block 910, a substrate 1002 is provided. The substrate 1002 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator substrate, a semiconductor wafer, etc., and may be doped (e.g., having p-type or n-type dopants) or undoped. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 1002 may comprise silicon. In various embodiments, the substrate 1002 is a planar surface having a uniform thickness.

[0226] In block 920, method 900 includes optionally forming a pixel shallow trench isolation region in the substrate, surrounding a pixel in the substrate with a pixel sensor region. (See reference...) Figure 10B In one embodiment of block 920, a pixel shallow trench isolation region 1004 is formed in the substrate 1002 surrounding the pixel sensor region 1006 of the substrate 1002. Specific methods for forming the pixel shallow trench isolation region 1004 are beyond the scope of this disclosure. However, it should be understood that any method may be employed. In some embodiments, the pixel shallow trench isolation region 1004 is formed as a dielectric region embedded in the substrate 1002.

[0227] In block 930, method 900 includes forming a vertical trench in the pixel sensor region of the substrate. The vertical trench is formed as part of forming a switching transistor in the pixel sensor region. The switching transistor is formed to connect a photodetector (e.g., a photodiode) to a charge storage node in the pixel. The vertical trench extends laterally along multiple sides of the pixel segment surrounding the pixel sensor region in the substrate (e.g., sides 203-1, 203-2, 203-3 and 203-4 of pixel segment 203; sides 303-1, 303-2, 303-3 and 303-4 of pixel segment 302-1; sides 403-1, 403-2, 403-3 and 403-4 of pixel segment 402-1; sides 503-1, 503-2, 503-3 and 503-4 of pixel segment 502-1). In various embodiments, the vertical trench extends vertically to a predetermined depth, which is determined based on the light wavelength to be sensed by a photodetector formed in the pixel sensing area (e.g., wall depth 714, wall depth 724, wall depth 734, wall depth 744, wall depth 754). In various embodiments, forming the vertical trench involves executing blocks 932 and 934.

[0228] In block 932, method 900 includes depositing a layer of photoresist on a substrate and patterning the photoresist using lithography to form openings defining the locations of vertical trenches in the substrate. (See reference...) Figure 10C In one embodiment of block 932, a photoresist 1008 is deposited on a substrate 1002 and the photoresist 1008 is patterned to form an opening 1010 that defines the location of a vertical trench subsequently formed in the substrate 1002.

[0229] In block 934, method 900 includes removing exposed substrate below the opening to form a vertical trench. In various embodiments, a dry etching technique can be used to remove the exposed substrate and form the vertical trench. (See reference...) Figure 10D In one embodiment of block 934, the exposed substrate below opening 1010 has been removed to form vertical trench 1012.

[0230] In block 940, method 900 includes forming a gate oxide layer above the substrate and in a vertical trench. (See reference...) Figure 10EIn one embodiment of block 940, a gate oxide layer 1014 is formed on substrate 1002 and in vertical trench 1012. In various embodiments, the gate oxide layer 1014 comprises a high-κ dielectric. In various embodiments, the high-κ dielectric is deposited on substrate 1002 to form vertical trench 1012 and isolates subsequently formed vertical transmission gates from substrate 1002. In various embodiments, the high-κ dielectric comprises one or more materials having a dielectric constant κ greater than that of silicon dioxide (i.e., a dielectric constant κ greater than 3.9). In various embodiments, the high-κ dielectric may comprise HfO2, AlO3, and Ta2O5.

[0231] In block 950, method 900 includes forming a gate aggregation region for a vertical transmission gate transistor above the gate oxide layer on the substrate and in a vertical trench. In various embodiments, the gate aggregation region has a plurality of wall segments that extend vertically to the substrate and laterally to a side adjacent to a pixel segment (e.g., wall segments 306-1, 306-2, 306-3, and 306-4 of vertical transmission gate structure 306; wall segments 406-1, 406-2, 406-3, and 406-4 of vertical transmission gate structure 406; wall segments 506-1, 506-2, 506-3, and 506-4 of vertical transmission gate structure 506; wall segments 606-1, 606-2, 606-3, and 606-4 of vertical transmission gate structure 606). In various embodiments, the gate aggregation region forming the vertical transmission gate transistor involves execution blocks 952, 954, 956, 958, and 959. In this embodiment, each wall segment extends a distance greater than half the length of the adjacent corresponding side of that wall segment.

[0232] In block 952, method 900 includes depositing a gate polymer layer on a substrate, including filling vertical trenches. In various embodiments, the gate polymer layer comprises a conductive material. In various embodiments, the gate polymer layer comprises polysilicon, but other gate materials, such as metals, are also feasible. Reference Figure 10F In one embodiment of block 952, a gate polymer layer 1016 is deposited on a substrate 1002, and a vertical trench 1012 is filled with the gate polymer layer 1016.

[0233] In block 954, method 900 includes depositing a photoresist layer on the gate polymerization layer on the substrate, and in block 956, method 900 includes patterning the photoresist using lithography to define the location of the gate polymerization region for the vertical transmission gate on the substrate. (See again) Figure 10FIn one embodiment of blocks 954 and 956, photoresist 1018 has been deposited on gate polymerization layer 1016 on a substrate, and photoresist 1018 has been patterned to define the location of gate polymerization regions for vertical transmission gates on the substrate.

[0234] In block 958, method 900 includes patterning a gate aggregation layer based on patterned photoresist to form a gate aggregation region for a vertical transmission gate. (See reference...) Figure 10G In one embodiment of block 958, the gate aggregation layer 1016 is patterned based on photoresist 1018 to form the gate aggregation region 1020 of the vertical transmission gate.

[0235] In block 959, method 900 involves removing the patterned photoresist layer. (See reference...) Figure 10H In one embodiment of block 958, the patterned photoresist layer has been removed, leaving the gate aggregation region 1020 of the vertical transmission gate in the substrate 1002.

[0236] In block 960, method 900 includes performing further manufacturing operations to complete the image sensor element.

[0237] In some aspects, the technology described herein relates to a semiconductor structure comprising: a plurality of pixel segments arranged in a substrate, each pixel segment having a plurality of sides; and a first pixel segment of the plurality of pixel segments comprising: a photodetector; and a vertical transmission gate structure disposed above the photodetector, the vertical transmission gate structure having a laterally extending body portion and a plurality of wall segments connected to different end regions of the body portion and extending vertically to the substrate, wherein at least one of the plurality of wall segments, a first wall segment, extends laterally to a first distance adjacent to a first side of the first pixel segment, and a second wall segment of the plurality of wall segments extends laterally to a second distance adjacent to a second side of the first pixel segment, wherein the first distance is greater than half the length of the first side and the second distance is greater than half the length of the second side.

[0238] In some respects, the technology described herein relates to a semiconductor structure in which a first pixel segment and neighboring pixel segments of a plurality of pixel segments are separated at the boundary between the first pixel segment and the neighboring pixel segments by an isolation layer, and a plurality of wall segments are disposed in portions of the pixel segments separated by the isolation layer.

[0239] In some respects, the techniques described herein relate to semiconductor structures in which a first pixel segment is separated from neighboring pixel segments of a plurality of pixel segments, and there is no isolation layer at the boundary between the first pixel segment and the neighboring pixel segments.

[0240] In some respects, the technology described herein relates to a semiconductor structure in which a first pixel segment is separated from a first adjacent pixel segment and no isolation layer is provided at the boundary between the first pixel segment and the first adjacent pixel segment, wherein a first pixel segment is separated from a second adjacent pixel segment and an isolation layer is provided at the boundary between the first pixel segment and the second adjacent pixel segment, wherein a wall segment of a plurality of wall segments is disposed in a portion of a pixel segment isolated from the second adjacent pixel segment.

[0241] In some respects, the technology described herein relates to a semiconductor structure in which: a pixel segment comprises four sides and four corners; and a plurality of vertically extending wall segments comprise four wall segments extending laterally along the four sides of the pixel segment.

[0242] In some respects, the technology described herein relates to a semiconductor structure in which each of the four corners is adjacent to the other two wall segments are connected.

[0243] In some respects, the technology described herein relates to a semiconductor structure in which three of the four corners are adjacent, two of the four wall segments are connected, and there is no connection between the fourth corner and any of the four wall segments.

[0244] In some respects, the technology described herein relates to a semiconductor structure comprising: a pixel segment in a substrate; a photodetector in the pixel segment; and a vertical transmission gate structure disposed above the photodetector, the vertical transmission gate structure having a laterally extending body portion and a plurality of wall segments connected to end regions of the body portion, the wall segments extending vertically to a predetermined depth in the substrate; wherein the predetermined depth is configured based on a wavelength of captured light that the photodetector is configured to detect.

[0245] In some respects, the techniques described herein relate to semiconductor structures in the near-infrared band with a depth of approximately 6.0 μm to 20 μm.

[0246] In some respects, the techniques described herein relate to semiconductor structures in which the wavelengths are clear and the depth is approximately 3.0 μm to 10 μm.

[0247] In some respects, the techniques described herein relate to semiconductor structures in the red band with a depth of approximately 3.0 μm to 6.0 μm.

[0248] In some respects, the techniques described herein relate to semiconductor structures in which the wavelength is green and the depth is approximately 1.0 μm to 3.0 μm.

[0249] In some respects, the techniques described herein relate to semiconductor structures in which the wavelength is blue and the depth is approximately 0.5 μm to 1.5 μm.

[0250] In some respects, the technology described herein relates to a semiconductor structure in which: a vertical transmission gate structure includes two or more wall segments below a body portion, the two or more wall segments extending vertically to a predetermined depth in a substrate; the two or more wall segments have different depths; and the different depths of two adjacent wall segments are configured for a specific wavelength band.

[0251] In some aspects, the technology described herein relates to a semiconductor structure in which: a vertical transmission gate structure comprises four wall segments below a body portion and is configured for three different wavelength bands; and the wall segment depths of a first set of two adjacent wall segments are configured for a first wavelength band, the wall segment depths of a second set of two adjacent wall segments are configured for a second wavelength band, and the wall segment depths of a third set of two adjacent wall segments are configured for a third wavelength band. The four wall segments extend around a first pixel segment.

[0252] In some aspects, the technology described herein relates to a method comprising: providing a substrate; forming a vertical trench in a pixel sensor region of the substrate, wherein the trench extends laterally along a polygon surrounding the pixel sensor region; forming a gate oxide layer in the vertical trench; and forming a gate aggregation region for a vertical transmission gate transistor on the gate oxide layer, wherein the gate aggregation region has a plurality of wall segments connected at different end regions extending vertically to a body portion of the substrate, wherein at least a first wall segment of the plurality of wall segments extends laterally to a first distance adjacent to a first side of defining the pixel sensor region, and a second wall segment of the plurality of wall segments extends laterally to a second distance adjacent to a second side of defining the pixel sensor region, wherein the first distance is greater than half the length of the first side, and the second distance is greater than half the length of the second side.

[0253] In some respects, the techniques described herein relate to a method in which forming a gate aggregation region includes forming four wall segments extending along four sides that surround a pixel sensor region.

[0254] In some respects, the technology described herein relates to a method in which: each of the four wall segments extends substantially along the entire length of the side surrounding the pixel sensor region; and is adjacent to each of the four corners of the pixel sensor region, and two of the four wall segments are connected.

[0255] In some respects, the technology described herein relates to a method in which: each of the four wall segments extends substantially along the entire length of the side surrounding the pixel sensor region; two of the four wall segments are connected and adjacent to three of the four corners of the pixel sensor region; and no wall segments are connected and adjacent to a fourth of the four corners of the pixel sensor region.

[0256] In some respects, the technology described herein relates to a method in which: a plurality of wall segments include two wall segments extending laterally along two of the four sides of a pixel sensor region; and the two wall segments are adjacent to and connected to the corners of the pixel sensor region.

[0257] While at least one exemplary entity has been presented in the foregoing detailed description of this disclosure, it should be understood that numerous variations exist. It should also be understood that the exemplary entities or exemplary models are merely embodiments and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing exemplary embodiments of this disclosure. It will be self-evident that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A semiconductor structure, characterized in that, Include: Multiple pixel segments are arranged in a substrate, each of the multiple pixel segments having multiple sides; and A first pixel segment of the plurality of pixel segments includes: A light detector; and A vertical transmission gate structure is disposed above the photodetector. The vertical transmission gate structure has a laterally extending body portion and a plurality of wall segments extending vertically into the substrate and connected to different end regions of the body portion. At least a first wall segment of the plurality of wall segments extends laterally by a first distance adjacent to a first side of the first pixel segment, and a second wall segment of the plurality of wall segments extends laterally by a second distance adjacent to a second side of the first pixel segment. The first distance is greater than half the length of the first side, and the second distance is greater than half the length of the second side.

2. The semiconductor structure as described in claim 1, characterized in that, The first pixel segment and its neighboring pixel segments among the plurality of pixel segments are separated by an isolation layer at the boundary between the first pixel segment and the plurality of neighboring pixel segments, and the plurality of wall segments are disposed in a portion of the first pixel segment separated by the isolation layer.

3. The semiconductor structure as described in claim 1, characterized in that, The first pixel segment is separated from the neighboring pixel segments among the plurality of pixel segments, and there is no isolation layer at the boundary between the first pixel segment and the plurality of neighboring pixel segments.

4. The semiconductor structure as described in claim 1, characterized in that, The first pixel segment is separated from a first neighboring pixel segment, and there is no isolation layer at a boundary between the first pixel segment and the first neighboring pixel segment, wherein the first pixel segment and a second neighboring pixel segment are separated by an isolation layer at a boundary between the first pixel segment and the second neighboring pixel segment, wherein one of the plurality of wall segments is disposed in a portion of the first pixel segment isolated by the second neighboring pixel segment.

5. The semiconductor structure as described in claim 1, characterized in that: The first pixel segment includes four sides and four corners; and The vertically extending plurality of wall segments comprise four wall segments that extend laterally along the four sides of the first pixel segment.

6. The semiconductor structure as described in claim 5, characterized in that, Adjacent to each of the four corners, there are two wall segments connected by the four wall segments.

7. The semiconductor structure as described in claim 5, characterized in that, Three of the four corners are adjacent to each other, two of the four wall segments are connected, and the fourth of the four corners is adjacent to each other, and there is no connection between each of the four wall segments.

8. A semiconductor structure, characterized in that, Include: Multiple pixel segments are arranged in a substrate, each of the multiple pixel segments having multiple sides; and A first pixel segment of the plurality of pixel segments includes: A light detector; and A vertical transmission gate structure is disposed above the photodetector. The vertical transmission gate structure includes a body portion and two or more wall segments extending vertically into the substrate below the body portion. The two or more wall segments have different depths. A first wall segment of the two or more wall segments extends laterally by a first side of a first pixel segment by a first distance, and a second wall segment of the two or more wall segments extends laterally by a second side of a first pixel segment by a second distance. The first distance is greater than half the length of the first side, and the second distance is greater than half the length of the second side.

9. A semiconductor structure, characterized in that, Include: Multiple pixel segments are arranged in a substrate, each of the multiple pixel segments having multiple sides; and A first pixel segment of the plurality of pixel segments includes: A light detector; and A vertical transmission gate structure is disposed above the photodetector. The vertical transmission gate structure includes a main body and four wall sections below the main body. A first wall section of the four wall sections extends laterally by a first side of the first pixel section by a first distance, and a second wall section of the four wall sections extends laterally by a second side of the first pixel section by a second distance. The first distance is greater than half the length of the first side, and the second distance is greater than half the length of the second side.

10. The semiconductor structure as described in claim 9, characterized in that, The four wall segments extend around the first pixel segment.

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