Solar cells and photovoltaic modules

Abstract

The application relates to the technical field of solar cells, in particular to a solar cell and a photovoltaic module, so as to improve the bifacial rate and overall efficiency of the solar cell. The solar cell comprises a substrate, the substrate has a first surface and a second surface oppositely arranged along the thickness direction thereof, and an isolation groove is arranged on the first surface, the isolation groove separates the first surface into a first region and a second region; an emitter is arranged in the first region; a base is arranged in the second region; a first non-silicon passivation anti-reflection layer is arranged in the first region, the second region and the isolation groove; a first electrode is arranged in the first region and electrically connected with the emitter; a second electrode is arranged in the second region and electrically connected with the base; wherein, the area ratio of the first region is less than or equal to 25% and the area ratio of the second region is less than or equal to 15% based on the total area of the first surface being 100%.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a solar cell and a photovoltaic module. Background Technology

[0002] TBC (Total Back Contact Battery) is a battery structure that combines TOPCon (Tunnel Oxide Passivated Contact) technology and IBC (Interdigitated Back Contact) technology, and its photoelectric conversion efficiency can reach more than 27%.

[0003] In order to achieve better passivation performance, the passivation contact structure of the mainstream TBC battery generally includes a doped polycrystalline silicon layer. Since the refractive index of the doped polycrystalline silicon layer is close to or even higher than that of the substrate, it is difficult for reflection or total reflection to occur at their interface, resulting in parasitic absorption loss, which in turn causes short-circuit current loss and limits the improvement of the bifaciality and overall efficiency of this type of battery. Utility Model Content

[0004] Based on this, some embodiments of this application provide a solar cell and a photovoltaic module to improve the bifaciality and overall efficiency of the solar cell.

[0005] In a first aspect, a solar cell is provided, comprising:

[0006] The substrate has a first surface and a second surface disposed opposite to each other along its thickness direction, and an isolation groove formed on the first surface, the isolation groove dividing the first surface into a first region and a second region.

[0007] An emitter is disposed in the first region;

[0008] The base is disposed in the second region;

[0009] A first non-silicon passivation anti-reflection layer is disposed in the first region, the second region, and the isolation trench;

[0010] A first electrode is disposed in the first region and electrically connected to the emitter.

[0011] The second electrode is disposed in the second region and is electrically connected to the base electrode;

[0012] Wherein, taking the total area of ​​the first surface as 100%, the area ratio of the first region is less than or equal to 25%, and the area ratio of the second region is less than or equal to 15%.

[0013] Optionally, the area of ​​the first region is greater than or equal to 5% and less than or equal to 25%, and the area of ​​the second region is greater than or equal to 5% and less than or equal to 15%.

[0014] Optionally, the substrate is supported by the second surface as a plane, and the height of the first surface in the first region is greater than the height of the first surface in the second region, and the height of the first surface in the second region is greater than the height of the bottom surface of the isolation groove.

[0015] Optionally, the bottom surface of the isolation groove is a plane, or the bottom surface of the isolation groove has a tower base structure or a velvet surface structure.

[0016] Optionally, the dimension L1 of the first region in the first direction satisfies: L1 is greater than or equal to 0.05*L and less than or equal to 0.25*L; the dimension L2 of the second region in the first direction satisfies: L2 is greater than or equal to 0.05*L and less than or equal to 0.15*L; and the dimension L3 of the isolation groove between adjacent emitters and bases along the first direction satisfies: L3 is greater than or equal to 0.6*L and less than or equal to 0.9*L; where L represents the distance between the outer edges of adjacent first and second regions, the first direction is parallel to the plane where the base is located, and points from the first region to the second region.

[0017] Optionally, the bottom surface of the isolation groove has a velvety texture;

[0018] L2 is greater than or equal to 0.05*L and less than or equal to 0.1*L.

[0019] Optionally, the bottom surface of the isolation groove has a velvety texture;

[0020] L3 is greater than or equal to 0.7*L and less than or equal to 0.9*L.

[0021] Optionally, the bottom surface of the isolation trench is a plane or a tower base structure;

[0022] L3 is greater than or equal to 0.7*L and less than or equal to 0.9*L.

[0023] Optionally, the bottom surface of the isolation groove is a plane or a tower base structure; the distance L between the outer edges of adjacent first and second regions is greater than or equal to 100 μm and less than or equal to 500 μm.

[0024] Optionally, the bottom surface of the isolation trench is a plane or a tower base structure; the substrate is supported by the second surface as a plane, and the solar cell satisfies at least one of the following conditions:

[0025] (1) The height difference L4 between the portion of the first surface located in the first region and the portion of the first surface located in the second region is greater than or equal to 0.5 μm and less than or equal to 3 μm;

[0026] (2) The height difference L5 between the portion of the first surface located in the second region and the bottom surface of the isolation groove is greater than or equal to 0.5 μm and less than or equal to 3 μm.

[0027] Optionally, the bottom surface of the isolation groove has a velvety structure, and the distance L between the outer edges of adjacent first and second regions is greater than or equal to 100 μm and less than or equal to 400 μm.

[0028] Optionally, the bottom surface of the isolation groove has a velvety texture; the second surface serves as a plane to support the substrate, and the solar cell satisfies at least one of the following conditions:

[0029] (1) The height difference L4 between the first surface in the first region and the first surface in the second region is greater than or equal to 0.5 μm and less than or equal to 5 μm;

[0030] (2) The height difference L5 between the height of the first surface in the second region and the bottom surface of the isolation groove is greater than or equal to 0.5 μm and less than or equal to 5 μm.

[0031] In a second aspect, a photovoltaic module is provided, comprising: a plurality of solar cells connected in series and / or in parallel;

[0032] At least one of the solar cells is a solar cell as described in the first aspect.

[0033] Compared with related technologies, the beneficial technical effects of this application are as follows:

[0034] When the area of ​​the emitter is reduced, its impact on the photoelectric conversion efficiency of the solar cell is less than its impact on the front side. As the area ratio of the first region and the area ratio of the second region decrease, the area of ​​the isolation trench increases, which can reduce the area of ​​the passivation contact structure contained in the emitter and base, thereby reducing parasitic absorption. At the same time, the first passivation antireflection layer can not only play a surface passivation role, but also improve the antireflection effect. The refractive index of the substrate is much greater than the refractive index of the first passivation antireflection layer. Therefore, the number of reflections or even total internal reflections at the interface between the substrate and the first passivation antireflection layer reaches 20 times or more, which can improve the light utilization rate. Therefore, the solar cell provided in this application embodiment can reduce metal contact recombination, reduce surface recombination as a whole, and reduce parasitic absorption, thereby improving the bifaciality and overall efficiency of the solar cell. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of another solar cell structure provided in an embodiment of this application;

[0037] Figure 3 A schematic flowchart of steps (2) to (5) of a method for preparing a solar cell provided in this application embodiment;

[0038] Figure 4 The embodiments provided in this application are based on Figure 3 A flowchart of steps (6) to (9) of the preparation method;

[0039] Figure 5 The embodiments provided in this application are based on Figure 4 A flowchart of steps (10) to (13) of the preparation method;

[0040] Figure 6 The embodiments provided in this application are based on Figure 5 A flowchart of steps (14) to (17) of the preparation method;

[0041] Figure 7 The embodiments provided in this application are based on Figure 6 A flowchart of steps (18) to (20) of the preparation method;

[0042] Figure 8 A schematic flowchart of steps (2) to (5) of another method for preparing a solar cell provided in this application embodiment;

[0043] Figure 9 Provided for the application embodiments based on Figure 8 A flowchart of steps (6) to (10) of the preparation method;

[0044] Figure 10 Provided for the application embodiments based on Figure 9 A flowchart of steps (11) to (14) of the preparation method;

[0045] Figure 11 The embodiments provided in this application are based on Figure 3 A flowchart of step (1) of the preparation method.

[0046] Reference numerals: 11, substrate; 12, emitter; 13, base; 14, first passivation antireflection layer; 15, first electrode; 16, second electrode; 11a, first surface; 11b, second surface; V, isolation trench; A, first region; B, second region; 121, first tunneling oxide layer; 122, first doped polysilicon layer; 131, second tunneling oxide layer; 132, second doped polysilicon layer; 101, first tunneling oxide film; 102. 103. First doped polycrystalline silicon thin film; 11c. Side surface; 201. Second tunneling oxide thin film; 202. Second doped polycrystalline silicon thin film; 203. Second doped dielectric thin film; 100. First protective layer; 300. Oxide protective layer; 141. First passivation layer; 142. First antireflection layer; 17. Second passivation and antireflection layer; 171. Second passivation layer; 172. Second antireflection layer; 10. Impurity; 200. Second protective layer. Detailed Implementation

[0047] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0048] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0049] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0050] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0051] In this document, unless otherwise stated, "one or more" means one or more.

[0052] In this document, terms such as "for example," "like," "example," and "exemplary" are used for descriptive purposes to indicate a connection in the content covered by different technical solutions presented earlier and later. However, they should not be construed as limitations on the preceding technical solution or as restrictions on the scope of protection of this document. In this document, unless otherwise specified, A (like B) indicates that B is a non-limiting example of A, and it can be understood that A is not limited to B.

[0053] In this article, "optionally," "optionally," and "optional" mean that something is optional, that is, it means that it is selected from either "with" or "without." If there are multiple "options" in a technical solution, unless otherwise specified, and there are no contradictions or mutual constraints, then each "option" is independent.

[0054] In this article, descriptions such as "optionally contains" and "optionally includes" indicate whether or not the component X is present. "Optional component X" indicates whether component X is present or absent, or whether or not component X is present.

[0055] In this document, the terms "first aspect," "second aspect," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly indicating the importance or quantity of the indicated technical features.

[0056] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0058] In this article, the technical features described in an open-ended manner include both closed technical solutions composed of the listed features and open technical solutions that include the listed features.

[0059] In this document, "at least one" means one or more, such as one, two, or more. "Multiple" or "several" means at least two, such as two, three, etc., and "multi-layered" means at least two layers, such as two layers, three layers, etc., unless otherwise expressly and specifically defined. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise expressly and specifically defined.

[0060] In this document, when referring to numerical intervals (i.e., numerical ranges), unless otherwise specified, the distribution of selectable values ​​within a numerical interval is considered continuous, and includes the two endpoints (i.e., the minimum and maximum values) of the numerical interval, as well as every value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed herein should be understood to include any and all subranges included therein. The "numerical value" in this numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, and other numerical interval types.

[0061] In this article, unless otherwise specified, percentage content refers to mass percentage for solid-liquid mixtures and solid-phase-solid mixtures, and volume percentage for liquid-phase-liquid mixtures.

[0062] Unless otherwise specified, all percentage concentrations mentioned in this article refer to the final concentration. The final concentration refers to the proportion of the added ingredient in the system after the addition of that ingredient.

[0063] In this article, % (w / w) and wt% both represent weight percentage, % (v / v) refers to volume percentage, and % (w / v) refers to mass-volume percentage.

[0064] In this document, temperature parameters are used. Unless otherwise specified, both isothermal processing and processing within a certain temperature range are permitted. The isothermal processing allows temperature fluctuations within the precision range controlled by the instrument.

[0065] In this document, the terms "room temperature" or "normal temperature" generally refer to 4°C to 35°C, for example, 20°C ± 5°C. In some embodiments of this document, "room temperature" or "normal temperature" refers to 10°C to 30°C. In some embodiments of this document, "room temperature" or "normal temperature" refers to 20°C to 30°C.

[0066] The fill factor (FF) used in this paper refers to the ratio of the actual maximum obtainable power (Pm or Vmp*Jmp) to the theoretical (not actually obtainable) power (Jsc*Voc). Therefore, FF can be determined by the following formula:

[0067] FF = (Vmp * Jmp) / (Jsc * Voc)

[0068] Where Jmp and Vmp represent the current density and voltage at the maximum power point (Pm), respectively, this point is obtained by changing the resistance in the circuit until J*V reaches its maximum value; Jsc and Voc represent the short-circuit current and open-circuit voltage, respectively. The fill factor is a key parameter for evaluating solar cells. Commercial solar cells typically have a fill factor of approximately 60% or higher.

[0069] The open-circuit voltage (Voc) used in this paper is the potential difference between the anode and cathode of the device under conditions of no external load connection.

[0070] The power conversion efficiency (PCE) of solar cells used in this article refers to the percentage of power converted from absorbed light into electrical energy. The PCE of a solar cell can be measured under standard test conditions (STC) based on incident light irradiance (E: W / m²). 2 ) and the surface area of ​​solar cells (Ac:m 2 Calculated by dividing by the point of maximum power (Pm). STC usually refers to the value at a temperature of 25°C and an irradiance of 1000 W / m². 2 The spectrum of air quality 1.5 (AM1.5).

[0071] The passivated contact structure on the back of TBC cells in related technologies causes significant parasitic absorption losses, which is detrimental to improving the bifaciality and overall efficiency of solar cells. The specific implementation method of this application is described below:

[0072] Firstly, some embodiments of this application provide a solar cell, such as... Figures 1-2 As shown, the solar cell includes: a substrate 11, an emitter 12, a base 13, a first passivation antireflection layer 14, a first electrode 15, and a second electrode 16. The substrate 11 has a first surface 11a and a second surface 11b disposed opposite to each other along its thickness direction, and an isolation trench V formed on the first surface 11a. The isolation trench V divides the first surface 11a into a first region A and a second region B. The emitter 12 is disposed in the first region A, the base 13 is disposed in the second region B, the first passivation antireflection layer 14 is disposed in the first region A, the second region B, and the isolation trench V, the first electrode 15 is disposed in the first region A and electrically connected to the emitter 12, and the second electrode 16 is disposed in the second region B and electrically connected to the base 13.

[0073] The first passivation antireflection layer 14 may have slots in the portions of the first region A and the second region B. The first electrode 15 and the second electrode 16 may be electrically connected to the emitter 12 and the base 13 respectively through the slots in their respective regions. Alternatively, the first electrode 15 and the second electrode 16 may be disposed on the side of the first passivation antireflection layer 14 away from the substrate 11, and the first passivation antireflection layer 14 may be burned through by a conductive paste sintering process to be electrically connected to the emitter 12 and the base 13 respectively. No specific limitation is made here.

[0074] The material of the first passivation antireflection layer 14 may include one or more of silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride.

[0075] In some embodiments, with the total area of ​​the first surface 11a being 100%, the area of ​​the first region A is less than or equal to 25%, and the area of ​​the second region B is less than or equal to 15%.

[0076] The first region A and the second region B can be considered as planes, while the bottom and / or side surfaces of the isolation groove V may not be planes but rather uneven surfaces with a certain degree of roughness.

[0077] Here, the total area of ​​the first surface 11a can be considered as the total area of ​​the first region A, the second region B, and the bottom surface of the isolation trench V located on the same plane, which is equal to the sum of the area of ​​the first region A, the area of ​​the second region B, and the orthographic projection area of ​​the bottom surface of the isolation trench V onto the plane where the base 11 is located. Accordingly, the number of isolation trenches V can be one or more. In this case, the first region A and the second region B can also be one or more. Here, the area percentage of the first region A refers to the total area percentage of all first regions A, and the area percentage of the second region B refers to the total area percentage of all second regions B.

[0078] Research has found that when the area of ​​the emitter 12 is reduced, its impact on the photoelectric conversion efficiency of the solar cell is less than its impact on the front side. As the area ratio of the first region A and the area ratio of the second region B decrease, the area of ​​the isolation trench V increases, which can reduce the area of ​​the passivation contact structure contained in the emitter 12 and the base 13, thereby reducing parasitic absorption. At the same time, the first passivation antireflection layer 14 can not only play a surface passivation role, but also improve the antireflection effect. The refractive index of the substrate 11 is much greater than the refractive index of the first passivation antireflection layer 14. Therefore, the number of reflections or even total internal reflections at the interface between the substrate 11 and the first passivation antireflection layer 14 reaches 20 times or more, which can improve the light utilization rate. Therefore, the solar cell provided in this application embodiment can reduce metal contact recombination, reduce surface recombination as a whole, and reduce parasitic absorption, thereby improving the bifaciality and overall efficiency of the solar cell.

[0079] In some embodiments, the area of ​​the first region A is greater than or equal to 5% and less than or equal to 25%, and the area of ​​the second region B is greater than or equal to 5% and less than or equal to 15%.

[0080] In some embodiments, such as Figures 1-2 As shown, the emitter 12 includes a first tunneling oxide layer 121 and a first doped polysilicon layer 122 stacked sequentially in a direction gradually moving away from the substrate 11; and / or, the base 13 includes a second tunneling oxide layer 131 and a second doped polysilicon layer 132 stacked sequentially in a direction gradually moving away from the substrate 11.

[0081] In these embodiments, the emitter 12 and base 13 have good passivation properties, which can effectively reduce surface recombination and metal contact recombination losses.

[0082] In some embodiments, the thickness of the first tunneling oxide layer 121 is 1 nm to 3 nm, and the thickness of the first doped polysilicon layer 122 is 50 nm to 200 nm.

[0083] In these embodiments, the first doped polysilicon layer 122 can minimize surface recombination and metal-to-metal contact recombination losses, and has better local passivation performance.

[0084] In some embodiments, the thickness of the second tunneling oxide layer 131 is 1 nm to 3 nm, and the thickness of the second doped polysilicon layer 132 is 30 nm to 180 nm.

[0085] In these embodiments, the second doped polysilicon layer 132 can minimize surface recombination and metal-to-metal contact recombination losses, and has better local passivation performance.

[0086] In some embodiments, the first doped polysilicon layer 122 may be a P-type doped polysilicon layer or an N-type doped polysilicon layer, and in this case, the second doped polysilicon layer 132 may be an N-type doped polysilicon layer or a P-type doped polysilicon layer.

[0087] In these embodiments, regardless of whether the first doped polycrystalline silicon layer 122 is a P-type doped polycrystalline silicon layer or an N-type doped polycrystalline silicon layer, it is possible to reduce surface recombination and metal contact recombination losses, improve local passivation performance, and take into account the overall efficiency and bifaciality of the solar cell.

[0088] In some embodiments, the bottom surface of the isolation groove V is a plane, or the bottom surface of the isolation groove V has a tower base structure or a velvet surface structure.

[0089] In these embodiments, when the bottom surface of the isolation groove V is flat, it means that the bottom surface of the isolation groove V does not have a base structure or a textured surface, and is approximately flat. When the bottom surface of the isolation groove V has a base structure or a textured surface, the bottom surface of the isolation groove V has a certain degree of roughness, which can improve the light trapping effect to a certain extent.

[0090] The velvet surface can be either a complete or incomplete velvet structure. Taking a pyramidal velvet structure as an example, a complete velvet structure means that the pyramids completely cover the surface and are arranged relatively regularly. This results in a more uniform and consistent characteristic in terms of light scattering and absorption, effectively reducing light reflection and improving light absorption efficiency. In an incomplete velvet structure, the pyramid coverage is lower and the distribution is uneven, leading to relatively weaker light scattering and absorption, and potentially slightly higher reflectivity.

[0091] In some implementations, specific optical performance requirements can be achieved by adjusting the coverage and pyramid distribution. For example, the pyramid coverage can range from 10% to 80%.

[0092] In this application, the second surface 11b (front side) of the solar cell has a textured structure, which can improve the light-trapping effect of the front side of the solar cell, thereby improving the front efficiency of the solar cell. When the bottom surface of the isolation trench V has a tower base structure, the back efficiency and bifaciality of the solar cell will be slightly reduced compared to the textured structure. When the bottom surface of the isolation trench V has a textured structure, the back efficiency and bifaciality of the solar cell can be further improved.

[0093] In some embodiments, the base structure of the bottom surface of the isolation groove V can be formed by polishing the velvet structure formed on the first surface 11a of the substrate 11.

[0094] In other embodiments, the textured surface of the bottom surface of the isolation groove V can be the same as the textured surface of the second surface 11b of the substrate 11, for example, both can be pyramid textured surfaces. In this case, the textured surface of the bottom surface of the isolation groove V and the textured surface of the second surface 11b of the substrate 11 can be formed by the same textured process.

[0095] In some embodiments, the first region A is in a first direction (e.g. Figure 1 and Figure 2 The dimension L1 in the direction indicated by the middle arrow a satisfies: L1 is greater than or equal to 0.05*L and less than or equal to 0.25*L. The dimension L2 of the second region B in the first direction satisfies: L2 is greater than or equal to 0.05*L and less than or equal to 0.15*L. The dimension L3 of the isolation groove between adjacent emitters and bases along the first direction satisfies: L3 is greater than or equal to 0.6*L and less than or equal to 0.9*L. L represents the distance between the outer edges of adjacent first regions A and second regions B. The first direction is parallel to the plane where the substrate 11 is located and points from the first region A to the second region B.

[0096] Here, the dimension L1 of the first region A in the first direction is equal to the dimension of the emitter 12 in the first direction, and the dimension L2 of the second region B in the first direction is equal to the dimension of the base 13 in the first direction.

[0097] In these embodiments, the widths of the emitter 12 and the base 13 can be reduced, thereby reducing parasitic absorption while ensuring that the emitter 12 and the base 13 have good carrier selective transport performance, and improving the overall passivation performance, bifaciality and efficiency of the solar cell.

[0098] In some embodiments, an isolation trench V may be formed on the first surface 11a of the substrate 11 using deposition and patterning processes, an emitter 12 may be formed in the first region A of the first surface 11a, and a base 13 may be formed in the second region B of the first surface 11a.

[0099] Here, taking the example that both the emitter 12 and the base 13 include a tunneling oxide layer and a doped polysilicon layer (for example, the emitter 12 includes a first tunneling oxide layer 121 and a first doped polysilicon layer 122 (such as a P-type doped polysilicon layer), and the base 13 includes a second tunneling oxide layer 131 and a second doped polysilicon layer 132 (such as an N-type doped polysilicon layer)), the first tunneling oxide layer 121 and the first doped polysilicon layer 122 can be formed in the first region A of the first surface 11a by any possible deposition and patterning process, the second tunneling oxide layer 131 and the second doped polysilicon layer 132 can be formed in the second region B of the first surface 11a, and an isolation trench V can be formed between the first region A and the second region B, without specific limitations.

[0100] In some embodiments of this application, the specific methods for forming a first tunneling oxide layer 121 and a first doped polysilicon layer 122 in the first region A, forming a second tunneling oxide layer 131 and a second doped polysilicon layer 132 in the second region B, and forming an isolation trench V between the first region A and the second region B may include:

[0101] like Figures 3 to 10As shown, a first tunneling oxide film 101, a first doped polysilicon film 102, and a first doped dielectric film 103 are deposited on the first surface 11a, the second surface 11b, and the side surface 11c of the substrate 11. Then, the portions of the first tunneling oxide film 101, the first doped polysilicon film 102, and the first doped dielectric film 103, except for those located in the first region A, are removed by sequential masking and acid-base etching processes or a combination of laser and acid-base etching processes. The first thickness portion of the first surface 11a, except for the portion located in the first region A, is etched away, thereby obtaining the portion of the first doped dielectric film 103 located in the first region A, the first tunneling oxide layer 121, and the first doped polysilicon layer 122. Next, a second tunneling oxide film 201 and a second doped polysilicon film 202 are formed on the first surface 11a, the second surface 11b, and the side surface 11c of the substrate 11. 02. Similarly, the second doped dielectric film 203 can also be removed by sequentially performing a masking process and an acid-base etching process or a combination of laser and acid-base etching to remove the remaining parts of the second tunneling oxide film 201, the second doped polysilicon film 202, and the second doped dielectric film 203 outside the second region B. The second thickness portion of the first surface 11a, except for the portion located in the first region A and the second region B, can be etched away. Thus, the isolation trench V, the portion of the second doped dielectric film 203 located in the second region B, the second tunneling oxide layer 131, and the second doped polysilicon layer 132 can be obtained. Finally, by immersing the back side of the substrate 11 with the front side facing up and the back side immersed in an acid solution (such as hydrofluoric acid solution), the portion of the first doped dielectric film 103 located in the first region A and the portion of the second doped dielectric film 203 located in the second region B on the back side can be removed to prepare the emitter 12, the base 13, and the isolation trench V.

[0102] In some possible implementations, such as Figure 3 As shown, when the first tunneling oxide film 101, the first doped polysilicon film 102, and the first doped dielectric film 103 are removed from the portion outside the first region A using a sequential masking process and acid-base etching process, an acid-base resistant first protective layer 100, i.e., a mask layer, can be formed on the surface of the first doped dielectric film 103 located on the portion of the first region A on the first surface 11a. Then, under the protection of this first protective layer 100, as... Figure 3 As shown, the portion of the first doped dielectric film 103 located on the second surface 11b and side surface 11c is removed by immersing the second surface 11b and side surface 11c in an acid solution (such as hydrofluoric acid solution) with the first surface 11a facing upwards. Then, as... Figure 3 and Figure 4As shown, under the protection of the first protective layer 100, the portions of the first doped polycrystalline silicon thin film 102 and the first tunneling oxide thin film 101 located on the second surface 11b, the side surface 11c and the first surface 11a, excluding the first region A, can be removed by using an alkaline solution or an alkaline polishing liquid, thereby preparing the emitter 12.

[0103] To prevent the first protective layer 100 from being completely etched away in acidic or alkaline solutions and thus failing to function as a mask, the first protective layer 100 can be an acid- and alkali-resistant polymer layer. When etching with an alkaline solution, to prevent the portion of the first doped dielectric film 103 located in the first region A from being etched away and failing to protect the underlying film layers, an alkaline solution with a lower concentration can be selected for etching at a lower temperature and for a shorter time. For example, the alkaline solution could be an aqueous solution of TMAH (tetramethylammonium hydroxide) with a volume concentration less than or equal to 10%, with an etching temperature of 50–90°C and a time of 80–200 seconds. During this process, the thickness loss of the portion of the first doped dielectric film 103 located in the first region A can be controlled to be less than 1%, and the first protective layer 100 will break down into fragments that can be removed by cleaning. Even if a small amount of residue adheres to the surface of the substrate 11, the adhesion is very weak and can be completely removed by subsequent immersion in an alkaline solution.

[0104] At the same time, during subsequent soaking in an alkaline solution, such as Figure 3 and Figure 4 As shown, to control the thickness loss of the portion of the first doped dielectric film 103 located in the first region A, an alkaline solution of appropriate concentration can be selected. For example, in some optional embodiments of this application, a mixed solution of alkali metal hydroxide and hydrogen peroxide is used, and the film is immersed at 50–70°C for 50–90 seconds. This also forms a hydrophilic oxide layer on the exposed surface of the first doped polycrystalline silicon film 102 (i.e., the portion of the first doped polycrystalline silicon film 102 other than that located in the first region A), providing a clean and uniform surface for subsequent polishing and preventing defects such as black spots and mottled patterns after polishing. During this process, the thickness loss of the portion of the first doped dielectric film 102 located in the first region A can be controlled to be within 2%.

[0105] Next, as Figure 4 As shown, an alkaline polishing solution can be used to remove the portion of the first doped polysilicon thin film 102 except for the portion located in the first region A, and to remove the first thickness portion of the first surface 11a of the substrate 11 except for the portion located in the first region A. The thickness of the first thickness portion can be 0.3 to 2 μm. During this process, the thickness loss of the first doped dielectric thin film 103 can be controlled to be less than 40%.

[0106] In some other possible implementations, such as Figure 8As shown, when removing the portions of the first tunneling oxide film 101, the first doped polysilicon film 102, and the first doped dielectric film 103 outside the first region A using a combination of laser and acid-base etching, a suitable laser ablation process can be used to irradiate the portions of the first doped dielectric film 103 outside the first region A. This will ablate the portions of the first doped dielectric film 103 outside the first region A. Subsequently, the portions of the first doped dielectric film 103 located on the second surface 11b and the side surface 11c can be removed by immersing the first surface 11a of the substrate upwards and the second surface 11b and the side surface 11c in an acid solution (such as hydrofluoric acid solution), while retaining the portion of the first doped dielectric film 103 located in the first region A of the first surface 11a. Then, as... Figure 8 As shown, under the protection of the first region A portion of the first doped dielectric film 103 located on the first surface 11a, the portions of the first doped polycrystalline silicon film 102 and the first tunneling oxide film 101 located on the second surface 11b, side surface 11c and first surface 11a, excluding the first region A, can be removed by using an alkaline solution or alkaline polishing liquid, thereby preparing the emitter 12.

[0107] In some embodiments, the specific operation of removing the remaining portions of the second tunneling oxide film 201, the second doped polysilicon film 202, and the second doped dielectric film 203 outside the second region B using a sequential masking process and an acid-base etching process can be similar to the specific operation of removing the remaining portions of the first tunneling oxide film 101, the first doped polysilicon film 102, and the first doped dielectric film 103 outside the first region A using a sequential masking process and an acid-base etching process. For a detailed description, please refer to Embodiment 1 below.

[0108] In other embodiments, the specific operation of removing the remaining portions of the second tunneling oxide film 201, the second doped polysilicon film 202, and the second doped dielectric film 203 outside the second region B using a process combining laser and acid-base etching can be similar to the specific operation of removing the remaining portions of the first tunneling oxide film 101, the first doped polysilicon film 102, and the first doped dielectric film 103 outside the first region A using a process combining laser and acid-base etching. For a detailed description, please refer to Embodiment 2 below.

[0109] After the second tunneling oxide layer 131 and the second doped polysilicon layer 132 are subsequently formed in the second region B, and the portion of the second doped dielectric film 203 located in the second region B is retained, as follows: Figure 9As shown, the substrate 11 can be immersed in an alkaline texturing solution to form a textured structure on the second surface 11b and the bottom surface of the isolation tank V. Alternatively, the textured structure on the bottom surface of the isolation tank V of the substrate 11 can be polished with an alkaline polishing solution to form a tower base structure on the bottom surface of the isolation tank V. In this case, the substrate 11 may have a textured structure formed on the first surface 11a and the second surface 11b beforehand. For example, when removing the second doped polysilicon film 202 and the second tunneling oxide film 201 except for the portion located in the second region B, an alkaline texturing solution can be used instead of an alkaline polishing solution to remove the portion of the second doped polysilicon film 202 and the second tunneling oxide film 201 except for the portion located in the second region B, and to remove the second thickness portion of the first surface 11a of the substrate 11 except for the portion located in the first region A and the second region B.

[0110] In some embodiments, when the bottom surface of the isolation groove V is a plane, such as Figure 5 and Figure 6 As shown, after removing the second doped polysilicon thin film 202 and the second tunneling oxide thin film 201 using an alkaline polishing solution, and removing the second thickness portion of the first surface 11a of the substrate 11 other than the first region A and the second region B, an oxide protective layer 300 can be formed on the second surface 11b and the remaining portion of the first surface 11a other than the first region A and the second region B. Then, a textured structure is formed on the second surface 11b by single-sided etching, and the oxide protective layer 300, the portion of the first doped dielectric film 103 located in the first region A, and the portion of the second doped dielectric film 203 located in the second region B of the remaining portion of the first surface 11a other than the first region A and the second region B can be removed simultaneously using an acidic solution (such as hydrofluoric acid), thereby forming an isolation trench V.

[0111] Among them, single-sided etching refers to etching the second surface 11b with an alkaline texturing solution to form a textured structure on the second surface 11b.

[0112] In some embodiments, such as Figure 2 As shown, the bottom surface of the isolation groove V has a velvety structure; the dimension L3 of the isolation groove V between adjacent emitters 12 and bases 13 along the first direction satisfies: L3 is greater than or equal to 0.7*L and less than or equal to 0.9*L, where L represents the distance between the outer edges of adjacent first regions A and second regions B.

[0113] In these embodiments, the isolation trench V on the back of the solar cell can be obtained by etching with an alkaline texturing solution. Since the alkaline texturing solution will cause lateral etching, the size L3 of the isolation trench V between adjacent emitters 12 and bases 13 along the first direction is larger, which can minimize parasitic absorption loss.

[0114] In some embodiments, such as Figure 1 As shown, the bottom surface of the isolation trough V is a plane or a tower base structure; the dimension L3 of the isolation trough V between adjacent emitters 12 and bases 13 along the first direction satisfies: L3 is greater than or equal to 0.7*L and less than or equal to 0.9*L.

[0115] In some embodiments, such as Figure 2 As shown, the bottom surface of the isolation groove V has a velvety surface; the distance L between the outer edges of the adjacent first region A and second region B is greater than or equal to 100 μm and less than or equal to 400 μm.

[0116] In some embodiments, such as Figure 5 and Figure 6 As shown, when the first tunneling oxide film 101, the first doped polysilicon film 102, and the first doped dielectric film 103 are removed except for the portion located in the first region A using a sequential masking process and an acid-base etching process, the portion of the first surface 11a other than the portion located in the first region A will not be significantly damaged. Similarly, when the second tunneling oxide film 201, the second doped polysilicon film 202, and the second doped dielectric film 203 are removed except for the portion located in the second region B using a sequential masking process and an acid-base etching process, the portion of the first surface 11a other than the portion located in the first region A and the portion located in the second region B will not be significantly damaged. In this case, the height difference L4 between the portion of the first surface 11a located in the first region A and the portion located in the second region B, and the height difference L5 between the portion of the first surface 11a located in the second region B and the bottom surface of the isolation trench V are both small, reaching 0.5 to 3 μm.

[0117] That is, such as Figure 1 As shown, the height difference L4 between the portion of the first surface 11a located in the first region A and the portion of the first surface 11a located in the second region B is greater than or equal to 0.5 μm and less than or equal to 3 μm; and / or, the height difference L5 between the portion of the first surface 11a located in the second region B and the bottom surface of the isolation groove V is greater than or equal to 0.5 μm and less than or equal to 3 μm.

[0118] In some embodiments, such as Figure 2 As shown, the bottom surface of the isolation groove V has a velvety surface structure; L2 is greater than or equal to 0.05*L and less than or equal to 0.1*L.

[0119] In these embodiments, the isolation trench V on the back of the solar cell can be obtained by etching with an alkaline texturing solution. Since the alkaline texturing solution causes lateral etching, the size L2 of the second region B in the first direction is smaller.

[0120] In some embodiments, such as Figure 2 As shown, the distance L between the outer edges of adjacent first region A and second region B is greater than or equal to 100 μm and less than or equal to 400 μm.

[0121] In some embodiments, such as Figure 1 and Figure 2 As shown, the second surface 11b is used as a plane to support the base 11. The height of the first surface 11a in the first region A is greater than the height of the first surface 11a in the second region B. The height of the first surface 11a in the second region B is greater than the height of the bottom surface of the isolation groove V.

[0122] In some embodiments, such as Figure 9 As shown, when the first tunneling oxide film 101, the first doped polysilicon film 102, and the first doped dielectric film 103 are removed from the portion outside the first region A using a combination of laser and acid-base etching, laser damage will be caused to the portion outside the first region A. When the second tunneling oxide film 201, the second doped polysilicon film 202, and the third doped dielectric film 203 are removed from the portion outside the second region B using a combination of laser and acid-base etching, laser damage will be caused to the portion outside the second region B. When alkaline polishing solution and alkaline texturing solution are used to remove laser damage, the height difference L4 between the first surface 11a in the first region A and the first surface 11a in the second region B, and the height difference L5 between the first surface 11a in the second region B and the bottom surface of the isolation trench V are both relatively large, reaching 0.5 to 5 μm.

[0123] That is, the height difference L4 between the first surface 11a in the first region A and the first surface 11a in the second region B is greater than or equal to 0.5 μm and less than or equal to 5 μm; and / or, the height difference L5 between the first surface 11a in the second region B and the bottom surface of the isolation groove V is greater than or equal to 0.5 μm and less than or equal to 5 μm.

[0124] It should be noted that when the bottom surface of the isolation trough V has a velvety surface, the height difference L5 between the first surface 11a located in the second region B and the bottom surface of the isolation trough V is equal to the height difference between the first surface 11a located in the second region B and the highest point of the bottom surface of the isolation trough V. When the bottom surface of the isolation trough V is a flat surface or a tower base structure, the height difference L5 between the first surface 11a located in the second region B and the bottom surface of the isolation trough V is equal to the height difference between the first surface 11a located in the second region B and the highest point of the bottom surface of the isolation trough V.

[0125] In some embodiments, such as Figure 1 and Figure 2 As shown, the first passivation antireflection layer 14 includes a first passivation layer 141 and a first antireflection layer 142 stacked together;

[0126] The first antireflection layer 142 includes a silicon nitride layer with a thickness of 70 nm to 100 nm and a refractive index of 1.95 to 2.1. Alternatively, the first antireflection layer 142 includes a silicon nitride layer with a thickness of 30 nm to 50 nm and a silicon oxynitride layer with a thickness of 30 nm to 50 nm. The silicon nitride layer is closer to the substrate 11 than the silicon oxynitride layer. The refractive index of the silicon nitride layer is 1.95 to 2.1, and the refractive index of the silicon oxynitride layer is 1.7 to 1.8.

[0127] In some embodiments, such as Figure 1 and Figure 2 As shown, the solar cell also includes a second passivation antireflection layer 17 disposed on the second surface 11b;

[0128] The second passivation and anti-reflection layer 17 includes: a stacked second passivation layer 171 and a second anti-reflection layer 172;

[0129] The second antireflection layer 172 includes a silicon nitride layer with a thickness of 35 nm to 50 nm and a silicon oxide layer with a thickness of 55 nm to 75 nm. The silicon nitride layer is closer to the substrate than the silicon oxide layer. The refractive index of the silicon nitride layer is 1.95 to 2.1, and the refractive index of the silicon oxide layer is 1.48 to 1.55.

[0130] Secondly, some embodiments of this application provide a photovoltaic module, which includes: a plurality of solar cells connected in series and / or in parallel;

[0131] At least one of the solar cells is a solar cell as described in the first aspect.

[0132] Since the photovoltaic module includes the solar cell provided by the above embodiments, it has the same beneficial effects as the solar cell described in the first aspect above, and will not be repeated here.

[0133] Thirdly, some embodiments of this application provide a photovoltaic system including the photovoltaic module as described in the second aspect.

[0134] Since the photovoltaic system includes the photovoltaic module provided by the above embodiments, it has the same beneficial effects as the photovoltaic module described in the second aspect above, and will not be repeated here.

[0135] Photovoltaic systems can be applied in photovoltaic power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios of photovoltaic systems are not limited to these; that is, photovoltaic systems can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system grid as an example, a photovoltaic system can include photovoltaic arrays, combiner boxes, and inverters. A photovoltaic array can be a combination of multiple solar cells; for example, multiple solar cells can form multiple photovoltaic arrays. The photovoltaic arrays are connected to combiner boxes, which collect the current generated by the photovoltaic arrays. The collected current flows through an inverter, converts it into AC power required by the mains grid, and then connects to the mains grid to achieve solar power supply.

[0136] In order to objectively evaluate the technical effects of the embodiments of this application, this application will be described in detail by way of example through the following embodiments and comparative examples.

[0137] In the following examples and comparative examples, all raw materials were commercially available, and to maintain the reliability of the experiments, the raw materials used in the following examples and comparative examples had the same physical and chemical parameters or were prepared by the same processing method.

[0138] Example 1

[0139] The method for preparing the solar cell provided in Example 1 is as follows: Figures 3-7 and Figure 11 As shown, the steps are as follows:

[0140] like Figure 11 As shown, (1) the substrate 11 (such as an N-type silicon substrate) is subjected to a phosphorus diffusion process with a sheet resistance of 100 ohm / sq and a drive temperature of 750°C for gettering. During this process, impurities 10 inside the substrate 11 will move to the surface of the substrate 11 and accumulate. The phosphorus-silicon glass layer generated on the surface is removed in an acidic solution, and then the surface of the substrate 11 is etched. Usually, chemical etching with an alkaline solution is used to remove about 0.8 μm of the substrate thickness to remove the surface material enriched with impurities 10, while making the surface of the substrate 11 smoother.

[0141] like Figure 3As shown, (2) a first tunneling oxide film 101 with a thickness of 2 nm is formed on the back side (i.e., the first surface 11a), the front side (i.e., the second surface 11b) and the side side 11c of the substrate 11 by thermal oxidation at a temperature of 550°C, and a first doped amorphous silicon film is deposited on the first tunneling oxide film 101. Then, the first doped amorphous silicon film is crystallized at a temperature of 800°C to prepare a first doped polycrystalline silicon film 102. Oxygen is introduced during the doping and crystallization process to form a first doped dielectric film 103 on the surface of the first doped polycrystalline silicon film 102.

[0142] (3) A first protective layer 100 is prepared by screen printing on a portion of the surface of the first doped dielectric film 103 on the back side located in the first region A. The first protective layer 100 is a polymer protective layer (such as acrylic resin), and then dried at 100°C.

[0143] (4) Use hydrofluoric acid solution to remove the first doped dielectric film 103 except for the protected area of ​​the first protective layer 100.

[0144] (5) The first protective layer 100 is removed by using an aqueous solution of tetramethylammonium hydroxide (TMAH) at a temperature of 50°C for 80 seconds. The first protective layer 100 is broken into fragments. A small number of fragments of the first protective layer 100 will adhere to the surface of the first doped dielectric film 103 located in the first region A. The thickness loss of the first doped dielectric film 103 located in the first region A is controlled to be less than 1%, which can protect the first doped polysilicon film 102 from damage by the subsequent chemical etching process.

[0145] During this process, since the alkaline solution used to remove the first protective layer 100 is an aqueous solution of tetramethylammonium hydroxide (TMAH) at a temperature of 50°C, the thickness loss of the first doped dielectric film 103 can be controlled to be less than 1%. This can prevent the second doping element (such as P element) from entering the portion of the first doped polysilicon film 102 located in the first region A when it is subsequently doped, thus protecting the portion of the first doped polysilicon film 102 located in the first region A from damage by the subsequent chemical etching process.

[0146] like Figure 4As shown, (6) the substrate 11 prepared in step (5) is immersed in a mixed solution of potassium hydroxide and hydrogen peroxide at 60°C for 50 seconds to remove the fragments of the first protective layer 100. At the same time, a very thin hydrophilic oxide is formed on the surface of the exposed first doped polycrystalline silicon film 102 (that is, the first doped polycrystalline silicon film 102 not covered by the first doped dielectric film 103), providing a clean and uniform surface for subsequent polishing and avoiding defects such as black spots and mottled spots after polishing. In this process, the above-mentioned immersion temperature and the concentration of the mixed solution can control the thickness loss of the first doped dielectric film 103 to <2%, which is convenient for the first doped dielectric film 103 to protect the first doped polycrystalline silicon film 102 on its bottom.

[0147] (7) The first doped polysilicon film 102, except for the protected area of ​​the first doped dielectric film 103, is removed by using an alkaline polishing solution, and the first thickness portion of the first surface 11a of the substrate 11, except for the area located in the first region A, is removed. The thickness of the first thickness portion is 0.3 μm. During this process, the concentration of the polishing solution can be controlled to reduce the thickness loss of the first doped dielectric film 103 to <40%.

[0148] (8) A second tunneling oxide film 201 with a thickness of 2 nm is formed on the first surface 11a, the second surface 11b and the side surface 11c of the substrate 11 by thermal oxidation at a temperature of 540°C, and a second doped amorphous silicon film is deposited. Then, the second doped amorphous silicon film is crystallized at a temperature of 750°C to obtain a second doped polycrystalline silicon film 202. Oxygen is introduced during the doping and crystallization process to form a second doped dielectric film 203 with a thickness of 80 nm on the second doped polycrystalline silicon film 202.

[0149] (9) A second protective layer 200 is prepared by screen printing on the surface of the second doped dielectric film 203 located in the second region B. The first protective layer 100 is a polymer protective layer (such as acrylic resin), and then dried at 100°C.

[0150] like Figure 6 As shown, (10) the second doped dielectric film 203, excluding the protected area of ​​the second protective layer 200, is removed by using hydrofluoric acid solution.

[0151] (11) The second protective layer 200 is removed using an aqueous solution of TMAH (tetramethylammonium hydroxide) at a temperature of 50°C for 80 seconds. During this process, the thickness loss of the second doped dielectric film 203 can be controlled to <3%. At the same time, this process causes the second protective layer 200 to decompose into fragments, making the cleaning solution a suspension. The fragments of the second protective layer 200 will adhere to the surface of the second doped polycrystalline silicon film 202, but the adhesion is very weak.

[0152] It should be noted that since the second doped dielectric film 203 is formed at a lower temperature, which is 70°C lower than the temperature at which the first doped dielectric film 103 is formed, the second doped dielectric film 203 is less resistant to removal by potassium hydroxide or sodium hydroxide solution and is more easily damaged. Therefore, in step (8), the thickness of the second doped dielectric film 203 should be increased as much as possible compared to the first doped dielectric film 103. That is, in step (8), the thickness of the second doped dielectric film 203 is greater than the thickness of the first doped dielectric film 103.

[0153] (12) The substrate 11 prepared in step (11) is immersed in a mixed solution of potassium hydroxide and hydrogen peroxide at 60°C for 50 seconds to remove the fragments of the second protective layer 200. At the same time, a very thin hydrophilic oxide layer is formed on the surface of the second doped polycrystalline silicon film 202, providing a clean and uniform surface for subsequent polishing and avoiding defects such as black spots and mottled spots after polishing. In this process, the above-mentioned immersion temperature and the concentration of the mixed solution can control the thickness loss of the second doped dielectric film 203 to <15%, which is convenient for the second doped dielectric film 203 to protect the underlying second doped polycrystalline silicon film 202.

[0154] (13) Using an alkaline polishing slurry at 65°C, the second doped polysilicon film 202, excluding the protected region of the second doped dielectric film 203, is removed, and the second thickness portion of the remaining region of the first surface 11a of the substrate 11, excluding the first region A and the second region B, is also removed. The thickness of this second thickness portion is 0.3 μm. During this process, the concentration of the polishing slurry can be controlled to ensure that the thickness loss of the second doped dielectric film 203 is <28%.

[0155] like Figure 6 As shown, (14) the surface of the substrate 11 obtained in step (13) is cleaned, and then a protective oxide layer 300 with a thickness of 3nm is formed on the remaining areas of the first surface 11a of the substrate 11 except for the first region A and the second region B, the second surface 11b and the side surface 11c by hot oxygen oxidation at a temperature of 750℃.

[0156] (15) The oxide protective layer 300 of the front (i.e., the second surface 11b) and the side 11c is removed by using hydrofluoric acid solution. Specifically, the first surface 11a is placed facing upwards and pure water is dripped onto it to form a water film for protection. The second surface 11b and the side 11c are immersed in hydrofluoric acid solution and the oxide protective layer 300 of the front and side 11c is removed by roller support and conveying.

[0157] (16) A pyramidal textured surface structure is formed on the front side (second surface 11b) using an alkaline texturing solution.

[0158] (17) Use hydrofluoric acid solution to remove the oxide protective layer 300 on the back side, the portion of the first doped dielectric film 103 located in the first region A and the portion of the second doped dielectric film 203 located in the second region B, and clean the surface of the substrate 11 with hydrofluoric acid solution.

[0159] like Figure 7 As shown, (18) ALD is used to deposit a first passivation layer 141 and a second passivation layer 171 on the first surface 11a and the second surface 11b respectively. The first passivation layer 141 and the second passivation layer 171 can both be aluminum oxide layers, and a very thin aluminum oxide layer will also be deposited on the side.

[0160] (19) A first antireflection layer 142 is deposited on the first surface 11a, and a second antireflection layer 172 is deposited on the second surface 11b. The first antireflection layer 142 comprises a stacked structure of a silicon nitride layer with a thickness of 40 nm and a refractive index of 1.95–2.1 and a silicon oxynitride layer with a thickness of 40 nm and a refractive index of 1.7–1.8, wherein the silicon nitride layer is closer to the substrate 11 than the silicon oxynitride layer. The second antireflection layer 172 comprises a stacked structure of a silicon nitride layer with a thickness of 40 nm and a refractive index of 1.95–2.1 and a silicon oxide layer with a thickness of 65 nm and a refractive index of 1.48–1.55, wherein the silicon nitride layer is closer to the substrate 11 than the silicon oxide layer.

[0161] (20) Conductive paste is printed in the first region A and the second region B by screen printing, and a first electrode 15 electrically connected to the emitter 12 and a second electrode 16 electrically connected to the base 13 are prepared by sintering. The sintering temperature is 820℃. After sintering, the electrode is annealed at 280℃ for 100 min.

[0162] Example 2

[0163] The method for preparing the solar cell provided in Example 2 is as follows: Figures 8-11 As shown, the steps are as follows:

[0164] (1) See step (1) in Example 1 for details.

[0165] like Figure 8 As shown, (2) a first tunneling oxide film 101 with a thickness of 3 nm is formed on the back side (i.e., the first surface 11a), the front side (i.e., the second surface 11b) and the side side 11c of the substrate 11 by thermal oxidation at a temperature of 650°C, and a first intrinsic amorphous silicon film is deposited on the first tunneling oxide film 101. Then, the first intrinsic amorphous silicon film is doped and crystallized at a temperature of 950°C to obtain a first doped polycrystalline silicon film 102. Oxygen is introduced during the doping and crystallization process to form a first doped dielectric film 103 on the surface of the first doped polycrystalline silicon film 102.

[0166] (3) Laser ablation is performed on the back side (i.e., the first surface 11a) of the substrate 11 prepared in step (2) to remove the remaining part of the first doped dielectric film 103 except for the part located in the first region A. The laser ablation cannot completely remove the first doped dielectric film 103 and there will be very little residue.

[0167] (4) The first doped dielectric film 103 on the front side (i.e., the second surface 11b) and the side side 11c is removed by using hydrofluoric acid solution. Specifically, the back side of the substrate 11 is facing upwards, and pure water is dripped on it to form a water film for protection. The front side and the side side are immersed in hydrofluoric acid solution, and the first doped dielectric film 103 on the front side and the side side is removed by using roller support and conveying.

[0168] (5) The first doped polysilicon film 102, except for the protected area of ​​the first doped dielectric film 103, is removed by using an alkaline polishing solution, and the first thickness portion of the first surface 11a of the substrate 11, except for the area located in the first region A, is removed. The thickness of the first thickness portion is 2 μm. The first doped dielectric film 103 remaining after the back side is laser ablated will peel off along with the first doped polysilicon film 102. During this process, the thickness loss of the first doped dielectric film 103 that has not undergone laser ablation treatment can be controlled to <35%.

[0169] like Figure 9 As shown, (6) the surface of the substrate 11 prepared in step (5) with the first thickness portion removed is cleaned, and then a second tunneling oxide film 201 with a thickness of 0.5 nm is formed at 640°C on the portion of the first doped dielectric film 103 located in the first region A, the remaining portion of the first surface 11a of the substrate 11 excluding the portion located in the first region, the side surface and the second surface 11b. Then, a second intrinsic amorphous silicon film is deposited on the second tunneling oxide film 201. Next, the second intrinsic amorphous silicon film is doped and crystallized at a temperature of 930°C to prepare a second doped polycrystalline silicon film 202, and a second doped dielectric film 203 is formed on the surface of the second doped polycrystalline silicon film 202. The temperature of the thermal oxidation in this step is 10 to 30°C different from the temperature of the thermal oxidation in step (2). Here, the temperature of the thermal oxidation in this step is 10°C lower than the temperature of the thermal oxidation in step (2).

[0170] (7) The back side (i.e., the first surface 11a) of the substrate 11 prepared in step (6) is ablated by laser to remove the second doped medium film 203 except for the part located in the second region B. The laser ablation cannot completely remove the second doped medium film 203 and there will be very little residue.

[0171] (8) The second doped dielectric film 203 on the front and side surfaces of the substrate 11 prepared in step (7) is removed using the method described in step (4).

[0172] (9) Using an alkaline polishing solution, the second doped polysilicon film 202, except for the protected area of ​​the second doped dielectric film 203, is removed, and the second thickness portion of the first surface 11a of the substrate 11, except for the area located in the first region A and the second region B, is removed. The thickness of the second thickness portion is 2 μm. The second doped dielectric film 203 remaining after the back side is laser ablated will peel off along with the second doped polysilicon film 202. During this process, the thickness loss of the second doped dielectric film 203 that has not undergone laser ablation treatment can be controlled to <40%.

[0173] (10) The front and back sides of the substrate prepared in step (9) are not covered by the first doped dielectric film 103 and the second doped dielectric film 203 by using an alkaline texturing solution to form an isolation groove V separating the first region A and the second region B on the first surface 11a. The bottom surface and the second surface 11b of the isolation groove V are both textured structures.

[0174] like Figure 10 As shown, (11) the first doped dielectric film 103 and the second doped dielectric film 203 are removed by hydrofluoric acid solution, and the hydrofluoric acid solution on the surface of the substrate 11 is cleaned.

[0175] (12) A first passivation layer 141 and a second passivation layer 171 are deposited on the first surface 11a and the second surface 11b respectively using ALD. The first passivation layer 141 and the second passivation layer 171 can both be aluminum oxide layers, and a very thin aluminum oxide layer will also be deposited on the side.

[0176] (13) A first antireflection layer 142 is deposited on the first surface 11a, and a second antireflection layer 172 is deposited on the second surface 11b. The first antireflection layer 142 comprises a stacked structure of a silicon nitride layer with a thickness of 40 nm and a refractive index of 1.95-2.1 and a silicon oxynitride layer with a thickness of 40 nm and a refractive index of 1.7-1.8, wherein the silicon nitride layer is closer to the substrate 11 than the silicon oxynitride layer. The second antireflection layer 172 comprises a stacked structure of a silicon nitride layer with a thickness of 40 nm and a refractive index of 1.95-2.1 and a silicon oxide layer with a thickness of 65 nm and a refractive index of 1.48-1.55, wherein the silicon nitride layer is closer to the substrate 11 than the silicon oxide layer.

[0177] (14) Conductive paste is printed in the first region A and the second region B by screen printing, and a first electrode 15 electrically connected to the emitter 12 and a second electrode 16 electrically connected to the base 13 are prepared by sintering. The sintering temperature is 860℃. After sintering, the electrode is annealed at 380℃ for 100min.

[0178] Test case

[0179] 1. The dimensions of the solar cell provided in Example 1 were tested, and the test results are shown in Table 1 below:

[0180] Table 1

[0181]

[0182]

[0183] As shown in Table 1, the dimension L1 of the first region A in the first direction is equal to 0.25*L, the dimension L2 of the second region B in the first direction is equal to 0.15*L, and the dimension L3 of the isolation groove V between the adjacent emitter 12 and base 13 in the first direction is equal to 0.6*L.

[0184] 2. Performance tests were conducted on the solar cell provided in Example 1. The specific test results are shown in Table 2 below:

[0185] Table 2

[0186] Example 1 16.07 0.7354 10.24 86.6 26.8

[0187] As shown in Table 2, the solar cell provided in this application embodiment has a high photoelectric conversion efficiency of over 26%, which is close to the theoretical efficiency of silicon-based cells. This indicates that the solar cell provided in this application embodiment can minimize parasitic absorption and improve passivation effect and bifaciality to the greatest extent.

[0188] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0189] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A solar cell, characterized in that, include: The substrate has a first surface and a second surface disposed opposite to each other along its thickness direction, and an isolation groove formed on the first surface, the isolation groove dividing the first surface into a first region and a second region. An emitter is disposed in the first region; The base is disposed in the second region; A first passivation and anti-reflection layer is disposed in the first region, the second region, and the isolation trench; A first electrode is disposed in the first region and electrically connected to the emitter. The second electrode is disposed in the second region and is electrically connected to the base electrode; Wherein, taking the total area of ​​the first surface as 100%, the area ratio of the first region is less than or equal to 25%, and the area ratio of the second region is less than or equal to 15%.

2. The solar cell according to claim 1, characterized in that, The area of ​​the first region is greater than or equal to 5% and less than or equal to 25%, and the area of ​​the second region is greater than or equal to 5% and less than or equal to 15%.

3. The solar cell according to claim 1, characterized in that, The substrate is supported by the second surface as a plane, and the height of the first surface in the first region is greater than the height of the first surface in the second region, and the height of the first surface in the second region is greater than the height of the bottom surface of the isolation groove.

4. The solar cell according to any one of claims 1 to 3, characterized in that, The bottom surface of the isolation groove is a plane, or the bottom surface of the isolation groove has a tower base structure or a velvet surface structure.

5. The solar cell according to claim 4, characterized in that, The dimension L1 of the first region in the first direction satisfies: L1 is greater than or equal to 0.05*L and less than or equal to 0.25*L; the dimension L2 of the second region in the first direction satisfies: L2 is greater than or equal to 0.05*L and less than or equal to 0.15*L; the dimension L3 of the isolation groove between adjacent emitters and bases along the first direction satisfies: L3 is greater than or equal to 0.6*L and less than or equal to 0.9*L; where L represents the distance between the outer edges of adjacent first and second regions, the first direction is parallel to the plane where the base is located, and points from the first region to the second region.

6. The solar cell according to claim 5, characterized in that, The bottom surface of the isolation groove has a velvety texture; L2 is greater than or equal to 0.05*L and less than or equal to 0.1*L.

7. The solar cell according to claim 5, characterized in that, The bottom surface of the isolation groove has a velvety texture; L3 is greater than or equal to 0.7*L and less than or equal to 0.9*L.

8. The solar cell according to claim 5, characterized in that, The bottom surface of the isolation trench is either a plane or a tower base structure; L3 is greater than or equal to 0.7*L and less than or equal to 0.9*L.

9. The solar cell according to claim 5, characterized in that, The bottom surface of the isolation trench is a plane or a tower base structure, and the distance L between the outer edges of adjacent first and second regions is greater than or equal to 100 μm and less than or equal to 500 μm.

10. The solar cell according to claim 5, characterized in that, The bottom surface of the isolation groove has a velvety structure, and the distance L between the outer edges of adjacent first and second regions is greater than or equal to 100μm and less than or equal to 400μm.

11. The solar cell according to claim 4, characterized in that, The bottom surface of the isolation trench is a plane or a tower base structure; the second surface is used as a plane to support the substrate, and the solar cell satisfies at least one of the following conditions: (1) The height difference L4 between the portion of the first surface located in the first region and the portion of the first surface located in the second region is greater than or equal to 0.5 μm and less than or equal to 3 μm; (2) The height difference L5 between the portion of the first surface located in the second region and the bottom surface of the isolation groove is greater than or equal to 0.5 μm and less than or equal to 3 μm.

12. The solar cell according to claim 4, characterized in that, The bottom surface of the isolation groove has a velvety texture; the second surface is used as a plane to support the substrate, and the solar cell satisfies at least one of the following conditions: (1) The height difference L4 between the first surface in the first region and the first surface in the second region is greater than or equal to 0.5 μm and less than or equal to 5 μm; (2) The height difference L5 between the height of the first surface in the second region and the bottom surface of the isolation groove is greater than or equal to 0.5 μm and less than or equal to 5 μm.

13. A photovoltaic module, characterized in that, include: Multiple solar cells connected in series and / or in parallel; At least one of the solar cells is a solar cell as described in any one of claims 1 to 12.

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