Micro light emitting diode, pixel array, and micro display

Abstract

The utility model provides a kind of micro light emitting diode, pixel array and micro display screen, including first contact layer, first semiconductor layer, functional layer, second semiconductor layer and second contact layer that are sequentially stacked from bottom to top;The size of first semiconductor layer and first contact layer gradually decreases along the direction away from functional layer, to form at least one step in the side wall of first semiconductor layer and the side wall of first contact layer;And / or, the length of second semiconductor layer and second contact layer gradually decreases along the direction away from functional layer, to form at least one step in the side wall of second semiconductor layer and the side wall of second contact layer.Such, effectively reduce the influence of total reflection to micro light emitting diode, increase the transmittance of light, and then reduce the loss of functional area light extraction, so as to improve luminous efficiency, solve the problem of how to improve the luminous efficiency of micro light emitting diode.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a micro light-emitting diode, pixel array, and micro display screen. Background Technology

[0002] In the field of microdisplays, especially mini LEDs and micro LEDs, there is a size effect; that is, as the size of an LED shrinks, its luminous efficiency decreases. Luminous efficiency is mainly determined by internal quantum efficiency and light extraction efficiency. Since internal quantum efficiency is affected by material defects and other factors, it is difficult to improve. Therefore, in the chip industry, the overall luminous efficiency is mainly improved by enhancing light extraction efficiency.

[0003] However, as the size of LEDs shrinks, the proportion of sidewall area in the overall surface area increases, and nonradiative recombination of sidewall defects significantly reduces luminous efficiency. To address this issue, techniques such as surface roughening, surface photonic crystals, surface hemispherical shaping (microlenses), resonant cavities, and reflective cups are commonly used to improve sidewall defects and thus enhance luminous efficiency. However, these existing technologies suffer from complexity, difficulty in manufacturing processes, and high costs. Especially when LEDs are very small (e.g., ≤3μm), miniaturization becomes difficult, thus limiting the improvement of luminous efficiency in micro-LEDs. Utility Model Content

[0004] The purpose of this invention is to provide a miniature light-emitting diode, a pixel array, and a micro-display to solve the problem of how to improve the luminous efficiency of miniature light-emitting diodes.

[0005] To solve the above-mentioned technical problems, this utility model provides a miniature light-emitting diode, comprising a first contact layer, a first semiconductor layer, a functional layer, a second semiconductor layer, and a second contact layer stacked sequentially from bottom to top; The dimensions of the first semiconductor layer and the first contact layer gradually decrease in the direction away from the functional layer to form at least one step on the sidewall of the first semiconductor layer and the sidewall of the first contact layer; and / or, the lengths of the second semiconductor layer and the second contact layer gradually decrease in the direction away from the functional layer to form at least one step on the sidewall of the second semiconductor layer and the sidewall of the second contact layer.

[0006] Optionally, in the aforementioned micro light-emitting diode, the functional layer includes an active region or multiple quantum wells; the first semiconductor layer includes at least one of a first barrier layer, a first confinement layer, and a first waveguide layer; the second semiconductor layer includes at least one of a second barrier layer, a second confinement layer, and a second waveguide layer.

[0007] Optionally, in the micro light-emitting diode, the first contact layer and the first semiconductor layer are both P-type or N-type, the second semiconductor layer and the second contact layer are both N-type or P-type, and the types of the first contact layer and the first semiconductor layer are different from the types of the second semiconductor layer and the second contact layer.

[0008] Optionally, in the aforementioned micro-light-emitting diode, the first contact layer and the second contact layer are made of metal oxide, metal dopant, single-layer metal, multi-layer metal, or alloy, wherein the metal oxide is ZnO or ITO, the metal dopant is GaP, AlGaAs, GaAs, or GaN, and the single-layer metal, multi-layer metal, or alloy is made of Au, Ag, Zn, Ge, Ni, or Al; the first semiconductor layer or the second semiconductor layer is made of AlInP, AlGaAs, AlGaN, AlGaInP, GaAs, or GaN; and the functional layer is made of AlGaInP, AlGaAs, or InGaN.

[0009] Optionally, in the micro light-emitting diode, the angle between the sidewall and the bottom of the first contact layer is 90±60°, the angle between the sidewall and the bottom of the first semiconductor layer is 90±45°, the angle between the sidewall and the bottom of the functional layer is 90±45°, the angle between the sidewall and the bottom of the second semiconductor layer is 90±45°, and the angle between the sidewall and the bottom of the second contact layer is 90±60°.

[0010] Optionally, in the micro light-emitting diode, the total thickness of the first contact layer and the first semiconductor layer is 100~400nm, the total thickness of the second semiconductor layer and the second contact layer is 100~400nm, the thickness of the functional layer is 100~300nm, and the thickness between the first contact layer and the second contact layer is 0.3~5μm.

[0011] Optionally, in the aforementioned micro-light-emitting diode, the micro-light-emitting diode further includes a buffer layer located at the bottom of the first contact layer.

[0012] Optionally, in the aforementioned micro light-emitting diode, the buffer layer is made of AlGaInP, AlGaAs, GaInP, InGaN, or AlN.

[0013] Optionally, in the aforementioned micro-light-emitting diode, the micro-light-emitting diode further includes a discontinuous metal layer located on top of the second contact layer.

[0014] Optionally, in the aforementioned micro light-emitting diode, the discontinuous metal layer comprises a mirror layer, a barrier layer, and a bonding metal layer arranged sequentially from bottom to top; the material of the mirror layer includes Au, Ag, Al, Ni / Ag, Ni / Al, Ag / Al, Ag / Ni / Au, Al / Ni / Au, Ir / Ag, or AuBe / Ag; the material of the bonding metal layer includes Au, Cu, AuSn, and CuSn; and the material of the barrier layer includes one or more of Ti, Ni, Pt, Cr, TiN, and TaN.

[0015] To solve the above-mentioned technical problems, the present invention also provides a pixel array, which includes a plurality of micro light-emitting diodes arranged in an array as described in any of the preceding claims.

[0016] To solve the above-mentioned technical problems, the present invention also provides a micro display screen, which includes a micro light-emitting diode as described in any of the preceding claims, or includes a pixel array as described above.

[0017] This invention provides a micro light-emitting diode, its manufacturing method, pixel array, and microdisplay, comprising a first contact layer, a first semiconductor layer, a functional layer, a second semiconductor layer, and a second contact layer stacked sequentially from bottom to top. The dimensions of the first semiconductor layer and the first contact layer gradually decrease in the direction away from the functional layer, forming at least one step on the sidewalls of the first semiconductor layer and the first contact layer; and / or, the lengths of the second semiconductor layer and the second contact layer gradually decrease in the direction away from the functional layer, forming at least one step on the sidewalls of the second semiconductor layer and the second contact layer. By forming at least one step on the sidewalls of the first semiconductor layer and the first contact layer, and / or forming at least one step on the sidewalls of the second semiconductor layer and the second contact layer, the effects of total internal reflection are effectively reduced, light transmittance is increased, and thus the loss of light extraction in the functional area is reduced, improving luminous efficiency and solving the problem of how to improve the luminous efficiency of micro light-emitting diodes. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the miniature light-emitting diode provided in this embodiment; Figures 2(a) to 2(g) are schematic diagrams of the structures of various miniature light-emitting diodes provided in this embodiment; Figure 3 A schematic diagram illustrating the included angle of the miniature light-emitting diode provided in this embodiment; Figure 4 The light transmittance curves of the micro-light-emitting diodes obtained after removing the second semiconductor layer to different degrees are provided in this embodiment. Figure 5A flowchart illustrating the manufacturing method of the miniature light-emitting diode provided in this embodiment; Figures 6(A) to 6(Q) are schematic diagrams of the device structure corresponding to each step in the manufacturing method of the miniature light-emitting diode provided in this embodiment; The labels in the accompanying drawings are explained as follows: 100 - Substrate; 210 - First contact layer; 220 - First semiconductor layer; 221 - Step; 230 - Functional layer; 240 - Second semiconductor layer; 241 - Step; 250 - Second contact layer; 300 - Driving wafer; 310 - Bonding layer; 400 - Passivation layer; 410 - Reflective cup; 500 - Insulating layer; 600 - Conductive thin film; 610 - Reinforcing cathode; 700 - Microlens. Detailed Implementation

[0019] The miniature light-emitting diode, pixel array, and microdisplay proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the explanation of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may emphasize different aspects and sometimes use different proportions.

[0020] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this utility model are used to distinguish similar objects in order to describe embodiments of this utility model, and are not used to describe a specific order or sequence. It should be understood that such structures can be interchanged where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0021] This embodiment provides a miniature light-emitting diode, such as Figure 1 As shown, it includes a first contact layer 210, a first semiconductor layer 220, a functional layer 230, a second semiconductor layer 240, and a second contact layer 250 stacked sequentially from bottom to top; The dimensions of the first semiconductor layer 220 and the first contact layer 210 gradually decrease in the direction away from the functional layer 230 to form at least one step on the sidewall of the first semiconductor layer 220 and the sidewall of the first contact layer 210; and / or, the lengths of the second semiconductor layer 240 and the second contact layer 250 gradually decrease in the direction away from the functional layer 230 to form at least one step on the sidewall of the second semiconductor layer 240 and the sidewall of the second contact layer 250.

[0022] The micro light-emitting diode provided in this embodiment effectively reduces the effects of total internal reflection and increases light transmittance by forming at least one step on the sidewalls of the first semiconductor layer 220 and the first contact layer 210, and / or forming at least one step on the sidewalls of the second semiconductor layer 240 and the second contact layer 250. This reduces the loss of light extraction in the functional area and improves the luminous efficiency, thus solving the problem of how to improve the luminous efficiency of micro light-emitting diodes.

[0023] In practical applications, such as Figure 1 As shown, the sides of the second semiconductor layer 240 and the second contact layer 250 can be removed so that the remaining second semiconductor layer 240 forms a second boss structure, wherein the second boss structure covers the functional region 230. At this time, a step 241 is formed at the boss of the second semiconductor layer 240. Preferably, in order to reduce total internal reflection and improve the light transmittance of the device, in this embodiment, the dimensions of the first contact layer 210, the first semiconductor layer 220, the functional layer 230, the second semiconductor layer 240, and the second contact layer 250 can be controlled to gradually decrease along the height direction, that is, the overall shape is narrower at the top and wider at the bottom.

[0024] In other embodiments, it is also possible to Figure 1 Based on the structure shown, as shown in Figure 2(a), both sides of the second semiconductor layer 240 are completely removed to expose the functional layer 230. At this time, a step 241 is formed at the junction of the second semiconductor layer 240 and the functional layer 230.

[0025] In other embodiments, as shown in FIG2(b), the middle portion of the second semiconductor layer 240 and the second contact layer 250 can be removed to form a second groove in the second semiconductor layer 240, wherein the bottom of the second groove is the second semiconductor layer 240. In this case, a step 241 is formed at the groove of the second semiconductor layer 240.

[0026] In other embodiments, based on the structure shown in FIG2(b), as shown in FIG2(c), the middle portion of the second semiconductor layer 240 can be completely removed to expose the functional layer 230. In this case, a step 241 is formed at the junction of the second semiconductor layer 240 and the functional layer 230 within the second groove.

[0027] In other embodiments, as shown in FIG2(d), the sides of the first semiconductor layer 220 and the first contact layer 210 can be removed so that the remaining first semiconductor layer 220 forms a first boss structure, wherein the first boss structure covers the functional region 230. In this case, a step 221 is formed at the boss of the first semiconductor layer 220. Preferably, in order to reduce total internal reflection and improve the light transmittance of the device, in this embodiment, the dimensions of the first contact layer 210, the first semiconductor layer 220, the functional layer 230, the second semiconductor layer 240 and the second contact layer 250 can be controlled to gradually increase along the height direction, that is, the overall shape is wider at the top and narrower at the bottom.

[0028] Alternatively, referring to the modification in Figure 2(a), both sides of the first semiconductor layer 220 in Figure 2(d) can be completely removed to expose the functional layer 230. In this case, a step 221 is formed at the junction of the first semiconductor layer 220 and the functional layer 230.

[0029] In other embodiments, as shown in FIG2(e), both sides of the second semiconductor layer 240 and the second contact layer 250, as well as both sides of the first semiconductor layer 220 and the first contact layer 210, can be removed simultaneously. In this case, a step 241 is formed at the boss of the second semiconductor layer 240, and a step 221 is formed at the boss of the first semiconductor layer 220.

[0030] Alternatively, referring to the modification in Figure 2(a), both sides of the second semiconductor layer 240 and both sides of the first semiconductor layer 220 in Figure 2(e) can be completely removed to expose the functional layer 230. In this case, a step 241 is formed at the junction of the second semiconductor layer 240 and the functional layer 230, and a step 221 is formed at the junction of the first semiconductor layer 220 and the functional layer 230.

[0031] In other embodiments, as shown in FIG2(f), multiple steps 241 may also be formed at the second semiconductor layer 240. This allows for the expansion of large currents by retaining more of the second semiconductor layer 240. Similarly, multiple steps 221 may also be formed at the first semiconductor layer 220.

[0032] Furthermore, in other embodiments, a step may be formed at the junction of the second contact layer 250 and the second semiconductor layer 240. Correspondingly, one or more steps may also be formed at the junction of the first contact layer 210 and the first semiconductor layer 220.

[0033] Furthermore, in practical applications, as shown in Figure 2(g), a portion of the second contact layer 250 and the second semiconductor layer 240 can be removed through a small array patterning, thereby forming special optical structures such as metasurfaces. This effectively reduces the carrier concentration participating in nonradiative recombination in the functional region 230, thereby reducing nonradiative recombination by altering the current distribution, further improving luminous efficiency and device performance.

[0034] In practical applications, those skilled in the art can, based on the above examples, reasonably set the number of steps and the location and method of forming the steps according to the thickness of each layer and the requirements of the device. This application does not impose any restrictions on this.

[0035] Furthermore, in this embodiment, the functional layer 230 includes an active region or a multiple quantum well (MQW); the first semiconductor layer 220 includes at least one of a first barrier layer, a first confinement layer, and a first waveguide layer; the second semiconductor layer 240 includes at least one of a second barrier layer, a second confinement layer, and a second waveguide layer. The barrier layer, confinement layer, and waveguide layer are all structural layers well-known to those skilled in the art, and will not be described in detail here.

[0036] Specifically, in this embodiment, the first contact layer 210 and the first semiconductor layer 220 are both P-type or N-type, and the second semiconductor layer 240 and the second contact layer 250 are both N-type or P-type. Furthermore, the types of the first contact layer 210 and the first semiconductor layer 220 are different from the types of the second semiconductor layer 240 and the second contact layer 250. That is, when the first contact layer 210 and the first semiconductor layer 220 are P-type, the second semiconductor layer 240 and the second contact layer 250 should be N-type; when the first contact layer 210 and the first semiconductor layer 220 are N-type, the second semiconductor layer 240 and the second contact layer 250 should be P-type.

[0037] Specifically, in this embodiment, the materials of the first contact layer 210 and the second contact layer 250 can be metal oxides, metal dopants, single-layer metals, multi-layer metals, or alloys. Among them, the metal oxides can be ZnO or ITO, etc., the metal dopants can be GaP, AlGaAs, GaAs, or GaN, etc., and the metals selected for single-layer metals, multi-layer metals, or alloys can be Au, Ag, Zn, Ge, Ni, Al, etc.; the materials of the first semiconductor layer 220 or the second semiconductor layer 240 can be AlInP, AlGaAs, AlGaN, AlGaInP, GaAs, or GaN, etc.; the materials of the functional layer can be AlGaInP, AlGaAs, or InGaN, etc.

[0038] The micro light-emitting diode provided in this embodiment uses inorganic compound materials for its light-emitting material (functional layer 230). Combined with the device structure of the micro light-emitting diode provided in this embodiment, it can better improve light extraction and obtain better luminous efficiency.

[0039] In practical applications, AlGaInN can be used as the luminescent material for miniature LEDs that need to emit blue-green light, while AlGaInN or AlGaInP can be used as the luminescent material for miniature LEDs that need to emit red light.

[0040] To achieve better luminous efficiency, in this embodiment, such as Figure 3 As shown, the angle A between the sidewall and the bottom of the first contact layer 210 is 90±60°, the angle B between the sidewall and the bottom of the first semiconductor layer 220 is 90±45°, the angle C between the sidewall and the bottom of the functional layer 230 is 90±45°, the angle D between the sidewall and the bottom of the second semiconductor layer 240 is 90±45°, and the angle E between the sidewall and the bottom of the second contact layer 250 is 90±60°.

[0041] In practical applications, the specific values ​​of the included angles A, B, C, D, and E can be the same or different. The values ​​of each included angle can be determined by comprehensively considering the stability of the device structure and the light emission angle.

[0042] In this embodiment, the total thickness of the first contact layer 210 and the first semiconductor layer 220 is 100~400nm, the total thickness of the second semiconductor layer 240 and the second contact layer 250 is 100~400nm, and the thickness of the functional layer 230 is 100~300nm; the thickness between the first contact layer 210 and the second contact layer 250 is 0.3~5μm.

[0043] In practical applications, to ensure mass production yield and performance, when partially removing the second contact layer 250 and the second semiconductor layer 240 so that the formed second boss structure covers the functional layer 230 (e.g.) Figure 1 As shown in Figure 2(d), the thickness of the remaining second semiconductor layer 240 should be no less than 30 nm. Similarly, when the first contact layer 210 and the first semiconductor layer 220 are partially removed so that the formed first boss structure covers the functional layer 230 (as shown in Figure 2(d)), the thickness of the remaining first semiconductor layer 220 should be no less than 30 nm.

[0044] Furthermore, in practical applications, to ensure mass production yield and performance, when partially removing the second contact layer 250 and the second semiconductor layer 240 to expose the functional layer 230 of the formed second protrusion structure (as shown in Figure 2(a)), a high-selectivity etching scheme should be used to completely remove the second semiconductor layer 240. Specifically, atomic layer etching (ALT) can be used to remove the second contact layer 250 and the second semiconductor layer 240. Similarly, when partially removing the first contact layer 210 and the first semiconductor layer 220 to expose the functional layer 230 of the formed first protrusion structure, a high-selectivity etching scheme should be used to completely remove the first semiconductor layer 220. Specifically, atomic layer etching (ALT) can be used to remove the first contact layer 210 and the first semiconductor layer 220.

[0045] Furthermore, to facilitate manufacturing processes, in this embodiment, the micro LED further includes a buffer layer located at the bottom of the first contact layer 210. Specifically, the buffer layer is made of AlGaInP, AlGaAs, GaInP, InGaN, or AlN.

[0046] Furthermore, to facilitate electrical connection of the device and achieve better bond warpage and metal cost control, in this embodiment, the micro light-emitting diode further includes a discontinuous metal layer located on top of the second contact layer 250. Specifically, the discontinuous metal layer includes a mirror layer, a barrier layer, and a bonding metal layer arranged sequentially from bottom to top. The mirror layer is made of Au, Ag, Al, Ni / Ag, Ni / Al, Ag / Al, Ag / Ni / Au, Al / Ni / Au, Ir / Ag, or AuBe / Ag; the bonding metal layer is made of Au, Cu, AuSn, or CuSn; and the barrier layer is made of one or more of Ti, Ni, Pt, Cr, TiN, and TaN.

[0047] To clearly illustrate the technical advantages of the micro LED provided in this embodiment compared to existing conventional cylindrical or trapezoidal micro LEDs in terms of light transmittance, this embodiment uses a specific example for comparison: In this embodiment, the micro-light-emitting diode is configured such that the first contact layer 210 is P-type, the first semiconductor layer 220 is P-type, the second semiconductor layer 240 is N-type, and the second contact layer 250 is N-type. Specifically, the second contact layer 250 is made of GaAs with a thickness of 10 nm; the second semiconductor layer 240 is made of AlInP with a thickness of 300 nm; and the functional layer 230 is an active region made of AlGaInP, serving as the light-emitting region. Light passes from the active region through the second semiconductor layer 240 into the air. The second semiconductor layer 240 is removed to varying degrees, and the measured light transmittance of the micro-light-emitting diode is as follows: Figure 4 As shown.

[0048] from Figure 4 It can be seen that with the second semiconductor layer 240 intact (before removal - solid green line), the light transmittance of the micro-LED is the lowest in the wavelength range of 400~700nm; with the remaining 300nm of the second semiconductor layer 240 (solid black line), the light transmittance of the micro-LED increases slightly; as the degree of removal increases, from the remaining 200nm of the second semiconductor layer (bright blue dashed line), the remaining 100nm of the second semiconductor layer (dark blue dashed line), the remaining 50nm of the second semiconductor layer (solid orange line), the remaining 20nm of the second semiconductor layer (solid purple line), to the complete removal of the second semiconductor layer (solid red line), the light transmittance of the micro-LED increases sequentially in the wavelength range of 400~700nm; after the second semiconductor layer is completely removed, the light transmittance of the micro-LED is the highest in the wavelength range of 400~700nm, reaching over 60%.

[0049] Therefore, the micro light-emitting diode provided in this embodiment effectively reduces the influence of total internal reflection and increases the light transmittance by forming at least one step on the sidewalls of the first semiconductor layer 220 and the first contact layer 210, and / or forming at least one step on the sidewalls of the second semiconductor layer 240 and the second contact layer 250, thereby reducing the loss of light extraction in the functional area and improving the luminous efficiency, thus solving the problem of how to improve the luminous efficiency of micro light-emitting diodes.

[0050] Based on the miniature light-emitting diode provided in this embodiment, this embodiment also provides a method for manufacturing a miniature light-emitting diode, such as... Figure 5 As shown, the manufacturing method includes: S1, as shown in Figure 6(A), provides a substrate 100.

[0051] The substrate 100 can be a silicon substrate, a sapphire substrate, a GaN substrate, or a GaAs substrate, etc.

[0052] Preferably, to facilitate process implementation, in this embodiment, a buffer layer may also be formed on the surface of the substrate 100, wherein the material of the buffer layer may be AlGaInP, AlGaAs, GaInP, InGaN or AlN.

[0053] S2, as shown in Figure 6(B), a first contact layer, a first semiconductor layer, a functional layer, a second semiconductor layer, and a second contact layer are sequentially formed on a substrate to obtain a basic device.

[0054] Specifically, a deposition process can be used to sequentially deposit a first contact layer 210, a first semiconductor layer 220, a functional layer 230, a second semiconductor layer 240, and a second contact layer 250 on the substrate 100. The deposition process is well known to those skilled in the art, and will not be described in detail here.

[0055] Preferably, after obtaining the basic device, the manufacturing method further includes: S21, a discontinuous metal layer is formed on the surface of the second contact layer 250, the discontinuous metal layer comprising a mirror layer, a barrier layer and a bonding metal layer formed sequentially from bottom to top.

[0056] Specifically, the material of the reflector layer includes Au, Ag, Al, Ni / Ag, Ni / Al, Ag / Al, Ag / Ni / Au, Al / Ni / Au, Ir / Ag, or AuBe / Ag; the material of the bonding metal layer includes Au, Cu, AuSn, and CuSn; and the material of the barrier layer includes one or more of Ti, Ni, Pt, Cr, TiN, and TaN.

[0057] In one specific embodiment, the second contact layer 250 and the reflector layer are both made of Au, and the total thickness of the two is 100 nm; the barrier layer includes 50 nm thick Ni, 50 nm thick Cr and 50 nm thick Pt; the bonding metal layer includes 100 nm thick Au and 100 nm thick Sn.

[0058] S22 provides drive wafer 300.

[0059] In practical applications, the basic devices can be formed on a compound wafer. In order to electrically connect the micro LEDs to other circuit structures, a driver wafer can be provided, on which CMOS circuits such as transistors are formed for connection to the positive electrode of the micro LEDs.

[0060] S23, as shown in Figure 6(C), a patterned bonding layer 310 is fabricated on the driving wafer 300.

[0061] Specifically, the bonding layer 310 on the driving wafer 300 should correspond to the bonding metal layer on the compound wafer to facilitate subsequent bonding.

[0062] In this embodiment, an adhesion barrier layer may also be formed between the driving wafer 300 and the bonding layer 310. The bonding layer 310 may be made of Au, Cu, AuSn, CuSn, etc. The adhesion barrier layer may be made of one or more of Ti, Ni, Pt, Cr, TiN, TaN, etc.

[0063] In one specific embodiment, the adhesion barrier layer comprises 50 nm thick Cr and 50 nm thick Pt; the bonding layer comprises 100 nm thick Au and 100 nm thick Sn.

[0064] S23, the bonding metal layer is bonded to the bonding layer 310.

[0065] The specific implementation of the bonding is well known to those skilled in the art, and will not be described in detail here.

[0066] The resulting device structure is shown in Figure 6(D).

[0067] S24, as shown in Figure 6(E), remove the substrate 100 to expose the first contact layer 210.

[0068] In practical applications, chemical mechanical polishing can be used to polish the first contact layer 210, thereby reducing the thickness of the first contact layer 210 and making the surface of the first contact layer 210 flat.

[0069] At this point, the electrical connection between the compound wafer and the driver wafer is complete. The micro-LEDs are now positioned in an inverted manner on the surface of the driver wafer.

[0070] S3, perform patterned multi-step processing on the basic device to form at least one step on the sidewall of the first contact layer and the sidewall of the first semiconductor layer, and / or, form at least one step on the sidewall of the second semiconductor layer and the sidewall of the second contact layer.

[0071] Specifically, the steps and methods include: Remove a portion of the second contact layer 250 and the second semiconductor layer 240 so that the remaining second semiconductor layer 240 forms a second boss structure, wherein the second boss structure covers the functional layer 230, or the second boss structure exposes the functional layer 230; and / or remove a portion of the first contact layer 210 and the first semiconductor layer 220 so that the remaining first semiconductor layer 210 forms a first boss structure, wherein the first boss structure covers the functional layer 230, or the first boss structure exposes the functional layer 230; Alternatively, a portion of the second contact layer 250 and the second semiconductor layer 240 may be removed to form a second groove in the second semiconductor layer 240, wherein the bottom of the second groove is the second semiconductor layer 240, or the bottom of the second groove exposes the functional layer 230; and / or a portion of the first contact layer 210 and the first semiconductor layer 220 may be removed to form a first groove in the first semiconductor layer 220, wherein the bottom of the first groove is the first semiconductor layer 220, or the bottom of the first groove exposes the functional layer 230.

[0072] To ensure mass production yield, when the second protrusion structure covers the functional layer 230, the thickness of the second semiconductor layer 240 is greater than or equal to 30nm; when the first protrusion structure covers the functional layer 230, the thickness of the first semiconductor layer 220 is greater than or equal to 30nm.

[0073] Furthermore, a high selectivity etching scheme, such as atomic layer etching, is used to remove a portion of the second contact layer 250 and the second semiconductor layer 240 to expose the functional layer 230 of the second boss structure; a high selectivity etching scheme, such as atomic layer etching, is used to remove a portion of the first contact layer 210 and the first semiconductor layer 220 to expose the functional layer 230 of the first boss structure.

[0074] Preferably, a small array pattern can be used to remove portions of the second contact layer 250 and the second semiconductor layer 240 to form special optical structures, such as metasurfaces, on the surfaces of the second contact layer 250 and the second semiconductor layer 240; similarly, a small array pattern can be used to remove portions of the first contact layer 210 and the first semiconductor layer 220 to form special optical structures, such as metasurfaces, on the surfaces of the first contact layer 210 and the first semiconductor layer 220. This effectively reduces the carrier concentration participating in nonradiative recombination in the functional region, thereby reducing nonradiative recombination by changing the current distribution, further improving luminous efficiency and device performance.

[0075] Specifically, as shown in Figure 6(F), steps can be formed using photolithography. Considering that multiple light-emitting diodes (LEDs) can be arrayed on a wafer, an isolation region is formed between adjacent LEDs, with the bottom of the isolation region exposing the second semiconductor layer 240. Simultaneously, the isolation region allows the size of each LED to gradually decrease from bottom to top, thereby further improving the luminous efficiency of the micro LEDs. At this time, a step 221 is formed at the first semiconductor layer 220, and a step 241 is formed at the second semiconductor layer 240.

[0076] In practical applications, the thickness of the second semiconductor layer 240 retained at the bottom of the isolation region is controlled between 30nm and 300nm, which is beneficial for controlling the stability of the device structure and for the fabrication of the pixel array. Of course, in other embodiments, the isolation region can also be formed by directly etching to the second contact layer 250 or to the surface of the driving wafer 300, thereby completing the isolation of a single light-emitting diode (pixel).

[0077] Furthermore, in this embodiment, the manufacturing method further includes: S4, as shown in Figure 6(G), a passivation layer 400 is deposited on the surface of the device after patterning multi-step processing. The passivation layer 400 is made of one or more of aluminum oxide, silicon oxide, and silicon nitride.

[0078] Specifically, the passivation layer 400 at least covers the exposed surfaces of the sidewalls and top of the second semiconductor layer 240, the functional layer 230, the first semiconductor layer 220, and the first contact layer 210.

[0079] By passivating the surface of a device, it is possible to effectively protect the device, prevent surface contamination or electrical breakdown, and improve the device's service life.

[0080] After passivation, individual devices can be segmented, as shown in Figure 6(H). This involves etching the passivation layer 400, the second semiconductor layer 240, the second contact layer 250, and the bonding layer 310 between two adjacent light-emitting diodes to obtain independent light-emitting diodes. The bottom of each light-emitting diode is connected to the anode (red transistor symbol in Figure 6(H)) in the driving wafer 300 via the bonding layer 310; while independent structures that do not form light-emitting diodes have their bottoms connected to the cathode (black transistor symbol in Figure 6(H)) in the driving wafer 300 via the bonding layer 310.

[0081] Preferably, in this embodiment, as shown in FIG6(I), a reflective cup 410 can also be formed around each individual pixel unit (light-emitting diode), thereby achieving isolation of the individual pixel unit using the reflective cup 410 at the sidewall. Simultaneously, the reflective cup 410 can also improve the internal optical path of the light-emitting diode, increasing its luminous efficiency. In practical applications, the height of the reflective cup 410 is no higher than the second semiconductor layer 240.

[0082] S5, an insulating layer 500 is prepared on the surface of the device.

[0083] Specifically, in this embodiment, an insulating material can be deposited on the device surface using a deposition process to form an insulating layer 500. The thickness of the insulating layer 500 is not limited; it can be relatively thick, as shown in Figure 6(J), thereby completely filling the gap between adjacent light-emitting diodes; or it can be relatively thin, as shown in Figure 6(K), thereby forming an insulating thin film on the device surface.

[0084] S6, patterning is performed on the surface of the insulating layer 500 to expose the first contact layer 210, and the first contact layer 210 is electrically connected.

[0085] Specifically, in this embodiment, after patterning and etching to expose the first contact layer 210, a conductive thin film 600 is prepared on the exposed surface of the light-emitting diode (LED) to achieve cathode connection of the LED. Preferably, to ensure the luminous efficiency of the LED, the conductive thin film can be a transparent conductive film, such as ITO or ZnO. Figures 6(L) and 6(M) are schematic diagrams of the device structure after the conductive thin film 600 is formed on the device structure corresponding to Figures 6(J) and 6(K), respectively.

[0086] Preferably, the patterned metal layer (conductive thin film) can also be cathode-enhanced to achieve electrical extension and optical confinement. Specifically, as shown in Figures 6(N) and 6(O), which are schematic diagrams of the device structure after forming the enhanced cathode 610 on the device structure corresponding to Figure 6(L), the enhanced cathode 610 can be formed on the top of the conductive thin film 600, as shown in Figure 6(N). In this case, the enhanced cathode 610 needs to be formed after the conductive thin film 600 is formed. Alternatively, the enhanced cathode 610 can be formed in the lower part of the conductive thin film 600 and embedded in the insulating layer 500, as shown in Figure 6(O). In this case, after the insulating layer 500 is formed, it needs to be patterned and etched, and then the grooves left after etching are filled with metal to form the enhanced cathode 610, and then the conductive thin film 600 is prepared. Figure 6(P) shows a schematic diagram of the device structure after forming the reinforcing cathode 610 on the device structure corresponding to Figure 6(M). The reinforcing cathode 610 is formed on top of the conductive thin film 600 and located in a groove between adjacent light-emitting diodes. Regardless of the method, the reinforcing cathode 610 should avoid the light-emitting surface of the light-emitting diode, i.e., avoid the first contact layer 210 and the first semiconductor layer 220, thereby ensuring the luminous efficiency of the light-emitting diode.

[0087] Furthermore, in order to achieve better light extraction efficiency and better light pattern constraint, in this embodiment, the manufacturing method further includes: S7, Microlenses 700 are fabricated on the surface of the device after patterning and multi-step processing.

[0088] Specifically, taking the device structure shown in Figure 6(N) as an example, after forming the microlens 700 on it, the device structure is as shown in Figure 6(Q). In practical applications, the existing process for forming the microlens 700 can be used to form the microlens 700 based on the device structure provided in this application, which will not be described in detail here.

[0089] The method for manufacturing a micro light-emitting diode provided in this embodiment effectively reduces the effect of total internal reflection and increases the light transmittance by forming at least one step on the sidewalls of the first semiconductor layer and the first contact layer, and / or forming at least one step on the sidewalls of the second semiconductor layer and the second contact layer. This reduces the loss of light extraction in the functional area and improves the luminous efficiency, thus solving the problem of how to improve the luminous efficiency of micro light-emitting diodes.

[0090] Furthermore, this embodiment also provides a pixel array, which includes a plurality of miniature light-emitting diodes arranged in an array as described above.

[0091] Furthermore, this embodiment also provides a microdisplay screen, which includes the micro light-emitting diodes as described above, or includes the pixel array as described above.

[0092] The circuit connection of each micro light-emitting diode in the pixel array is well known to those skilled in the art, and will not be described in detail here.

[0093] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this utility model does not limit this.

[0094] The micro-light-emitting diode, pixel array, and micro-display provided in this embodiment include a first contact layer, a first semiconductor layer, a functional layer, a second semiconductor layer, and a second contact layer stacked sequentially from bottom to top. The dimensions of the first semiconductor layer and the first contact layer gradually decrease in the direction away from the functional layer, forming at least one step on the sidewalls of the first semiconductor layer and the first contact layer; and / or, the lengths of the second semiconductor layer and the second contact layer gradually decrease in the direction away from the functional layer, forming at least one step on the sidewalls of the second semiconductor layer and the second contact layer. By forming at least one step on the sidewalls of the first semiconductor layer and the first contact layer, and / or forming at least one step on the sidewalls of the second semiconductor layer and the second contact layer, the effects of total internal reflection are effectively reduced, the light transmittance is increased, and the loss of light extraction in the functional area is reduced, thereby improving the luminous efficiency and solving the problem of how to improve the luminous efficiency of micro-light-emitting diodes.

[0095] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A miniature light-emitting diode, characterized in that, It includes a first contact layer, a first semiconductor layer, a functional layer, a second semiconductor layer, and a second contact layer, which are stacked sequentially from bottom to top; The dimensions of the first semiconductor layer and the first contact layer gradually decrease in the direction away from the functional layer, so as to form at least one step on the sidewall of the first semiconductor layer and the sidewall of the first contact layer; And / or, the lengths of the second semiconductor layer and the second contact layer gradually decrease in the direction away from the functional layer, so as to form at least one step on the sidewall of the second semiconductor layer and the sidewall of the second contact layer.

2. The miniature light-emitting diode according to claim 1, characterized in that, The functional layer includes an active region or multiple quantum wells; the first semiconductor layer includes at least one of a first barrier layer, a first confinement layer, and a first waveguide layer; the second semiconductor layer includes at least one of a second barrier layer, a second confinement layer, and a second waveguide layer.

3. The miniature light-emitting diode according to claim 1, characterized in that, The first contact layer and the first semiconductor layer are both P-type or N-type, the second semiconductor layer and the second contact layer are both N-type or P-type, and the types of the first contact layer and the first semiconductor layer are different from the types of the second semiconductor layer and the second contact layer.

4. The miniature light-emitting diode according to claim 1, characterized in that, The first contact layer and the second contact layer are made of metal oxide, metal dopant, single-layer metal, multi-layer metal, or alloy. The metal oxide is ZnO or ITO, the metal dopant is GaP, AlGaAs, GaAs, or GaN, and the single-layer metal, multi-layer metal, or alloy is made of Au, Ag, Zn, Ge, Ni, or Al. The first semiconductor layer or the second semiconductor layer is made of AlInP, AlGaAs, AlGaN, AlGaInP, GaAs, or GaN. The functional layer is made of AlGaInP, AlGaAs, or InGaN.

5. The miniature light-emitting diode according to claim 1, characterized in that, The angle between the sidewall and the bottom of the first contact layer is 90±60°, the angle between the sidewall and the bottom of the first semiconductor layer is 90±45°, the angle between the sidewall and the bottom of the functional layer is 90±45°, the angle between the sidewall and the bottom of the second semiconductor layer is 90±45°, and the angle between the sidewall and the bottom of the second contact layer is 90±60°.

6. The miniature light-emitting diode according to claim 1, characterized in that, The total thickness of the first contact layer and the first semiconductor layer is 100~400nm, the total thickness of the second semiconductor layer and the second contact layer is 100~400nm, and the thickness of the functional layer is 100~300nm; the thickness between the first contact layer and the second contact layer is 0.3~5μm.

7. The miniature light-emitting diode according to claim 1, characterized in that, The micro LED also includes a buffer layer located at the bottom of the first contact layer.

8. The miniature light-emitting diode according to claim 7, characterized in that, The buffer layer is made of AlGaInP, AlGaAs, GaInP, InGaN, or AlN.

9. The miniature light-emitting diode according to claim 1, characterized in that, The micro LED also includes a discontinuous metal layer located on top of the second contact layer.

10. The miniature light-emitting diode according to claim 9, characterized in that, The discontinuous metal layer comprises a mirror layer, a barrier layer, and a bonding metal layer arranged sequentially from bottom to top; the mirror layer is made of Au, Ag, Al, Ni / Ag, Ni / Al, Ag / Al, Ag / Ni / Au, Al / Ni / Au, Ir / Ag, or AuBe / Ag; the bonding metal layer is made of Au, Cu, AuSn, or CuSn; and the barrier layer is made of one or more of Ti, Ni, Pt, Cr, TiN, and TaN.

11. A pixel array, characterized in that, The pixel array includes a plurality of miniature light-emitting diodes arranged in an array as described in any one of claims 1 to 10.

12. A micro-display screen, characterized in that, The microdisplay includes a micro light-emitting diode as described in any one of claims 1 to 10, or includes a pixel array as described in claim 11.

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