Semiconductor device

Abstract

A semiconductor device (e.g., a microdisplay device) includes isolation structures around sub-pixels of at least a portion of display pixels in a display pixel array of the semiconductor device. The isolation structures (e.g., isolation trenches, isolation rings) confine light generated by the sub-pixels such that the light generated by the sub-pixels can be highly enclosed and collimated. As a result, the isolation structures reduce lateral scattering of light emitted by the sub-pixels, which reduces the amount of cross-color between the sub-pixels. This enables the display pixel array to produce images and / or movies with high-precision color representation and high contrast ratio, among other things.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] A microdisplay device is a display device formed on a semiconductor wafer. Microdisplay devices enable organic displays to be integrated with complementary metal-oxide-semiconductor (CMOS) technology to achieve low power consumption, high resolution, fast response time, and high contrast. Applications of microdisplay devices include camera sensors, near-eye (NTE) displays, and / or projection systems. Utility Model Content

[0003] According to one embodiment of the present invention, a semiconductor device includes a display pixel array, the display pixel array including a plurality of display pixels. One of the plurality of display pixels includes a first electrode, a dielectric region above the first electrode, a light-generating film stack above the dielectric region, a second electrode above the light-generating film stack, and an isolation structure laterally surrounding the dielectric region.

[0004] According to another embodiment of the present invention, a semiconductor device includes a semiconductor substrate. This semiconductor device includes a plurality of integrated circuit devices within the semiconductor substrate. The semiconductor device includes an interconnect layer located above the semiconductor substrate. The semiconductor device includes a display pixel array located above the interconnect layer, the display pixel array including a plurality of display pixels. One of the plurality of display pixels includes a plurality of sub-pixels. Each of the plurality of sub-pixels includes a bottom electrode, a resonant region above the bottom electrode, a light-generating film stack above the resonant region, a top electrode above the light-generating film stack, and an isolation structure laterally surrounding the resonant region. Attached Figure Description

[0005] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 This is a diagram of an example of the subpixel circuit described in this article.

[0007] Figure 2A-2C This is a diagram of an example of the semiconductor device described in this article.

[0008] Figure 3 This is a diagram illustrating an exemplary implementation of a subpixel in a display pixel of a semiconductor device described herein.

[0009] Figure 4A and Figure 4B This is a diagram illustrating an example of the display operation of a display pixel in a semiconductor device described in this article.

[0010] Figures 5A-5D This is a diagram of an exemplary embodiment that forms part of the semiconductor device described herein.

[0011] Figure 6A-6I This is a diagram of an exemplary embodiment that forms part of the semiconductor device described herein.

[0012] Figure 7 This is a flowchart of an exemplary process associated with the formation of the semiconductor device described in this article.

[0013] Figure 8 This is a flowchart of an exemplary process associated with the formation of the semiconductor device described in this article. Detailed Implementation

[0014] The following disclosure discloses numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second features. The first and second features are arranged such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature shown in the accompanying drawings and another element. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0016] A microdisplay device may include an array of display pixels above an interconnect layer of the microdisplay device. The interconnect layer electrically connects the display pixel array to an integrated circuit in a semiconductor layer of the microdisplay device that controls the operation of the display pixel array. The display pixel array generates light by emitting photons generated by an organic emitting layer stack between a set of electrodes. The electrodes generate a current that excites the organic emitting layer stack (e.g., through the integrated circuit in the semiconductor layer), and the organic emitting layer stack emits photons under excitation.

[0017] A display pixel array can include multiple subpixels, each with a different type of color filter. For example, a red, green, and blue (RGB) display pixel can include red, green, and blue subpixels, each with a red, green, and blue color filter for filtering specific wavelengths of light emitted by the display pixel. Subpixels, or display pixels, can be activated in various combinations to achieve the overall color of the light emitted by the display pixel.

[0018] In some cases, color mixing can occur between subpixels and display pixels. Color mixing refers to the light produced when one subpixel passes through the color filter of another subpixel due to lateral scattering of light. Color mixing can lead to inaccurate color representation of display pixels. If color mixing occurs on a display pixel array, the image or video displayed by the display pixel array may exhibit inaccurate color representation of the displayed content and / or may exhibit low contrast, etc.

[0019] In some embodiments described herein, a semiconductor device (e.g., a microdisplay device) includes an isolation structure surrounding at least a portion of the subpixels of a display pixel array within the semiconductor device. The isolation structure (e.g., an isolation trench, an isolation ring) confines the light emitted by the subpixels, allowing the light to be highly confined and collimated. Therefore, the isolation structure reduces lateral scattering of light emitted by the subpixels, which reduces color mixing between subpixels. This enables the display pixel array to produce images and / or videos with high-precision color performance and high contrast, among other things.

[0020] Figure 1This is a diagram illustrating an example of the subpixel circuit 100 described herein. The subpixel circuit 100 may include a subpixel 102 configured to generate light and a driving circuit 104 electrically coupled to the subpixel 102. The subpixel 102 may include a light-emitting diode (LED) based subpixel, such as an organic LED (OLED) subpixel. The driving circuit 104 may include a combination of active integrated circuit devices and passive integrated circuit devices configured to control access to and operation of the subpixel 102. Therefore, the subpixel circuit 100 may include an active-matrix OLED (AMOLED) pixel circuit.

[0021] The driving circuit 104 is electrically coupled to the scan line 106 and the data transmission line 108. The scan line 106 and the data transmission line 108 enable independent selection and activation of sub-pixel circuits 100 within a matrix of multiple sub-pixel circuits 100 in the display pixel array. The scan line 106 is electrically coupled to the gate of the switching transistor 110 in the driving circuit 104. The data transmission line 108 is electrically coupled to the source / drain of the switching transistor 110. "Source / drain" refers to the source, drain, or a combination of source and drain, depending on the context. The switching transistor 110 enables the sub-pixel 102 to be selectively turned on or off. For example, a signal can be selectively applied to the gate of the switching transistor 110 through the scan line 106 to selectively activate or deactivate the sub-pixel circuit 100.

[0022] Another source / drain of the switching transistor 110 is electrically connected to the storage capacitor 112 and the driving transistor 114. The sources / drains of the storage capacitor 112 and the driving transistor 114 are electrically coupled to the current source 116. The driving transistor 114 drives the sub-pixel 102 based on the current supplied from the current source 116. The magnitude of the current supplied to the sub-pixel 102 (and therefore the brightness of the sub-pixel 102) can be controlled by the gate of the driving transistor 114. Specifically, a drive signal can be provided from the data transmission line 108 to the switching transistor 110 to the gate of the driving transistor 114 to control the magnitude of the current supplied to the sub-pixel 102. The storage capacitor 112 may be included to stabilize the drive signal, thereby stabilizing the brightness of the sub-pixel 102 and reducing and / or minimizing the flicker of the sub-pixel 102.

[0023] The transistors in the driving circuit 104 (including the switching transistor 110 and the driving transistor 114) can be physically implemented as thin-film transistors (TFTs), fin field-effect transistors (FFETs), nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate-on-a-base (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors), and / or other types of transistor structures. The capacitors in the driving circuit 104 (including the storage capacitor 112) can be physically implemented as planar metal-insulator-metal (MIM) capacitors, deep trench capacitors (DTCs), and / or other types of capacitor structures.

[0024] In some implementations, multiple subpixel circuits 100 may be physically grouped and / or logically grouped together to form display pixels in a display pixel array. Each of the subpixel circuits 100 and each display pixel may be configured to produce light of a specific color. The subpixel circuits 100 of the display pixels may be independently controlled and driven such that the colors of the subpixel circuits 100 may be mixed to produce a wide color gamut of the display pixels.

[0025] As mentioned above, Figure 1 This is provided as an example. Other examples may be similar. Figure 1 The differences are not described herein. Specifically, other configurations of the sub-pixel circuit 100 are also within the scope of this disclosure. The driving circuit 104 may include [missing information - likely related to a specific circuit or module]. Figure 1 The different components, different numbers of components, and / or different arrangements and / or connections of components shown. The drive circuit 104 may include additional components for implementing brightness compensation, increasing frame rate, and / or other functions.

[0026] Figure 2A-2C This is a diagram of an example of the semiconductor device 200 described in this article. Figure 2A A top view of the semiconductor device 200 is shown. (As shown) Figure 2A As shown, the semiconductor device 200 may include a display device having a display pixel array 202. The display pixel array 202 includes a plurality of display pixels 204, which are configured to centrally generate images and / or videos. In some embodiments, the display pixels 204 are arranged in a grid, such as... Figure 2A The example shown is illustrated in the diagram. However, other arrangements of display pixels 204 in display pixel array 202 are also within the scope of this disclosure. In some embodiments, display pixels 204 include OLED display pixels, and display pixel array 202 includes an OLED display. However, other types of display pixels and display pixel arrays are also within the scope of this disclosure.

[0027] like Figure 2AAs further shown, a display pixel 204 may comprise a plurality of subpixels 102. For example, a display pixel 204 may include a subpixel 102a configured to emit light of a first color (e.g., red light), a subpixel 102a configured to emit light of a second color (e.g., green light), and a subpixel 102a configured to emit light of a third color (e.g., blue light). However, other configurations and combinations of the subpixels 102 of the display pixel 204 are also within the scope of this disclosure. Two or more subpixels 102 in the display pixel 204 may have the same size and / or shape, or two or more subpixels 102 in the display pixel 204 may have different sizes and / or different shapes, or combinations thereof.

[0028] like Figure 2A As further shown, isolation structure 206 is included around one or more sub-pixels 102a-102c in display pixel 204. Isolation structure 206 may be included around the periphery of sub-pixels 102 of display pixel 204 to limit the light emitted by sub-pixels 102 and prevent, minimize, and / or otherwise reduce the diffusion of light emitted by sub-pixels 102 into areas of display pixel 204 occupied by other sub-pixels 102. For example, isolation structure 206 may be included around the periphery of sub-pixels 102a of display pixel 204 to prevent, minimize, and / or otherwise reduce the diffusion of light emitted by sub-pixels 102a into sub-pixels 102b and 102c of display pixel 204. As another example, isolation structure 206 may be included around the periphery of sub-pixels 102b of display pixel 204 to prevent, minimize, and / or otherwise reduce the diffusion of light emitted by sub-pixels 102b into sub-pixels 102a and 102c of display pixel 204. As another example, isolation structure 206 may be included around the periphery of subpixel 102c of display pixel 204 to prevent, minimize and / or otherwise reduce the diffusion of light emitted by subpixel 102c into subpixels 102a and 102b of display pixel 204.

[0029] The isolation structure 206 may include a closed-loop isolation structure that completely surrounds the periphery of the relevant sub-pixel 10.

[0030] The isolation structure 206 may include a closed-loop trench (e.g., a deep trench isolation (DTI) structure) in the semiconductor device 200 and / or other types of structures that extend in the z-direction (e.g., the vertical direction). The top view shape of the isolation structure 206 may conform to the shape of the sub-pixel 102 and may include a closed-loop isolation ring, a closed-loop isolation square, a closed-loop isolation rectangle, and / or other closed-loop shapes.

[0031] In some embodiments, the isolation structure 206 includes one or more materials having low reflectivity in the visible light spectrum to minimize halos and other types of display degradation in images and / or videos generated by the display pixel array 202. For example, the isolation structure 206 may include titanium nitride (TiN) (e.g., having a specular reflectance of about 50% or less in the visible light spectrum from about 380 nm to about 750 nm). In some embodiments, the isolation structure 206 includes one or more materials having high reflectivity in the visible light spectrum to achieve low light loss and enable the display pixel array 202 to achieve a large display brightness. For example, the isolation structure 206 may include copper (Cu), aluminum (Al), and / or tungsten (W), etc.

[0032] Figure 2B An example display with 204 pixels along the edge is shown. Figure 2A The cross-sectional view of lines AA and BB in the diagram. Figure 2B The cross-sectional view shows an exemplary structural arrangement of sub-pixel circuits 100a-100c for sub-pixels 102a-102c of display pixel 204. For example... Figure 2B As shown, the semiconductor device 200 may include a microdisplay device, wherein sub-pixels 102 of the display pixel array 202 are included on the semiconductor device 200. Therefore, the semiconductor device 200 may include an OLED on silicon device, a display on silicon device, and / or other types of microdisplay devices, wherein the display pixel array 202 is integrated on a semiconductor device having CMOS integrated circuits.

[0033] like Figure 2B As shown, the sub-pixels 102 of the display pixel array 202 are contained above the device layer 208 and interconnect layer 210 of the semiconductor device 200. The device layer 208 may include a semiconductor layer 212 corresponding to a portion of the semiconductor wafer on which the semiconductor device 200 is formed. The semiconductor layer 212 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates.

[0034] The device layer 208 includes an integrated circuit device 214 in and / or above the semiconductor layer 212. The integrated circuit device 214 may include components of a driving circuit 104, such as that of the sub-pixel circuits 100a-100c of the display pixel 204. For example, the integrated circuit device 214 may include a switching transistor 110, a storage capacitor 112, a driving transistor 114, and / or other components of the driving circuit 104. The transistors of the driving circuit 104 (e.g., the switching transistor 110, the driving transistor 114) may be implemented as planar transistors, finFETs, GAA transistors, and / or other types of transistors in and / or above the semiconductor layer 212.

[0035] The interconnect layer 210 includes conductive structures that interconnect the integrated circuit devices 214 of the driving circuit 104 and electrically connect the integrated circuit devices 214 of the driving circuit 104 to the sub-pixels 102 of the sub-pixel circuits 100a-100c. The interconnect layer 210 includes one or more dielectric layers 216 arranged along a direction generally perpendicular to the semiconductor layer 212 (e.g., the z-direction). Each dielectric layer 216 may each include a back-end dielectric layer (e.g., an interlayer dielectric (ILD) layer, an intermetallic dielectric (IMD) layer) and an etch stop layer (ESL) arranged alternately in the interconnect layer 210. Each dielectric layer 216 may each include an oxide (e.g., silicon oxide (SiO2)). x (and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorinated silicate glass (FSG), extremely low dielectric constant (ELK) dielectric materials with a dielectric constant less than about 2.5, silicon nitride (Si) x N y ), silicon carbide (SiC), silicon oxynitride (SiON) and / or other suitable dielectric materials.

[0036] The conductive structures in the dielectric layer 216 of the interconnect layer 210 may include metallization layers 218 (e.g., trenches, conductive lines) interconnected through interlayer connection structures 220 (e.g., vias). The metallization layer 218 and the interlayer connection structure 220 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0037] The conductive structures of interconnect layer 210 may be arranged vertically (e.g., in the z-direction) to facilitate the routing of electrical signals and / or power between integrated circuit devices 214 in device layer 208 and sub-pixels 102 above interconnect layer 210 and / or between integrated circuit devices 214 through interconnect layer 210. The conductive structures may be configured in alternating layers of metallization layers 218 (referred to as “M” layers) and interlayer connection structures 220 (referred to as “V” layers). Each metallization layer 218 (e.g., each M layer) may include one or more metallization layers 218 arranged laterally in interconnect layer 210, and each interlayer connection structure 220 (e.g., each V layer) may include one or more interlayer connection structures 220 interconnecting metallization layers 218 between vertically adjacent metallization layers 218 in interconnect layer 210. As an example, a metal 0 (M0) layer may be located at the bottom of interconnect layer 210 and coupled to integrated circuit device 214 in device layer 208; a via 1 (V1) layer may be located above and coupled to the M1 layer in interconnect layer 210; a metal 1 (M1) layer may be located above and coupled to the V1 layer in interconnect layer 210; a via 2 (V2) layer may be located above and coupled to the M1 layer in interconnect layer 210; a metal 2 (M2) layer may be located above and electrically coupled to the V2 layer in interconnect layer 210, and so on. In some embodiments, interconnect layer 210 includes nine (9) stacked metallization layers (e.g., M0-M8). In some embodiments, interconnect layer 210 includes another number of stacked metallization layers.

[0038] The top of the interconnect layer 210 is a passivation layer 222, with top metal pads 224 located within the passivation layer 222, and top metal vias 226 located on the top metal pads 224 within the passivation layer 222. The passivation layer 222 may comprise an oxide (e.g., silicon oxide (SiO2)). x (and / or another oxide material), USG, ELK dielectric material, and / or another suitable dielectric material. The top metal pad 224 and the top metal via 226 may each comprise one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0039] like Figure 2B As further shown, sub-pixels 102 of display pixel 204 are contained above interconnect layer 210 of semiconductor device 200. A portion of sub-pixels 102 is contained in a cavity oxide layer 228 above passivation layer. Cavity oxide layer 228 may comprise silicon oxide (SiOx, such as SiO2) and / or another optically transparent (or semi-transparent) dielectric material.

[0040] Each sub-pixel 102 may include a first electrode 230 (e.g., an anode) located at the bottom of the cavity oxide layer 228. The first electrode 230 may be included on the passivation layer 222 and may be electrically connected to the top metal via 226 of the interconnect layer 210. This allows electrical input from the driving circuitry 104 to be applied to the sub-pixel 102 through the first electrode 230. The first electrode 230 may be referred to as the bottom electrode and may include one or more reflective materials, such as aluminum (Al), tungsten (W), and / or copper (Cu). The reflective material of the first electrode 230 enables it to reflect light emitted by the sub-pixel 102 (e.g., reflect light upwards) to minimize the amount of light lost into the interconnect layer 210.

[0041] like Figure 2B As shown, each of the first electrodes 230 has a thickness in the z-direction (vertical), which includes the first thickness of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100a. Figure 2B (represented as dimension D1), the second thickness of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100b ( Figure 2B (represented as dimension D2), the third thickness of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100c ( Figure 2B (Represented as size D3), etc. In some embodiments, the first electrode 230 in two or more sub-pixels 102 is formed with approximately the same thickness in the z-direction. For example, sizes D1, D2, and D3 may all be approximately equal.

[0042] In some implementations, the first electrodes 230 in two or more sub-pixels 102 are formed with different z-direction thicknesses. This allows for different z-direction thicknesses to be achieved for the resonant cavity 232 of the sub-pixel 102. The resonant cavity 232 of the sub-pixel 102 includes a dielectric region (e.g., a resonant region) of a cavity oxide layer 228 above the first electrodes 230 of the sub-pixel 102, where a specific wavelength of light generated by the sub-pixel 102 can be amplified. The top surface of the cavity oxide layer 228 can be substantially flat and uniform over the entire cavity oxide layer 228. Furthermore, the bottom surfaces of the sub-pixel 102 with the first electrodes 230 can be substantially coplanar. Therefore, the thickness of the resonant cavity 232 of the sub-pixel 102 is based on the z-direction thickness of the first electrodes 230 of the sub-pixel 102. The greater the thickness of the first electrode 230 of a sub-pixel 102, the smaller the z-direction thickness of the resonant cavity 232 of the sub-pixel 102. Conversely, the smaller the thickness of the first electrode 230 of the sub-pixel 102, the larger the thickness of the resonant cavity 232 of the sub-pixel 102 in the z direction.

[0043] As an example, the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100c can be formed such that the z-direction thickness (dimension D3) of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100c is greater than the z-direction thickness (dimension D2) of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100b, and greater than the z-direction thickness (dimension D1) of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100a. This causes the z-direction thickness of the resonant cavity 232 of the sub-pixel 102 of the sub-pixel circuit 100c to be configured to amplify light with shorter wavelengths (e.g., blue light) than that of the sub-pixel 102 of the sub-pixel circuits 100a and 100b.

[0044] As another example, the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100a can be formed such that the z-direction thickness (dimension D1) of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100a is smaller than the z-direction thickness (dimension D2) of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100b, and smaller than the z-direction thickness (dimension D3) of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100c. This results in the z-direction thickness of the resonant cavity 232 of the sub-pixel 102 of sub-pixel circuit 100a being configured to amplify light with a longer wavelength (e.g., red light) than that of the sub-pixel 102 of sub-pixel circuits 100b and 100c. The bottom surface of the resonant cavity 232 can be closer to the interconnect layer 210 than the resonant cavities 232 of the other sub-pixels 102.

[0045] As another example, the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100b can be formed such that the z-direction thickness (dimension D2) of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100b is smaller than the z-direction thickness (dimension D3) of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100c, and smaller than the z-direction thickness (dimension D1) of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100a. This results in the z-direction thickness of the resonant cavity 232 of the sub-pixel 102 of the sub-pixel circuit 100a being configured to amplify light wavelengths (e.g., green light) between those emitted by the sub-pixels 102 of the sub-pixel circuits 100a and 100c.

[0046] The different z-direction thicknesses of the first electrode 230 of the sub-pixel 102 in the sub-pixel circuits 100a-100c result in the top surface of the first electrode 230 being located at different vertical (z-direction) heights within the semiconductor device 200. Furthermore, the different z-direction thicknesses of the first electrode 230 of the sub-pixel 102 in the sub-pixel circuits 100a-100c result in the bottom surface of the resonant cavity 232 being located at different vertical (z-direction) heights within the semiconductor device 200.

[0047] For example, the z-direction thickness of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100b is greater than the z-direction thickness of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100a (e.g., dimension D2 > dimension D1), causing the top surface of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100b to be located at a greater z-direction height in the semiconductor device 200 than the top surface of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100a. As another example, the z-direction thickness of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100b is greater than the z-direction thickness of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100a (e.g., dimension D2 > dimension D1), causing the bottom surface of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100b to be located in the semiconductor device 200 at a lower z-direction position than the bottom surface of the first electrode 230 of the sub-pixel 102 of the sub-pixel circuit 100a.

[0048] As another example, the z-direction thickness of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100c is greater than the z-direction thickness of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100b (e.g., dimension D3 > dimension D2), causing the top surface of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100c to be located at a greater z-direction height in the semiconductor device 200 than the top surface of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100b. As another example, the z-direction thickness of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100c is greater than the z-direction thickness of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100b (e.g., dimension D3 > dimension D2), causing the bottom surface of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100c to be located at a lower z-direction position in the semiconductor device 200 than the top surface of the first electrode 230 of the sub-pixel 102 of sub-pixel circuit 100b.

[0049] like Figure 2B As further shown, an isolation structure 206 is included above the first electrode 230 of the sub-pixel 102 of the sub-pixel circuits 100a-100c. The isolation structure 206 may include an elongated structure (e.g., a deep trench) extending from the top of the cavity oxide layer 228 into the cavity oxide layer 228 to the first electrode 230 of the sub-pixel 102. The isolation structure 206 may extend to the top surface of the first electrode 230 of the sub-pixel 102, or to a portion of the first electrode 230, to provide a continuous barrier surrounding the resonant cavity 232 of the sub-pixel 102. This minimizes the amount of light emitted by the sub-pixel 102 that laterally diffuses into adjacent sub-pixels 102.

[0050] The isolation structure 206 can have the following properties: Figure 2BThe z-direction thickness (or z-direction height) is indicated by dimension D4. In some embodiments, the z-direction thickness (dimension D4) of the isolation structures 206 of the sub-pixels 102 in the display pixel 204 is substantially the same. In these embodiments, the bottom surfaces of the isolation structures 206 may be substantially coplanar and located at substantially the same z-direction depth in the semiconductor device 200. The z-direction thickness (dimension D4) of each isolation structure 206 of the sub-pixels 102 in the display pixel 204 may be selected such that the isolation structure 206 of the sub-pixel 102 having the thinnest first electrode 230 at least falls on the top surface of the first electrode 230. In some embodiments, the z-direction thickness (dimension D4) of the isolation structures 206 of two or more sub-pixels 102 in the display pixel 204 is different.

[0051] like Figure 2B As further shown, sub-pixel 102 may include a pixel definition layer 234, a substrate layer 236, and another pixel definition layer 238, which are included to define the position of the light generation filmstack 240 of sub-pixel 102. Pixel definition layer 234, substrate layer 236, and pixel definition layer 238 may each include one or more optically transparent or translucent materials, such as silicon oxide (SiOx, e.g., SiO2), indium tin oxide (ITO), indium zinc oxide (IZO), and / or another optically transparent (or translucent) material.

[0052] The light-generating film stack 240 of sub-pixel 102, together with the second electrode 242 above the light-generating film stack 240, is included in the pixel definition layer 238. Each of the light-generating film stacks 240 comprises multiple layers of organic material capable of generating and emitting light based on electrical inputs applied to the first electrode 230 and the second electrode 242. Figure 2C An example of a light-generating film stack 240 is shown and described. The second electrode 242 may be referred to as the top electrode and may comprise one or more optically transparent and conductive materials, such as ITO and / or IZO.

[0053] The second electrode 242 includes a passivation layer 244, and the passivation layer 244 includes a color filter 246. The color filter 246 of the sub-pixel 102 filters specific wavelengths of light emitted by the light-generating thin film stack 240 of the sub-pixel 102, and allows other wavelengths to pass through the color filter 246. For example, the "blue" color filter 246 allows wavelengths corresponding to blue visible light to pass through and blocks wavelengths corresponding to other colors of visible light. As another example, the "green" color filter 246 allows wavelengths corresponding to green visible light to pass through and blocks wavelengths corresponding to other colors of visible light. As another example, the "red" color filter 246 allows wavelengths corresponding to red visible light to pass through and blocks wavelengths corresponding to other colors of visible light.

[0054] Figure 2C An example of a light-generating film stack 240 that may be included in a sub-pixel 102 of a display pixel 204 in a display pixel array 202 of a semiconductor device 200 is shown. The display pixel 204 in the display pixel array 202 may include an OLED pixel. Therefore, the light-generating film stack 240 of the sub-pixel 102 may include one or more layers of organic material, including an emission layer formed of one or more organic materials. These layers may include a hole injection layer 248, a hole transport layer 250 on the hole injection layer 248, an electron blocking layer 252 on the hole transport layer 250, an emission layer 254 on the electron blocking layer 252, a hole blocking layer 256 on the emission layer 254, an electron transport layer 258 on the hole blocking layer 256, and / or an electron injection layer 260 on the electron transport layer 258, etc.

[0055] Hole injection layer 248 is configured to inject holes into emitter layer 254 via hole transport layer 250 when an electrical input is applied to hole injection layer 248 through first electrode 230 (e.g., anode) of sub-pixel 102. Electron injection layer 260 is configured to inject electrons into emitter layer 254 via electron transport layer 258 when an electrical input is applied to electron injection layer 260 through second electrode 242 (e.g., cathode) of sub-pixel 102. Hole blocking layer 256 is configured to suppress the propagation of holes generated by hole injection layer 248 through emitter layer 254, and electron blocking layer 252 is configured to suppress the propagation of electrons generated by electron injection layer 260 through emitter layer 254. Emitter layer 254 includes one or more organic materials capable of emitting light based on holes and electrons injected into emitter layer 254. For example, emitter layer 254 may include one or more organic fluorescent emitting materials and / or one or more phosphorescent emitting materials, etc.

[0056] As mentioned above, providing Figure 2A-2C As an example. Other examples can be found related to... Figure 2A-2C The descriptions are different.

[0057] Figure 3 This is a diagram of an exemplary embodiment 300 of a sub-pixel 102 in a display pixel 204 of the semiconductor device 200 described herein. Specifically, exemplary embodiment 300 includes various examples of a first electrode 230 and an isolation structure 206 for the sub-pixel 102 of the display pixel 204.

[0058] like Figure 3 As shown, the first electrode 230 (e.g., bottom electrode or anode) of the sub-pixels 102a-102c of the display pixels 204 of the semiconductor device 200 is formed on the passivation layer 222, such that the first electrode 230 is electrically connected to the top metal via 226. For different sub-pixels, the first electrode 230 can be formed with different z-direction thicknesses. This allows the resonant cavity of the sub-pixels to achieve different z-direction thicknesses.

[0059] For example, since sub-pixel 102c is a blue sub-pixel configured to emit light (e.g., blue light) with a shorter wavelength than sub-pixels 102a and 102b, the first electrode 230 of sub-pixel 102c can be formed such that the z-direction thickness of the first electrode 230 of sub-pixel 102c is greater than the z-direction thickness of the first electrode 230 of sub-pixel 102b and the z-direction thickness of the first electrode 230 of sub-pixel 102a. The first electrode 230 of sub-pixel 102c is formed such that the size of the resonant cavity of sub-pixel 102c is favorable for the resonance of the wavelength of sub-pixel 102c.

[0060] As another example, because sub-pixel 102b is a green light sub-pixel configured to emit light (e.g., green light) with a shorter wavelength than that of sub-pixel 102a (e.g., which can be configured to emit red light), the first electrode 230 of sub-pixel 102b can be formed such that the z-direction thickness of the first electrode 230 of sub-pixel 102b is greater than the z-direction thickness of the first electrode 230 of sub-pixel 102a. The first electrode 230 of sub-pixel 102b is formed such that the size of the resonant cavity of sub-pixel 102b is favorable for the resonance of the wavelength of sub-pixel 102b.

[0061] As another example, since sub-pixel 102a is a red light sub-pixel configured to emit light (e.g., red light) with a longer wavelength than sub-pixels 102b and 102c, the first electrode 230 of sub-pixel 102a can be formed such that the z-direction thickness of the first electrode 230 of sub-pixel 102a is less than the z-direction thickness of the first electrode 230 of sub-pixel 102b and the z-direction thickness of the first electrode 230 of sub-pixel 102c. The first electrode 230 of sub-pixel 102a is formed such that the size of the resonant cavity of sub-pixel 102a is favorable for the resonance of the wavelength of sub-pixel 102a.

[0062] The nitride layer 302 may be included on the passivation layer 222. The nitride layer 302 may include tantalum nitride (TaN) and / or another nitride-containing material. The nitride layer 302 may serve as a barrier layer for the first electrode 230 and / or promote adhesion between the first electrode 230 and the passivation layer 222.

[0063] like Figure 3 As further shown, each first electrode 230 may include one or more metal layers 304 and one or more nitride layers 306 disposed on a nitride layer 302. For example, the first electrode 230 in sub-pixel 102a (e.g., the red sub-pixel) may include a metal layer 304 on a nitride layer 302. As another example, the first electrode 230 of sub-pixel 102b may include multiple metal layers 304 and nitride layers 306 between the metal layers 304. The metal layers 304 and nitride layers 306 are arranged alternately along the z-direction in the semiconductor device 200. As another example, the first electrode 230 of sub-pixel 102c may include multiple metal layers 304 and multiple nitride layers 306 between the metal layers 304. The metal layers 304 and nitride layers 306 are arranged alternately along the z-direction in the semiconductor device 200.

[0064] The alternating arrangement of metal layer 304 and nitride layer 306 enables one or more first electrodes 230 to effectively function as a multilayer mirror. Metal layer 304 may comprise one or more reflective metals, such as aluminum (Al), molybdenum (Mo), and / or tungsten. Nitride layer 306 may comprise a metal nitride layer, including titanium nitride (TiN) and / or another metal nitride. Alternatively, silicon (Si) and / or other materials may be used instead of nitride layer 306.

[0065] like Figure 3 As further shown, in some sub-pixels 102, the bottom surface of the isolation structure 206 may rest on the top surface of the topmost metal layer 304 of the first electrode 230. In other sub-pixels 102, the bottom surface of the isolation structure 206 may extend into the first electrode 230. Therefore, the isolation structure 206 may extend through one or more metal layers 304 and / or one or more nitride layers 306 in the first electrode 230.

[0066] The isolation structure 206 may include a groove structure that extends in the z-direction, such that the z-direction thickness of the isolation structure 206 (in Figure 3 The dimension D4 is greater than the lateral width of the isolation structure 206 at the top of the isolation structure 206. Figure 3 The dimension is represented as D5, and is greater than the lateral width of the isolation structure 206 at the bottom of the isolation structure 206. Figure 3(Dimension D6). In some embodiments, the isolation structure 206 has a tapered cross-sectional profile, such that the lateral width (dimension D5) of the isolation structure 206 at the top of the isolation structure 206 is greater than the lateral width (dimension D6) of the isolation structure 206 at the bottom of the isolation structure 206.

[0067] like Figure 3 As further shown, the isolation structure 206 may include an isolation layer 308 and one or more pads 310 between the isolation layer 308 and the cavity oxide layer 228. The isolation layer 308 may include copper (Cu), tungsten (W), titanium nitride (TiN), and / or other suitable materials. The one or more pads 310 may include a tantalum nitride (TaN) barrier layer, a tantalum (Ta) barrier layer, a copper (Cu) layer, and / or another type of pad.

[0068] As mentioned above, Figure 3 This is provided as an example. Other examples may be similar. Figure 3 The differences described in [the text].

[0069] Figure 4A and Figure 4B This is a diagram of an example 400 of the display operation of the display pixel 204 of the semiconductor device 200 described herein. (See diagram 400 for example.) Figure 4A As shown, each sub-pixel 102 of the display pixel array 202 of the semiconductor device 200 can be configured to emit light rays 402. To emit light rays 402, an electrical input (e.g., current, voltage) is applied to a first electrode 230 and a second electrode 242 of the sub-pixel 102. The electrical input can be applied through a driving circuit 104 associated with the sub-pixel 102.

[0070] An electrical input applied to the first electrode 230 (e.g., anode) causes the hole injection layer 248 to inject holes 404 through the hole transport layer 250 into the emission layer 254 of the light-generating film stack 240 (e.g., an organic thin film stack) of the sub-pixel 102. The hole blocking layer 256 of the light-generating film stack 240 inhibits the propagation of holes 404 through the emission layer 254. An electrical input applied to the second electrode 242 (e.g., cathode) causes the electron injection layer 260 to inject electrons 406 through the electron transport layer 258 into the emission layer 254. The electron blocking layer 252 of the light-generating film stack 240 inhibits the propagation of electrons 406 through the emission layer 254. The injected holes 404 and electrons 406 are localized on the same molecule in the emission layer 254, resulting in the formation of excitons, which are localized electron-hole pairs with excited energy states. When the exciton relaxes due to photoemission, light ray 402 is emitted from sub-pixel 102.

[0071] The light 402 emitted from the light-generating thin-film stack 240 of sub-pixel 102 can contain "white light" because the light 402 contains light across multiple wavelengths spanning the visible light spectrum. At least a portion of the light 402 propagates downward in the z-direction through the resonant cavity 232 and is reflected from the first electrode 230 (which is reflective), and the first electrode 230 can reflect the light 402 upward toward the color filter 246 of the sub-pixel 102. The isolation structure 206 that laterally surrounds the resonant cavity 232 confines the light 402 within the sub-pixel 102 and minimizes the amount of light 402 diffusing into adjacent sub-pixels 102.

[0072] Light 402 can propagate through the second electrode 242 (which can be transparent or translucent) and through the color filter 246. The color filter 246 filters the light 402 so that only light 402 of a specific wavelength passes through the color filter 246 and is emitted from the sub-pixel 102. The dimensions of the resonant cavity 232 are designed (e.g., in the z-direction) such that these specific wavelengths are amplified.

[0073] Figure 4B Examples are shown of the light intensity 408 of different wavelengths 410 of the emitted light rays 402 of sub-pixels 102a-102c configured to emit visible light of different colors. For example... Figure 4B As shown, sub-pixel 102 of sub-pixel circuit 100a can be configured to emit light with the longest wavelength (e.g., red light), sub-pixel 102 of sub-pixel circuit 100c can be configured to emit light with the shortest wavelength (e.g., blue light), and sub-pixel 102 of sub-pixel circuit 100b can be configured to emit light with wavelengths between those emitted by sub-pixel circuits 100a and 100c (e.g., green light). However, sub-pixel 102 of sub-pixel circuits 100a-100c can be configured to emit other combinations of light wavelengths.

[0074] like Figure 4B As further shown, the isolation structure 206 is included in the resonant cavity 232 surrounding the first electrode 230 and laterally surrounding the sub-pixels 102a-102c, reducing and / or minimizing the mixing (or overlap) of wavelengths of light emitted by the sub-pixels 102a-102c. For example, the range of light emitted by sub-pixels 102a can be from about 550 nanometers to about 650 nanometers, the range of light emitted by sub-pixels 102b can be from about 500 nanometers to about 650 nanometers, and the range of light emitted by sub-pixels 102c can be from about 425 nanometers to about 500 nanometers.

[0075] As mentioned above, providing Figure 4A and 4B As an example. Other examples can be found related to... Figure 4A and 4B The descriptions are different.

[0076] Figures 5A-5D This is a diagram of an exemplary embodiment 500 that forms part of the semiconductor device 200 described herein. Specifically, exemplary embodiment 500 may include examples of forming the device layer 208 and interconnect layer 210 of the semiconductor device 200, including driving circuitry 104 of the sub-pixel circuitry 100 of the display pixel array 202 of the semiconductor device 200. In some embodiments, one or more semiconductor processing tools may be used to perform one or more of the operations described in connection with exemplary embodiment 500, such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, and / or another type of semiconductor processing tool.

[0077] Turn Figure 5A A semiconductor layer 212 may be provided. The semiconductor layer 212 may be provided in the form of a silicon (Si) wafer, a semiconductor die, and / or a semiconductor wafer of another type of semiconductor workpiece.

[0078] like Figure 5B As shown, integrated circuit device 214 can be formed in and / or over semiconductor layer 212 in device layer 208 of semiconductor device 200. One or more semiconductor processing tools can be used to form one or more portions of integrated circuit device 214. For example, deposition tools can be used to perform various deposition operations to deposit layers of integrated circuit device 214, and / or deposit photoresist layers for etching portions of semiconductor layer 212 and / or deposited layers. As another example, exposure tools can be used to expose photoresist layers to form patterns in the photoresist layers. As another example, development tools can be used to develop patterns in the photoresist layers. As another example, etching tools can be used to etch portions of semiconductor layer 212 and / or deposited layers to form integrated circuit device 214. As another example, planarization tools can be used to planarize portions of integrated circuit device 214. As another example, electroplating tools can be used to deposit metal structures and / or layers of integrated circuit device 214. As another example, ion implantation tools can be used to dope one or more portions of semiconductor layer 212 to form integrated circuit device 214.

[0079] like Figure 5CAs shown, an interconnect layer 210 is formed over a device layer 208. A dielectric layer 216 may be deposited over and / or over a semiconductor layer 212 (including an integrated circuit device 214), while a metallization layer 218 and an interlayer interconnect structure 220 may be formed in the dielectric layer 216. To form the interconnect layer 210, a deposition tool may be used to deposit the first dielectric layer 216 (e.g., using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation, and / or another suitable deposition technique). In some embodiments, a planarization tool may be used to planarize the first dielectric layer 216 after deposition. Deposition tools, exposure tools, development tools, and / or etching tools may be used to pattern the first dielectric layer 216 to form recesses in the first dielectric layer 216. Deposition tools can be used to deposit (e.g., using PVD, ALD, CVD, electroplating, and / or other suitable deposition techniques) a first layer-to-layer connection structure 220 in the recess. A second dielectric layer 216 can be deposited on the first dielectric layer 216 using the deposition tools. The second dielectric layer 216 can be patterned, and a first metallization layer 218 can be formed in the second dielectric layer 216, such that the first metallization layer 218 is electrically coupled to the first layer-to-layer connection structure 220. The dielectric layer 216, metallization layer 218, and layer-to-layer connection structure 220 of subsequent interconnect layers 210 can be formed in a similar manner.

[0080] like Figure 5D As shown, a passivation layer 222 is formed above and / or above the topmost dielectric layer 216. Deposition tools can be used to deposit the passivation layer 222 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, a planarization tool can be used to planarize the passivation layer 222 after deposition. The passivation layer 222 can be patterned to form recesses, and top metal pads 224 and top metal vias 226 can be formed within these recesses. The top metal pads 224 can be configured such that they are electrically and / or physically coupled to the topmost interlayer connection structure 220 in the interconnect layer 210. The top metal vias 226 can be configured such that they are electrically and / or physically coupled to the top metal pads 224.

[0081] As mentioned above, providing Figures 5A-5D As an example. Other examples can be found related to... Figures 5A-5D The descriptions are different.

[0082] Figure 6A-6IThis is a diagram of an exemplary embodiment 600 that forms part of the semiconductor device 200 described herein. Specifically, embodiment 600 may include an example of forming sub-pixels 102 or display pixels 204 in a display pixel array 202 of the semiconductor device 200. In some embodiments, one or more semiconductor processing tools may be used to perform one or more of the operations described in connection with exemplary embodiment 600, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, and / or another type of semiconductor processing tool.

[0083] Turn Figure 6A In combination Figures 5A-5D The operations described herein are followed by one or more operations described in conjunction with Exemplary Implementation 600. For example, after forming the device layer 208 and interconnect layer 210 of the semiconductor device 200, one or more operations described in conjunction with Exemplary Implementation 600 are performed.

[0084] like Figure 6B As shown, the first electrode 230 (e.g., bottom electrode or anode) of the sub-pixels 102a-102 of the display pixels 204 of the semiconductor device 200 is formed on the passivation layer 222, such that the first electrode 230 is electrically connected to the top metal via 226. For different sub-pixels, the first electrode 230 can be formed with different z-direction thicknesses. This allows the resonant cavity of the sub-pixels to achieve different z-direction thicknesses.

[0085] For example, since sub-pixel 102c is a blue sub-pixel configured to emit light (e.g., blue light) with a shorter wavelength than sub-pixels 102a and 102b, the first electrode 230 of sub-pixel 102c can be formed such that the z-direction thickness of the first electrode 230 of sub-pixel 102c is greater than the z-direction thickness of the first electrode 230 of sub-pixel 102b and the z-direction thickness of the first electrode 230 of sub-pixel 102a. The first electrode 230 of sub-pixel 102c is formed such that the size of the resonant cavity of sub-pixel 102c is favorable for the resonance of the wavelength of sub-pixel 102c.

[0086] As another example, because sub-pixel 102b is configured to emit light of a shorter wavelength (e.g., green light) than sub-pixel 102a (e.g., which may be configured to emit red light), the first electrode 230 of sub-pixel 102b can be formed such that the z-direction thickness of the first electrode 230 of sub-pixel 102b is greater than the z-direction thickness of the first electrode 230 of sub-pixel 102a. The first electrode 230 of sub-pixel 102b is formed such that the size of the resonant cavity of sub-pixel 102b is favorable for the resonance of the wavelength of sub-pixel 102b.

[0087] As another example, since sub-pixel 102a is a red sub-pixel configured to emit light (e.g., red light) with a longer wavelength than sub-pixels 102b and 102c, the first electrode 230 of sub-pixel 102a can be formed such that the z-direction thickness of the first electrode 230 of sub-pixel 102a is less than the z-direction thickness of the first electrode 230 of sub-pixel 102b and the z-direction thickness of the first electrode 230 of sub-pixel 102c. The first electrode 230 of sub-pixel 102a is formed such that the size of the resonant cavity of sub-pixel 102a is favorable for the resonance of the wavelength of sub-pixel 102a.

[0088] A nitride layer 302 may be formed on the passivation layer 222. The nitride layer 302 may include tantalum nitride (TaN) and / or another nitride-containing material. The nitride layer 302 may serve as a barrier layer for the first electrode 230 and / or promote adhesion between the first electrode 230 and the passivation layer 222. Deposition tools may be used to deposit the nitride layer 302 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, a planarization tool may be used to planarize the nitride layer 302 after deposition.

[0089] In some embodiments, to form the first electrode 230 of sub-pixels 102a-102c, a stack can be formed on the nitride layer 302 and etched thereon to form the first electrode 230. For example, an alternating arrangement of metal layer 304 and nitride (e.g., titanium nitride (TiN)) layer 306 can be deposited on the nitride layer 302. The alternating arrangement of metal layer 304 and nitride layer 306 can be patterned and etched to define the first electrode 230. Subsequent masking and etching operations can be performed to remove the metal layer 304 and / or nitride layer 306 from the first electrode 230 of one or more of the sub-pixels 102a-102c to form the first electrode 230 of one or more of the sub-pixels 102a-102c to the desired z-direction thickness. As an example, after the alternating arrangement of etched metal layer 304 and nitride layer 306 is used to define the first electrode 230, the first electrode 230 of sub-pixel 102c can be covered so that the first electrodes 230 of sub-pixels 102a and 102b to be etched can remove one or more metal layers 304 and / or one or more nitride layers 306 from the first electrodes 230 in sub-pixels 102a and 102b.

[0090] In some embodiments, to form the first electrodes 230 of sub-pixels 102a-102c, an aluminum layer is formed on the nitride layer 302 and etched to form the first metal layer 304 of the first electrodes 230 of sub-pixels 102a-102c. The first electrode 230 of sub-pixels 102a is then covered, and additional metal layers 304 and nitride layers 306 are deposited on the first metal layers 304 of sub-pixels 102b and 102c. The first electrode 230 of sub-pixel 102b is then covered, followed by the deposition of the remaining metal layers 304 and nitride layers 306 of sub-pixels 102c.

[0091] Deposition tools can be used to deposit the metal layer 304 and nitride layer 306 of the first electrode 230 using PVD, ALD, CVD, and / or another suitable deposition technique. In some embodiments, planarization tools can be used to planarize one or more of the metal layers 304 and / or one or more of the nitride layers 306.

[0092] like Figure 6C As shown, a cavity oxide layer 228 is formed on the first electrode 230 of sub-pixels 102a-102c, such that the first electrode 230 is covered by the cavity oxide layer 228. Deposition tools can be used to deposit the cavity oxide layer 228 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, a planarization tool can be used to planarize the cavity oxide layer 228 after deposition.

[0093] like Figure 6D As shown, a recess 602 is formed in the cavity oxide layer 228 above or above the first electrode 230 of sub-pixels 102a-102c. For example, the recess 602 may be formed above and / or above the first electrode 230 of sub-pixels 102a, the recess 602 may be formed above and / or above the first electrode 230 of sub-pixels 102b, the recess 602 may be formed above and / or above the first electrode 230 of sub-pixels 102c, and so on.

[0094] The recess 602 above the first electrode 230 of the sub-pixel 102a can be formed as a metal layer 304 of the first electrode 230 of the sub-pixel 102a. Alternatively, the recess 602 above the first electrode 230 of the sub-pixel 102a can be formed such that the recess 602 extends to the metal layer 304 of the first electrode 230 of the sub-pixel 102a.

[0095] The recess 602 above the first electrode 230 of the sub-pixel 102b can be formed such that the recess 602 extends into one or more metal layers 304 and / or one or more nitride layers 306 in the first electrode 230 of the sub-pixel 102b. Therefore, the bottom of the recess 602 is lower than the top surface of the first electrode 230 of the sub-pixel 102b.

[0096] The recess 602 above the first electrode 230 of the sub-pixel 102c can be formed such that the recess 602 extends into one or more metal layers 304 and / or one or more nitride layers 306 in the first electrode 230 of the sub-pixel 102c. Therefore, the bottom of the recess 602 is lower than the top surface of the first electrode 230 of the sub-pixel 102c.

[0097] Further as Figure 6D As shown, the recess 602 above the first electrode 230 of sub-pixel 102a can be formed with a first depth (in Figure 6D The recess 602 above the first electrode 230 of sub-pixel 102b (denoted as size D7) can be formed as a second depth (in Figure 6D The recess 602 above the first electrode 230 of sub-pixel 102c (denoted as size D8) can be formed as a third depth (in Figure 6D (represented as dimension D9).

[0098] In some embodiments, the first depth, the second depth, and the third depth are substantially the same depth, such that the bottom surfaces of the recess 602 are substantially coplanar and located at substantially the same z-direction depth in the semiconductor device 200 (e.g., dimensions D7, D8, and D9 are substantially equal). In these embodiments, the recess 602 above the first electrode 230 of sub-pixel 102c may extend further or deeper into the first electrode 230 of sub-pixel 102c than the recess 602 above the first electrode 230 of sub-pixel 102b, and / or may extend further or deeper into the first electrode 230 of sub-pixel 102c than the recess 602 above the first electrode 230 of sub-pixel 102a.

[0099] In some embodiments, the first depth, the second depth, and the third depth are different depths, such that the bottom surface of the recess 602 is located at different z-direction depths in the semiconductor device 200 (e.g., dimensions D7, D8, and D9 are different). In some embodiments, the recess 602 may extend to approximately the same distance in the first electrode 230 of the sub-pixels 102a-102c.

[0100] In some embodiments, the pattern in the photoresist layer is used to etch a cavity oxide layer 228, one or more metal layers 304 in one or more first electrodes 230, and / or one or more nitride layers 306 in one or more first electrodes 230 to form a recess 602. In these embodiments, a deposition tool can be used to form the photoresist layer on the cavity oxide layer 228. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the cavity oxide layer 228, one or more metal layers 304 in one or more first electrodes 230, and / or one or more nitride layers 306 in one or more first electrodes 230 based on the pattern to form the recess 602. In some embodiments, the etching operation includes a dry etching operation (e.g., a plasma-based etching operation, a gas-based etching operation), a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the recess 602 based on the pattern.

[0101] In some embodiments, a cyclic etching technique is used to form the recess 602 to achieve a relatively high aspect ratio between the depth and lateral width of the recess 602. For example, a cyclic etching technique is used to form the recess 602 such that the recess 602 has an aspect ratio of at least about 8:1 between its depth and lateral width. However, other values ​​for the aspect ratio of the recess 602 are also within the scope of this disclosure.

[0102] In some embodiments, a high aspect ratio of the recess 602 can be achieved using deep reactive ion etching (sometimes referred to as "BOSCH" etching). Deep reactive ion etching is a cyclic etching technique in which a protective liner is used to perform multiple deposition and etching cycles to minimize lateral etching. For example, a deep reactive ion etching cycle may include etching the recess 602 in the cavity oxide layer 228 to a first depth, forming a protective liner on the sidewalls and bottom surface of the recess 602, etching the protective liner to remove it from the bottom surface of the recess 602, and etching the bottom of the recess 602 to increase the depth of the recess 602 to a second depth, while the protective liner protects the sidewalls of the recess 602 from lateral etching. Additional cycles may be performed to achieve a specific depth of the recess 602.

[0103] like Figure 6EAs shown in the top view of the semiconductor device 200, the recess 602 may include a closed-loop recess 602 (e.g., a closed-loop trench) surrounding the periphery of the sub-pixels 102a-102c. The closed-loop recess 602 may be formed surrounding the periphery of the sub-pixels 102a-102c.

[0104] like Figure 6F As shown, the isolation structure 206 is formed in the recess 602. For example, the isolation structure 206 may be formed in the recess 602 above the first electrode 230 of the sub-pixel 102a, such that the isolation structure rests on the metal layer 304 of the first electrode 230 of the sub-pixel 102a. Alternatively, the isolation structure 206 of the sub-pixel 102a may be formed in the recess 602 above the first electrode 230 of the sub-pixel 102a, such that the bottom surface of the isolation structure extends into the metal layer 304 of the first electrode 230 of the sub-pixel 102a.

[0105] As another example, the isolation structure 206 can be formed in the recess 602 above the first electrode 230 of the sub-pixel 102b, such that the isolation structure rests on the metal layer 304 of the first electrode 230 of the sub-pixel 102b. Alternatively, the isolation structure 206 of the sub-pixel 102b can be formed in the recess 602 above the first electrode 230 of the sub-pixel 102b, such that the bottom surface of the isolation structure extends into one or more metal layers 304 of the first electrode 230 of the sub-pixel 102b and / or extends into one or more nitride layers 306 of the first electrode 230 of the sub-pixel 102b.

[0106] As another example, the isolation structure 206 can be formed in the recess 602 above the first electrode 230 of the sub-pixel 102c, such that the isolation structure rests on the metal layer 304 of the first electrode 230 of the sub-pixel 102c. Alternatively, the isolation structure 206 of the sub-pixel 102c can be formed in the recess 602 above the first electrode 230 of the sub-pixel 102c, such that the bottom surface of the isolation structure extends into one or more metal layers 304 of the first electrode 230 of the sub-pixel 102c and / or extends into one or more nitride layers 306 of the first electrode 230 of the sub-pixel 102c.

[0107] The isolation structure 206 may include trenches (e.g., DTI structures) in the semiconductor device 200 and / or another type of structure extending in the z-direction (e.g., the vertical direction). Deposition tools may be used to deposit the isolation structure 206 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, planarization tools are used to perform planarization operations (e.g., chemical mechanical planarization (CMP) operations) to planarize the isolation structure 206 after deposition.

[0108] like Figure 6G As shown, each isolation structure 206 may include a closed-loop isolation structure that completely surrounds the periphery of the associated sub-pixels in sub-pixels 102a-102c. The top view shape of the isolation structure 206 may correspond to the shape of the closed-loop recess 602 forming the isolation structure 206, and may include a closed-loop isolation ring, a closed-loop isolation square, a closed-loop isolation rectangle, and / or other closed-loop shapes.

[0109] Figure 6H An example process for forming the isolation structure 206 in the recess 602 is shown. For example... Figure 6H As shown, one or more pads 310 may be conformally deposited on the sidewalls and bottom surface of the recess 602 such that the one or more pads 310 conform to the contour of the recess 602. Deposition tools may be used to deposit the one or more pads 310 using conformal deposition techniques such as ALD or CVD. The one or more pads 310 may include a tantalum nitride (TaN) barrier layer, a tantalum (Ta) barrier layer, a copper (Cu) layer, and / or another type of pad.

[0110] like Figure 6H As further shown, the recess 602 is then filled with material on one or more pads 310 to form an isolation layer 308 in the recess 602. The isolation layer 308 may include copper (Cu), tungsten (W), titanium nitride (TiN), and / or other suitable materials. Deposition tools may be used to deposit the material of the isolation layer 308 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique.

[0111] like Figure 6H As further shown, material can be deposited into the isolation layer 308 such that excess material of the isolation layer 308 extends over the top of the recess 602 and / or over the top surface of the cavity oxide layer 228. This ensures that the recess 602 is completely filled with the material of the isolation layer 308, thereby minimizing the possibility of forming seams and / or voids in the isolation layer 308. Therefore, after depositing the isolation layer 308, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the isolation layer 308. The planarization operation can also be performed to remove material from one or more pads 310 from the top surface of the cavity oxide layer 228. The planarization operation results in the top surface of the isolation layer 308 being substantially coplanar with the top surface of the cavity oxide layer 228.

[0112] like Figure 6IAs shown, the remaining layers of sub-pixel 102 may be disposed on the cavity oxide layer 228 and above the isolation structure 206. In some embodiments, the substrate layer 236, pixel definition layers 234 and 238, light generating film stack 240, second electrode 242, passivation layer 244, and color filter 246 may be formed as an integrated unit placed on the cavity oxide layer 228 after fabrication. In some embodiments, one or more of the substrate layer 236, pixel definition layers 234 and 238, light generating film stack 240, second electrode 242, passivation layer 244, and / or color filter 246 are formed on the cavity oxide layer 228.

[0113] As mentioned above, providing Figure 6A-6I As an example. Other examples can be found related to... Figure 6A-6I The descriptions are different.

[0114] Figure 7 This is a flowchart of an exemplary process 700 associated with forming the semiconductor device described herein. In some embodiments, Figure 7 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, bonding tools, wafer / die transport tools and / or another type of semiconductor processing tool.

[0115] like Figure 7 As shown, process 700 may include a first electrode (block 710) of a sub-pixel of a display pixel array of a display device formed over an interconnect layer of a semiconductor device. For example, one or more semiconductor processing tools may be used to form a first electrode 230 of a sub-pixel 102 of a display pixel 204 of a display pixel array 202 of a semiconductor device over an interconnect layer 210 of a semiconductor device 200, as described herein.

[0116] like Figure 7 As further shown, process 700 may include forming a dielectric layer (block 720) over the first electrode. For example, as described herein, a cavity oxide layer 228 may be formed on the first electrode 230 using one or more semiconductor processing tools.

[0117] like Figure 7 As further shown, process 700 may include forming a recess (block 730) in the dielectric layer surrounding the periphery of the first electrode. For example, one or more semiconductor processing tools may be used to form a recess 602 surrounding the periphery of the first electrode 230 in the cavity oxide layer 228, as described herein.

[0118] like Figure 7As further shown, process 700 may include forming an isolation structure (block 740) in the recess. For example, as described herein, one or more semiconductor processing tools may be used to form the isolation structure 206 in the recess 602. In some embodiments, the isolation structure 206 defines a resonant cavity 232 of the sub-pixel 102 above the first electrode 230.

[0119] like Figure 7 As further shown, process 700 may include a light-generating film stack (block 750) forming sub-pixels over the isolation structure. For example, as described herein, the light-generating film stack 240 may be formed over the isolation structure 206 using one or more semiconductor processing tools.

[0120] like Figure 7 As further shown, process 700 may include a second electrode (block 760) forming a sub-pixel over the light-generating film stack. For example, one or more semiconductor processing tools may be used to form a second electrode 242 over the light-generating film stack 240, as described herein.

[0121] The process 700 may include other implementations, such as any single implementation or any combination of multiple implementations of one or more other processes described below and / or described elsewhere herein.

[0122] although Figure 7 An example block of process 700 is shown, but in some embodiments, process 700 includes... Figure 7 The blocks depicted in the diagram are those that are additional, fewer, different, or arranged differently. Alternatively, two or more of the blocks or processes in 700 can be executed in parallel.

[0123] Figure 8 This is a flowchart of an exemplary process 800 associated with the formation of the semiconductor device described herein. In some embodiments, Figure 8 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, bonding tools, wafer / die transport tools and / or another type of semiconductor processing tool.

[0124] like Figure 8As shown, process 800 may include a first electrode (block 810) of a first sub-pixel of a display pixel array of a display pixel array of a semiconductor device formed over an interconnect layer of the semiconductor device. For example, one or more semiconductor processing tools may be used to form a first electrode 230 of a first sub-pixel 102 of a display pixel array 204 of a display pixel array 202 of a semiconductor device over an interconnect layer 210 of the semiconductor device 200, as described herein.

[0125] like Figure 8 As further shown, process 800 may include a second electrode (block 820) for forming a second sub-pixel of a display pixel over an interconnect layer. For example, one or more semiconductor processing tools may be used to form a second electrode (e.g., another first electrode 230) of a second sub-pixel 102 of a display pixel 204 over an interconnect layer 210, as described herein.

[0126] like Figure 8 As further shown, process 800 may include forming a dielectric layer (block 830) over the first electrode and the second electrode. For example, one or more semiconductor processing tools may be used to form a dielectric layer (e.g., a cavity oxide layer 228) over the first electrode 230 and the second electrode (e.g., another first electrode 230), as described herein.

[0127] like Figure 8 As further shown, process 800 may include forming a first closed-loop recess (block 840) in the dielectric layer that surrounds a first periphery of the first electrode. For example, one or more semiconductor processing tools may be used to form a first closed-loop recess 602 surrounding a first periphery of the first electrode 230 in the dielectric layer, as described herein.

[0128] like Figure 8 As further shown, process 800 may include forming a second closed-loop recess (block 850) in the dielectric layer that surrounds a second periphery of the second electrode. For example, one or more semiconductor processing tools may be used to form a second closed-loop recess 602 in the dielectric layer that surrounds a second periphery of the second electrode (e.g., another first electrode 230), as described herein.

[0129] like Figure 8 As further shown, process 800 may include forming a first closed-loop isolation structure (block 860) in the first closed-loop recess. For example, one or more semiconductor processing tools may be used to form the first closed-loop isolation structure 206 in the first closed-loop recess 602, as described herein. In some embodiments, the first closed-loop isolation structure 206 defines a first dielectric resonant cavity 232 above the first electrode 230.

[0130] like Figure 8As further shown, process 800 may include forming a second closed-loop isolation structure (block 870) in the second closed-loop recess. For example, one or more semiconductor processing tools may be used to form the second closed-loop isolation structure 206 in the second closed-loop recess 602, as described herein. In some embodiments, the second closed-loop isolation structure 206 defines a second dielectric resonant cavity 232 above the first electrode 230.

[0131] The process 800 may include other implementations, such as any single implementation or any combination of multiple implementations of one or more other processes described below and / or described elsewhere herein.

[0132] In a first embodiment, forming a first electrode 230 includes forming a first electrode 230 such that a first top surface of the first electrode 230 is located at a first height in the semiconductor device 200, and forming a second electrode (e.g., another first electrode 230) includes forming a second electrode such that a second top surface of the second electrode is located at a second height in the semiconductor device 200, wherein the first height is greater than the second height.

[0133] In the second embodiment, a first closed-loop recess 602 is formed, either alone or in combination with the first embodiment. This includes forming the first closed-loop recess 602 to a first depth (e.g., size D7, size D8, size D9) in a dielectric layer (e.g., cavity oxide layer 228), and forming a second closed-loop recess 602, which includes forming the second closed-loop recess 602 to a second depth (e.g., size D7, size D8, size D9) in the dielectric layer. The first depth and the second depth are approximately the same.

[0134] In the third embodiment, forming the first closed-loop recess 602, alone or in combination with one or more of the first and second embodiments, includes forming the first closed-loop recess 602 such that the first closed-loop recess 602 extends into the first electrode 230.

[0135] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 800 includes planarizing the first closed-loop isolation structure 206 and the second closed-loop isolation structure 206 such that the first top surface of the first closed-loop isolation structure 206 and the second top surface of the second closed-loop isolation structure 206 are substantially coplanar.

[0136] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the process 800 includes providing a first organic light-generating film stack 240 over the first dielectric resonant cavity 232 and providing a second organic light-generating film stack 240 over the second dielectric resonant cavity 232.

[0137] although Figure 8An example block of process 800 is shown, but in some embodiments, process 800 includes... Figure 8 The blocks depicted in the diagram are those that are additional, fewer, different, or arranged differently. Alternatively, two or more of the blocks or processes 800 can be executed in parallel.

[0138] In this manner, a semiconductor device (e.g., a microdisplay device) includes an isolation structure around at least a portion of the subpixels of a display pixel array within the semiconductor device. This isolation structure (e.g., isolation trenches, isolation rings) confines the light emitted by the subpixels, allowing the light to be highly confined and collimated. Consequently, the isolation structure reduces lateral scattering of light emitted by the subpixels, which reduces color mixing between subpixels. This enables the display pixel array to produce images and / or videos with high-precision color performance and high contrast.

[0139] As described in more detail above, some embodiments described herein provide a semiconductor device. This semiconductor device includes a display pixel array comprising a plurality of display pixels. One of the plurality of display pixels includes a first electrode, a dielectric region above the first electrode, a light-generating film stack above the dielectric region, a second electrode above the light-generating film stack, and an isolation structure laterally surrounding the dielectric region.

[0140] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a semiconductor substrate. This semiconductor device includes a plurality of integrated circuit devices within the semiconductor substrate. The semiconductor device includes an interconnect layer located above the semiconductor substrate. The semiconductor device includes a display pixel array located above the interconnect layer, the display pixel array including a plurality of display pixels. One of the plurality of display pixels includes a plurality of sub-pixels. Each of the plurality of sub-pixels includes a bottom electrode, a resonant region above the bottom electrode, a light-generating film stack above the resonant region, a top electrode above the light-generating film stack, and an isolation structure laterally surrounding the resonant region.

[0141] As described in more detail above, some embodiments described herein provide a method. This method includes forming a first electrode of a first sub-pixel of a display pixel array of a semiconductor device over an interconnect layer of the semiconductor device. The method includes forming a second electrode of a second sub-pixel of the display pixel over the interconnect layer. The method includes forming a dielectric layer over the first and second electrodes. The method includes forming a first closed-loop recess in the dielectric layer surrounding a first periphery of the first electrode. The method includes forming a second closed-loop recess in the dielectric layer surrounding a second periphery of the second electrode. The method includes forming a first closed-loop isolation structure in the first closed-loop recess, wherein the first closed-loop isolation structure defines a first dielectric resonant cavity over the first electrode. The method includes forming a second closed-loop isolation structure in the second closed-loop recess, wherein the second closed-loop isolation structure defines a second dielectric resonant cavity over the second electrode.

[0142] The terms “approximately” and “substantially” can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not intended to be limiting. It should be understood that, according to this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0143] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A display pixel array contains multiple display pixels. One of the plurality of display pixels includes: First electrode; The dielectric region is located above the first electrode; A light-generating film stack is placed above the dielectric region; The second electrode is located above the stack of light-generating films; and An isolation structure laterally surrounds the dielectric region.

2. The semiconductor device according to claim 1, characterized in that, The bottom surface of the isolation structure extends into the first electrode.

3. The semiconductor device according to claim 1, characterized in that, The bottom surface of the isolation structure is located on top of the first electrode.

4. The semiconductor device according to claim 1, characterized in that, The vertical thickness of the isolation structure is approximately equal to the thickness of the dielectric region.

5. A semiconductor device, characterized in that, include: Semiconductor substrate; Multiple integrated circuit devices are located in the semiconductor substrate; An interconnect layer is located above the semiconductor substrate; as well as A display pixel array, above the interconnect layer, includes a plurality of display pixels. One of the plurality of display pixels includes a plurality of sub-pixels. Each of the plurality of sub-pixels includes: Bottom electrode; The resonant region is located above the bottom electrode; A stack of light-generating films is positioned above the resonant region; Top electrode, above the light-generating film stack; and An isolation structure laterally surrounds the resonant region.

6. The semiconductor device according to claim 5, characterized in that, The first isolation structure of the first sub-pixel among the plurality of sub-pixels has a first vertical thickness; The second isolation structure of the second sub-pixel among the plurality of sub-pixels has a second vertical thickness; and The first vertical thickness and the second vertical thickness are approximately the same.

7. The semiconductor device according to claim 5, characterized in that, The first bottom electrode of the first sub-pixel among the plurality of sub-pixels has a first vertical thickness; The second bottom electrode of the second sub-pixel among the plurality of sub-pixels has a second vertical thickness; and The first vertical thickness and the second vertical thickness are different thicknesses.

8. The semiconductor device according to claim 5, characterized in that, The first bottom surface of the first resonant region of the first sub-pixel among the plurality of sub-pixels is closer to the interconnect layer than the second bottom surface of the second resonant region of the second sub-pixel among the plurality of sub-pixels.

9. The semiconductor device according to claim 5, characterized in that, The first bottom electrode of the first sub-pixel of the plurality of sub-pixels includes a first metal layer; The second bottom electrode of the second sub-pixel among the plurality of sub-pixels includes: Second metal layer; A metal nitride layer is disposed on the second metal layer; and A third metal layer is disposed on the metal nitride layer; The first isolation ring of the first sub-pixel is located on the top surface of the first metal layer; and The second metal isolation structure of the second sub-pixel is located on the second metal layer and extends through the metal nitride layer and the third metal layer.

10. The semiconductor device according to claim 5, characterized in that, The first bottom electrode of the first sub-pixel among the plurality of sub-pixels includes: The first multiple metal layers; and One or more first metal nitride layers; The second bottom electrode of the second sub-pixel among the plurality of sub-pixels includes: Second multiple metal layers; and One or more second metal nitride layers; and The first number of metal layers in the first plurality of metal layers is greater than the second number of metal layers in the second plurality of metal layers.

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