A three-dimensional packaging structure

Abstract

The utility model provides a kind of three-dimensional packaging structure, including substrate, chip, connecting plate and fin;Substrate is connected with system PCB, and cavity is opened on substrate;First chip and second chip are up and down distribution, connecting plate is located between first chip and second chip, the first surface of connecting plate is connected with first chip by high-density connecting point, the second surface of connecting plate is connected with second chip by high-density connecting point, the second surface of connecting plate is interconnected with substrate by low-density connecting point;First fin contacts with first chip, second fin contacts with second chip, and simultaneously, second fin contacts with copper layer leaked out by system PCB windowing. The utility model not only solves the space problem of short-distance interconnection between chip, optimizes electrical connection performance, but also greatly improves the heat dissipation performance of packaging structure, thereby improving the working performance and reliability of packaging structure.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and in particular to a three-dimensional packaging structure. Background Technology

[0002] With the development of AI computing, the interactions and functional requirements between chips are becoming increasingly complex, necessitating the integration of multiple chips within a single packaging system. Due to process limitations and miniaturization requirements, the dimensions in the planar direction cannot be further expanded. In 3D packaging, vertically stacking chips connects them with shorter interconnects and higher bandwidth, further compensating for the shortcomings of planar packaging design. Replacing the long-range interconnects of 2D packaging with the short-range vertical interconnects of 3D packaging is an inevitable trend in the development of packaging technology to a higher level. However, directly stacking chips vertically can easily lead to chip breakage and other problems. Furthermore, vertical chip stacking can cause heat to accumulate on the bottom chip, which cannot dissipate in time, easily leading to overheating and chip failure. Therefore, these problems need to be addressed. Utility Model Content

[0003] The purpose of this invention is to provide a solution that addresses the shortcomings of the aforementioned background technology by solving both the spatial arrangement and electrical connection performance of chip packaging, while also greatly optimizing heat dissipation performance.

[0004] To achieve the above objectives, this utility model provides a three-dimensional packaging structure, including a substrate, a chip, a connecting plate, and a heat sink;

[0005] The substrate is connected to the system PCB, and a cavity is formed on the substrate;

[0006] The chip includes at least a first chip and a second chip, which are arranged vertically. The connecting plate is located between the first chip and the second chip. The first surface of the connecting plate is connected to the first chip through high-density connection points, and the second surface of the connecting plate is connected to the second chip through high-density connection points. The second surface of the connecting plate is interconnected with the substrate through low-density connection points, so that the first chip, the second chip and the substrate can communicate.

[0007] The heat sink includes at least a first heat sink and a second heat sink. The first heat sink is in contact with the first chip, the second heat sink is in contact with the second chip, and the second heat sink is in contact with the copper layer exposed through the window of the system PCB.

[0008] Furthermore, the wiring spacing of the connecting plate is smaller than the wiring spacing of the substrate.

[0009] Furthermore, the substrate is connected to the system PCB via solder balls.

[0010] Furthermore, the first surface of the connecting plate is connected to the first chip via microbumps, the second surface of the connecting plate is connected to the second chip via microbumps, and the second surface of the connecting plate is connected to the substrate via conventional bumps.

[0011] Furthermore, the active surfaces of the first chip and the second chip are both located on one side of the microbump, and the conventional bumps are distributed around the microbump.

[0012] Furthermore, the substrate has a cavity, the length and width of which are larger than the size of the second chip, and the second chip is disposed in the cavity.

[0013] Furthermore, the lower surface of the second chip contacts the upper surface of the second heat sink.

[0014] Furthermore, thermally conductive adhesive is filled between the first chip and the first heat sink, and between the second chip and the heat sink.

[0015] The above-mentioned solution of this utility model has the following beneficial effects:

[0016] The three-dimensional packaging structure provided by this utility model, through the connection method between the connecting plate and the first chip, the second chip, etc., and the specific arrangement of the first heat sink and the second heat sink, not only solves the space problem of short-distance interconnection between chips and optimizes the electrical connection performance, but also greatly improves the heat dissipation performance of the packaging structure, thereby improving the working performance and reliability of the packaging structure.

[0017] Other beneficial effects of this invention will be described in detail in the following detailed description section. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall structure of this utility model;

[0019] Figure 2 This is another schematic diagram of the overall structure of this utility model (hidden system PCB).

[0020] [Explanation of Labels in the Attached Image]

[0021] 1-Substrate; 2-Connecting plate; 3-Solder ball; 4-System PCB; 5-First chip; 6-Second chip; 7-Micro bump; 8-Conventional bump; 9-First heat sink; 10-Second heat sink; 11-Thermal conductive adhesive. Detailed Implementation

[0022] To make the technical problems, solutions, and advantages of this utility model clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0023] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0025] like Figure 1 , Figure 2 As shown, an embodiment of this utility model provides a three-dimensional packaging structure, including a substrate 1, a chip, a connecting plate 2, and a heat sink. The substrate 1 is normally connected to the system PCB 4 via solder balls 3, so that the three-dimensional packaging structure is correctly packaged in the corresponding position on the system PCB. The chip includes at least a first chip 5 and a second chip 6, and the first chip 5 and the second chip 6 are distributed vertically, for example, the first chip 5 is located on the upper layer and the second chip 6 is located on the lower layer. The first chip 5 and the second chip 6 are interconnected via the connecting plate 2.

[0026] Specifically, the connecting plate 2 is located between the first chip 5 and the second chip 6. The upper surface of the connecting plate 2 is connected to the first chip 5 through microbumps 7, and the lower surface of the connecting plate 2 is connected to the second chip 6 through microbumps 7, thereby achieving vertical interconnection between the first chip 5 and the second chip 6. In addition, the lower surface of the connecting plate 2 is interconnected with the substrate 1 through conventional bumps 8, thereby forming an interconnection between the first chip 5, the second chip 6 and the substrate 1.

[0027] It should be noted that this positioning of the connecting plate 2 ensures vertical interconnection when the first chip 5 and the second chip 6 are distributed vertically. Correspondingly, the active surfaces of the chips are all located on one side of the microbumps 7, that is, the active surface of the first chip 5 is located on the lower surface, and the active surface of the second chip 6 is located on the upper surface. The connecting plate 2 is connected to the substrate 1 through conventional bumps 8 that surround it relatively to the outside.

[0028] Due to the positioning and connection method of the connecting plate 2 to the substrate 1, the gap between the connecting plate 2 and the conventional substrate 1 cannot accommodate the second chip 6, etc. Therefore, in this embodiment, a hollow cavity is created at the center of the substrate 1, making the substrate 1 overall "U"-shaped. The length and width of the cavity are larger than the size of the second chip 6, allowing the second chip 6 to be inserted through the cavity during encapsulation without obstruction from the substrate 1. Since the second chip 6 is not directly connected to the substrate 1, it can communicate smoothly with both the connecting plate 2 and the substrate 1.

[0029] It should be noted that the manufacturing process of the interconnect board 2 in this embodiment can adopt the silicon interposer manufacturing process to manufacture an interconnect board 2 with finer pitch wiring, which is smaller than the wiring pitch of the substrate 1, thus avoiding the situation where the minimum pitch of the conventional bumps 7 is insufficient to support the interconnection of multiple chips. At the same time, since the chips are distributed vertically, the size of the interconnect board 2 can be manufactured smaller than that of a planar distribution, thus the cost can also be controlled.

[0030] In this embodiment, the heat sink includes a first heat sink 9 and a second heat sink 10. The first heat sink 9 is cap-shaped, with its lower central surface normally in contact with the upper surface of the first chip 5, allowing for rapid heat dissipation by quickly removing heat generated by the first chip 5 through the first heat sink 9 (and the system heat sink, etc.). For the second chip 6, since it is located at the bottom of the entire package structure, heat accumulation at this location is normally difficult to dissipate quickly. Therefore, in this embodiment, the second heat sink 10 enables the rapid dissipation of heat generated and accumulated at the bottom by the second chip 6.

[0031] Specifically, a window is made at the corresponding position on the system PCB4, and the second heat sink 10 is positioned below the second chip 6. The upper surface of the second heat sink 10 contacts the lower surface of the second chip 6, and the lower surface of the second heat sink 10 can directly contact the copper layer at the window position on the system PCB4. Therefore, the heat from the second chip 6 can be quickly transferred to the system PCB4 side and dissipated, thereby quickly removing the heat generated by the second chip 6 and effectively solving the problem of heat accumulation at the bottom.

[0032] It should be noted that, in this embodiment, the contact surfaces of the first heat sink 9 and the first chip 5, and the contact surfaces of the second heat sink 10 and the second chip 6, can be further coated with thermally conductive adhesive 11. Under the action of the heat sink and the thermally conductive adhesive 11, the structural thermal resistance inside the package will be greatly reduced, thereby significantly improving the heat dissipation performance.

[0033] In summary, the three-dimensional packaging structure provided in this embodiment, through the connection method between the connecting plate 2 and the first chip 5, the second chip 6, etc., and the specific arrangement of the first heat sink 9 and the second heat sink 10, not only solves the space problem of short-distance interconnection between chips and optimizes the electrical connection performance, but also greatly improves the heat dissipation performance of the packaging structure, thereby enhancing the working performance and reliability of the packaging structure.

[0034] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0035] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A three-dimensional packaging structure, characterized in that, Includes substrate, chip, connector board and heat sink; The substrate is connected to the system PCB, and a cavity is formed on the substrate; The chip includes at least a first chip and a second chip, which are arranged vertically. The connecting plate is located between the first chip and the second chip. The first surface of the connecting plate is connected to the first chip through high-density connection points, and the second surface of the connecting plate is connected to the second chip through high-density connection points. The second surface of the connecting plate is interconnected with the substrate through low-density connection points, so that the first chip, the second chip and the substrate can communicate. The heat sink includes at least a first heat sink and a second heat sink. The first heat sink is in contact with the first chip, the second heat sink is in contact with the second chip, and the second heat sink is in contact with the copper layer exposed through the window of the system PCB.

2. The three-dimensional packaging structure according to claim 1, characterized in that, The wiring spacing of the connecting plate is smaller than that of the substrate.

3. The three-dimensional packaging structure according to claim 1, characterized in that, The substrate is connected to the system PCB via solder balls.

4. The three-dimensional packaging structure according to claim 1, characterized in that, The first surface of the connecting plate is connected to the first chip via microbumps, the second surface of the connecting plate is connected to the second chip via microbumps, and the second surface of the connecting plate is connected to the substrate via conventional bumps.

5. A three-dimensional packaging structure according to claim 4, characterized in that, The active surfaces of the first chip and the second chip are both located on one side of the microbump, and the conventional bumps are distributed around the microbump.

6. A three-dimensional packaging structure according to claim 1, characterized in that, The substrate has a cavity, the length and width of which are larger than the size of the second chip, and the second chip is inserted through the cavity.

7. A three-dimensional packaging structure according to claim 6, characterized in that, The lower surface of the second chip is in contact with the upper surface of the second heat sink.

8. A three-dimensional packaging structure according to claim 1, characterized in that, Thermally conductive adhesive is used to fill the space between the first chip and the first heat sink, and between the second chip and the heat sink.

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