A semiconductor power device

Abstract

The application provides a kind of semiconductor power device, it is related to the field of semiconductor technology.Semiconductor power device includes plastic package shell, it is known that semiconductor power is packaged by plastic package, so that semiconductor power device has better anti-vibration, waterproof, dustproof, oxidation prevention etc.Capability, and improve the insulation performance of semiconductor power device, also reduce the volume of semiconductor power device.In addition, the semiconductor power device provided in the application, the length of the first side of the current terminal is greater than the length of the second side, to design the current terminal as short and wide shape, so that the parasitic inductance of the current terminal in the semiconductor power device and system can be reduced, and the fixed connection between the current terminal and other lines is facilitated, thereby improving the performance of semiconductor power device and related system.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor power device. Background Technology

[0002] With the development of power electronics technology, semiconductor power devices have attracted increasing attention. Semiconductor power devices are devices that combine semiconductor power chips according to specific functions and patterns and then package them into a single unit. They are mainly used in the power circuits of power electronic systems and are the core hardware for realizing power conversion. Therefore, high-performance semiconductor power devices and corresponding systems are one of the important research technologies in the semiconductor field. Utility Model Content

[0003] In view of this, this application provides a semiconductor power device that effectively solves the technical problems existing in the prior art, enabling the semiconductor power device and related systems to have better performance.

[0004] To achieve the above objectives, the technical solution provided in this application is as follows:

[0005] A semiconductor power device, comprising:

[0006] Power circuit board;

[0007] A plastic-encapsulated housing that encapsulates the power circuit board;

[0008] At least one current terminal, the current terminal including at least one first type of current terminal and / or at least one second type of current terminal; in a direction parallel to the thickness of the semiconductor power device, the first type of current terminal is located on the surface of one side of the plastic encapsulation housing; in a direction perpendicular to the thickness of the semiconductor power device, the second type of current terminal is located on the side of one side of the plastic encapsulation housing; the power circuit board is electrically connected to the current terminal through the plastic encapsulation housing; wherein, in an orthographic projection onto a reference plane perpendicular to the thickness direction of the semiconductor power device, the length of the first side of the current terminal is greater than the length of the second side of the current terminal, the extension direction of the first side of the current terminal is the same as the extension direction of the adjacent side of the plastic encapsulation housing, and the extension direction of the second side of the current terminal intersects with the extension direction of the adjacent side of the plastic encapsulation housing;

[0009] At least one functional terminal is located on one side of the plastic encapsulation housing in a thickness direction parallel to the semiconductor power device, and the functional terminal is electrically connected to the power circuit board through the plastic encapsulation housing.

[0010] Optionally, the semiconductor power device further includes:

[0011] The heat dissipation surface is located on one side surface of the power circuit board in a direction parallel to the thickness of the semiconductor power device, and the heat dissipation surface is exposed by the plastic encapsulation housing.

[0012] Optionally, the current terminals include two second-type current terminals, which are respectively disposed on opposite sides of the plastic-encapsulated housing.

[0013] Optionally, the first side of the first type of current terminal and the first side of the second type of current terminal extend in the same direction;

[0014] The second side of the first type of current terminal and the second side of the second type of current terminal extend in the same direction.

[0015] Optionally, the functional terminal and the first type of current terminal are located on the same side of the plastic-encapsulated housing.

[0016] Optionally, the functional terminals include at least one first-type functional terminal;

[0017] In the orthographic projection of the reference plane, and along the extension direction of the first side of the first type of current terminal, the first type of functional terminal is located on one side of the first type of current terminal.

[0018] Optionally, the functional terminals further include at least one second type of functional terminal, and at least one pair of the first type of functional terminals and the second type of functional terminals have the same function;

[0019] In the orthographic projection of the reference plane, and along the extension direction of the first side of the first type of current terminal, the first type of functional terminal and the second type of functional terminal are respectively located on both sides of the first type of current terminal.

[0020] Optionally, at least one pair of functionally identical first-type functional terminals and second-type functional terminals are electrically connected.

[0021] Optionally, the first type of current terminal includes a DC negative terminal, and the second type of current terminal includes a DC positive terminal and an AC terminal;

[0022] The functional terminals include at least one of control terminals and detection terminals.

[0023] Optionally, the power circuit board includes a half-bridge power circuit.

[0024] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:

[0025] This application provides a semiconductor power device, which includes a plastic encapsulation housing. The plastic encapsulation method provides the semiconductor power device with better resistance to vibration, water, dust, and oxidation, improves its insulation performance, and reduces its size. Furthermore, in the semiconductor power device provided in this application, the length of the first side of the current terminal is greater than the length of its second side, allowing the current terminal to be designed as a short and wide shape. This reduces the parasitic inductance of the current terminal in the semiconductor power device and system, and facilitates the fixed connection between the current terminal and other circuits, thereby improving the performance of the semiconductor power device and related systems. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0027] Figure 1 A top view of a semiconductor power device provided in an embodiment of this application;

[0028] Figure 2 A side view of a semiconductor power device provided in an embodiment of this application;

[0029] Figure 3 This application provides a partial stacked diagram of a semiconductor power device according to an embodiment of the present application;

[0030] Figure 4 A top view of another semiconductor power device provided in an embodiment of this application;

[0031] Figure 5 A top view of yet another semiconductor power device provided in an embodiment of this application;

[0032] Figure 6 A top view of yet another semiconductor power device provided in an embodiment of this application;

[0033] Figure 7 A partial stacked view of a semiconductor power device in a top view, provided in an embodiment of this application;

[0034] Figure 8 A partial stacked view of another semiconductor power device provided in the embodiments of this application from a top view perspective;

[0035] Figure 9 A partial stacked diagram of a semiconductor power system provided in an embodiment of this application;

[0036] Figure 10 A partial top view of a semiconductor power system provided in an embodiment of this application;

[0037] Figure 11 A partial top view of another semiconductor power system provided in an embodiment of this application;

[0038] Figure 12 A partial top view of yet another semiconductor power system provided in this application embodiment;

[0039] Figure 13 This is a partial stacked diagram of another semiconductor power device provided in an embodiment of this application.

[0040] Figure label:

[0041] 101-Passive component; 102-Passive component negative terminal; 103-Passive component positive terminal; 20-Current terminal; 02-External connection wire; 21-Type I current terminal; 22-Type II current terminal; 021-Type I external connection wire; 022-Type II external connection wire; 2201-Molding layer; 201-Molding housing; 202-DC positive terminal; 203-DC positive external connection wire; 204-DC positive connection wire; 205-First surface circuit layer; 206-Circuit board body; 207-Dissipative Hot surface; 209 - First power chip; 210 - Chip connection part; 211 - Surface circuit connection part; 212 - First internal connection line; 213 - DC negative terminal; 214 - DC negative external connection line; 215 - DC negative connection line; 216 - Second power chip; 217 - AC external connection line; 218 - AC terminal; 219 - AC connection line; 220 - Second surface circuit layer; 230 - DC negative parallel bus electrode; 240 - DC positive parallel bus electrode; 231 - AC electrode; 24 1- AC parallel bus electrode; 300- Functional terminal; 3001- First type of functional terminal; 3002- Second type of functional terminal; 301, 341- Upper tube D-terminal detection terminal; 302, 342- Upper tube G-terminal control terminal; 303, 343- Upper tube S-terminal control terminal; 304- First temperature detection terminal on the first side; 305- First side resistor; 306- Second temperature detection terminal on the first side; 344- First temperature detection terminal on the second side; 345- Second side resistor; 346- Second temperature detection terminal on the second side Temperature detection terminal; 307, 347 - Lower transistor S-terminal control terminal; 308, 348 - Lower transistor G-terminal control terminal; 309, 349 - Lower transistor D-terminal detection terminal; 311, 351 - Upper transistor D-terminal bonding wire; 312, 352 - Upper transistor G-terminal bonding wire; 321 - Upper transistor power chip G-terminal; 313, 353 - Upper transistor S-terminal bonding wire; 318, 358 - Lower transistor G-terminal bonding wire; 322 - Lower transistor power chip G-terminal; 319, 359 - Lower transistor D-terminal bonding wire; 400 - Semiconductor power device. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] As described in the background section, with the development of power electronics technology, semiconductor power devices have attracted increasing attention. Semiconductor power devices are devices that combine semiconductor power chips according to specific functions and patterns and then package them into a single unit. They are mainly used in the power circuits of power electronic systems and are the core hardware for realizing power conversion. Therefore, high-performance semiconductor power devices and corresponding systems are one of the important research technologies in the semiconductor field.

[0044] Based on this, the embodiments of this application provide a semiconductor power device and a semiconductor power system, which effectively solves the technical problems existing in the prior art and enables the semiconductor power device and semiconductor power system to have better performance.

[0045] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 13 The technical solutions provided in the embodiments of this application will be described in detail.

[0046] Combination Figures 1 to 3 As shown, Figure 1 This is a top view of a semiconductor power device provided in an embodiment of this application. Figure 2 This is a side view of a semiconductor power device provided in an embodiment of this application. Figure 3 This is a partial stack-up diagram of a semiconductor power device provided in an embodiment of this application. The semiconductor power device 400 provided in this embodiment includes: a power circuit board (not shown), a plastic encapsulation housing 201, at least one current terminal 20, and at least one functional terminal 300.

[0047] The power circuit board provided in this application embodiment includes: a circuit board body 206, a first power chipset to an Nth power chipset, and a first internal connection line to an Nth internal connection line (hereinafter referred to as...). Figure 3 The first internal connection line 212 is shown as an illustration. Each internal connection line may include a chip connection portion 210 electrically connected to the chip and a surface line connection portion 211 electrically connected to the surface line layer, and at least one external connection line 02. The i-th power chip group includes at least one i-th power chip (with... Figure 3 The first power chip 209 and the second power chip 216 are shown in the diagram; in the thickness direction parallel to the semiconductor power device 400, one side surface of the circuit board body 206 includes a first surface circuit layer to an Nth surface circuit layer (to be continued). Figure 3(The first surface circuit layer 205 and the second surface circuit layer 220 are shown in the diagram). The i-th power chip group is electrically connected to the i-th surface circuit layer. The i-th power chip group is electrically connected to the (i+1)-th surface circuit layer through the i-th internal connection line. N is an integer not less than 1, and i is a positive integer not greater than N. That is, the first power chip 209 is disposed on the first surface circuit layer 205, the second power chip 216 is disposed on the second surface circuit layer 220, and the first internal connection line 212 electrically connects the first power chip 209 and the second surface circuit layer 220, thereby realizing the electrical connection between the first power chip 209 and the second power chip 216 according to a set method. Among them, at least one power chip group from the first power chip group to the Nth power chip group is electrically connected to the corresponding external connection line 02, and / or, at least one surface circuit layer from the first surface circuit layer to the Nth surface circuit layer is electrically connected to the corresponding external connection line 02. Optionally, the circuit board body 206 provided in this embodiment can be the intermediate ceramic layer of a ceramic copper-clad substrate. The surface circuit layer can be the copper layer on the upper surface of a ceramic copper-clad substrate, and the chip can be soldered onto this copper layer; for example, the first power chip 209 can be soldered onto the first surface circuit layer 205, and the second power chip 216 can be soldered onto the second surface circuit layer 220. The internal connection lines can be the bonding copper strips inside the device.

[0048] In some embodiments, the external connection line 02 provided in this application includes at least one first type external connection line 021 and / or at least one second type external connection line 022; the first type external connection line 021 is electrically connected to the power chipset, and the first type external connection line 021 is located on the side of the power chipset away from the circuit board body 206; in the thickness direction parallel to the semiconductor power device 400, the first type external connection line 021 extends toward the side away from the circuit board body 206 and passes through the surface of the plastic encapsulation housing 201; the second type external connection line 022 is electrically connected to the surface circuit layer, and the second type external connection line 022 is located on the side of the surface circuit layer away from the circuit board body 206; in the thickness direction perpendicular to the semiconductor power device 400, the second type external connection line 022 extends toward the side away from the power chipset and passes through the side of the plastic encapsulation housing 201.

[0049] The plastic encapsulation shell 201 provided in this application embodiment encapsulates the power circuit board, thereby protecting the internal components of the power circuit board.

[0050] The current terminal 20 provided in this embodiment is located outside the plastic encapsulation housing 201. The current terminal 20 includes at least one first-type current terminal 21 and / or at least one second-type current terminal 22. In the thickness direction parallel to the semiconductor power device 400 (i.e., direction Y), the first-type current terminal 21 is located on the surface of one side of the plastic encapsulation housing 201. In the thickness direction perpendicular to the semiconductor power device 400, the second-type current terminal 22 is located on the side of one side of the plastic encapsulation housing 201. In the orthographic projection onto a reference plane perpendicular to the thickness direction of the semiconductor power device 400 (i.e., direction X), the length a1 of the first side of the current terminal 20 is greater than the length a2 of the second side of the current terminal 20. The extension direction of the first side of the current terminal 20 is the same as the extension direction of the adjacent side of the plastic encapsulation housing 201, and the extension direction of the second side of the current terminal 20 intersects with the extension direction of the adjacent side of the plastic encapsulation housing 201. Optionally, the orthographic projection of the current terminal 20 provided in this embodiment on the reference plane can be rectangular, and this application does not impose specific limitations on this. The power circuit board is electrically connected to the current terminal 20 through the plastic encapsulation housing 201; that is, the external connection line 02 is electrically connected to the corresponding current terminal 20 through the plastic encapsulation housing 201 respectively; specifically, the first type of current terminal 21 is electrically connected to the corresponding first type of external connection line 021, and the second type of current terminal 22 is electrically connected to the corresponding second type of external connection line 022.

[0051] The functional terminal 300 provided in this application embodiment is located outside the plastic encapsulation housing 201. In the thickness direction parallel to the semiconductor power device 400, the functional terminal 300 is located on one side of the plastic encapsulation housing 201, and the functional terminal 300 is electrically connected to the power circuit board through the plastic encapsulation housing 201.

[0052] It is understood that in the technical solution provided in this application embodiment, the semiconductor power device 400 includes a plastic encapsulation shell 201. This indicates that the semiconductor power device 400 is packaged using a plastic encapsulation method, thereby giving it better resistance to vibration, water, dust, and oxidation, improving its insulation performance, and reducing its size. Furthermore, in the semiconductor power device 400 provided in this application embodiment, the length a1 of the first side of the current terminal 20 is greater than the length a2 of its second side, allowing the current terminal 20 to be designed as a short and wide shape. This reduces the parasitic inductance of the current terminal 20 in the semiconductor power device 400 and the system, and facilitates the fixed connection between the current terminal 20 and other circuits, thereby improving the performance of the semiconductor power device 400 and the semiconductor power system using this semiconductor power device 400. In addition, the stacked structure of the semiconductor power device 400 provided in this application embodiment can reduce the area of ​​the main power circuit, reduce the parasitic inductance of the main power circuit, and further improve the device's performance.

[0053] Continue as Figure 2 and Figure 3 As shown in the embodiments of this application, the semiconductor power device 400 further includes a heat dissipation surface 207. In the thickness direction parallel to the semiconductor power device 400, the heat dissipation surface 207 is located on one side surface of the power circuit board. Specifically, the heat dissipation surface 207 is located on the side of the power circuit board facing away from its surface circuit layer, and the molding compound 201 exposes the heat dissipation surface 207. The heat dissipation surface 207 can be soldered or pressed onto a heat sink to achieve heat dissipation for the device. Optionally, the heat dissipation surface 207 can be the copper plating layer of the circuit board body 206, i.e., the lower copper plating layer of the ceramic copper-clad substrate. Furthermore, the functional terminal 300 and the first type of current terminal 21 provided in these embodiments are located on the same side of the molding compound 201, i.e., both the functional terminal 300 and the first type of current terminal 21 are located on the side of the molding compound 201 facing away from the heat dissipation surface 207, thereby facilitating the centralized design of the heat dissipation surface 207 and better heat dissipation.

[0054] In some embodiments, the current terminal 20 provided in this embodiment may include two second-type current terminals 22, which are respectively disposed on opposite sides of the plastic encapsulation housing 201. In the orthographic projection onto the reference plane, the first side of the first-type current terminal 21 and the first side of the second-type current terminal 22 extend in the same direction; the second side of the first-type current terminal 21 and the second side of the second-type current terminal 22 also extend in the same direction. The first-type current terminal 21 and the second-type current terminal 22 are designed to be short and wide, thereby reducing the parasitic inductance of the current terminal 20 in the semiconductor power device 400 and the system, and facilitating the fixed connection between the current terminal 20 and other lines, thereby improving the performance of the semiconductor power device 400 and the semiconductor power system using the semiconductor power device 400.

[0055] Specifically, the power circuit board provided in this application embodiment may include a half-bridge power circuit. The power circuit board provided in this application embodiment includes: a first power chipset and a second power chipset. The first power chipset includes at least one parallel upper-side power chip (i.e., the first power chip 209 is the upper-side power chip), and the second power chipset includes at least one parallel lower-side power chip (i.e., the second power chip 216 is the lower-side power chip). The external connection lines include a DC negative external connection line, a DC positive external connection line, and an AC external connection line. The current terminals can be high-voltage current terminals. The first type of current terminal 21 includes a DC negative terminal 213, and the second type of current terminal 22 includes a DC positive terminal 202 and an AC terminal 218. The functional terminal 300 includes at least one of a control terminal and a detection terminal. Figure 3 and Figure 4 As shown, Figure 4This is a top view of another semiconductor power device provided in the embodiments of this application. Taking a power circuit board including a half-bridge power circuit as an example, that is, taking the semiconductor power device 400 as a corresponding device of the half-bridge power circuit as an example, the first type of current terminal 21 includes a DC negative terminal 213, and the external connection line 02 includes a DC negative external connection line 214. The DC negative terminal 213 and the DC negative external connection line 214 are electrically connected to form a DC negative connection line 215. The DC negative connection line 215 can be a copper busbar electrically connected to the negative terminal of the DC bus capacitor. The second type of current terminal 22 includes a DC positive terminal 202 and an AC terminal 218. The external connection line 02 also includes a DC positive external connection line 203 and an AC external connection line 217. The DC positive external connection line 203 and the DC positive terminal 202 are electrically connected to form a DC positive connection line 204. The AC terminal 218 and the AC external connection line 217 are electrically connected to form an AC connection line 219. The DC positive connection line 204 can be a copper busbar electrically connected to the positive terminal of the DC bus capacitor, and the AC connection line 219 can be an AC copper busbar. The first power chip 209 is the upper-side power chip, and the second power chip 216 is the lower-side power chip. At least the drain (D) and positive DC terminal (DC) connection 204 of the upper power chip are electrically connected to the first surface circuit layer 205, thus connecting the drain (D) and positive DC terminal (DC) connection 204 of the upper power chip. At least the drain (D) and AC connection 219 of the lower power chip are electrically connected to the second surface circuit layer 220, thus connecting the drain (D) of the lower power chip to the AC connection 219 and the source (S) of the lower power chip to the negative DC terminal (DC) connection 215. The first internal connection line 212 connects the source (S) of the upper power chip to the second surface circuit layer 220, thereby achieving that the source (S) of the upper power chip and the drain (D) of the lower power chip are both electrically connected to the AC connection 219.

[0056] In the orthographic projection of the reference plane, the DC positive terminal 202 and AC terminal 218 provided in this embodiment can be respectively disposed on opposite sides of the plastic-encapsulated housing 201, and the DC negative terminal 213 can be disposed between the DC positive terminal 202 and the AC terminal 218. Furthermore, the DC positive terminal 202, DC negative terminal 213, and AC terminal 218 are designed with a short and wide shape, which can reduce the parasitic inductance of the current terminal 20, making it suitable for laser welding and improving the performance of related devices. (Continue referring to...) Figure 4As shown, the functional terminal 300 and the DC negative terminal 213 provided in this embodiment are both located on the same side of the plastic encapsulation housing 201, that is, in the thickness direction of the parallel semiconductor power device 400, the functional terminal 300 and the DC negative terminal 213 are both located on the side of the plastic encapsulation housing 201 away from the heat dissipation surface 207. Among them, the functional terminal 300 may include detection terminals and control terminals, specifically including the upper tube drain detection terminal 301 (the upper tube refers to the upper tube power chip), the upper tube gate control terminal 302, the upper tube source control terminal 303, the first temperature detection terminal 304 on the first side, the second temperature detection terminal 306 on the first side, the lower tube source control terminal 307 (the lower tube refers to the lower tube power chip), the lower tube gate control terminal 308, and the lower tube drain detection terminal 309. The upper MOSFET's drain (D) detection terminal 301 is electrically connected to the drain (D) terminal of the upper MOSFET power chip in the half-bridge power circuit, used to detect the drain voltage of the upper MOSFET power chip; the upper MOSFET's gate (G) control terminal 302 is electrically connected to the gate (G) terminal of the upper MOSFET power chip in the half-bridge power circuit, used to control the gate (G) terminal of the upper MOSFET power chip; the upper MOSFET's source (S) control terminal 303 is electrically connected to the source (S) terminal of the upper MOSFET power chip in the half-bridge power circuit, working in conjunction with the upper MOSFET's gate control terminal 302 to control the gate (G) terminal of the upper MOSFET power chip. Similarly, the lower MOSFET's source (S) detection terminal 307 is electrically connected to the source (S) terminal of the lower MOSFET power chip in the half-bridge power circuit, working in conjunction with the lower MOSFET's gate (G) control terminal 308 to control the gate (G) terminal of the lower MOSFET power chip; the lower MOSFET's gate (G) control terminal 308 is electrically connected to the gate (G) terminal of the lower MOSFET power chip in the half-bridge power circuit, used to control the gate (G) terminal of the lower MOSFET power chip; and the lower MOSFET's drain (D) detection terminal 309 is electrically connected to the drain (D) terminal of the lower MOSFET power chip in the half-bridge power circuit, used to detect the drain voltage of the lower MOSFET power chip.

[0057] like Figure 1 As shown, the functional terminal 300 provided in this embodiment may include at least one first-type functional terminal 3001; in the orthographic projection of the reference plane, and along the extending direction of the first side of the first-type current terminal 21, the first-type functional terminal 3001 is located on one side of the first-type current terminal 21; all first-type functional terminals 3001 may be spaced apart along the extending direction of the second side of the first-type current terminal 21, and the spacing between two adjacent first-type functional terminals 3001 may be set to not less than 0.5 mm. When the power circuit board includes a half-bridge power circuit, such as Figure 4 As shown, the first type of functional terminal 3001 may include an upper tube D-pole detection terminal 301, an upper tube G-pole control terminal 302, an upper tube S-pole control terminal 303, a first temperature detection terminal 304 on the first side, a second temperature detection terminal 306 on the first side, a lower tube S-pole control terminal 307, a lower tube G-pole control terminal 308, and a lower tube D-pole detection terminal 309.

[0058] like Figure 5The diagram shows a top view of another semiconductor power device provided in this application embodiment. The functional terminal 300 provided in this application embodiment further includes at least one second-type functional terminal 3002. At least one pair of first-type functional terminals 3001 and second-type functional terminals 3002 have the same function. At least some terminals in the second-type functional terminals 3002 are equivalent to spare terminals. Users can select the functional terminals 300 as needed, improving flexibility. Optionally, the first-type functional terminals 3001 and second-type functional terminals 3002 with the same function provided in this application embodiment can be symmetrically arranged, which is beneficial for the layout design of devices and systems. This application does not impose specific limitations on this. In the orthographic projection of the reference plane, and along the extension direction of the first side of the first-type current terminal 21, the first-type functional terminals 3001 and second-type functional terminals 3002 are respectively located on both sides of the first-type current terminal 21. All first-type functional terminals 3001 can be spaced apart along the extension direction of the second side of the first-type current terminal 21, and the distance between two adjacent first-type functional terminals 3001 can be set to not less than 0.5 mm. Similarly, all second-class functional terminals 3002 can be spaced apart along the extension direction of the second side of the first-class current terminal 21, and the spacing between two adjacent second-class functional terminals 3002 can be set to be not less than 0.5 mm. (Reference) Figure 6 The diagram shows a top view of another semiconductor power device provided in an embodiment of this application. When the power circuit board includes a half-bridge power circuit, the first type of functional terminal 3001 and the second type of functional terminal 3002 can be respectively disposed on both sides of the DC negative terminal 213 in the direction of its first side extension. The first type of functional terminal 3001 may include an upper tube drain detection terminal 301, an upper tube gate control terminal 302, an upper tube source control terminal 303, a first temperature detection terminal 304 on the first side, a second temperature detection terminal 306 on the first side, a lower tube source control terminal 307, a lower tube gate control terminal 308, and a lower tube drain detection terminal 309; while the second type of functional terminal 3002 may include an upper tube drain detection terminal 341, an upper tube gate control terminal 342, an upper tube source control terminal 343, a first temperature detection terminal 344 on the second side, a second temperature detection terminal 346 on the second side, a lower tube source control terminal 347, a lower tube gate control terminal 348, and a lower tube drain detection terminal 349.

[0059] In some embodiments, at least one pair of functionally identical first-type functional terminals 3001 and second-type functional terminals 3002 provided in this application are electrically connected. Specifically, as shown below... Figure 7The diagram shown is a partial stacked view from a top perspective of a semiconductor power device provided in an embodiment of this application. When the power circuit board provided in this embodiment includes a half-bridge power circuit, the drain (D) terminal of the upper transistor power chip is electrically connected to the first surface circuit layer 205. Therefore, the upper transistor D-terminal detection terminal 301 can be electrically connected to the first surface circuit layer 205 via the upper transistor D-terminal bonding wire 311, and the upper transistor D-terminal detection terminal 341 can be electrically connected to the first surface circuit layer 205 via the upper transistor D-terminal bonding wire 351, thereby achieving an electrical connection between the upper transistor D-terminal detection terminals 301 and 341. The upper transistor G-terminal control terminal 302 can be electrically connected to the gate (G) terminal 321 of the upper transistor power chip via the upper transistor G-terminal bonding wire 312, and the upper transistor G-terminal control terminal 342 can be electrically connected to the gate (G) terminal 321 of the upper transistor power chip via the upper transistor G-terminal bonding wire 352, thereby achieving an electrical connection between the upper transistor G-terminal control terminals 302 and 342. The source (S) terminal of the upper MOSFET power chip is electrically connected to the chip connection portion 210. Therefore, the upper MOSFET S-terminal control terminal 303 is electrically connected to the chip connection portion 210 via the upper MOSFET S-terminal bonding wire 313, and the upper MOSFET S-terminal control terminal 343 is electrically connected to the chip connection portion 210 via the upper MOSFET S-terminal bonding wire 353, thus achieving an electrical connection between the upper MOSFET S-terminal control terminals 303 and 343. Similarly, the lower MOSFET G-terminal control terminal 308 is electrically connected to the gate (G) terminal 322 of the lower MOSFET power chip via the lower MOSFET G-terminal bonding wire 318, and the lower MOSFET G-terminal control terminal 348 is electrically connected to the gate (G) terminal 322 of the lower MOSFET power chip via the lower MOSFET G-terminal bonding wire 358, thus achieving an electrical connection between the lower MOSFET G-terminal control terminals 308 and 348. The drain (D) terminal of the lower MOSFET power chip is electrically connected to the second surface circuit layer 220. Therefore, the lower MOSFET drain detection terminal 309 can be electrically connected to the second surface circuit layer 220 via the lower MOSFET drain bonding wire 319, and the lower MOSFET drain detection terminal 349 can be electrically connected to the second surface circuit layer 220 via the lower MOSFET drain bonding wire 359, thus achieving electrical connection between the lower MOSFET drain detection terminals 309 and 349. (Reference) Figure 8The diagram shown is a partial stacked view from a top perspective of another semiconductor power device provided in this application embodiment. In this embodiment, the power circuit board includes a half-bridge power circuit, and the source (S) terminal of the lower transistor power chip is electrically connected to the surface connection portion 211. Thus, the lower transistor S-terminal detection terminal 307 is electrically connected to the surface connection portion 211 via a lower transistor S-terminal bonding wire (not shown), and the lower transistor S-terminal detection terminal 347 is electrically connected to the surface connection portion 211 via another lower transistor S-terminal bonding wire (not shown), thereby achieving electrical connection between the lower transistor S-terminal detection terminals 307 and 347. Furthermore, the power circuit board includes a first-side resistor 305 and / or a second-side resistor 345 to detect the device temperature in the corresponding area. The first temperature detection terminal 304 and the second temperature detection terminal 306 on the first side are electrically connected to both ends of the first-side resistor 305, and the first temperature detection terminal 344 and the second temperature detection terminal 346 on the second side are electrically connected to both ends of the second-side resistor 345.

[0060] Combination Figure 7 and Figure 8 As shown, the circuit formed by connecting the first type of current terminal 21 and the first type of external connection line 021 provided in this application embodiment has at least one encapsulated through-hole. Also, the internal connection line provided in this application embodiment has at least one encapsulated through-hole. For example, the circuit composed of the DC negative terminal 213 and the DC negative external connection line 214 has at least one encapsulated through-hole, and the first internal connection line 212 has at least one encapsulated through-hole, thereby facilitating the entry of encapsulation material into the area between the stacked layers and improving the encapsulation effect of the device.

[0061] In some embodiments, the first power chip group and the Nth power chip group provided in this application can be arranged side by side in a row. Simultaneously, in the first to Nth power chip groups, all power chips in each power chip group can be arranged side by side in a row, and the side-by-side arrangement direction of the power chips can intersect with the side-by-side arrangement direction of the power chip groups. Alternatively, the first power chip group and the Nth power chip group provided in this application can be arranged side by side in a row. Simultaneously, in the first to Nth power chip groups, all power chips in each power chip group can be arranged in multiple rows, the side-by-side arrangement direction of each row of power chips can intersect with the side-by-side arrangement direction of the power chip groups, and the arrangement direction of all rows of power chips in a power chip group can be the same as the side-by-side arrangement direction of the power chip groups. The impedance difference between the side-by-side power chips and the current terminals is small, which can reduce the current unevenness on different power chips and improve device performance. In this embodiment, the first power chip group and the N power chip group are arranged side-by-side in the same direction as the extension direction of the second side of the current terminal 20; the side-by-side arrangement direction of a row of power chips in the power chip group is the same as the extension direction of the first side of the current terminal 20. Optionally, all power chips in the power chip group provided in this embodiment can be electrically connected in parallel. Figure 7 and Figure 8 As shown in the embodiments of this application, when the power circuit board includes a half-bridge power circuit, the first power chip group and the second power chip group are arranged side by side in a row. Similarly, the upper power chip (i.e., the first power chip 209) can be arranged side by side and connected in parallel in a row, and the lower power chip (i.e., the second power chip 216) can be arranged side by side and connected in parallel in a row. The side-by-side arrangement direction of the power chip groups and the side-by-side arrangement direction of the power chips intersect (e.g., are perpendicular). This application embodiment does not impose specific limitations on the number of upper and lower power chips. The impedance difference between the side-by-side upper power chips and the DC positive terminal 202 is small, which can reduce the uneven current flow of the chips. The impedance difference between the side-by-side lower power chips and the DC negative terminal 213 is small, which can reduce the uneven current flow of the chips. At the same time, the impedance difference between the side-by-side upper and lower power chips and the AC terminal 218 is small, which can reduce the uneven current flow of the chips.

[0062] In some embodiments, the power chip provided in this application can be an IGBT (Insulated Gate Bipolar Transistor) chip. An IGBT chip has three terminals: collector (C), emitter (E), and gate (G). When the voltage between the gate and emitter exceeds a certain value (threshold voltage), the IGBT chip conducts, and current can flow from the collector to the emitter, but it cannot conduct in the reverse direction. To provide a reverse conduction path for the IGBT chip, a diode is typically connected in anti-parallel within the IGBT chip. Alternatively, the power chip provided in this application can be a MOSFET (Metal Oxide Semiconductor FET) chip. A MOSFET chip has three terminals: drain (D), source (S), and gate (G). When the voltage between the gate and source exceeds a certain value (threshold voltage), the MOSFET chip conducts, and current can flow from the drain to the source. Because of the structure of the MOSFET chip, it contains a reverse-parallel diode, so current can flow from the source (S) to the drain (D) terminal regardless of whether the MOSFET chip is in the on state. Furthermore, the power chip provided in this application embodiment can also be other types of chips, and this application does not impose specific limitations on them.

[0063] Based on the same inventive concept, this application also provides a semiconductor power system. Referring to the accompanying drawings illustrating the semiconductor power device 400 above, and also referring to... Figure 9 As shown, Figure 9 This is a partial stack-up diagram of a semiconductor power system provided in an embodiment of this application. The semiconductor power system includes at least one semiconductor power device 400 and a passive device 101. The semiconductor power device 400 is the semiconductor power device provided in any of the above embodiments. The semiconductor power device 400 provided in this embodiment includes: a power circuit board (not shown), a plastic encapsulation housing 201, at least one current terminal 20, and at least one functional terminal 300.

[0064] The power circuit board provided in this application embodiment includes: a circuit board body 206, a first power chipset to an Nth power chipset, and a first internal connection line to an Nth internal connection line (hereinafter referred to as...). Figure 3 The first internal connection line 212 is shown as an illustration. Each internal connection line may include a chip connection portion 210 electrically connected to the chip and a surface line connection portion 211 electrically connected to the surface line layer, and at least one external connection line 02. The i-th power chip group includes at least one i-th power chip (with... Figure 3The first power chip 209 and the second power chip 216 are shown in the diagram; in the thickness direction parallel to the semiconductor power device 400, one side surface of the circuit board body 206 includes a first surface circuit layer to an Nth surface circuit layer (to be continued). Figure 3 (The first surface circuit layer 205 and the second surface circuit layer 220 are shown in the diagram). The i-th power chip group is electrically connected to the i-th surface circuit layer. The i-th power chip group is electrically connected to the (i+1)-th surface circuit layer through the i-th internal connection line. N is an integer not less than 1, and i is a positive integer not greater than N. That is, the first power chip 209 is disposed on the first surface circuit layer 205, the second power chip 216 is disposed on the second surface circuit layer 220, and the first internal connection line 212 electrically connects the first power chip 209 and the second surface circuit layer 220, thereby realizing the electrical connection between the first power chip 209 and the second power chip 216 according to a set method. Among them, at least one power chip group from the first power chip group to the Nth power chip group is electrically connected to the corresponding external connection line 02, and / or, at least one surface circuit layer from the first surface circuit layer to the Nth surface circuit layer is electrically connected to the corresponding external connection line 02. Optionally, the circuit board body 206 provided in this embodiment can be the intermediate ceramic layer of a ceramic copper-clad substrate. The surface circuit layer can be the copper layer on the upper surface of a ceramic copper-clad substrate, and the chip can be soldered onto this copper layer; for example, the first power chip 209 can be soldered onto the first surface circuit layer 205, and the second power chip 216 can be soldered onto the second surface circuit layer 220. The internal connection lines can be the bonding copper strips inside the device.

[0065] In some embodiments, the external connection line 02 provided in this application includes at least one first type external connection line 021 and / or at least one second type external connection line 022; the first type external connection line 021 is electrically connected to the power chipset, and the first type external connection line 021 is located on the side of the power chipset away from the circuit board body 206; in the thickness direction parallel to the semiconductor power device 400, the first type external connection line 021 extends toward the side away from the circuit board body 206 and passes through the surface of the plastic encapsulation housing 201; the second type external connection line 022 is electrically connected to the surface circuit layer, and the second type external connection line 022 is located on the side of the surface circuit layer away from the circuit board body 206; in the thickness direction perpendicular to the semiconductor power device 400, the second type external connection line 022 extends toward the side away from the power chipset and passes through the side of the plastic encapsulation housing 201.

[0066] The plastic encapsulation shell 201 provided in this application embodiment encapsulates the power circuit board, thereby protecting the internal components of the power circuit board.

[0067] The current terminal 20 provided in this embodiment is located outside the plastic encapsulation housing 201. The current terminal 20 includes at least one first-type current terminal 21 and / or at least one second-type current terminal 22. In the thickness direction parallel to the semiconductor power device 400 (i.e., direction Y), the first-type current terminal 21 is located on the surface of one side of the plastic encapsulation housing 201. In the thickness direction perpendicular to the semiconductor power device 400, the second-type current terminal 22 is located on the side of one side of the plastic encapsulation housing 201. In the orthographic projection onto a reference plane perpendicular to the thickness direction of the semiconductor power device 400 (i.e., direction X), the length a1 of the first side of the current terminal 20 is greater than the length a2 of the second side of the current terminal 20. The extension direction of the first side of the current terminal 20 is the same as the extension direction of the adjacent side of the plastic encapsulation housing 201, and the extension direction of the second side of the current terminal 20 intersects with the extension direction of the adjacent side of the plastic encapsulation housing 201. Optionally, the orthographic projection of the current terminal 20 provided in this embodiment on the reference plane can be rectangular, and this application does not impose specific limitations on this. The power circuit board is electrically connected to the current terminal 20 through the plastic encapsulation housing 201; that is, the external connection line 02 is electrically connected to the corresponding current terminal 20 through the plastic encapsulation housing 201 respectively; specifically, the first type of current terminal 21 is electrically connected to the corresponding first type of external connection line 021, and the second type of current terminal 22 is electrically connected to the corresponding second type of external connection line 022.

[0068] The functional terminal 300 provided in this application embodiment is located outside the plastic encapsulation housing 201. In the thickness direction parallel to the semiconductor power device 400, the functional terminal 300 is located on one side of the plastic encapsulation housing 201, and the functional terminal 300 is electrically connected to the power circuit board through the plastic encapsulation housing 201.

[0069] The passive device 101 is electrically connected to the current terminal 20 in the semiconductor power device 400. That is, the passive device 101 is electrically connected to the corresponding first type of current terminal 21 in the semiconductor power device 400, and / or, the passive device 101 is electrically connected to the corresponding second type of current terminal 22 in the semiconductor power device 400.

[0070] In some embodiments, when the semiconductor power system provided in this application includes at least two semiconductor power devices 400, the current terminals 20 of different semiconductor power devices 400 can each be electrically connected to the electrodes of the passive device 101. The following description uses an inverter system as an example of the semiconductor power system. The power circuit board provided in this application includes a half-bridge power circuit, and the passive device 101 includes a bus capacitor. The first type of current terminal 21 includes a DC negative terminal 213, and the second type of current terminal 22 includes a DC positive terminal 202 and an AC terminal 218; the functional terminal 300 includes at least one of a control terminal and a detection terminal. The structure of this semiconductor power device 400 is the same as the device structure provided in any of the above embodiments, and therefore will not be described in detail here. Reference Figure 10 The image shown is a partial top view of a semiconductor power system provided in an embodiment of this application. The passive device 101 provided in this embodiment includes a passive device negative terminal 102 and a passive device positive terminal 103. The passive device negative terminal 102 is the negative terminal of the bus capacitor, and the passive device positive terminal 103 is the positive terminal of the bus capacitor. The DC positive terminal 202 of each semiconductor power device 400 is electrically connected to the passive device positive terminal 103 of the passive device 101; and the AC terminal 218 of each semiconductor power device 400 is electrically connected to its corresponding AC electrode 231.

[0071] Alternatively, when the semiconductor power system provided in this application includes at least two semiconductor power devices 400, the current terminals 20 of different semiconductor power devices 400 can be connected in parallel using parallel electrodes, and then the parallel electrodes are electrically connected to the passive device 101. That is, the semiconductor power system includes: at least two semiconductor power devices 400 connected in parallel; wherein, the semiconductor power system includes: at least one parallel bus electrode, the parallel bus electrode being electrically connected to a parallel current terminal 20 of the same type, and the passive device 101 being electrically connected to at least a portion of the parallel bus electrode. Specifically, the parallel bus electrode includes at least one first-type parallel bus electrode and / or at least one second-type parallel bus electrode; wherein, one first-type parallel bus electrode is electrically connected to a parallel first-type current terminal 21 of the same type; one second-type parallel bus electrode is electrically connected to a parallel second-type current terminal 22 of the same type; and the passive device 101 is electrically connected to the corresponding parallel bus electrode. See details. Figure 11The diagram shows a partial top view of another semiconductor power system provided in this embodiment. The passive device 101 provided in this embodiment includes a passive device negative terminal 102 and a passive device positive terminal 103. The passive device negative terminal 102 is the negative terminal of the bus capacitor, and the passive device positive terminal 103 is the positive terminal of the bus capacitor. The semiconductor power system includes a DC negative parallel bus electrode 230 electrically connected to the DC negative terminals 213 of all semiconductor power devices 400. The DC negative parallel bus electrode 230 is electrically connected to the passive device negative terminal 102. Simultaneously, the semiconductor power system includes multiple AC parallel bus electrodes 241, each AC parallel bus electrode 241 being electrically connected to the AC terminals 218 of at least two semiconductor power devices 400.

[0072] The above illustration shows that the DC negative terminal 213 can be connected in parallel via the DC negative bus electrode 230, and the AC terminal 218 can be connected in parallel via the AC parallel bus electrode 241. Furthermore, the DC positive terminal 202 provided in this embodiment can also be connected in parallel using the DC positive bus electrode; this application does not impose specific limitations on this.

[0073] The semiconductor power system provided in this application does not impose specific limitations on the number of parallel bus electrodes and their corresponding connections. For example... Figure 12 The image shown is a partial top view of another semiconductor power system provided in this application embodiment. The semiconductor power system provided in this application embodiment includes a DC negative parallel bus electrode 230 electrically connected to the DC negative terminal 213 of all semiconductor power devices 400. The DC negative parallel bus electrode 230 is electrically connected to the negative terminal 102 of the passive device. The semiconductor power system no longer includes an AC parallel bus electrode 241, but includes an AC electrode 231 that is individually electrically connected to the AC terminal 218 of one semiconductor power device 400. This needs to be specifically analyzed according to the actual application.

[0074] Combination Figures 10 to 11 As shown, the semiconductor power devices 400 connected in parallel according to the embodiments of this application can be arranged side by side; in the direction perpendicular to the side-by-side arrangement of the semiconductor power devices 400, the second type of current terminals 22 of the same type used for parallel connection in all the semiconductor power devices 400 are located on the same side of the semiconductor power devices 400, thereby facilitating the electrical connection between the parallel bus electrode and the current terminal 20. Figure 11All AC terminals 218 of the semiconductor power devices 400 are located on the same side, facilitating the connection between the AC parallel bus electrode 241 and different AC terminals 218. Optionally, in the thickness direction parallel to the semiconductor power devices 400, the parallel bus electrode and the electrically connected current terminal 20 are in overlapping contact for electrical connection; this application does not impose specific limitations on this. The parallel bus electrode can also be electrically connected to the current terminal 20 in other ways, which needs to be specifically analyzed according to the actual application.

[0075] In some embodiments, the functional terminal 300 and the first type of current terminal 21 provided in this application are located on the same side of the plastic encapsulation housing 201; when the first type of parallel bus electrode covers the functional terminal 300, the first type of parallel bus electrode is provided with a through hole through the functional terminal 300, and there is an isolation gap between the functional terminal 300 and the through hole. Figure 11 and Figure 12 The DC negative parallel bus electrode 230 is electrically connected to the DC negative terminal 213 of all semiconductor power devices 400. In the path from the DC negative parallel bus electrode 230 to all DC negative terminals 213, it is unavoidable that the functional terminal 300 will be covered, such as... Figure 11 The diagram shows the upper tube's D-pole detection terminal 341, upper tube's G-pole control terminal 342, upper tube's S-pole control terminal 343, the second-side first temperature detection terminal 344, upper tube's D-pole detection terminal 301, upper tube's G-pole control terminal 302, upper tube's S-pole control terminal 303, and the first-side first temperature detection terminal 304. The DC negative parallel bus electrode 230 is provided with through holes corresponding to these terminals so that these functional terminals 300 can be normally connected to external lines and to prevent these functional terminals 300 from being short-circuited with the DC negative parallel bus electrode 230.

[0076] In some embodiments, the parallel bus electrodes located on the upper surface of the plastic encapsulation housing 201 can also be encapsulated. That is, the external connection line 02 provided in this embodiment includes at least one first-type external connection line; the first-type external connection line is electrically connected to the power chipset, and the first-type external connection line is located on the side of the power chipset away from the circuit board body 206; in the thickness direction parallel to the semiconductor power device 400, the first-type external connection line extends through the surface of the plastic encapsulation housing 201 in the direction away from the circuit board body 206; the current terminal 20 includes at least one first-type current terminal 21; in the thickness direction parallel to the semiconductor power device 400, the first-type current terminal 21 is located on the surface of one side of the plastic encapsulation housing 201, and the first... A type of current terminal 21 is electrically connected to a corresponding type of first-class external connection line; the parallel bus electrode includes at least one type of first-class parallel bus electrode, one type of first-class parallel bus electrode is electrically connected to a parallel type of first-class current terminal 21 of the same type, the type of first-class parallel bus electrode is located on the side of the first-class current terminal 21 away from the plastic encapsulation housing 201, and there is a gap between the type of first-class parallel bus electrode and the plastic encapsulation housing 201; the semiconductor power system further includes: a plastic encapsulation layer 2201, the plastic encapsulation layer 2201 is located on the side of the plastic encapsulation housing 201 facing the type of first-class parallel bus electrode, and the plastic encapsulation layer 2201 at least partially covers the type of first-class parallel bus electrode. See details. Figure 13 As shown, the DC negative parallel bus electrode 230 provided in this application embodiment is a first type of parallel bus electrode, and the plastic encapsulation layer 2201 encapsulates at least part of the DC negative parallel bus electrode 230.

[0077] In summary, this application provides a semiconductor power device and a semiconductor power system. The semiconductor power device includes a plastic encapsulation shell, indicating that the semiconductor power device is packaged using a plastic encapsulation method. This gives the semiconductor power device better resistance to vibration, water, dust, and oxidation, and improves its insulation performance while reducing its size. Furthermore, in the semiconductor power device provided in this application, the length of the first side of the current terminal is greater than the length of its second side, allowing the current terminal to be designed as a short and wide shape. This reduces the parasitic inductance of the current terminal in the semiconductor power device and system, and facilitates the fixed connection between the current terminal and other lines, thereby improving the performance of the semiconductor power device and the semiconductor power system. In addition, the stacked structure of the semiconductor power device 400 provided in this application can reduce the area of ​​the main power circuit, reduce the parasitic inductance of the main power circuit, and further improve the performance of the device.

[0078] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0079] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0080] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0081] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0082] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0083] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A semiconductor power device, characterized in that, include: Power circuit board; A plastic-encapsulated housing that encapsulates the power circuit board; At least one current terminal, the current terminal including at least one first type of current terminal and / or at least one second type of current terminal; in a direction parallel to the thickness of the semiconductor power device, the first type of current terminal is located on the surface of one side of the plastic encapsulation housing; in a direction perpendicular to the thickness of the semiconductor power device, the second type of current terminal is located on the side of one side of the plastic encapsulation housing; the power circuit board is electrically connected to the current terminal through the plastic encapsulation housing; wherein, in an orthographic projection onto a reference plane perpendicular to the thickness direction of the semiconductor power device, the length of the first side of the current terminal is greater than the length of the second side of the current terminal, the extension direction of the first side of the current terminal is the same as the extension direction of the adjacent side of the plastic encapsulation housing, and the extension direction of the second side of the current terminal intersects with the extension direction of the adjacent side of the plastic encapsulation housing; At least one functional terminal is located on one side of the plastic encapsulation housing in a thickness direction parallel to the semiconductor power device, and the functional terminal is electrically connected to the power circuit board through the plastic encapsulation housing.

2. The semiconductor power device according to claim 1, characterized in that, The semiconductor power device further includes: The heat dissipation surface is located on one side surface of the power circuit board in a direction parallel to the thickness of the semiconductor power device, and the heat dissipation surface is exposed by the plastic encapsulation housing.

3. The semiconductor power device according to claim 1, characterized in that, The current terminals include two second-type current terminals, which are respectively disposed on opposite sides of the plastic-encapsulated housing.

4. The semiconductor power device according to claim 3, characterized in that, The first side of the first type of current terminal and the first side of the second type of current terminal extend in the same direction; The second side of the first type of current terminal and the second side of the second type of current terminal extend in the same direction.

5. The semiconductor power device according to claim 1, characterized in that, The functional terminals and the first type of current terminals are located on the same side of the plastic-encapsulated housing.

6. The semiconductor power device according to claim 5, characterized in that, The functional terminals include at least one type of first-class functional terminal; In the orthographic projection of the reference plane, and along the extension direction of the first side of the first type of current terminal, the first type of functional terminal is located on one side of the first type of current terminal.

7. The semiconductor power device according to claim 6, characterized in that, The functional terminals also include at least one second type of functional terminal, and at least one pair of the first type of functional terminals and the second type of functional terminals have the same function; In the orthographic projection of the reference plane, and along the extension direction of the first side of the first type of current terminal, the first type of functional terminal and the second type of functional terminal are respectively located on both sides of the first type of current terminal.

8. The semiconductor power device according to claim 7, characterized in that, At least one pair of functionally identical first-type functional terminals and second-type functional terminals are electrically connected.

9. The semiconductor power device according to claim 1, characterized in that, The first type of current terminal includes a DC negative terminal, and the second type of current terminal includes a DC positive terminal and an AC terminal; The functional terminals include at least one of control terminals and detection terminals.

10. The semiconductor power device according to claim 1, characterized in that, The power circuit board includes a half-bridge power circuit.

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