A dual range piezoresistive pressure sensor chip

Abstract

The utility model relates to a double range piezoresistive pressure sensor chip. The utility model discloses a SOI substrate structure, top layer thin oxide layer, low range pressure sensitive area, set up in the top silicon, and low range pressure sensitive area includes low range pressure sensitive area heavy doping P+ structure and low range pressure sensitive area light doping P type pressure sensitive resistance that low range pressure sensitive area heavy doping P+ structure electricity is connected, and low range pressure sensitive area is located in the area that chip plane direction is far away from the chip center, high range pressure sensitive area, set up in the top silicon, and high range pressure sensitive area includes high range pressure sensitive area heavy doping P+ structure and high range pressure sensitive area light doping P type pressure sensitive resistance that high range pressure sensitive area heavy doping P+ structure electricity is connected, and high range pressure sensitive area is located in the area that chip plane direction is close to the chip center, still include pressure sensitive area electricity connection metal layer, dielectric film, electric isolation layer and external connection PAD structure. The utility model can reduce the dependence on different specifications chips under different pressure detection scenes.

Description

Technical Field

[0001] This utility model relates to the field of piezoresistive pressure sensor technology, and in particular to a dual-range piezoresistive pressure sensor chip. Background Technology

[0002] Piezoresistive pressure sensor chips typically utilize the elastic deformation of a silicon sensitive diaphragm under external pressure, causing a change in the resistance of a piezoresistor mounted on the diaphragm. This change in resistance is then converted into an electrical signal via a bridge circuit. These chips are characterized by their small size, fast response speed, and ease of miniaturization and integration, making them highly valuable for pressure detection applications.

[0003] Because the pressure detection objects vary greatly in different scenarios, piezoresistive pressure sensors are required to have good range adaptability in order to reduce the adaptation costs and packaging complexity caused by repeatedly replacing different specifications of chips in different scenarios.

[0004] However, existing piezoresistive pressure sensors have a relatively limited range, and a single chip can usually only be adapted to a fixed pressure range. They are difficult to be compatible with high-pressure and low-pressure conditions, and different chips are required for multi-scenario detection, which increases the adaptation cost and packaging complexity. Utility Model Content

[0005] Therefore, the technical problem to be solved by this utility model is to overcome the problem that the piezoresistive pressure sensor in the prior art has a relatively limited range, which leads to increased adaptation costs and packaging complexity.

[0006] To solve the above-mentioned technical problems, this utility model provides a dual-range piezoresistive pressure sensor chip, comprising: The SOI substrate structure includes a supporting silicon wafer, a buried oxide insulating layer, and a top silicon wafer arranged sequentially from bottom to top. A thin oxide layer is disposed on the top silicon surface; A low-range varistor region is disposed within the top silicon. The low-range varistor region includes a heavily doped P+ structure and a lightly doped P- type varistor electrically connected to the heavily doped P+ structure. The low-range varistor region is located in a region away from the center of the chip in the chip plane direction. A high-range varistor region is disposed within the top silicon. The high-range varistor region includes a heavily doped P+ structure and a lightly doped P- type varistor that is electrically connected to the heavily doped P+ structure. The high-range varistor region is located in the region near the center of the chip in the chip plane direction. A varistor region electrically connected metal layer is disposed on the surface of the top thin oxide layer. The varistor region electrically connected metal layer includes a low-range varistor region electrically connected to the heavily doped P+ structure of the low-range varistor region and a high-range varistor region electrically connected to the heavily doped P+ structure of the high-range varistor region. A dielectric film is disposed on the surface of the top thin oxide layer and covers the electrically connected metal layer of the pressure-sensitive region; An electrical isolation layer is disposed on the surface of the dielectric film; An external connection PAD structure is disposed on the surface of the electrical isolation layer. The external connection PAD structure includes a low-range PAD structure electrically connected to the low-range varistor region electrical connection metal layer and a high-range PAD structure electrically connected to the high-range varistor region electrical connection metal layer.

[0007] In one embodiment of this utility model, four high-range pressure-sensitive areas are provided, which are centrally symmetrically distributed around the center of the chip. Four low-range pressure-sensitive areas are also provided, which are centrally symmetrically distributed around the center of the chip and are located outside the four high-range pressure-sensitive areas.

[0008] In one embodiment of this utility model, the two high-range varistor regions located on the upper and lower sides of the chip are arranged opposite each other along the Y-axis of the chip plane, and the two high-range varistor regions located on the left and right sides of the chip are arranged opposite each other along the X-axis of the chip plane; the two low-range varistor regions located on the upper and lower sides of the chip are arranged opposite each other along the Y-axis of the chip plane, and the two low-range varistor regions located on the left and right sides of the chip are arranged opposite each other along the X-axis of the chip plane.

[0009] In one embodiment of this utility model, a back release cavity is further included. The back release cavity is disposed on the back side of the supporting silicon wafer and extends to the back side of the buried oxide insulating layer. The projection of the back release cavity toward the low-range varistor region and the high-range varistor region respectively covers the corresponding low-range varistor region and the high-range varistor region.

[0010] In one embodiment of this utility model, the back release cavity includes a first release area located in the central region of the chip, a second release area extending from the first release area to each of the high-range pressure-sensitive areas, and a third release area extending from the first release area to each of the low-range pressure-sensitive areas. The projection of each second release area onto the corresponding high-range pressure-sensitive area covers the corresponding high-range pressure-sensitive area, and the projection of each third release area onto the corresponding low-range pressure-sensitive area covers the corresponding low-range pressure-sensitive area.

[0011] In one embodiment of the present invention, a thin oxide layer is provided on the back side of the supporting silicon wafer, and the back release cavity penetrates the thin oxide layer and extends to the back side of the buried oxide insulating layer.

[0012] In one embodiment of this utility model, the junction depth of the lightly doped P-type varistor in the low-range varistor region is greater than that of the lightly doped P-type varistor in the high-range varistor region.

[0013] In one embodiment of this invention, the doping concentration of the lightly doped P-type varistor in the high-range varistor region is greater than the doping concentration of the lightly doped P-type varistor in the low-range varistor region.

[0014] In one embodiment of this utility model, the target detection range of the low-range pressure-sensitive region is 0~500kPa, and the target detection range of the high-range pressure-sensitive region is 1MPa~5MPa.

[0015] In one embodiment of this utility model, The above-mentioned technical solution of this utility model has the following advantages compared with the prior art: The present invention discloses a dual-range piezoresistive pressure sensor chip, which addresses the problem that a single chip cannot simultaneously adapt to micro-pressure, low-pressure, and high-pressure detection. By setting low-range and high-range piezoresistive regions separately in the top silicon of the same SOI substrate structure, a single chip can simultaneously form a low-range pressure detection channel and a high-range pressure detection channel, reducing the dependence on different specifications of chips in different pressure detection scenarios.

[0016] This invention places the high-range varistor region near the center of the chip in the chip plane, and the low-range varistor region away from the chip center and outside the high-range varistor region. This ensures that the varistors of different ranges are located within strain regions that match their detection requirements. The low-range varistor region provides a deformation response more suitable for low-voltage detection, while the high-range varistor region provides a stable deformation response more suitable for high-voltage detection, thus balancing low-range detection sensitivity and high-range detection withstand voltage stability.

[0017] This invention utilizes a heavily doped P+ structure in the low-range varistor region, a lightly doped P- type varistor in the low-range varistor region, a heavily doped P+ structure in the high-range varistor region, a lightly doped P- type varistor in the high-range varistor region, and independent electrical connection metal layers and PAD structures to extract pressure detection signals of different ranges, thereby improving the stability of the signal path. Attached Figure Description

[0018] To make the content of this utility model easier to understand, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0019] Figure 1 This is a schematic diagram of the longitudinal cross-sectional structure of the dual-range piezoresistive pressure sensor chip of this utility model.

[0020] Figure 2 This is a schematic diagram of the planar layout of the low-range pressure-sensitive area and the high-range pressure-sensitive area of ​​this utility model.

[0021] Figure 3 This is a schematic diagram of the planar layout of the low-range pressure-sensitive area, the high-range pressure-sensitive area, and the rear release cavity of this utility model.

[0022] Figure 4 This is a schematic diagram of the planar layout of the low-range pressure-sensitive area and the high-range pressure-sensitive area of ​​this utility model.

[0023] Explanation of reference numerals in the instruction manual: 1. Supporting silicon wafer; 2. Buried oxide insulating layer; 3. Top silicon; 4. Top thin oxide layer; 41. Low-range varistor region; 42. High-range varistor region; 5. Heavy doped P+ structure in the low-range varistor region; 6. Lightly doped P- type varistor in the low-range varistor region; 7. Heavy doped P+ structure in the high-range varistor region; 8. Lightly doped P- type varistor in the high-range varistor region; 9. Electrical connection metal layer in the varistor region; 91. Electrical connection metal layer in the low-range varistor region; 92. Electrical connection metal layer in the high-range varistor region; 10. Bottom thin oxide layer; 11. Dielectric film; 12. Electrical isolation layer; 13. External connection PAD structure; 131. Low-range PAD structure; 132. High-range PAD structure; 14. Backside release cavity; 141. First release region; 142. Second release region; 143. Third release region. Detailed Implementation

[0024] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments are not intended to limit the present invention.

[0025] In this utility model, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this utility model, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model.

[0026] In this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc. are understood to exclude the stated number; "above," "below," "within," etc. are understood to include the stated number. In the description of this utility model, if "first" or "second" is used, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the order of the indicated technical features.

[0027] In this utility model, unless otherwise explicitly defined, terms such as "set," "install," and "connect" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model based on the specific content of the technical solution.

[0028] Reference Figures 1 to 4 As shown, a dual-range piezoresistive pressure sensor chip of this utility model includes: The SOI substrate structure includes a supporting silicon wafer 1, a buried oxide insulating layer 2, and a top silicon wafer 3 arranged sequentially from bottom to top. A top thin oxide layer 4 is disposed on the surface of the top silicon 3; A low-range varistor region 41 is disposed within the top silicon 3. The low-range varistor region 41 includes a heavily doped P+ structure 5 and a lightly doped P-type varistor 6 electrically connected to the heavily doped P+ structure 5. The low-range varistor region 41 is located in a region away from the center of the chip in the chip plane direction. A high-range varistor region 42 is disposed within the top silicon 3. The high-range varistor region 42 includes a heavily doped P+ structure 7 and a lightly doped P-type varistor 8 electrically connected to the heavily doped P+ structure 7. The high-range varistor region 42 is located in the region near the center of the chip in the chip plane direction. A varistor region electrical connection metal layer 9 is disposed on the surface of the top thin oxide layer 4. The varistor region electrical connection metal layer 9 includes a low-range varistor region electrical connection metal layer 91 electrically connected to the low-range varistor region heavily doped P+ structure 5 and a high-range varistor region electrical connection metal layer 92 electrically connected to the high-range varistor region heavily doped P+ structure 7. Dielectric film 11 is disposed on the surface of the top thin oxide layer 4 and covers the pressure-sensitive area electrical connection metal layer 9; An electrical isolation layer 12 is disposed on the surface of the dielectric film 11; An external connection PAD structure 13 is disposed on the surface of the electrical isolation layer 12. The external connection PAD structure 13 includes a low-range PAD structure 131 electrically connected to the low-range varistor region electrical connection metal layer 91 and a high-range PAD structure 132 electrically connected to the high-range varistor region electrical connection metal layer 92.

[0029] In one embodiment, four high-range pressure-sensitive regions 42 are provided, and the four high-range pressure-sensitive regions 42 are centrally symmetrically distributed around the center of the chip. Four low-range pressure-sensitive regions 41 are provided, and the four low-range pressure-sensitive regions 41 are centrally symmetrically distributed around the center of the chip, and are respectively located outside the four high-range pressure-sensitive regions 42.

[0030] Specifically, the two high-range varistor regions 42 located on the upper and lower sides of the chip are arranged opposite each other along the Y-axis of the chip plane, and the two high-range varistor regions 42 located on the left and right sides of the chip are arranged opposite each other along the X-axis of the chip plane; the two low-range varistor regions 41 located on the upper and lower sides of the chip are arranged opposite each other along the Y-axis of the chip plane, and the two low-range varistor regions 41 located on the left and right sides of the chip are arranged opposite each other along the X-axis of the chip plane.

[0031] With the above layout, both the low-range pressure-sensitive region 41 and the high-range pressure-sensitive region 42 can form a symmetrical detection structure around the center of the chip.

[0032] In one embodiment, a back-side release cavity 14 is further included. The back-side release cavity 14 is disposed on the back side of the supporting silicon wafer 1 and extends to the back side of the buried oxide insulating layer 2. The projection of the back-side release cavity 14 toward the low-range varistor region 41 and the high-range varistor region 42 respectively covers the corresponding low-range varistor region 41 and the high-range varistor region 42.

[0033] In one embodiment, the back-side release cavity 14 includes a first release region 141 located in the central region of the chip, a second release region 142 extending from the first release region 141 to each of the high-range pressure-sensitive regions 42, and a third release region 143 extending from the first release region 141 to each of the low-range pressure-sensitive regions 41. The projection of each second release region 142 toward the corresponding high-range pressure-sensitive region 42 covers the corresponding high-range pressure-sensitive region 42, and the projection of each third release region 143 toward the corresponding low-range pressure-sensitive region 41 covers the corresponding low-range pressure-sensitive region 41.

[0034] With the above configuration, the back release chamber 14 is used to form a pressure-sensitive membrane that can be deformed under pressure in the top silicon 3, so that the low-range pressure-sensitive region 41 and the high-range pressure-sensitive region 42 are in an effective strain region that matches their detection range.

[0035] In one embodiment, a thin oxide layer 10 is provided on the back side of the supporting silicon wafer 1, and the back release cavity 14 penetrates the thin oxide layer 10 and extends to the back side of the buried oxide insulating layer 2.

[0036] In one embodiment, the surface of the top thin oxide layer 4 is provided with a first electrical connection hole extending to the heavily doped P+ structure 5 in the low-range varistor region and the heavily doped P+ structure 7 in the high-range varistor region. The varistor region electrical connection metal layer 9 is connected to the corresponding heavily doped P+ structure 5 in the low-range varistor region and the heavily doped P+ structure 7 in the high-range varistor region through the first electrical connection hole. The surface of the electrical isolation layer 12 is provided with a second electrical connection hole extending to the varistor region electrical connection metal layer 9. The external connection PAD structure 13 is connected to the varistor region electrical connection metal layer 9 through the second electrical connection hole.

[0037] In one embodiment, the lightly doped P-type varistor 6 in the low-range varistor region is formed by boron ion implantation, with an implantation energy of 50 keV to 130 keV and an implantation dose of 0.5 × 10⁻⁶. 14 cm -2 ~1.8×10 14 cm -2 The low-range varistor region heavily doped P+ structure 5 is formed by boron ion implantation at an implantation energy of 30 keV to 80 keV and an implantation dose of 3 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 The annealing temperature for the low-range varistor region 41 is 1050℃~1150℃, and the annealing time is 120min~240min. Because the low-range varistor region 41 is close to the chip edge, it has the strongest pressure sensitivity and is most sensitive to pressure changes. Low-doping concentration and long-term high-temperature deep annealing are used, resulting in a larger junction depth and a higher piezoresistive coefficient. The target range of the low-range varistor region 41 can reach 0~500kPa. The heavily doped P+ structure 5 of the low-range varistor region is connected to the lightly doped P-type varistor 6 of the low-range varistor region, and forms a Wheatstone bridge with the electrically connected metal layer 91 of the low-range varistor region. To reduce resistance errors in the circuit, the resistance value of the internal interconnect structure should be as small as possible.

[0038] A high-range varistor region 42 is formed in the top silicon 3 near the center of the chip. A heavily doped P+ structure 7 and a lightly doped P-type varistor 8 are formed in the high-range varistor region 42. The heavily doped P+ structure 7 and the lightly doped P-type varistor 8 are connected and form a Wheatstone bridge with the high-range varistor region electrically connected metal layer 92. In order to reduce the resistance error in the circuit, the resistance value of the internal interconnect structure should be as small as possible.

[0039] The high-range varistor region, lightly doped P-type varistor 8, is formed by boron ion implantation with an implantation energy of 50 keV to 90 keV and an implantation dose of 0.5 × 10⁻⁶. 15 cm -2 ~2×10 15 cm -2 The high-range varistor region heavily doped P+ structure 7 is formed by boron ion implantation at an implantation energy of 20 keV to 60 keV and an implantation dose of 1 × 10⁻⁶. 16 cm -2 ~3×10 16 cm -2 The high-range varistor region 42 has an annealing temperature of 900℃~1050℃ and an annealing time of 60min~100min, which can accurately form gradient junction depth and sensitivity partitioning. The high-range varistor region 42 is located near the chip center, resulting in the strongest voltage resistance. It employs high doping concentration and short-time low-temperature shallow annealing, resulting in a shallower junction depth and stronger structural voltage resistance, making it suitable for high-pressure operating conditions. The target range of the high-range varistor region 42 can reach 1MPa~5MPa. Therefore, the same chip can simultaneously cover both low-range and high-range pressure detection needs, making it suitable for pressure detection in multiple scenarios.

[0040] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solution of this utility model and not to limit it. Although this utility model has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solution of this utility model without departing from the spirit and scope of the technical solution of this utility model, and all such modifications and substitutions should be covered within the scope of the claims of this utility model.

Claims

1. A dual-range piezoresistive pressure sensor chip, characterized in that, include: The SOI substrate structure includes a supporting silicon wafer (1), a buried oxide insulating layer (2), and a top silicon wafer (3) arranged sequentially from bottom to top. A top thin oxide layer (4) is disposed on the surface of the top silicon (3); A low-range varistor region (41) is disposed within the top silicon (3). The low-range varistor region (41) includes a heavily doped P+ structure (5) and a lightly doped P-type varistor (6) electrically connected to the heavily doped P+ structure (5). The low-range varistor region (41) is located in a region away from the center of the chip in the chip plane direction. A high-range varistor region (42) is disposed within the top silicon (3). The high-range varistor region (42) includes a heavily doped P+ structure (7) and a lightly doped P-type varistor (8) electrically connected to the heavily doped P+ structure (7). The high-range varistor region (42) is located in the region near the center of the chip in the chip plane direction. A varistor region electrical connection metal layer (9) is disposed on the surface of the top thin oxide layer (4). The varistor region electrical connection metal layer (9) includes a low-range varistor region electrical connection metal layer (91) electrically connected to the low-range varistor region heavily doped P+ structure (5) and a high-range varistor region electrical connection metal layer (92) electrically connected to the high-range varistor region heavily doped P+ structure (7). A dielectric film (11) is disposed on the surface of the top thin oxide layer (4) and covers the pressure-sensitive area electrical connection metal layer (9). An electrical isolation layer (12) is disposed on the surface of the dielectric film (11); An external connection PAD structure (13) is disposed on the surface of the electrical isolation layer (12). The external connection PAD structure (13) includes a low-range PAD structure (131) electrically connected to the low-range varistor region electrical connection metal layer (91) and a high-range PAD structure (132) electrically connected to the high-range varistor region electrical connection metal layer (92).

2. The dual-range piezoresistive pressure sensor chip according to claim 1, characterized in that, Four high-range pressure-sensitive areas (42) are provided, and the four high-range pressure-sensitive areas (42) are centrally symmetrically distributed around the center of the chip. Four low-range pressure-sensitive areas (41) are provided, and the four low-range pressure-sensitive areas (41) are centrally symmetrically distributed around the center of the chip, and are respectively located outside the four high-range pressure-sensitive areas (42).

3. The dual-range piezoresistive pressure sensor chip according to claim 2, characterized in that, The two high-range varistor regions (42) located on the upper and lower sides of the chip are arranged opposite each other along the Y-axis of the chip plane, and the two high-range varistor regions (42) located on the left and right sides of the chip are arranged opposite each other along the X-axis of the chip plane; the two low-range varistor regions (41) located on the upper and lower sides of the chip are arranged opposite each other along the Y-axis of the chip plane, and the two low-range varistor regions (41) located on the left and right sides of the chip are arranged opposite each other along the X-axis of the chip plane.

4. The dual-range piezoresistive pressure sensor chip according to claim 2, characterized in that, It also includes a back release cavity (14), which is disposed on the back side of the supporting silicon wafer (1) and extends to the back side of the buried oxide insulating layer (2). The projection of the back release cavity (14) toward the low-range varistor (41) and the high-range varistor (42) respectively covers the corresponding low-range varistor (41) and the high-range varistor (42).

5. A dual-range piezoresistive pressure sensor chip according to claim 4, characterized in that, The back release cavity (14) includes a first release region (141) located in the central region of the chip, a second release region (142) extending from the first release region (141) to each of the high-range pressure-sensitive regions (42), and a third release region (143) extending from the first release region (141) to each of the low-range pressure-sensitive regions (41). The projection of each second release region (142) onto the corresponding high-range pressure-sensitive region (42) covers the corresponding high-range pressure-sensitive region (42), and the projection of each third release region (143) onto the corresponding low-range pressure-sensitive region (41) covers the corresponding low-range pressure-sensitive region (41).

6. A dual-range piezoresistive pressure sensor chip according to claim 4, characterized in that, The back side of the supporting silicon wafer (1) is provided with a bottom thin oxide layer (10), and the back release cavity (14) penetrates the bottom thin oxide layer (10) and extends to the back side of the buried oxide insulating layer (2).

7. A dual-range piezoresistive pressure sensor chip according to claim 1, characterized in that, The junction depth of the lightly doped P-type varistor (6) in the low-range varistor region is greater than that of the lightly doped P-type varistor (8) in the high-range varistor region.

8. A dual-range piezoresistive pressure sensor chip according to claim 1, characterized in that, The target detection range of the low-range pressure-sensitive region (41) is 0~500kPa, and the target detection range of the high-range pressure-sensitive region (42) is 1MPa~5MPa.

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