Electrostatic discharge clamp device

Abstract

The utility model provides a kind of electrostatic discharge clamping device.Electrostatic discharge clamping device device includes discharging device, electrostatic discharge (ESD) detection circuit and latch circuit.Discharging device is connected to first power grid and second power grid, and is configured to discharge ESD current during ESD event.ESD detection circuit is connected to discharging device, and is configured to detect ESD event, and start discharging device to discharge ESD current during ESD event.Latch circuit includes input and output, input is configured to receive precharge voltage during precharge phase to latch latch circuit, and track first power grid voltage on first power grid during ramp-up phase.Output is coupled to discharging device to prevent the start of discharging device during precharge phase and during ramp-up phase.

Description

Technical Field

[0001] This utility model relates to an electrostatic discharge clamping device. Background Technology

[0002] Electrostatic discharge (ESD) is the release of static electricity caused by a sudden and instantaneous flow of current between two objects with different charges. Some ESD events produce visible sparks associated with the current flow between the objects, while other, less noticeable forms of ESD may be neither visible nor audible, yet can still damage electronic devices. To prevent ESD damage to circuitry, electronic devices typically include ESD protection circuitry to discharge ESD signals. Utility Model Content

[0003] This utility model provides an electrostatic discharge clamping device.

[0004] This invention relates to an electrostatic discharge clamping device. The electrostatic discharge clamping device includes: a discharge device connected to a first power grid and a second power grid, configured to discharge an electrostatic discharge current during an electrostatic discharge event; an electrostatic discharge detection circuit connected to the discharge device, configured to detect the electrostatic discharge event and, during the electrostatic discharge event, activate the discharge device to discharge the electrostatic discharge current; and a latch circuit including an input and an output, wherein the input is configured to receive a pre-charge voltage during a pre-charge phase to latch the latch circuit, and to track a first power grid voltage on the first power grid during a ramp-up phase, and the output is coupled to the discharge device to prevent activation of the discharge device during the pre-charge phase and the ramp-up phase.

[0005] This utility model discloses an electrostatic discharge clamping device. The electrostatic discharge clamping device includes: a discharge device connected to a first power grid and a second power grid, configured to discharge an electrostatic discharge current during an electrostatic discharge event; an electrostatic discharge detection circuit connected to the discharge device and configured to detect the electrostatic discharge event and, during the electrostatic discharge event, activate the discharge device to discharge the electrostatic discharge current; and a latch circuit including an input and an output, the input being configured to receive a pre-charge voltage during a pre-charge phase to latch the latch circuit, and during a ramp-up phase to track a first power grid voltage at the output of the first power grid, the output being coupled to the discharge device to discharge the electrostatic discharge current during the pre-charge phase. During the period of the segment and the period of the ramp-up phase, the activation of the discharge device is prevented, wherein the latch circuit includes: a first PMOS transistor having a first gate connected to the first power grid and a first drain / source path connected to the input of the latch circuit; a second PMOS transistor having a second gate and a second drain / source path connected to the first drain / source path and the output of the latch circuit; and a latch inverter having a latch inverter input and a latch inverter output, the latch inverter input being connected to the output of the latch circuit, and the latch inverter output being connected to the second gate of the second PMOS transistor. Attached Figure Description

[0006] Figure 1 This is a schematic diagram illustrating an ESD protection device according to some embodiments.

[0007] Figure 2 This is a schematic diagram illustrating another ESD protection device according to some embodiments.

[0008] Figure 3 This is a schematic illustration of the pre-charge phase according to some embodiments. Figure 2 A diagram illustrating the operation of an ESD protection device.

[0009] Figure 4 This is a schematic illustration of the period during the ramp ascent phase, according to some embodiments. Figure 2 A diagram illustrating the operation of an ESD protection device.

[0010] Figure 5 It is illustrated according to some embodiments. Figure 2 The timing diagram of the ESD protection device during the pre-charge phase and the VDD ramp-up phase, showing the shutdown voltage VSD, output signal OUT, and power supply voltage VDD.

[0011] Figure 6 This is a schematic illustration of the period during an ESD event, based on some embodiments. Figure 2 A diagram illustrating the operation of an ESD protection device.

[0012] Figure 7 This is a schematic diagram illustrating an ESD protection device including a PMOS discharge device and various ESD detection circuits according to some embodiments.

[0013] Figure 8 This is a schematic diagram of an ESD protection device with an overdrive circuit according to some embodiments, the overdrive circuit including two power supply voltages VDD1, VDD2 and a reference voltage VSS.

[0014] Figure 9 This is a flowchart illustrating, according to some embodiments, a method of operating an ESD protection device during the pre-charge phase and the ramp-up phase of an ESD event.

[0015] Figure 10 This is a diagram illustrating, schematically, a method of operating an ESD protection device (also known as an ESD clamping device) according to some embodiments.

[0016] Figure 11 This is a block diagram illustrating, according to some embodiments, an example of a computer system configured to provide electronic devices, semiconductor elements, and methods disclosed herein.

[0017] Figure 12 This is a block diagram of a semiconductor device manufacturing system and a related semiconductor device manufacturing process according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. The specific examples of components and arrangements described below are for the purpose of simplifying this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "below," "lower part," "above," and "upper part" to describe the relationship between one element or feature and another element, as shown in the figure. In addition to the orientations shown in the figure, spatially related terms are also intended to cover different orientations of the device or operation in use. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein can be interpreted accordingly.

[0020] ESD protection circuits discharge ESD during an ESD event to protect other circuitry in an electronic device. Sometimes, clamping circuits are used in ESD protection circuits. Clamping circuits may be called ESD clamping circuits, ESD power rail clamping circuits, and / or pclamp circuits. During an ESD event, clamping circuits bypass positive or negative ESD currents through a low-resistance path, thereby preventing circuit failure. At least some clamping circuits include ESD detection circuitry for discharging ESD and a discharge device. Clamping circuits present high impedance during standby mode and low impedance during an ESD event. In some embodiments, the discharge device is a bigFET (Big Transistor). In some embodiments, the discharge device is an N-channel metal-oxide-semiconductor (NMOS) big transistor.

[0021] This disclosure provides an apparatus including a discharge device, an ESD detection circuit, and a latch circuit. The discharge device is connected to a first grid (e.g., a power voltage grid VDD) and a second grid (e.g., a reference voltage grid VSS) and is configured to discharge ESD current during an ESD event. The ESD detection circuit is connected to the discharge device and configured to detect an ESD event and activate the discharge device during the ESD event to discharge the ESD current. The latch circuit includes an input configured to receive a pre-charge voltage (e.g., a shutdown voltage VSD) during a pre-charge phase to latch the latch circuit, and during a ramp-up phase, to track the voltage on the first grid at the output of the latch circuit. The output is coupled to the discharge device to prevent activation of the discharge device during the pre-charge stage and the ramp-up stage, thereby providing low inrush current during the pre-charge stage and the ramp-up stage.

[0022] The method of operating the ESD clamping device includes receiving a pre-charge voltage at the input of the latch circuit during the pre-charge phase to latch the latch circuit, tracking a first grid voltage, such as the power supply voltage VDD, at the output of the latch circuit during the pre-charge phase, and preventing the discharge device from starting during the pre-charge phase and the ramp-up phase.

[0023] The advantages of the clamping device and the method of operating the clamping device include preventing the discharge device from starting during the pre-charge phase to achieve low inrush current, tracking the output of the latch circuit to the power supply voltage VDD during the ramp-up phase to prevent the discharge device from starting during the ramp-up phase, thereby achieving low inrush current, and disabling the latch circuit and starting the discharge device through the ESD detection circuit during an ESD event, thereby discharging the ESD current through the discharge device.

[0024] Figure 1 This is a schematic diagram illustrating an ESD protection device 20 according to some embodiments. The ESD protection device 20 includes a discharge device 22, an ESD detection circuit 24, and a latch circuit 26. The ESD protection device 20 may be a semiconductor element, an integrated circuit device, an electronic component device, an ESD power rail clamping device, an ESD clamping device, and / or other devices. In some embodiments, at least one of the discharge device 22, the ESD detection circuit 24, and the latch circuit 26 is connected to a first power grid 28, such as the power supply voltage grid VDD. In some embodiments, at least one of the discharge device 22, the ESD detection circuit 24, and the latch circuit 26 is connected to a second power grid 30, such as a reference voltage grid VSS. In some embodiments, each of the discharge device 22, the ESD detection circuit 24, and the latch circuit 26 is connected to the first power grid 28, such as the power supply voltage grid VDD. In some embodiments, each of the discharge device 22, the ESD detection circuit 24, and the latch circuit 26 is connected to the second power grid 30, such as the reference voltage grid VSS. In some embodiments, the reference voltage grid VSS is grounded.

[0025] Discharge device 22 is configured to discharge ESD current during an ESD event. Discharge device 22 is connected to ESD detection circuitry 24 and to a first grid 28 (e.g., power supply voltage grid VDD) and a second grid 30 (e.g., reference voltage grid VSS). In some embodiments, discharge device 22 includes a large transistor. In some embodiments, discharge device 22 includes an NMOS large transistor.

[0026] ESD detection circuit 24 is connected to discharge device 22 and configured to detect ESD events and, during an ESD event, activate discharge device 22 to discharge the ESD current. In some embodiments, ESD detection circuit 24 includes a resistor-capacitor (RC) network and an inverter with an inverter input and an inverter output. The RC network is connected to the inverter input, and discharge device 22 is connected to the inverter output.

[0027] Latch circuit 26 includes input 32 configured to receive a pre-charge voltage (e.g., a shutdown voltage VSD) during the pre-charge phase to latch latch circuit 26 and to track the voltage on the first grid 28 at output 34 of latch circuit 26 during the pre-charge phase. Output 34 provides an output signal OUT and is coupled to discharge device 22 to prevent activation of discharge device 22 during the pre-charge phase and the ramp-up phase. This provides low inrush current during the pre-charge phase and the ramp-up phase. In some embodiments, output 34 of latch circuit 26 is connected to ESD detection circuit 24. In some embodiments, output 34 of latch circuit 26 is directly connected to discharge device 22.

[0028] Operationally, during the pre-charge phase, latch circuit 26 receives a pre-charge shutdown voltage VSD at its input 32 to latch its output 34 at a high voltage. During the pre-charge phase, the high voltage bias at output 34 biases off discharge device 22 and provides low surge current. During the ramp-up phase, output 34 of latch circuit 26 tracks the voltage on the first grid 28, thereby preventing the discharge device 22 from activating and providing low inrush current during the ramp-up phase. During an ESD event, ESD detection circuit 24 detects the ESD event and disables latch circuit 26. Furthermore, during an ESD event, ESD detection circuit 24 biases on discharge device 22 to discharge the ESD current.

[0029] Figure 2 This is a schematic diagram illustrating another ESD protection device 40 according to some embodiments. The ESD protection device 40 may be a semiconductor element, integrated circuit device, electronic component device, ESD power rail clamping device, ESD clamping device, and / or other device. The ESD protection device 40 includes a discharge device 42, an ESD detection circuit 44, and a latch circuit 46. In some embodiments, the ESD protection device 40 is similar to... Figure 1 Device 20. In some embodiments, discharge device 42 is similar to Figure 1The discharge device 22 is included. In some embodiments, the ESD detection circuit 44 is similar to... Figure 1 The ESD detection circuit 24 is included. In some embodiments, the latch circuit 46 is similar. Figure 1 The latch circuit 26 in the middle.

[0030] Discharge device 42 is configured to discharge ESD current during an ESD event. Discharge device 42 is connected to a first power grid 48 providing a supply voltage VDD and to a second power grid 50 providing a reference voltage VSS, such as ground. Discharge device 42 includes an NMOS large transistor 52 having a gate 54 connected to an ESD detection circuit 44 and a drain / source path, wherein one end of the drain / source path is connected to the first power grid 48 and the other end is connected to the second power grid 50. The drain / source path can refer to a current path from source to drain or from drain to source via the transistor, individually or jointly, depending on the context. Furthermore, the drain / source terminals can refer individually or jointly to the source or drain, depending on the context.

[0031] ESD detection circuit 44 is connected to discharge device 42 and configured to detect ESD events and, during an ESD event, activate discharge device 42 to discharge the ESD current. ESD detection circuit 44 includes an RC network 56 and an inverter 58. RC network 56 includes a resistor 60 and a capacitor 62. Inverter 58 includes an input 64 and an output 66. One end of resistor 60 is connected to a first power grid 48, and the other end of resistor 60 is connected to one end of capacitor 62 and the input 64 of inverter 58. The other end of capacitor 62 is connected to a second power grid 50.

[0032] Inverter 58 includes a first inverter PMOS transistor 68 and a first inverter NMOS transistor 70. One end of the drain / source path of the first inverter PMOS transistor 68 is connected to a first power grid 48, and the other end of the drain / source path of the first inverter PMOS transistor 68 is connected to the drain / source path of the first inverter NMOS transistor 70 and one end of the output 66 of inverter 58. The other end of the drain / source path of the first inverter NMOS transistor 70 is connected to a second power grid 50. The gate of the first inverter PMOS transistor 68 is connected to the gate of the first inverter NMOS transistor 70 at the input 64 of inverter 58. The output 66 of inverter 58 is connected to the gate 54 of NMOS transistor 52.

[0033] Latch circuit 46 includes latch input 72, which is configured to receive a precharge turn-off voltage VSD during the precharge phase to latch latch circuit 46. Furthermore, during the ramp-up phase, latch circuit 46 tracks the voltage on the first grid 48 at latch output 74. Latch output 74 provides an output signal OUT to RC network 56 and input 64 of inverter 58 to prevent the NMOS large transistor 52 from starting up during both the precharge and ramp-up phases. This provides low inrush current during both the precharge and ramp-up phases.

[0034] The latch circuit 46 includes a first PMOS transistor 76, which has one end connected to a first drain / source path of the latch circuit 72 and the other end connected to one end of a first drain / source path of a second drain / source path of a second PMOS transistor 78. The other end of the second drain / source path of the second PMOS transistor 78 is connected to the latch output 74. The first gate of the first PMOS transistor 76 is connected to a first power grid 48.

[0035] The latch circuit 46 includes a latch inverter 80 having a latch inverter input 82 and a latch inverter output 84. The latch output 74 of the latch circuit 46 is connected to the latch inverter input 82, and the gate of the second PMOS transistor 78 is connected to the latch inverter output 84. The latch inverter 80 includes a third PMOS transistor 86 and a first NMOS transistor 88. One end of the third drain / source path of the third PMOS transistor 86 is connected to the first power grid 48, and the other end of the third drain / source path of the third PMOS transistor 86 is connected to the first NMOS transistor 88 and one end of the fourth drain / source path of the latch inverter output 84. The other end of the fourth drain / source path of the first NMOS transistor 88 is connected to the second power grid 50. The gate of the third PMOS transistor 86 is connected to the gate of the first NMOS transistor 88 and the gate of the latch inverter input 82. One end of the fourth drain / source path of the fourth PMOS transistor 90 is connected to the first drain / source path and the second drain / source path, and the other end is connected to the first power grid 48. The gate of the fourth PMOS transistor 90 is connected to the output of the latch inverter 84.

[0036] Figures 3 to 6 It is illustrated schematically according to some embodiments. Figure 2 The operation and diagram of ESD protection device 40. Figure 3 as well as Figure 4This is a schematic diagram illustrating the operation of individual ESD protection devices 40 during the pre-charging phase and during the ramp-up phase, according to some embodiments. Figure 5 It is a schematic diagram illustrating the voltage and timing during the pre-charge phase and the ramp-up phase according to some embodiments. Figure 6 This is a schematic diagram illustrating the operation of an ESD protection device 40 during an ESD event, according to some embodiments.

[0037] Figure 3 This is a schematic illustration of the pre-charge phase according to some embodiments. Figure 2 The diagram illustrates the operation of the ESD protection device 40. Initially, the first power grid 48 has a supply voltage VDD of 0 volts (V), and the gate of the first PMOS transistor 76 is at 0V. Additionally, the latch inverter output 84 is at 0V, the gate of the second PMOS transistor 78 is at 0V, and the gate of the fourth PMOS transistor 90 is at 0V.

[0038] Next, the turn-off voltage VSD ramps up from 0V to 0.5V. Each of the first PMOS transistor 76, the second PMOS transistor 78, and the fourth PMOS transistor 90 is biased to turn on, causing the output signal OUT provided by the latch output 74 to ramp up from 0V to 0.5V, and the power supply voltage VDD on the first grid 48 to ramp up from 0V to 0.5V.

[0039] When the output signal OUT is at 0.5V, the third PMOS transistor 86 is offset off, and the first NMOS transistor 88 is offset on, so as to keep the latch inverter output 84 at 0V. In addition, the power supply voltage VDD on the first grid 48 ramps up from 0V to 0.5V to bias off the first PMOS transistor 76, and the output signal OUT is latched at 0.5V.

[0040] When the output signal OUT is at 0.5V, the first inverter PMOS transistor 68 is biased off, and the first inverter NMOS transistor 70 is biased on to provide 0V at the gate 54 of the NMOS large transistor 52, and the NMOS large transistor 52 is biased off. This prevents the NMOS large transistor 52 from starting up during the precharge phase and achieves low inrush current.

[0041] Figure 4 This is a schematic illustration of the period during the ramp ascent phase, according to some embodiments. Figure 2The diagram illustrates the operation of the ESD protection device 40. Initially, the power supply voltage VDD of the first mains 48 is 0.5V, and the gate of the first PMOS transistor 76 is at 0.5V. Additionally, the latch inverter output 84 is at 0V, the gate of the second PMOS transistor 78 is at 0V, and the gate of the fourth PMOS transistor 90 is at 0V. Furthermore, the turn-off voltage VSD is 0.5V, and the first PMOS transistor 76 is biased off.

[0042] Next, the power supply voltage VDD on the first grid 48 ramps up from 0.5V to 0.75V (or higher). The second PMOS transistor 78 and the fourth PMOS transistor 90 are both biased on, causing the output signal OUT provided by the latch output 74 to ramp up from 0.5V to 0.75V. When the output signal OUT is at 0.75V, the third PMOS transistor 86 is offset off, and the first NMOS transistor 88 is offset on, to hold the latch inverter output 84 at 0V, and the latched output signal OUT ramps up to 0.75V.

[0043] When the output signal OUT is at 0.75V, the first inverter PMOS transistor 68 is biased off, and the first inverter NMOS transistor 70 is biased on to provide 0V at the gate 54 of the NMOS large transistor 52, and bias-off the NMOS large transistor 52. This prevents the NMOS large transistor 52 from starting up during the ramp-up phase and achieves low surge current.

[0044] Figure 5 It is illustrated according to some embodiments. Figure 2 The timing diagram shows the shutdown voltage VSD, output signal OUT, and power supply voltage VDD of the ESD protection device during the pre-charge phase and the VDD ramp-up phase. Time is plotted along the x-axis 110, and voltage is plotted along the y-axis 112.

[0045] During the VSD precharge phase 106, the shutdown voltage VSD 100 ramps up from 0V to 0.5V, which in turn ramps up the output signal OUT 102 and the power supply voltage VDD 104 from 0V to 0.5V. This prevents the NMOS large transistor 52 from starting up during the VSD precharge phase 106 and achieves low inrush current.

[0046] During the VDD ramp-up phase 108, the supply voltage VDD104 ramps up from 0.5V to 0.75V, thus ramping up the output signal OUT102 from 0.5V to 0.75V. This prevents the NMOS large transistor 52 from starting up during the VDD ramp-up phase 108 and achieves low inrush current.

[0047] Figure 6 This is a schematic illustration of the period during an ESD event, based on some embodiments. Figure 2 The diagram illustrates the operation of the ESD protection device. Initially, the power supply voltage VDD of the first mains 48 is 0.75V, the output signal OUT is at 0.75V, and the gate of the first PMOS transistor 76 is at 0.75V. When the output signal OUT is at 0.75V, the third PMOS transistor 86 is biased off, the first NMOS transistor 88 is biased on to hold the latch inverter output 84 at 0V, the gate of the second PMOS transistor 78 is held at 0V, and the gate of the fourth PMOS transistor 90 is held at 0V. The turn-off voltage VSD is lower than the power supply voltage VDD, at 0.75V, causing the first PMOS transistor 76 to be biased off. Additionally, when the output signal OUT is at 0.75V, the first inverter PMOS transistor 68 is biased off, and the first inverter NMOS transistor 70 is biased on to provide 0V at the gate 54 of the NMOS large transistor 52 and bias off the NMOS large transistor 52.

[0048] During an ESD event, the high voltage of the ESD event is located on the first mains 48, while the output signal OUT is at a low voltage. The third PMOS transistor 86 is biased to turn on, and the first NMOS transistor 88 is biased to turn off, providing a high voltage at the latch inverter output 84, the gate of the second PMOS transistor, and the gate of the fourth PMOS transistor 90. This biases off the second PMOS transistor 78 and the fourth PMOS transistor 90. Additionally, the first inverter PMOS transistor 68 is biased to turn on, and the first inverter NMOS transistor 70 is biased to turn off, providing a high voltage at the gate 54 of the NMOS large transistor 52. This biases on the NMOS large transistor 52 to discharge the ESD current from the ESD event via the bias of the large transistor 52.

[0049] Figure 7 This is a schematic diagram illustrating an ESD protection device 120 including a PMOS discharge device 122 and various ESD detection circuits 124 according to some embodiments. Device 120 may be a semiconductor element, integrated circuit device, electronic component device, ESD power rail clamping device, ESD clamping device, and / or other device. Device 120 includes a discharge device 122, ESD detection circuit 124, and latch circuit 126 (similar to...). Figure 1 (Latch circuit 46 in the middle). In some embodiments, device 120 is similar to Figure 1 Device 20. In some embodiments, discharge device 122 is similar to Figure 1The discharge device 22 is included. In some embodiments, the ESD detection circuit 124 is similar to... Figure 1 The ESD detection circuit 24 is included. In some embodiments, the latch circuit 126 is similar. Figure 1 The latch circuit 26 in the middle.

[0050] Discharge device 122 is configured to discharge ESD current during an ESD event. Discharge device 122 is connected to a first power grid 128 providing a supply voltage VDD and to a second power grid 130 providing a reference voltage VSS, such as ground. Discharge device 122 includes a PMOS large transistor 132 having a gate 134 connected to an ESD detection circuit 124 and a drain / source path, one end of which is connected to the first power grid 128 and the other end of which is connected to the second power grid 130.

[0051] ESD detection circuit 124 is connected to discharge device 122 and configured to detect ESD events and, during an ESD event, activate discharge device 122 to discharge the ESD current. ESD detection circuit 124 includes an RC network 136 and an inverter 138. RC network 136 includes a resistor 140 and a capacitor 142. Inverter 138 includes an input 144 and an output 146. One end of resistor 140 is connected to a second power grid 130, and the other end of resistor 140 is connected to one end of capacitor 142 and the input 144 of inverter 138. The other end of capacitor 142 is connected to a first power grid 128.

[0052] Inverter 138 includes a first inverter PMOS transistor 148 and a first inverter NMOS transistor 150. One end of the drain / source path of the first inverter PMOS transistor 148 is connected to a first power grid 128, and the other end of the drain / source path of the first inverter PMOS transistor 148 is connected to the drain / source path of the first inverter NMOS transistor 150 and one end of the output 146 of inverter 138. The other end of the drain / source path of the first inverter NMOS transistor 150 is connected to a second power grid 130. The gate of the first inverter PMOS transistor 148 is connected to the gate of the first inverter NMOS transistor 150 at the input 144 of inverter 138. The output 146 of inverter 138 is connected to the gate 134 of PMOS transistor 132 and to the latch output 154 of latch circuit 126.

[0053] The latch circuit 126 includes a latch input 152 configured to receive a precharge turn-off voltage VSD during the precharge phase to latch the latch circuit 126. Furthermore, during the ramp-up phase, the latch circuit 126 tracks the voltage on the first grid 128 at the latch output 154. The latch circuit 126 operates in a similar manner. Figures 2 to 6 46. ​​Latch circuit.

[0054] Latch output 154 provides an output signal OUT to the gate 134 of PMOS large transistor 132 to prevent the PMOS large transistor 132 from starting up during the precharge phase and the ramp-up phase. This provides low inrush current during the precharge phase and the ramp-up phase.

[0055] The latch circuit 126 includes a first PMOS transistor 156, which has one end connected to a first drain / source path connected to a latch input 152 and the other end connected to a second drain / source path connected to a second PMOS transistor 158. The other end of the second drain / source path of the second PMOS transistor 158 is connected to a latch output 154. The first gate of the first PMOS transistor 156 is connected to a first electrical grid 128.

[0056] The latch circuit 126 includes a latch inverter 160 having a latch inverter input 162 and a latch inverter output 164. The latch output 154 is connected to the latch inverter input 162, and the gate of a second PMOS transistor 158 is connected to the latch inverter output 164. The latch inverter 160 includes a third PMOS transistor 166 and a first NMOS transistor 168. One end of the third drain / source path of the third PMOS transistor 166 is connected to a first power grid 128, and the other end of the third drain / source path of the third PMOS transistor 166 is connected to the first NMOS transistor 168 and one end of the fourth drain / source path of the latch inverter output 164. The other end of the fourth drain / source path of the first NMOS transistor 168 is connected to a second power grid 130. The gate of the third PMOS transistor 166 is connected to the gate of the first NMOS transistor 168 and the gate of the latch inverter input 162. One end of the fourth drain / source path of the fourth PMOS transistor 170 is connected to the first drain / source path and the second drain / source path, and the other end is connected to the first power grid 128. The gate of the fourth PMOS transistor 170 is connected to the output of the latch inverter 164.

[0057] During the operation of the ESD protection device 120, in the pre-charge phase, initially, the first power grid 128 has a power supply voltage VDD of 0V, and the gate of the first PMOS transistor 156 is at 0V. Additionally, the latch inverter output 164 is at 0V, the gate of the second PMOS transistor 158 is at 0V, and the gate of the fourth PMOS transistor 170 is at 0V.

[0058] Next, the precharge shutdown voltage VSD ramps up from 0V to 0.5V. Each of the first PMOS transistor 156, the second PMOS transistor 158, and the fourth PMOS transistor 170 is biased to turn on, causing the output signal OUT provided by the latch output 154 to ramp up from 0V to 0.5V, and the power supply voltage VDD on the first grid 128 to ramp up from 0V to 0.5V.

[0059] When the output signal OUT is at 0.5V, the third PMOS transistor 166 is biased off, and the first NMOS transistor 168 is biased on, to maintain the latch inverter output 164 at 0V. Furthermore, the power supply voltage VDD on the first mains 128 ramps up from 0V to 0.5V to bias off the first PMOS transistor 156. Additionally, when the output signal OUT is at 0.5V, the PMOS large transistor 132 is biased off, thus preventing the PMOS large transistor 132 from starting up during the pre-charge phase and achieving low inrush current.

[0060] During the ramp-up phase, initially, the first grid 128 has a supply voltage VDD of 0.5V, and the gate of the first PMOS transistor 156 is at 0.5V. Additionally, the latch inverter output 164 is at 0V, the gate of the second PMOS transistor 158 is at 0V, and the gate of the fourth PMOS transistor 170 is at 0V. Furthermore, the precharge turn-off voltage VSD is at 0.5V, and the first PMOS transistor 156 is biased off.

[0061] Next, the power supply voltage VDD on the first grid 128 ramps up from 0.5V to 0.75V (or higher). The second PMOS transistor 158 and the fourth PMOS transistor 170 are both biased to turn on, causing the output signal OUT provided by the latch output 154 to ramp up from 0.5V to 0.75V. When the output signal OUT is at 0.75V, the third PMOS transistor 166 is biased to turn off, and the first NMOS transistor 168 is biased to turn on, holding the latch inverter output 164 at 0V, and the latched output signal OUT ramps up to 0.75V. When the output signal OUT is at 0.75V, the PMOS large transistor 132 is biased to turn off, thus preventing the PMOS large transistor 132 from starting up during the ramp-up phase and achieving low inrush current.

[0062] During an ESD event, initially, the first power grid 128 has a supply voltage VDD of 0.75V, the output signal OUT is at 0.75V, and the gate of the first PMOS transistor 156 is at 0.75V. When the output signal OUT is 0.75V, the third PMOS transistor 166 is biased off, the first NMOS transistor 168 is biased on to hold the latch inverter output 164 at 0V, the gate of the second PMOS transistor 158 is held at 0V, and the gate of the fourth PMOS transistor 170 is held at 0V. The turn-off voltage VSD is lower than the supply voltage VDD, at 0.75V, causing the first PMOS transistor 156 to be biased off. Additionally, when the output signal OUT is at 0.75V, the PMOS transistor 132 is biased off.

[0063] During an ESD event, the high voltage of the ESD event is located at input 144 of inverter 138, causing the first inverter PMOS transistor 148 to be biased off and the first inverter NMOS transistor 150 to be biased on, thus providing a low voltage at output 146 of inverter 138 and gate 134 of PMOS transistor 132. This bias turns on PMOS transistor 132 to discharge the ESD current from the ESD event. Furthermore, the low voltage at output 146 biases on the third PMOS transistor 166 and biases off the first NMOS transistor 168, providing a high voltage at latch inverter output 164, gate of the second PMOS transistor 158, and gate of the fourth PMOS transistor 170. This bias turns off the second PMOS transistor 158 and the fourth PMOS transistor 170.

[0064] Figure 8This is a schematic diagram of an ESD protection device 200 with an overdrive circuit according to some embodiments, the overdrive circuit including two power supply voltages VDD1, VDD2 and a reference voltage VSS. The ESD protection device 200 includes a first latch circuit 202, a first ESD detection circuit 204, a second latch circuit 206, a second ESD detection circuit 208, and a discharge device 210. Additionally, the ESD protection device 200 includes a first mains 212 providing the first power supply voltage VDD1, a second mains 214 providing the second power supply voltage VDD2, and a third mains 216 providing the reference voltage VSS. Each of the first latch circuit 202 and the first ESD detection circuit 204 is connected to the first mains 212 and the second mains 214, and each of the second latch circuit 206 and the second ESD detection circuit 208 is connected to the second mains 214 and the third mains 216. In some embodiments, the first power supply voltage VDD1 is 1.5V. In some embodiments, the second power supply voltage VDD2 is 0.75V. In some embodiments, the reference voltage VSS is ground.

[0065] The discharge device 210 is connected to a first power grid 212 and a third power grid 216. The discharge device 210 includes a first NMOS large transistor 218 and a second NMOS large transistor 220. One end of the first drain / source path of the first NMOS large transistor 218 is connected to the first power grid 212, and the other end of the first drain / source path is connected to the second drain / source path of the second NMOS large transistor 220. The other end of the second drain / source path is connected to the third power grid 216.

[0066] The first latch circuit 202 has a first input 222 that receives a first turn-off voltage VSD1 and is connected to a first ESD detection circuit 204, which is connected to the gate of a first NMOS large transistor 218. The second latch circuit 206 has a second input 224 that receives a second turn-off voltage VSD2 and is connected to a second ESD detection circuit 208, which is connected to the gate of a second NMOS large transistor 220. In some embodiments, one or more of the first latch circuit 202 and the second latch circuit 206 are similar. Figure 1 26. Latch circuit Figure 2 latch circuit 46 and / or Figure 7 The latch circuit 126. In some embodiments, one or more of the first ESD detection circuit 204 and the second ESD detection circuit 208 are similar. Figure 1 ESD detection circuit 24 Figure 2 ESD detection circuit 44 and / or Figure 7ESD detection circuit 124.

[0067] In operation, the first latch circuit 202 operates in a manner similar to Figure 1 26. Latch circuit Figure 2 latch circuit 46 and / or Figure 7 The latch circuit 126. The output of the first latch circuit 202 is latched to a high voltage, which biases and turns off the first NMOS large transistor 218 during the pre-charge phase and the ramp-up phase. Furthermore, the second latch circuit 206 operates similarly. Figure 1 26. Latch circuit Figure 2 latch circuit 46 and / or Figure 7 The latch circuit 126. The output of the second latch circuit 206 is latched at a high voltage, which biases off the second NMOS large transistor 220 during the pre-charge phase and the ramp-up phase.

[0068] During an ESD event, the operation of the first ESD detection circuit 204 is similar to Figure 1 ESD detection circuit 24 Figure 2 ESD detection circuit 44 and / or Figure 7 The ESD detection circuit 124 biases and turns on the first NMOS large transistor 218 to discharge the ESD current, and the operation of the second ESD detection circuit 208 is similar to that of the ESD detection circuit 24. Figure 1 ESD detection circuit 44 Figure 2 ESD detection circuit 44 and / or Figure 7 The ESD detection circuit 124 biases and turns on the second NMOS transistor 220 to discharge the ESD current. When the first NMOS transistor 218 and the second NMOS transistor 220 are biased and turned on, the ESD current discharges from the first grid 212 to the third grid 216.

[0069] Figure 9 This is a flowchart illustrating, schematically according to some embodiments, a method of operating an ESD protection device during the pre-charge phase and the ramp-up phase of an ESD event. In some embodiments, the ESD protection device 240 is similar to... Figure 1 The ESD protection device 20 is included. In some embodiments, the ESD protection device 240 is similar to... Figure 2 The ESD protection device 40 is included. In some embodiments, the ESD protection device 240 is similar to... Figure 7 ESD protection device 120.

[0070] In step 242, the precharge turn-off voltage VSD is latched to the latch circuit, and a high voltage is provided at the output of the latch circuit. This biases the large transistor discharge device to shut down and achieves low inrush current during the precharge phase.

[0071] In step 244, the output of the latch circuit tracks the ramp-up of the power supply voltage VDD. The large transistor discharge device is switched off by a higher voltage bias to achieve low inrush current during the ramp-up phase.

[0072] In step 246, the large transistor discharge device is offset off to achieve low inrush current during the pre-charge phase and the ramp-up phase.

[0073] In step 248, during an ESD event, the ESD detection circuit disables the latch circuit, and in step 250, the ESD detection circuit biases to enable the large transistor discharge device to discharge the ESD current.

[0074] Figure 10 This is a diagram schematically illustrating a method of operating an ESD protection device (also known as an ESD clamping device) according to some embodiments. In some embodiments, the ESD clamping device is similar to Figure 1 The ESD protection device 20 is included. In some embodiments, the ESD clamping device is similar to... Figure 2 The ESD protection device 40 is included. In some embodiments, the ESD clamping device is similar to... Figure 7 The ESD protection device 120 is included.

[0075] In step 260, the method includes: during the pre-charge phase, receiving a pre-charge voltage at an input to the latch circuit to latch the latch circuit. In some embodiments, the latch circuit is similar to... Figure 1 The latch circuit 26 is described above. In some embodiments, the latch circuit is similar to... Figure 2 The latch circuit 46 is described above. In some embodiments, the latch circuit is similar to... Figure 7 The latch circuit 126.

[0076] In some embodiments, during the pre-charge phase, a pre-charge voltage is received at the input of the latch circuit, and the latch circuit includes: receiving the pre-charge voltage at a first PMOS transistor, conducting the pre-charge voltage to a second PMOS transistor via the first PMOS transistor, and conducting the pre-charge voltage to the output of the latch circuit via the second PMOS transistor. In some embodiments, during the pre-charge phase, a pre-charge voltage is received at the input of the latch circuit, and the latch circuit includes: receiving the pre-charge voltage from the output of the latch circuit at the inverter input of an inverter, and latching the second PMOS transistor via the inverter output of the inverter.

[0077] In step 262, the method includes: tracking a first grid voltage of a first grid at the output of the latch circuit during the ramp-up phase. In some embodiments, the first grid provides a power supply voltage VDD. In some embodiments, tracking the first grid voltage at the output of the latch circuit during the ramp-up phase includes: receiving an inverter output at the gate of a third PMOS transistor connected to a first PMOS transistor, a second PMOS transistor, and the first grid, wherein the first grid voltage is conducted to the output of the latch circuit via the third PMOS transistor and the second PMOS transistor.

[0078] In step 264, the method includes preventing the discharge device from starting via the output of the latch circuit during the pre-charge phase and the ramp-up phase. Furthermore, in some embodiments, the method includes detecting an ESD event via an ESD detection circuit, disabling the latch circuit via the ESD detection circuit during the ESD event, and biasing the discharge device via the ESD detection circuit during the ESD event to discharge the ESD current.

[0079] Figure 11 This is a block diagram illustrating, schematically according to some embodiments, an example of a computer system 300 configured to provide electronic devices, semiconductor elements, and methods disclosed herein. Some or all of the design, layout, and fabrication of the semiconductor elements (also referred to as semiconductor circuits) can be performed via or assisted by the computer system 300. Similarly, some or all of the design, layout, and fabrication of the electronic devices can be performed by or assisted by the computer system 300. In some embodiments, the computer system 300 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor element is an IC.

[0080] In some embodiments, system 300 is a general-purpose computing device including processor 302 and a non-transitory computer-readable storage medium 304. Computer-readable storage medium 304 may be encoded using, for example, storing computer program code (e.g., executable instructions 306). Instructions 306, executed via processor 302, provide (at least partially) design tools for implementing some or all of the functionality of system 300, such as pre-placement simulation, post-placement simulation, routing, rerouting, and final placement fabrication. Furthermore, fabrication tools 308 are introduced to further place and physically implement the design and fabrication of semiconductor elements. In some embodiments, instructions 306, executed via processor 302, provide (at least partially) design tools for implementing some or all of the functionality of system 300. In some embodiments, system 300 includes a commercial router. In some embodiments, system 300 includes an automatic place and route (APR) system.

[0081] Processor 302 is electrically coupled to computer-readable storage medium 304 via bus 310 and to input / output (I / O) interface 312 via bus 310. Network interface 314 is electrically connected to processor 302 via bus 310. Network interface 314 is connected to network 316 so that processor 302 and computer-readable storage medium 304 can be connected to external components using network 316. Processor 302 is configured to execute computer program code or instructions 306 encoded in computer-readable storage medium 304 to cause system 300 to perform some or all of the functions of system 300, such as providing the semiconductor elements, methods, and other functions of system 300 disclosed herein. In some embodiments, processor 302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0082] In some embodiments, the computer-readable storage medium 304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, device, or apparatus. For example, the computer-readable storage medium 304 may include semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or magnetic disk. In some embodiments using optical discs, the computer-readable storage medium 304 may include an optical disc read-only memory (CD-ROM), an optical disc read / write memory (CD-R / W), and / or a digital video disc (DVD).

[0083] In some embodiments, computer-readable storage medium 304 stores computer program code or instructions 306 configured to cause system 300 to perform some or all of the functions of system 300. In some embodiments, computer-readable storage medium 304 further stores information to facilitate the execution of some or all of the functions of system 300. In some embodiments, computer-readable storage medium 304 stores a database 318 including one or more of a component library, a digital circuit unit library, and a database.

[0084] System 300 includes an I / O interface 312 coupled to external circuitry. In some embodiments, the I / O interface 312 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor direction keys for transmitting information and instructions to processor 302.

[0085] Network interface 314 is coupled to processor 302 and allows system 300 to communicate with network 316, and one or more other computer systems are also connected to network 316. Network interface 314 may include: a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In some embodiments, some or all of the functions of system 300 may be performed in two or more systems similar to system 300.

[0086] System 300 is configured to receive information via I / O interface 312. The information received via I / O interface 312 includes one or more of the following: instructions, data, design rules, components and cell libraries, and / or other parameters for processing by processor 302. The information is transferred to processor 302 via bus 310. Furthermore, system 300 is configured to receive information related to the user interface (UI) via I / O interface 312. This UI information may be stored as UI 320 in computer-readable storage medium 304.

[0087] In some embodiments, some or all of the functions of system 300 are implemented via a standalone software application executed by a processor. In some embodiments, some or all of the functions of system 300 are implemented in a software application as part of an additional software application. In some embodiments, some or all of the functions of system 300 are implemented as plug-ins to a software application. In some embodiments, at least one of the functions or system 300 is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the functions of system 300 are implemented as software applications used by system 300. In some embodiments, layout diagrams are generated using tools such as VIRTEOSO, available from CADENCE Design Systems, or other suitable layout generation tools.

[0088] In some embodiments, routing, layout, and other processing are implemented as program functions stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical discs, such as digital video discs or digital optical discs; magnetic disks such as hard disks; semiconductor memories such as ROM and RAM; and memory cards.

[0089] As described above, embodiments of system 300 include manufacturing tools 308 for implementing the manufacturing process of system 300. For example, based on the final layout, a photomask can be generated, which is used to manufacture semiconductor devices via manufacturing tools 308.

[0090] Combination Figure 12 Other aspects of the device's manufacturing process were revealed. Figure 12 This is a block diagram of a semiconductor device manufacturing system 322 and its associated semiconductor device manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 322 is used to manufacture at least one component of one or more semiconductor photomasks and / or a layer of a semiconductor device.

[0091] exist Figure 12In this semiconductor device manufacturing system 322, entities such as a design house 324, a mask house 326, and a semiconductor device manufacturing plant / fab 328 interact with each other during the design, development, and manufacturing cycles and / or services, such as the semiconductor devices described herein. The entities in system 322 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet, the Internet, etc. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 324, mask house 326, and semiconductor device manufacturing plant 328 are owned by a larger company. In some embodiments, two or more of the design house 324, mask house 326, and semiconductor device manufacturing plant 328 coexist in a shared facility and use shared resources.

[0092] Design company (or design team) 324 generates a semiconductor device design layout 330. The semiconductor device design layout 330 includes various geometric patterns or layouts of semiconductor devices specifically designed for semiconductor devices. The geometric patterns correspond to metal, oxide, or semiconductor layers that constitute the various components of the semiconductor structure to be manufactured. Different layers combine to form different semiconductor device features. For example, a portion of the semiconductor device design layout 330 includes various semiconductor device features to be formed in and disposed on a semiconductor substrate (e.g., a silicon chip) in various material layers, such as diagonal vias, active regions or regions, gate electrodes, source electrodes, drain electrodes, metal lines, partial vias, and pad openings. Design company 324 implements a design process to generate the semiconductor device design layout 330. The semiconductor device design layout 330 is presented in one or more data files containing information about geometric patterns. For example, the semiconductor device design layout 330 may be represented in GDSII or DFII file format. In some embodiments, the design flow includes one or more of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, and power distribution network (PDN) design. The power distribution network design includes power via design, power voltage trace design, reference voltage trace design, layout and routing path design, and physical layout design.

[0093] Photomask company 326 includes data preparation 332 and photomask fabrication 334. Photomask company 326 uses a semiconductor device design layout 330 to fabricate one or more photomasks 336 for use in fabricating layers of semiconductor devices or semiconductor structures. Photomask company 326 performs photomask data preparation 332, in which the semiconductor device design layout 330 is converted into a representative data file (RDF). Photomask data preparation 332 provides the RDF to photomask fabrication 334. Photomask fabrication 334 includes a photomask writer that converts the RDF into an image on a substrate, such as a photomask (reticle) 336 or a semiconductor wafer 338. The design layout 330 is manipulated by photomask data preparation 332 to conform to the characteristics of the photomask writer and / or the standards of the semiconductor device fabrication plant 328. Figure 12 In this embodiment, photomask data preparation 332 and photomask fabrication 334 are shown as separate elements. In some embodiments, photomask data preparation 332 and photomask fabrication 334 may be collectively referred to as photomask data preparation.

[0094] In some embodiments, the mask data preparation 332 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, and other process effects. OPC adjusts the semiconductor device design layout diagram 330. In some embodiments, the mask data preparation 332 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shifting masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0095] In some embodiments, the photomask data preparation 332 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the semiconductor device design layout 330, which has been processed in the OPC, to ensure sufficient margin to account for variability in the semiconductor manufacturing process. In some embodiments, the MRC modifies the semiconductor device design layout 330 to compensate for constraints during photomask fabrication 334, which may undo some modifications performed by the OPC to satisfy the photomask creation rules.

[0096] In some embodiments, mask data preparation 332 includes lithography process checking (LPC), which simulates the processes to be performed by the semiconductor device manufacturing plant 328. LPC simulates this process based on the semiconductor device design layout 330 to establish a simulated manufacturing apparatus. Processing parameters in the LPC simulation may include parameters associated with various processes in the semiconductor device manufacturing cycle, parameters associated with the tools used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, and combinations thereof. In some embodiments, after creating the simulated manufacturing apparatus via LPC, if the simulated apparatus shape is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the semiconductor device design layout 330.

[0097] For clarity, the above description of the photomask data preparation 332 has been simplified. In some embodiments, data preparation 332 includes additional features, such as logic operations (LOPs), to modify the semiconductor device design layout 330 according to manufacturing rules. Furthermore, the processes applied to the semiconductor device design layout 330 during data preparation 332 can be performed in various different sequences.

[0098] Following photomask data preparation 332 and during photomask fabrication 334, a photomask 336 or a set of photomasks 336 is fabricated based on a modified semiconductor device design layout 330. In some embodiments, photomask fabrication 334 includes performing one or more photolithographic exposures based on the semiconductor device design layout 330. In some embodiments, an electron beam or multiple electron beam apparatus forms a pattern on the photomask (photomask or photomask plate) 336 based on the modified semiconductor device design layout 330. The photomask 336 can be formed using a variety of techniques. In some embodiments, the photomask 336 is formed using a binary technique. In some embodiments, the photomask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the chip are blocked by the opaque areas and pass through the transparent areas. In one example, the binary mask version of photomask 336 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary photomask. In another example, photomask 336 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of photomask 336, the individual features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The photomask produced by photomask fabrication 334 can be used in a variety of processes. Referring to the figures, such a photomask is used, for example, in an ion implantation process to form various doped regions in a semiconductor wafer 338, in an etching process to form various etched regions in a semiconductor wafer 338, and / or in other suitable processes.

[0099] Semiconductor device manufacturing plant 328 includes wafer fabrication 340. Semiconductor device manufacturing plant 328 is a commercial operation for manufacturing semiconductor devices, comprising one or more manufacturing facilities for manufacturing various semiconductor device products. In some embodiments, semiconductor device manufacturing plant 328 is a semiconductor foundry. For example, there may be manufacturing facilities for manufacturing the front end of line (FEOL) of multiple semiconductor device products, while a second manufacturing facility may be used for manufacturing the interconnects and back end of line (BEOL) of the semiconductor device products, and a third manufacturing facility may provide other services for the foundry business.

[0100] Semiconductor device manufacturing plant 328 uses photomask 336 manufactured by photomask company 326 to manufacture the semiconductor structure or semiconductor device 342 disclosed herein. Therefore, semiconductor device manufacturing plant 328 uses semiconductor device design layout 330 at least indirectly to manufacture the semiconductor structure or semiconductor device 342 disclosed herein. Furthermore, semiconductor wafer 338 includes a silicon substrate or other suitable substrate on which material layers are formed, and semiconductor wafer 338 also includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent manufacturing steps). In some embodiments, semiconductor wafer 338 is manufactured by semiconductor device manufacturing plant 328 using photomask 336 to form the semiconductor structure or semiconductor device 342 disclosed herein. In some embodiments, semiconductor device manufacturing includes performing one or more photolithographic exposures at least indirectly based on semiconductor device design layout 330.

[0101] Therefore, embodiments of this disclosure provide an apparatus, a discharge device, an ESD detection circuit, and a latch circuit. The discharge device is connected to a first power grid (e.g., a power supply voltage grid VDD) and a second power grid (e.g., a reference voltage grid VSS) and is configured to discharge ESD current during an ESD event. The ESD detection circuit is connected to the discharge device and configured to detect an ESD event and, during the ESD event, activate the discharge device to discharge the ESD current. The latch circuit includes an input configured to receive a pre-charge voltage (e.g., a shutdown voltage VSD) during a pre-charge phase to latch the latch circuit and, during a ramp-up phase, to track the voltage rise on the first power grid at the output of the latch circuit. An output is coupled to the discharge device to prevent activation of the discharge device during both the pre-charge and ramp-up phases, wherein a low inrush current is provided during both the pre-charge and ramp-up phases.

[0102] Advantages of the ESD protection device and operating method include preventing the activation of the discharge device during the pre-charge phase to achieve low inrush current, tracking the output of the latch circuit to the power supply voltage VDD during the ramp-up phase to prevent the activation of the discharge device to achieve low inrush current, and disabling the latch circuit and activating the discharge device via the ESD detection circuit during an ESD event to discharge the ESD current.

[0103] According to some embodiments, the device includes a discharge device, an ESD detection circuit, and a latch circuit. The discharge device is connected to a first power grid and a second power grid and is configured to discharge ESD current during an ESD event. The ESD detection circuit is connected to the discharge device and configured to detect an ESD event and, during the ESD event, activate the discharge device to discharge the ESD current. The latch circuit includes an input and an output. The input is configured to receive a pre-charge voltage during a pre-charge phase to latch the latch circuit, and to track a first power grid voltage on the first power grid at the output during a ramp-up phase. The output is coupled to the discharge device to prevent activation of the discharge device during the pre-charge phase and the ramp-up phase.

[0104] In a related embodiment, the discharge device includes an NMOS large transistor.

[0105] In a related embodiment, the electrostatic discharge detection circuit includes a resistor-capacitor (RC) network and an inverter having an inverter input and an inverter output, the RC network being connected to the inverter input, and the discharge device being connected to the inverter output.

[0106] In a related embodiment, the output of the latch circuit is connected to the RC network and the inverter input.

[0107] In a related embodiment, the output of the latch circuit is connected to the discharge device.

[0108] In a related embodiment, the latch circuit includes a first PMOS transistor having a first drain / source path connected to the input of the latch circuit and a second drain / source path connected to a second PMOS transistor, the second drain / source path of the second PMOS transistor being connected to the output of the latch circuit.

[0109] In a related embodiment, the first gate of the first PMOS transistor is connected to the first power grid.

[0110] In a related embodiment, the electrostatic discharge clamping device further includes a latch inverter having a latch inverter input and a latch inverter output, wherein the output of the latch circuit is connected to the latch inverter input, and the second gate of the second PMOS transistor is connected to the latch inverter output.

[0111] In a related embodiment, the latch inverter includes a third PMOS transistor and a first NMOS transistor, the third PMOS transistor having a third drain / source path connected to the first power grid and a fourth drain / source path connected to the first NMOS transistor, the fourth drain / source path of the first NMOS transistor being connected to the second power grid.

[0112] In a related embodiment, the electrostatic discharge clamping device further includes a fourth PMOS transistor connected to the first drain / source path, the second drain / source path, and the first power grid, wherein the gate of the fourth PMOS transistor is connected to the output of the latch inverter.

[0113] According to other embodiments, the device includes a discharge device, an ESD detection circuit, and a latch circuit. The discharge device is connected to a first power grid and a second power grid and is configured to discharge ESD current during an ESD event. The ESD detection circuit is connected to the discharge device and configured to detect an ESD event and, during the ESD event, activate the discharge device to discharge the ESD current. The latch circuit includes an input and an output. The input is configured to receive a precharge voltage during a precharge phase to latch the latch circuit and, during a ramp-up phase, to track a first power grid voltage at the output. The output is coupled to the discharge device to prevent activation of the discharge device during the precharge phase and the ramp-up phase. The latch circuit includes a first PMOS transistor, a second PMOS transistor, and a latch inverter. The first PMOS transistor has a first gate connected to the first power grid and a first drain / source path connected to the input of the latch circuit. The second PMOS transistor has a second gate and a second drain / source path connected to the first drain / source path and the output of the latch circuit. The latch inverter has one latch inverter input and one latch inverter output. The latch inverter input is connected to the output of the latch circuit, and the latch inverter output is connected to the second gate of the second PMOS transistor.

[0114] In a related embodiment, the latch inverter includes a third PMOS transistor and a first NMOS transistor, the third PMOS transistor having a third drain / source path connected to the first power grid and a fourth drain / source path of the first NMOS transistor connected to the second power grid.

[0115] In a related embodiment, the electrostatic discharge clamping device further includes a fourth PMOS transistor connected to the first drain / source path, the second drain / source path, and the first power grid, wherein the gate of the fourth PMOS transistor is connected to the output of the latch inverter.

[0116] In a related embodiment, the electrostatic discharge detection circuit includes a resistor-capacitor (RC) network and an inverter having an inverter input and an inverter output. The RC network is connected to the inverter input, and the discharge device is connected to the inverter output. The output of the latch circuit is connected to the RC network and the inverter input.

[0117] In a related embodiment, the output of the latch circuit is connected to the discharge device.

[0118] According to some other disclosed aspects, a method of operating an ESD clamping device includes: during a precharge phase, receiving a precharge voltage at an input of a latch circuit to latch the latch circuit; and during a ramp-up phase, tracking a first grid voltage at an output of a first grid at an output of the latch circuit; and preventing the activation of the discharge device during both the precharge phase and the ramp-up phase.

[0119] In related embodiments, the method further includes: detecting an electrostatic discharge event via an electrostatic discharge detection circuit; disabling the latch circuit during the electrostatic discharge event via the electrostatic discharge detection circuit; and biasing the discharge device during the electrostatic discharge event via the electrostatic discharge detection circuit to discharge the electrostatic discharge current.

[0120] In a related embodiment, during the pre-charge phase, receiving the pre-charge voltage at the input of the latch circuit to latch the latch circuit includes: receiving the pre-charge voltage at a first PMOS transistor; conducting the pre-charge voltage to a second PMOS transistor via the first PMOS transistor; and conducting the pre-charge voltage to the output of the latch circuit via the second PMOS transistor.

[0121] In a related embodiment, during the pre-charge phase, receiving the pre-charge voltage at the input of the latch circuit to latch the latch circuit includes: receiving the pre-charge voltage from the output of the latch circuit at the inverter input of the inverter; and latching the second PMOS transistor via the inverter output of the inverter.

[0122] In a related embodiment, during the ramp-up phase, tracking the first grid voltage of the first grid at the output of the latch circuit includes receiving the inverter output at the gate of a third PMOS transistor connected to the first PMOS transistor, the second PMOS transistor, and the first grid, wherein the first grid voltage is conducted to the output of the latch circuit via the third PMOS transistor and the second PMOS transistor.

[0123] This disclosure outlines various embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An electrostatic discharge clamping device, characterized in that, include: A discharge device, connected to a first power grid and a second power grid, is configured to discharge electrostatic discharge current during an electrostatic discharge event; An electrostatic discharge detection circuit is connected to the discharge device and configured to detect the electrostatic discharge event, and during the electrostatic discharge event, activate the discharge device to discharge the electrostatic discharge current. as well as A latch circuit includes an input and an output, wherein the input is configured to receive a pre-charge voltage during a pre-charge phase to latch the latch circuit and to track a first grid voltage on the first grid during a ramp-up phase, and the output is coupled to the discharge device to prevent the discharge device from starting during the pre-charge phase and the ramp-up phase.

2. The electrostatic discharge clamping device according to claim 1, characterized in that, The discharge device mentioned above includes an NMOS large transistor.

3. The electrostatic discharge clamping device according to claim 1, characterized in that, The electrostatic discharge detection circuit includes a resistor-capacitor (RC) network and an inverter, the inverter having an inverter input and an inverter output, the resistor-capacitor network being connected to the inverter input, and the discharge device being connected to the inverter output.

4. The electrostatic discharge clamping device according to claim 1, characterized in that, The output of the latch circuit is connected to the discharge device.

5. The electrostatic discharge clamping device according to claim 1, characterized in that, The latch circuit includes a first PMOS transistor having a first drain / source path connected to the input of the latch circuit and a second drain / source path connected to a second PMOS transistor, the second drain / source path of the second PMOS transistor being connected to the output of the latch circuit.

6. The electrostatic discharge clamping device according to claim 5, characterized in that, The first gate of the first PMOS transistor is connected to the first power grid.

7. The electrostatic discharge clamping device according to claim 5, characterized in that, It further includes a latch inverter having a latch inverter input and a latch inverter output, wherein the output of the latch circuit is connected to the latch inverter input, and the second gate of the second PMOS transistor is connected to the latch inverter output.

8. The electrostatic discharge clamping device according to claim 7, characterized in that, The latch inverter includes a third PMOS transistor and a first NMOS transistor. The third PMOS transistor has a third drain / source path connected to the first power grid and a fourth drain / source path connected to the first NMOS transistor. The fourth drain / source path of the first NMOS transistor is connected to the second power grid.

9. The electrostatic discharge clamping device according to claim 8, characterized in that, It further includes a fourth PMOS transistor, which is connected to the first drain / source path, the second drain / source path and the first power grid, wherein the gate of the fourth PMOS transistor is connected to the output of the latch inverter.

10. An electrostatic discharge clamping device, characterized in that, include: A discharge device, connected to a first power grid and a second power grid, is configured to discharge electrostatic discharge current during an electrostatic discharge event; An electrostatic discharge detection circuit is connected to the discharge device and configured to detect the electrostatic discharge event and, during the electrostatic discharge event, activate the discharge device to discharge the electrostatic discharge current. as well as A latch circuit includes an input and an output. The input is configured to receive a pre-charge voltage during a pre-charge phase to latch the latch circuit, and to track a first grid voltage at the output of the first grid during a ramp-up phase. The output is coupled to the discharge device to prevent the discharge device from starting during both the pre-charge phase and the ramp-up phase. The latch circuit mentioned above includes: A first PMOS transistor has a first gate connected to the first power grid and a first drain / source path connected to the input of the latch circuit; A second PMOS transistor has a second gate and a second drain / source path connected to the first drain / source path and the output of the latch circuit; and A latch inverter has a latch inverter input and a latch inverter output, the latch inverter input being connected to the output of the latch circuit, and the latch inverter output being connected to the second gate of the second PMOS transistor.

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