A circuit for reducing the area of an h-bridge drive circuit

Abstract

The application relates to the technical field of integrated circuits, and provides a circuit for reducing the area of an H-bridge driving circuit, which comprises an H-bridge composed of four N-type power tubes, a digital control switch module, a charge pump module and a level conversion module, the charge pump module is used for generating a pump voltage VDDH higher than a power supply voltage VDD, and the circuit further comprises a selector module used for selecting the output VDDH or an output voltage VOUT of the H-bridge as an output voltage VCH according to the level of SW; a first control circuit CTL1 used for generating a first gate control signal CK1 for controlling the gate of the upper bridge arm power tube of the H-bridge; and a second control circuit CTL2, the power supply end of which is connected with an internal low-voltage power supply VDDL, and the ground end of which is connected with a chip ground GND. The application sets the pump voltage of the charge pump reasonably, selects the power supply voltage of the control circuit module during operation through a selection circuit, and achieves the purpose of reducing the voltage difference between the power supply and the ground during operation of the control circuit module, so that a non-high-voltage tube can be used, and the area of the control circuit module is optimized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and specifically to a circuit that reduces the area of ​​an H-bridge driver circuit. Background Technology

[0002] While the traditional H-bridge with four N-transistors improves efficiency, it requires a charge pump circuit and a control circuit to control the on / off state of the MOSFETs in the H-bridge in order to ensure complete signal transmission. Figure 1 As shown. When the H-bridge circuit involves high voltage, the control circuit must use high-voltage transistors. If the control circuit integrates algorithms and protection circuits and becomes very complex, the module area will become very large due to the use of high-voltage transistors.

[0003] Figure 1 This is a traditional half-side N-transistor H-bridge circuit, along with the gate control circuit for the H-bridge. Its components include a digital control switching circuit, a charge pump circuit, a level shifting circuit, and a control circuit (CTL). The charge pump circuit provides a voltage higher than VDD to the level shifting circuit and the control circuit (CTL). This ensures that when CK1 is high, the voltage exceeds VDD, guaranteeing... Figure 1 When LDNM1 is turned on, VDD can be transmitted to VOUT without loss. Since a high-voltage transistor is required when the control circuit (CTL) of this structure involves high voltage, it requires a relatively large area. Utility Model Content

[0004] To help solve the above-mentioned technical problems, this application provides a circuit that reduces the area of ​​the H-bridge drive circuit, using the following technical solution: A circuit for reducing the area of ​​an H-bridge drive circuit, comprising an H-bridge composed of four N-type power transistors, a digital control switch module, a charge pump module, and a level conversion module, wherein the charge pump module is used to generate a pump voltage VDDH higher than the power supply voltage VDD, and further comprising: The selector module has a first input terminal connected to the output terminal of the charge pump module to receive the VDDH voltage, a second input terminal connected to the output terminal of the H bridge, and a control terminal connected to a switch signal SW, which is used to select the output VDDH or the output voltage VOUT of the H bridge as the output voltage VCH according to the level of SW. The first control circuit CTL1 has its power supply terminal connected to the output terminal VCH of the selector module and its ground terminal connected to the output terminal of the H-bridge. It is used to generate the first gate control signal CK1 to control the gate of the power transistor in the upper arm of the H-bridge. The second control circuit CTL2 has its power supply terminal connected to the internal low-voltage power supply VDDL and its ground terminal connected to the chip ground GND. It is used to generate the second gate control signal CK2 to control the gate of the power transistor in the lower arm of the H-bridge. The voltage range of the first gate control signal CK1 is from VOUT to VDDH. The selector module dynamically selects the VCH voltage so that the voltage difference between the power supply terminal and the ground terminal of CTL1 is less than a preset voltage difference threshold, so that CTL1 is implemented using a non-high voltage MOSFET. The voltage range of the second gate control signal CK2 is from GND to VDDL. The voltage difference between the power supply terminal and the ground terminal is constant at VDDL, so that CTL2 is implemented using a non-high voltage MOSFET.

[0005] Preferably, the first control circuit CTL1 includes a PMOS transistor PM1 and an NMOS transistor NM1. The gate of the PMOS transistor PM1 is controlled by the signal SW1H, and the gate of the NMOS transistor NM1 is controlled by the signal SW2H. The source of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM1, and the connection point outputs the first gate control signal CK1.

[0006] Preferably, the second control circuit CTL2 includes a PMOS transistor PM2 and an NMOS transistor NM2. The gate of the PMOS transistor PM2 is controlled by the signal SW3H, and the gate of the NMOS transistor NM2 is controlled by the signal SW4H. The source of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM2, and the connection point outputs the second gate control signal CK2.

[0007] Preferably, the H-bridge includes an upper bridge arm power transistor LDNM1 and a lower bridge arm power transistor LDNM2. The gate of LDNM1 is used to receive a first gate control signal CK1, the drain is connected to the power supply, and the source is connected to the drain of LDNM2. The gate of LDNM2 is used to receive a second gate control signal CK2, and the source is grounded.

[0008] Preferably, the signal output by the digital control switch module is converted to obtain switch signals SW1H, SW2H, SW3H and SW4H. The switch signals SW1H and SW2H are in phase, the switch signals SW3H and SW4H are in phase, and SW1H and SW3H are out of phase.

[0009] Preferably, the level conversion module includes a first level conversion structure and a second level conversion structure. The input terminals of both the first and second level conversion structures are connected to a digital control switch module, and the output terminals are respectively connected to a first control circuit CTL1 and a second control circuit CTL2. The second level conversion structure is also connected to the pump voltage VDDH and the output voltage VOUT. The first level conversion structure is also connected to the chip ground GND and the internal low-voltage power supply VDDL.

[0010] Preferably, the switch signal SW connected to the control terminal of the selector module is obtained by converting the signal generated by the digital control switch module through the level conversion module.

[0011] Preferably, the NMOS transistor in the first control circuit CTL1 adopts a self-isolation structure.

[0012] In summary, this application achieves the goal of reducing the voltage difference between the power supply and ground when the control circuit module is working by reasonably setting the pump voltage of the charge pump and selecting the power supply voltage of the control circuit module through the selection circuit. This allows the use of non-high voltage tubes and optimizes the area of ​​the control circuit module. Attached Figure Description

[0013] Figure 1 The accompanying drawings are related to the background technology. Figure 2 This is a schematic diagram of a circuit structure for reducing the area of ​​an H-bridge drive circuit according to this application. Detailed Implementation

[0014] The present application will be further described below with reference to the accompanying drawings. The structure and principle of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0015] Figure 2 This is a schematic diagram of a circuit structure for reducing the area of ​​an H-bridge drive circuit according to this application. Figure 2 The charge pump module in Figure 1 Corresponding to the charge pump module in, Figure 2 The digital control switch module in the middle and Figure 1 Corresponding to the digital control switch module in, Figure 2 The level conversion structures 1 and 2 modules in the middle are Figure 1 Corresponding to the level conversion circuit module in, Figure 2 The CTL1 and CTL2 modules in Figure 1 This corresponds to the control circuit (CTL) in the system. Figure 2 An additional selector module was added, and modifications were made. Figure 1 The control circuit (CTL) in the middle becomes Figure 2 In the CTL1 and CTL2 modules, the voltage difference between the power supply and ground of each module is not large when they are in operation, thus optimizing the area of ​​the CTL1 and CTL2 modules. Therefore, the modules of the prior art will not be described in detail in this application.

[0016] The circuit for reducing the area of ​​the H-bridge drive circuit in this application includes an H-bridge composed of four N-type power transistors, a digital control switch module, a charge pump module, and a level conversion module. The charge pump module is used to generate a pump voltage VDDH that is higher than the power supply voltage VDD. It also includes: The selector module has a first input terminal connected to the output terminal of the charge pump module to receive the VDDH voltage, a second input terminal connected to the output terminal of the H bridge, and a control terminal connected to a switch signal SW, which is used to select the output VDDH or the output voltage VOUT of the H bridge as the output voltage VCH according to the level of SW. The first control circuit CTL1 has its power supply terminal connected to the output terminal VCH of the selector module and its ground terminal connected to the output terminal of the H-bridge. It is used to generate the first gate control signal CK1 to control the gate of the power transistor in the upper arm of the H-bridge. The second control circuit CTL2 has its power supply terminal connected to the internal low-voltage power supply VDDL and its ground terminal connected to the chip ground GND. It is used to generate the second gate control signal CK2 to control the gate of the power transistor in the lower arm of the H-bridge. The voltage range of the first gate control signal CK1 is from VOUT to VDDH. The selector module dynamically selects the VCH voltage so that the voltage difference between the power supply terminal and the ground terminal of CTL1 is less than the preset voltage difference threshold, so that CTL1 is implemented using a non-high voltage MOSFET. The voltage range of the second gate control signal CK2 is from GND to VDDL. The voltage difference between the power supply terminal and the ground terminal is constant at VDDL, so that CTL2 is implemented using a non-high voltage MOSFET.

[0017] Specifically, the circuit structure of this application includes: H-bridge: Both upper and lower LDNMOS transistors are used to reduce area.

[0018] Digital control switch: generates the most basic control signals to control the H-bridge to turn on and off.

[0019] Charge pump: Provides a VDDH voltage higher than VDD to ensure that VDD can be transferred from LDNM1 to VOUT without loss.

[0020] Level conversion structures 1 and 2: convert the output voltage of the digital control switch.

[0021] Selector: Selects whether to output VOUT or VDDH. When SW is high, the output is VDDH; when SW is low, the output is VOUT.

[0022] CTL1: A reasonable setting of the VDDH voltage allows the structure to be constructed using non-high-voltage MOS transistors, which are used to generate CK1 to control the gate terminal of LDNM1. The power supply is connected to VCH, and the ground is connected to VOUT. Since VOUT is not necessarily GND, the NMOS transistors in this structure are all self-isolated transistors.

[0023] CTL2: A reasonable setting of the VDDL voltage allows this structure to be constructed using a non-high-voltage MOS transistor, used to generate CK2 to control the gate terminal of LDNM2. The power supply is connected to VDDL, and the ground is connected to GND.

[0024] VDD is the chip's power input, GND is the chip's ground input, and VOUT is the H-bridge output. VDDH is generated by the chip's internal charge pump module, VDDL is the chip's internal low-voltage power supply, SW1H, SW2H, SW3L, and SW4L are obtained by converting signals generated by the digital control switch module, and CK1 and CK2 are generated by the CTL1 and CTL2 circuits to control the on and off states of LDNM1 and LDNM2.

[0025] Figure 2 The diagram also illustrates the algorithm and protection circuit. While the traditional H-bridge with four N-transistors improves efficiency, a charge pump circuit and a control circuit are needed to control the on / off state of the H-bridge's MOSFETs in order to ensure complete signal transmission. When the H-bridge circuit involves high voltage, the control circuit must use high-voltage transistors. If this control circuit integrates the algorithm and protection circuit, it becomes very complex, and the module area will become very large due to the use of high-voltage transistors. Therefore, the algorithm and protection circuit are only shown to illustrate the technical problems that existing technology would bring about by using this circuit. The internal structure of this circuit is not directly related to the inventive point of this application, so the internal structure of the circuit will not be described in detail here.

[0026] The first control circuit CTL1 includes a PMOS transistor PM1 and an NMOS transistor NM1. The gate of the PMOS transistor PM1 is controlled by the signal SW1H, and the gate of the NMOS transistor NM1 is controlled by the signal SW2H. The source of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM1, and the connection point outputs the first gate control signal CK1.

[0027] The second control circuit CTL2 includes a PMOS transistor PM2 and an NMOS transistor NM2. The gate of the PMOS transistor PM2 is controlled by the signal SW3H, and the gate of the NMOS transistor NM2 is controlled by the signal SW4H. The source of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM2, and the connection point outputs the second gate control signal CK2.

[0028] The H-bridge includes an upper arm power transistor LDNM1 and a lower arm power transistor LDNM2. The gate of LDNM1 is used to receive the first gate control signal CK1, the drain is connected to the power supply, and the source is connected to the drain of LDNM2. The gate of LDNM2 is used to receive the second gate control signal CK2, and the source is grounded.

[0029] The signals output by the digital control switch module are converted into switch signals SW1H, SW2H, SW3H and SW4H. Switch signals SW1H and SW2H are in phase, switch signals SW3H and SW4H are in phase, and SW1H and SW3H are out of phase.

[0030] The level conversion module includes a first level conversion structure (level conversion structure 1) and a second level conversion structure (level conversion structure 2). The input terminals of both the first and second level conversion structures are connected to the digital control switch module, and the output terminals are connected to the first control circuit CTL1 and the second control circuit CTL2, respectively. The second level conversion structure is also connected to the pump voltage VDDH and the output voltage VOUT. The first level conversion structure is also connected to the chip ground GND and the internal low-voltage power supply VDDL.

[0031] The switch signal SW, which is input to the control terminal of the selector module, is obtained by converting the signal generated by the digital control switch module through the level conversion module. The NMOS transistor in the first control circuit CTL1 adopts a self-isolation structure.

[0032] The working principle of this application will be explained below.

[0033] Assume VDD = 12V, VDDH = VDD + 5V = 17V, and VDDL = 5V. SW1H and SW2H are in phase, SW3L and SW4L are in phase, and SW1H and SW3L are out of phase. For example... Figure 2 As shown, for convenience, only half of the H-bridge is analyzed, and the operation of the SW1H, SW2H, SW3L, and SW4L control circuits is analyzed.

[0034] When SW1H and SW2H are VDDH, and SW3L and SW4L are GND.

[0035] PM2 is on, NM2 is off, so CK2 = VDDL, and LDNM2 is on. PM1 is off, NM1 is on, CK1 = VOUT, and LDNM1 is off. Because LDNM2 is on and LDNM1 is off, VOUT = GND, VCH = VOUT = GND. At this time, the ground of CTL1 is connected to VOUT, and the power supply is connected to VOUT. The ground of CTL2 is connected to GND, and the power supply is connected to VDDL. The voltage difference between the power supply and ground is relatively small, so high-voltage transistors are not necessary for CTL1 and CTL2. Since the ground of CTL1 is connected to VOUT, the NMOS transistor in CTL1 should be a self-isolated transistor.

[0036] When SW1H and SW2H are VOUT, and SW3L and SW4L are VDDL.

[0037] PM2 is off, NM2 is on, so CK2 = GND, and LDNM2 is off. PM1 is on, NM1 is off, CK1 = VDDH, and LDNM1 is on. Because LDNM1 is on and LDNM2 is off, VOUT = VDD, VCH = VDDH. At this time, the ground of CTL1 is connected to VOUT = VDD, and the power supply is connected to VDDH. The ground of CTL2 is connected to GND, and the power supply is connected to VDDL. The voltage difference between the power supply and ground is relatively small, so high-voltage transistors are not necessary for CTL1 and CTL2. Since the ground of CTL1 is connected to VOUT, the NMOS transistor in CTL1 should be a self-isolated transistor.

[0038] In summary, the CK1 variation range generated by CTL1 is between VOUT and VDDH, ensuring that VDD is completely transferred to VOUT. Furthermore, the charge pump and selector guarantee a relatively low voltage difference between the power supply and ground of this module, thus eliminating the need for a high-voltage transistor. During CTL2 operation, the voltage difference between the power supply and ground remains constant at VDDL, so a reasonable VDDL also ensures that the CTL2 module does not require a high-voltage transistor. This optimizes (reduces) the area of ​​the CTL module.

Claims

1. A circuit for reducing the area of ​​an H-bridge drive circuit, comprising an H-bridge composed of four N-type power transistors, a digital control switch module, a charge pump module, and a level conversion module, wherein the charge pump module is used to generate a pump voltage VDDH higher than the power supply voltage VDD, characterized in that, Also includes: The selector module has a first input terminal connected to the output terminal of the charge pump module to receive the VDDH voltage, a second input terminal connected to the output terminal of the H bridge, and a control terminal connected to a switch signal SW, which is used to select the output VDDH or the output voltage VOUT of the H bridge as the output voltage VCH according to the level of SW. The first control circuit CTL1 has its power supply terminal connected to the output terminal VCH of the selector module and its ground terminal connected to the output terminal of the H-bridge. It is used to generate the first gate control signal CK1 to control the gate of the power transistor in the upper arm of the H-bridge. The second control circuit CTL2 has its power supply terminal connected to the internal low-voltage power supply VDDL and its ground terminal connected to the chip ground GND. It is used to generate the second gate control signal CK2 to control the gate of the power transistor in the lower arm of the H-bridge. The voltage range of the first gate control signal CK1 is from VOUT to VDDH. The selector module dynamically selects the VCH voltage so that the voltage difference between the power supply terminal and the ground terminal of CTL1 is less than a preset voltage difference threshold, so that CTL1 is implemented using a non-high voltage MOSFET. The voltage range of the second gate control signal CK2 is from GND to VDDL. The voltage difference between the power supply terminal and the ground terminal is constant at VDDL, so that CTL2 is implemented using a non-high voltage MOSFET.

2. The circuit for reducing the area of ​​the H-bridge drive circuit according to claim 1, characterized in that, The first control circuit CTL1 includes a PMOS transistor PM1 and an NMOS transistor NM1. The gate of the PMOS transistor PM1 is controlled by the signal SW1H, and the gate of the NMOS transistor NM1 is controlled by the signal SW2H. The source of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM1, and the connection point outputs the first gate control signal CK1.

3. The circuit for reducing the area of ​​the H-bridge drive circuit according to claim 1, characterized in that, The second control circuit CTL2 includes a PMOS transistor PM2 and an NMOS transistor NM2. The gate of the PMOS transistor PM2 is controlled by the signal SW3H, and the gate of the NMOS transistor NM2 is controlled by the signal SW4H. The source of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM2, and the connection point outputs the second gate control signal CK2.

4. The circuit for reducing the area of ​​the H-bridge drive circuit according to claim 1, characterized in that, The H-bridge includes an upper arm power transistor LDNM1 and a lower arm power transistor LDNM2. The gate of LDNM1 is used to receive a first gate control signal CK1, the drain is connected to the power supply, and the source is connected to the drain of LDNM2. The gate of LDNM2 is used to receive a second gate control signal CK2, and the source is grounded.

5. The circuit for reducing the area of ​​the H-bridge drive circuit according to claim 1, characterized in that, The signals output by the digital control switch module are converted to obtain switch signals SW1H, SW2H, SW3H and SW4H. The switch signals SW1H and SW2H are in phase, the switch signals SW3H and SW4H are in phase, and SW1H and SW3H are out of phase.

6. The circuit for reducing the area of ​​the H-bridge drive circuit according to claim 1, characterized in that, The level conversion module includes a first level conversion structure and a second level conversion structure. The input terminals of both the first and second level conversion structures are connected to a digital control switch module, and the output terminals are connected to the first control circuit CTL1 and the second control circuit CTL2, respectively. The second level conversion structure is also connected to the pump voltage VDDH and the output voltage VOUT. The first level conversion structure is also connected to the chip ground GND and the internal low-voltage power supply VDDL.

7. The circuit for reducing the area of ​​the H-bridge drive circuit according to claim 1, characterized in that, The switch signal SW connected to the control terminal of the selector module is obtained by converting the signal generated by the digital control switch module through the level conversion module.

8. The circuit for reducing the area of ​​the H-bridge drive circuit according to claim 1, characterized in that, The NMOS transistor in the first control circuit CTL1 adopts a self-isolation structure.

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