A PCIe-to-afdx device

Abstract

The application provides a PCIE-to-AFDX device, which comprises one or more SFP connectors for connecting with an external AFDX network, a PMC / XMC connector for connecting with an external host computer, wherein the PMC / XMC connector is compatible with a PCI interface and a PCIe interface, and an FPGA connected with the SFP connector and the PMC / XMC connector respectively, and used for realizing conversion between a PCIE protocol and an AFDX protocol.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a PCIPCIe to AFDX device. Background Technology

[0002] AFDX (Avionics Full Duplex Switched Network) is a deterministic, highly reliable network protocol designed specifically for avionics systems, optimized from standard Ethernet technology. This protocol is widely used in commercial aircraft such as the Airbus A380, A350, and Boeing 787, and has also been adopted by domestic aircraft such as the C919. It is primarily used to connect critical subsystems such as flight control, navigation, and engines, meeting the stringent requirements of the aviation industry for real-time performance and fault tolerance.

[0003] PCI (Peripheral Component Interconnect) is a parallel bus interface standard for connecting computer peripherals. It was proposed by Intel in 1992. In fields such as industrial control and test measurement, there are still a large number of devices and systems based on the PCI interface.

[0004] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that supports point-to-point communication and has advantages such as high bandwidth and low latency. It has now become the core interconnect technology for mainstream computers and embedded platforms and is widely used in the connection of peripherals such as graphics cards, solid-state drives, and high-speed network cards.

[0005] In the research and testing of avionics systems, data interaction between different bus platforms / systems and AFDX networks is often required. Different systems have different requirements for the bus compatibility of AFDX interface devices. However, existing AFDX interface devices typically only support a single bus type (PCI or PCIe). When users need to switch between different host platforms, they must replace the compatible hardware, resulting in low equipment reuse rates, high procurement costs, and complex maintenance. Utility Model Content

[0006] The purpose of this application is to provide a PCIPCIe to AFDX converter, which uses one or more SFP connectors and PMC / XMC connectors to connect an external AFDX network to an external host, and an FPGA to perform data conversion between the PCIPCIe and AFDX protocols. This device solves the problems of poor bus compatibility and difficulty in cross-platform reuse of existing devices, and improves the adaptability and maintainability of the device in multi-host environments.

[0007] The embodiments of this application are implemented as follows: This application provides a PCIPCIe to AFDX converter, comprising: one or more SFP connectors for connecting to an external AFDX network; a PMC / XMC connector for connecting to an external host computer, the PMC / XMC connector being compatible with both PCI and PCIe interfaces; and an FPGA connected to both the SFP connector and the PMC / XMC connector, for implementing the conversion between the PCIPCIe protocol and the AFDX protocol.

[0008] In some embodiments of this application, each of the one or more SFP connectors is configured to mount an optical module or an electrical port module to enable AFDX communication via the optical or electrical interface.

[0009] In some embodiments of this application, the number of the one or more SFP connectors is four, configured to implement two-way dual-redundant AFDX communication, with each dual-redundant AFDX communication channel consisting of two SFP connectors.

[0010] In some embodiments of this application, the FPGA includes a PCI IP core and a PCIe IP core, which are used to implement PCI communication and PCIe communication, respectively.

[0011] In some embodiments of this application, the PCI IP core implements the PCI bus interface.

[0012] In some embodiments of this application, the PCIe IP core implements a PCIe 2.0 x4 interface.

[0013] The PCIPCIe to AFDX device provided in this application embodiment has at least the following beneficial effects, including but not limited to: By adopting PMC / XMC connectors compatible with PCI and PCIe interfaces, the same device can be used across different host platforms, solving the problem of repeated procurement of existing equipment due to bus incompatibility; the SFP connector supports flexible replacement of optical modules or electrical port modules, realizing the configurability of physical interfaces and improving the adaptability and reusability of the device in different AFDX network environments.

[0014] Four SFP connectors are used to form two dual-redundant AFDX communication channels to meet the high reliability requirements of avionics systems. The FPGA integrates PCI IP cores and PCIe IP cores to support the two bus protocols respectively, ensuring the flexibility and compatibility of protocol conversion. The PCI IP core supports the 32-bit 33MHz standard, and the PCIe IP core supports the PCIe 2.0 x4 interface, balancing performance and versatility. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of an AFDX fiber optic interface bus device; Figure 2 A schematic diagram of an AFDX bus device with an electrical interface; Figure 3 An exemplary structural diagram of a PCIPCIe to AFDX device provided in this application embodiment; Figure 4 This is an exemplary structural diagram of the power supply circuit in a PCIPCIe to AFDX device provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0020] In this application, the terms "first" and "second" are used to distinguish identical or similar items that have essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" do not necessarily imply that they are different.

[0021] It should be noted that, in this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0022] Furthermore, "at least one" refers to one or more, while "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0023] In the description of the embodiments of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] To facilitate understanding of the embodiments of this application, the relevant technologies of this application are described below.

[0025] The PCIPCIe to AFDX converter is a key component in avionics subsystems for achieving cross-platform data interoperability. Through efficient protocol conversion and reliable communication, it supports the efficient operation of flight control, avionics testing, and airborne networks, making it suitable for research and development and testing processes. In some implementations, a dedicated AFDX protocol chip can be used to convert data from the PCI or PCIe bus to the AFDX bus. Alternatively, protocol conversion can be implemented using an FPGA. Compared to dedicated chips, the FPGA solution offers advantages such as strong scalability, high flexibility, and low hardware cost.

[0026] Regarding AFDX physical layer interfaces, existing devices are typically divided into two categories based on application requirements: fiber optic interfaces and electrical interfaces. Fiber optic interfaces can be implemented using optical modules, while electrical interfaces can be implemented using Ethernet PHY chips in conjunction with network transformers. Figure 1 An exemplary AFDX bus device with a fiber optic interface is shown, wherein an external host is connected to a PCI or PCIe bridge via a PCI or PCIe bus, the bridge then interacts with an AFDX dedicated protocol chip or FPGA, and finally connects to the AFDX network through the fiber optic interface. Figure 2 An exemplary AFDX bus device is shown. The external host is also connected to the PCI or PCIe bridge via the PCI or PCIe bus. After the bridge interacts with the AFDX dedicated protocol chip or FPGA, it finally connects to the AFDX network through the PHY chip and transformer via the RJ45 interface.

[0027] Due to differences in hardware circuitry and signal processing between optical and electrical interfaces, existing products typically design them independently, making them incompatible. Furthermore, regarding host bus interfaces, PCI and PCIe, as different generations of bus standards, have different electrical characteristics and communication protocols. Existing devices generally only support one bus type, making it impossible to simultaneously support both PCI and PCIe interfaces on the same hardware platform. To meet different application scenarios, users need to configure four separate devices: PCI to AFDX electrical port, PCI to AFDX optical port, PCIe to AFDX electrical port, and PCIe to AFDX optical port. This not only increases hardware procurement and maintenance costs but also results in low reusability of devices across different platforms, making it difficult to adapt to changing testing and verification needs.

[0028] In summary, the existing solutions have the following technical problems: 1) The interface for communicating with the host is limited to either PCI or PCIe. Although only one interface may be used in a given instance, if the user has already purchased an AFDX bus device with a PCI interface and wants to switch to a PCIe computer, the user will need to purchase the device again, increasing the user's procurement costs and time. 2) The AFDX bus interface is limited, supporting only fiber optic interfaces or only RJ45 electrical interfaces. The hardware and software are different, resulting in high design and maintenance costs. When users need to change the interface, they need to purchase two different devices, increasing their procurement costs and time.

[0029] To address the aforementioned technical problems, this application provides a PCIPCIe to AFDX converter, wherein: 1) The AFDX bus device is designed as a PMC-compatible XMC structure, and implements both PCI and PCIe interfaces. Users only need to replace different carrier boards to meet the needs of users on different computer platforms. 2) The AFDX bus device is designed as a PMC-compatible XMC structure, and implements both PCI and PCIe interfaces. Users only need to replace different carrier boards to meet the needs of users on different computer platforms.

[0030] The embodiments of this application are described below.

[0031] In this embodiment of the application, a PCIPCIe to AFDX device includes: one or more SFP connectors for connecting to an external AFDX network; a PMC / XMC connector for connecting to an external host computer, wherein the PMC / XMC connector is compatible with both PCI and PCIe interfaces; and an FPGA connected to both the SFP connector and the PMC / XMC connector, for implementing the conversion between the PCIPCIe protocol and the AFDX protocol.

[0032] The PCIPCIe to AFDX converter proposed in this application connects to the AFDX network via an SFP connector, supporting flexible configuration of optical or electrical modules to adapt to different physical layer deployment requirements. The PMC / XMC connector serves as the host interface, compatible with both PCI and PCIe bus standards, allowing the same hardware to be reused across different host platforms without requiring device replacement due to different bus types. The FPGA, as the core processing unit, internally implements data encapsulation, parsing, and forwarding between the PCIPCIe and AFDX protocols, and completes AFDX data link layer communication by calling the SGMII interface core. This integrated design achieves efficient interoperability between cross-bus platforms and AFDX networks, solving the problems of poor bus compatibility and limited interfaces in existing devices, improving device versatility, and reducing procurement and maintenance costs for users in multi-platform environments.

[0033] In some embodiments of this application, each of the one or more SFP connectors is configured to mount an optical module or an electrical port module to enable AFDX communication via the optical or electrical interface.

[0034] Each SFP connector supports hot-swappable optical or electrical modules, allowing users to easily replace modules based on the network cabling type (fiber optic or twisted pair) without replacing the entire unit. The electrical modules support 10M / 100M / 1000Mbps speed switching via register configuration. This design breaks the limitations of fixed interfaces in traditional AFDX devices, enabling "one device for multiple uses" and significantly improving the flexibility and adaptability of the equipment in field applications.

[0035] In some embodiments of this application, the number of the one or more SFP connectors is four, configured to implement two-way dual-redundant AFDX communication, with each dual-redundant AFDX communication channel consisting of two SFP connectors.

[0036] The four SFP connectors are divided into two groups, with two in each group forming a dual-redundant AFDX communication channel. The system can simultaneously connect to the primary and backup AFDX networks, enabling dual-path data transmission. When the primary channel fails, it can seamlessly switch to the backup channel, ensuring continuous and reliable transmission of critical data such as flight control and navigation. This structure meets the high reliability and fault tolerance requirements of avionics systems and is suitable for testing and verification scenarios on aircraft such as the C919 and A380.

[0037] In some embodiments of this application, the FPGA includes a PCI IP core and a PCIe IP core, which are used to implement PCI communication and PCIe communication, respectively.

[0038] The FPGA integrates independent PCI and PCIe IP cores, allowing users to select and enable the appropriate IP core via hardware configuration or host software. The PCI IP core is enabled when a PCI host is connected, and the PCIe IP core is enabled when a PCIe host is connected. This dual-IP core architecture is the core mechanism for achieving single-hardware compatibility with dual buses, avoiding the need to repeatedly develop dedicated devices for different hosts.

[0039] In some embodiments of this application, the PCI IP core implements the PCI bus interface.

[0040] The PCI IP core implements a 32-bit 33MHz bus interface function compliant with the PCI standard. It communicates with the host through the PMC connector, ensuring stable interfacing with existing industrial control equipment and guaranteeing good compatibility.

[0041] In some embodiments of this application, the PCIe IP core implements a PCIe 2.0 x4 interface.

[0042] The PCIe IP core supports the PCIe 2.0 standard, meeting the data throughput requirements of AFDX networks. This interface connects to the host via an XMC connector, making it suitable for high-performance embedded platforms and ensuring real-time data transmission with low latency. The PCIe lane width can be configured as x1, x2, or x4 as needed.

[0043] Figure 3 This is an exemplary structural diagram of a PCIPCIe to AFDX device provided in an embodiment of this application. The number of SFP connectors is four. It is understood that the number of SFP connectors can be adjusted according to actual needs. Furthermore, the components, voltage, and other parameters shown in the diagram can also be changed according to specific application scenarios.

[0044] like Figure 3 As shown, an exemplary PCIPCIe to AFDX device according to an embodiment of this application may include the following components: (1) FPGA: The core of the PCIPCIe to AFDX protocol conversion is to implement PCIPCIe interface communication, receive data from the host, and then frame and send the received host data according to the AFDX protocol requirements. When data is received from the AFDX interface, the packet type is parsed, and the packets are reassembled and transmitted to the computer via PCIPCIe. The AFDX interface is implemented using the SGMII core.

[0045] The SPI FLASH is used to store the FPGA's configuration data and startup code. When the system powers on, the FPGA reads the configuration data from the SPI FLASH for initialization.

[0046] (2) PCI: The FPGA internally calls the PCI IP core to implement a 32-bit, 33MHz PCI interface, and the board communicates with the computer through the PCI connector.

[0047] (3) PCIe: The PCIe 2.0 interface is implemented using a PCIe IP core within the FPGA, and the board communicates with the computer via a PCIe connector. The PCIe speed and width are configurable as needed; the width can be configured to 1X, 2X, or 4X, and the speed can be configured to 2.5Gbps or 5Gbps.

[0048] (4) Crystal oscillator: Provides a reference clock for the SGMII transceiver interface, with a standard frequency of 125MHz.

[0049] The AFDX protocol stack operating clock is provided using a highly stable 25MHz temperature-compensated crystal oscillator, which is multiplied to 100MHz inside the FPGA for use by the AFDX protocol stack.

[0050] It provides a 200MHz clock speed to serve as a reference clock for DDR3.

[0051] (5) BUFF: This is used for interface protection between external interfaces and FPGA I / O, and the protection signals include JTAG interface, LED driver interface, PCI bus interface, and external connector I / O interface.

[0052] (6) SFP: This system provides an external interface connector for AFDX, which can be equipped with an electrical port module for AFDX electrical communication or an optical module for AFDX optical communication. The electrical port module can be configured via registers to switch between 10Mbps, 100Mbps, and 1000Mbps speeds.

[0053] (7) LED: Two LEDs are onboard to indicate the board's operating status.

[0054] (8) JTAG connector: Used in FPGA firmware.

[0055] (9) Connector: The PCI interface is implemented using a PMC connector, and the PCIe interface is implemented using an XMC connector.

[0056] (12) DDR3 memory: 32-bit DDR3 memory, 1GB capacity, provides caching for AFDX data transmission and reception.

[0057] (13) NOR FLASH: The FPGA firmware can be loaded via JTAG or via software through the PCIe interface.

[0058] (14) EEPROM: Store user information and configuration information, such as hardware version number, board serial number, software version number, and default configuration of electrical port modules.

[0059] (15) Power supply circuit: The power input from the host via the PCIe interface is converted into the power required by each chip on the board. The converted power supplies include the FPGA core power supply, auxiliary power supply, IO power supply, GTX core power supply, GTX auxiliary power supply, GTX transceiver power supply, SFP interface operating power supply, BUFF power supply, NOR FLASH, EEPROM, DDR3 operating power supply, and crystal oscillator operating power supply.

[0060] Figure 4 This is an exemplary structural diagram of the power supply circuit in a PCIPCIe to AFDX device provided in an embodiment of this application. It is understood that the components, voltages, and other parameters shown in the diagram can be changed according to specific application scenarios.

[0061] The power supply circuit can receive +5V input from the PCI interface and +12V input from the PCIe interface. Multiple voltage conversions are achieved through two DC-DC converters: the first DC-DC converter outputs +1.0V / 8A to power the FPGA core; it also outputs +1.2V / 4A to power the FPGA's GTX transceiver. The second DC-DC converter outputs +1.8V / 4A as auxiliary power for the FPGA; it outputs +3.3V / 4A to power peripheral circuits on the board; and it also outputs +1.5V / 4A as the operating power for the DDR3 memory. This +1.5V voltage is further connected to an LDO (low dropout linear regulator), and after regulation, it outputs +0.75V as the reference voltage (VTT) for the DDR3 memory. All power supplies are filtered and decoupled to ensure stable power supply, meeting the power accuracy and reliability requirements of the FPGA, DDR3, and high-speed interfaces.

[0062] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A PCIPCIe to AFDX converter, characterized in that, include: One or more SFP connectors for connecting to an external AFDX network; The PMC / XMC connector is used to connect to an external host computer. The PMC / XMC connector is compatible with both PCI and PCIe interfaces. The FPGA is connected to the SFP connector and the PMC / XMC connector respectively to realize the conversion between the PCIPCIe protocol and the AFDX protocol.

2. The apparatus according to claim 1, characterized in that, Each of the one or more SFP connectors is configured to mount an optical module or an electrical port module to enable AFDX communication via the optical or electrical interface.

3. The apparatus according to claim 2, characterized in that, The number of the one or more SFP connectors is four, configured to implement two-way dual-redundant AFDX communication, with each dual-redundant AFDX communication channel consisting of two SFP connectors.

4. The apparatus according to any one of claims 1-3, characterized in that, The FPGA includes a PCI IP core and a PCIe IP core, which are used to implement PCI communication and PCIe communication, respectively.

5. The apparatus according to claim 4, characterized in that, The PCI IP core implements the PCI bus interface.

6. The apparatus according to claim 4, characterized in that, The PCIe IP core implements the PCIe 2.0 x4 interface.

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