Semiconductor structure

Abstract

The utility model provides a kind of semiconductor structure, including p-type metal oxide semiconductor layer and n-type metal oxide semiconductor layer;Hydrogen-containing dielectric material part, it has the first type insulating surface of contact the n-type metal oxide semiconductor layer;And hydrogen-blocking dielectric material part, including a second type insulating surface of contact the p-type metal oxide semiconductor layer, the second type insulating surface is a non-hydrogen permeable surface.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure. Background Technology

[0002] Complementary transistor circuits (such as thin-film transistors or TFTs) require p-channel and n-channel transistors. A p-channel transistor comprises a p-type semiconductor material as the channel material, while an n-channel transistor comprises an n-type semiconductor material as the channel material. When the transistor operates in accumulation mode, the conduction mode of the carriers during operation may be the same as that of the channel material. In thin-film transistors operating in accumulation mode, holes are the carriers in p-channel thin-film transistors, while electrons are the carriers in n-channel thin-film transistors. Typically, p-type and n-type compound semiconductor materials are deposited separately to form p-channel and n-channel transistors. Multiple processing steps are used to deposit and pattern both types of compound semiconductor materials. This significantly increases manufacturing costs. Utility Model Content

[0003] This invention provides a semiconductor structure, comprising: a p-type metal oxide semiconductor layer and an n-type metal oxide semiconductor layer; a hydrogen-containing dielectric material portion having a first type of insulating surface in contact with the n-type metal oxide semiconductor layer; and a hydrogen-blocking dielectric material portion including a second type of insulating surface in contact with the p-type metal oxide semiconductor layer, wherein the second type of insulating surface is a hydrogen-impermeable surface. Attached Figure Description

[0004] The best understanding of the features of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0005] Figure 1 This is a vertical cross-sectional view of a first exemplary structure following the formation of a complementary metal-oxide-semiconductor (CMOS) transistor, a first metal interconnect structure formed in a lower dielectric layer, an insulating material layer, and a selective etch-blocking dielectric layer, according to one embodiment of the present disclosure.

[0006] Figure 2A and Figure 2BThis is a vertical cross-sectional view of a region of a first exemplary structure after the formation of a first conductive material layer, a first hydrogen-containing dielectric layer, a second conductive material layer, a first hydrogen-blocking dielectric layer, and a third conductive material layer, according to an embodiment of the present disclosure.

[0007] Figure 3A and Figure 3B This is a vertical cross-sectional view of a first exemplary structural region after patterning a first hydrogen-barrier dielectric layer and a third conductive material layer, according to an embodiment of this disclosure.

[0008] Figure 4A and Figure 4B This is a vertical cross-sectional view of a first exemplary structural region after the formation of a second hydrogen-containing dielectric layer and a fourth conductive material layer, according to one embodiment of the present disclosure.

[0009] Figure 5A and Figure 5B This is a vertical cross-sectional view of a first exemplary structural region after patterning a second hydrogen-containing dielectric layer and a fourth conductive material layer, according to one embodiment of the present disclosure.

[0010] Figure 6A and Figure 6B This is a vertical cross-sectional view of the first exemplary structural region after the formation of the second hydrogen-barrier dielectric layer and the fifth conductive material layer, according to an embodiment of this disclosure.

[0011] Figure 7A and Figure 7B This is a vertical cross-sectional view of a first exemplary structural region after patterning the second hydrogen-barrier dielectric layer and the fifth conductive material layer, according to an embodiment of this disclosure.

[0012] Figure 8A and Figure 8B This is a vertical cross-sectional view of a first exemplary structural region after the formation of a first through-hole cavity, according to an embodiment of the present disclosure.

[0013] Figure 9A and Figure 9B This is a vertical cross-sectional view of a first exemplary structural region after the formation of the second through-hole cavity, according to one embodiment of the present disclosure.

[0014] Figure 10A and Figure 10B This is a vertical cross-sectional view of a first exemplary structural region after the formation of the third through-hole cavity, according to one embodiment of the present disclosure.

[0015] Figure 11A and Figure 11BThis is a vertical cross-sectional view of a first exemplary structural region after the deposition of an amorphous metal oxide layer, according to one embodiment of the present disclosure.

[0016] Figure 12A and Figure 12B This is a vertical cross-sectional view of a first exemplary structural region after the deposition of a gate dielectric layer, according to an embodiment of this disclosure.

[0017] Figure 13A and Figure 13B This is a vertical cross-sectional view of a region of a first exemplary structure after the amorphous metal oxide layer has been transformed into a p-type metal oxide semiconductor layer and an n-type metal oxide semiconductor layer, according to one embodiment of the present disclosure.

[0018] Figure 14A and Figure 14B This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of the gate electrode, according to an embodiment of this disclosure.

[0019] Figure 15A and Figure 15B This is a vertical cross-sectional view of a region of a first exemplary structure after patterning a conductive material layer, a hydrogen-containing dielectric layer, and a hydrogen-resistant dielectric layer, according to one embodiment of the present disclosure.

[0020] Figure 16A and Figure 16B This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of a contact-level dielectric layer and a contact hole structure, according to one embodiment of the present disclosure.

[0021] Figure 17A and Figure 17B This is a top view of the configuration of the field-effect transistor stack and contact hole structure in the first exemplary structure according to an embodiment of the present disclosure.

[0022] Figure 18 This is a vertical cross-sectional view of a second exemplary structural region after forming a hydrogen-containing dielectric layer, according to one embodiment of the present disclosure.

[0023] Figure 19 This is a vertical cross-sectional view of a region of a second exemplary structure after the recessed region has been formed, according to one embodiment of the present disclosure.

[0024] Figure 20 This is a vertical cross-sectional view of a region of a second exemplary structure after the hydrogen-blocking dielectric material portion has been formed, according to one embodiment of the present disclosure.

[0025] Figure 21This is a vertical cross-sectional view of a region of a second exemplary structure after the source / drain cavity has been formed, according to one embodiment of the present disclosure.

[0026] Figure 22 This is a vertical cross-sectional view of a second exemplary structural region after the source / drain electrodes have been formed, according to one embodiment of the present disclosure.

[0027] Figure 23 This is a vertical cross-sectional view of a region of a second exemplary structure after the formation of an amorphous metal oxide layer and a gate dielectric layer, according to an embodiment of the present disclosure.

[0028] Figure 24 This is a vertical cross-sectional view of a region of a second exemplary structure after the amorphous metal oxide layer has been converted into a p-type metal oxide semiconductor layer and an n-type metal oxide semiconductor layer, according to one embodiment of the present disclosure.

[0029] Figure 25 This is a vertical cross-sectional view of a second exemplary structural region after the deposition of a gate material layer, according to one embodiment of the present disclosure.

[0030] Figure 26 This is a vertical cross-sectional view of a region of a second exemplary structure following a patterned gate structure, according to one embodiment of the present disclosure.

[0031] Figure 27 This is a vertical cross-sectional view of a second exemplary structural region after the contact layer dielectric layer and gate contact hole structure are formed, according to an embodiment of the present disclosure.

[0032] Figure 28 This is a vertical cross-sectional view of a region of an alternative configuration of a second exemplary structure after the formation of the contact layer dielectric layer and the gate contact hole structure, according to one embodiment of the present disclosure.

[0033] Figure 29 This is a vertical cross-sectional view of a third exemplary structural region after a gate electrode has been formed in a dielectric matrix layer, according to one embodiment of the present disclosure.

[0034] Figure 30 This is a vertical cross-sectional view of a region of a third exemplary structure after the gate dielectric component layer has been formed, according to one embodiment of the present disclosure.

[0035] Figure 31 This is a vertical cross-sectional view of a region of a third exemplary structure following a patterned second gate dielectric component layer, according to one embodiment of the present disclosure.

[0036] Figure 32This is a vertical cross-sectional view of a region of a third exemplary structure after the deposition of a hydrogen-containing dielectric layer, according to one embodiment of the present disclosure.

[0037] Figure 33 This is a vertical cross-sectional view of a region of a third exemplary structure after patterning a hydrogen-containing dielectric layer, according to one embodiment of the present disclosure.

[0038] Figure 34 This is a vertical cross-sectional view of a region of a third exemplary structure after the deposition of an amorphous metal oxide layer, according to one embodiment of the present disclosure.

[0039] Figure 35 This is a vertical cross-sectional view of a third exemplary structural region following a patterned amorphous metal oxide layer, according to one embodiment of the present disclosure.

[0040] Figure 36 This is a vertical cross-sectional view of a region of a third exemplary structure, according to one embodiment of the present disclosure, after the amorphous metal oxide layer has been converted into a p-type metal oxide semiconductor layer and an n-type metal oxide semiconductor layer.

[0041] Figure 37 This is a vertical cross-sectional view of a region of a third exemplary structure after the formation of the contact layer dielectric layer and the source / drain cavity, according to an embodiment of the present disclosure.

[0042] Figure 38 This is a vertical cross-sectional view of a region of a third exemplary structure after the formation of the source / drain electrodes, according to one embodiment of the present disclosure.

[0043] Figure 39 This is a vertical cross-sectional view of a region of a fourth exemplary structure, according to one embodiment of the present disclosure, after depositing a first gate dielectric component layer and a hydrogen-containing dielectric layer and patterning the hydrogen-containing dielectric layer.

[0044] Figure 40 This is a vertical cross-sectional view of a region of a fourth exemplary structure after the deposition of a second gate dielectric component layer, according to one embodiment of the present disclosure.

[0045] Figure 41 This is a vertical cross-sectional view of a region of a fourth exemplary structure after a patterned hydrogen-blocking dielectric layer, according to one embodiment of the present disclosure.

[0046] Figure 42 This is a vertical cross-sectional view of a region of a fourth exemplary structure after the deposition of an amorphous metal oxide layer, according to one embodiment of the present disclosure.

[0047] Figure 43This is a vertical cross-sectional view of a region of a fourth exemplary structure after a patterned amorphous metal oxide layer, according to one embodiment of the present disclosure.

[0048] Figure 44 This is a vertical cross-sectional view of a region of a fourth exemplary structure after the amorphous metal oxide layer has been converted into a p-type metal oxide semiconductor layer and an n-type metal oxide semiconductor layer, according to one embodiment of the present disclosure.

[0049] Figure 45 This is a vertical cross-sectional view of a region of a fourth exemplary structure after the formation of the contact layer dielectric layer and the source / drain cavity, according to one embodiment of the present disclosure.

[0050] Figure 46 This is a vertical cross-sectional view of a fourth exemplary structural region after the source / drain electrodes have been formed, according to one embodiment of the present disclosure.

[0051] Figure 47 This is a vertical cross-sectional view of a first exemplary structure after the formation of the upper metal interconnect structure, according to an embodiment of this disclosure.

[0052] Figure 48 This is a vertical cross-sectional view of a second, third, or fourth exemplary structure after the formation of the upper metal interconnect structure, according to one embodiment of the present disclosure.

[0053] Figure 49 This is the first flowchart, which illustrates the general processing steps for manufacturing the semiconductor device of this disclosure.

[0054] Figure 50 The second flowchart illustrates the general processing steps for manufacturing the semiconductor device of this disclosure. Detailed Implementation

[0055] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. The drawings are not to scale. Elements with the same reference numerals refer to the same element and are assumed to have the same material composition and the same thickness range, unless explicitly stated otherwise. Embodiments in which multiple instances of any described element are repeated are explicitly contemplated, unless explicitly stated otherwise. Embodiments in which non-essential elements are omitted are explicitly contemplated, even if such embodiments are not explicitly disclosed, but are known in the art.

[0056] Furthermore, for ease of explanation, this document may use spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein can be interpreted accordingly.

[0057] This disclosure relates to a semiconductor device using a modulated metal-oxide-semiconductor (MOS) material and a method for manufacturing the same. Specifically, the conductivity of the MOS material is modulated by controlling the local density of oxygen vacancies. A locally high concentration of oxygen vacancies in the MOS material induces n-type conductivity, and a locally low concentration of oxygen vacancies induces p-type conductivity. According to one aspect of this disclosure, the n-type semiconductor material can be provided by increasing the oxygen vacancies concentration in a first portion of the MOS material, and the p-type semiconductor material can be provided by decreasing the oxygen vacancies concentration in a second portion of the MOS material.

[0058] According to one aspect of this disclosure, embodiments of this disclosure improve the efficiency of manufacturing complementary field-effect transistors (CFPTs) by using a single semiconductor channel material deposition process, which can subsequently be used to form n-type and p-type metal-oxide-semiconductor (MOS) channels. This innovative approach eliminates the need for separate channel material deposition processes traditionally required for each semiconductor material, thereby reducing manufacturing costs and processing time. Furthermore, embodiments of this disclosure facilitate the integration of CFPTs into a variety of electronic devices by simplifying the manufacturing process and improving production scalability. The single deposition process used in the various embodiments disclosed herein not only simplifies the overall manufacturing sequence but also ensures consistent process control and reliable device characteristics for the CFPTs.

[0059] According to one aspect of this disclosure, n-type and p-type metal oxide semiconductor layers can be provided by depositing an amorphous metal oxide layer using a single deposition process and locally modulating the conductivity mode of the deposited amorphous metal oxide layer during an annealing process. The n-type metal oxide semiconductor material can be formed by promoting hydrogen diffusion from a hydrogen-containing dielectric layer to a first portion of the metal oxide semiconductor layer. For example, in some embodiments, the n-type metal oxide semiconductor material can be formed by promoting hydrogen diffusion from a hydrogen-containing dielectric layer to a first portion of the metal oxide semiconductor layer during an annealing process that crystallizes the amorphous metal oxide layer. However, in other embodiments, the n-type metal oxide semiconductor material can be formed by promoting hydrogen diffusion from a hydrogen-containing dielectric layer to a first portion of the amorphous metal oxide layer. Furthermore, a hydrogen-blocking dielectric layer, such as an alkaline earth metal oxide layer, can directly contact a second portion of the metal oxide semiconductor layer to suppress hydrogen diffusion to the second portion of the amorphous metal oxide layer, thereby forming a p-type metal oxide semiconductor layer during the annealing process.

[0060] By using only a single amorphous metal oxide deposition process to form p-type metal oxide semiconductor layers and n-type semiconductor layers, the various embodiments disclosed herein facilitate the fabrication of various types of thin-film transistor devices using complementary metal oxide semiconductor (CMOS) circuits. Furthermore, the various embodiments disclosed herein facilitate the fabrication process and device integration of vertical thin-film transistors by providing vertically stacked p-type metal oxide semiconductor layers and n-type semiconductor layers. For example, a CMOS inverter including vertical channels with different conductivity can be formed in a single via. Therefore, the embodiments disclosed herein facilitate the formation of high-density CMOS thin-film transistor circuits. Various aspects of this disclosure will now be described with reference to the accompanying drawings.

[0061] Reference Figure 1 This document describes a first exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 8. Typically, the substrate 8 comprises and / or is primarily composed of at least one material selected from insulating materials, semiconductor materials, and metallic materials. In one embodiment, the substrate 8 may be a commercially available semiconductor substrate such as a silicon substrate. The substrate 8 may include at least a semiconductor material layer 9 on its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate or a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 comprises a single-crystal semiconductor material, such as single-crystal silicon. In one embodiment, the substrate 8 may include a single-crystal silicon substrate comprising single-crystal silicon material.

[0062] The shallow trench isolation structure 720 includes a dielectric material, such as silicon oxide, which may be formed on the upper portion of the semiconductor material layer 9. Appropriately doped semiconductor wells, such as p-type and n-type wells, may be formed in each region laterally enclosed by a portion of the shallow trench isolation structure 720. Field-effect transistors 701 may be formed on the top surface of the semiconductor material layer 9. For example, each field-effect transistor 701 may include a source region 732, a drain region 738, a semiconductor channel 735 including a surface portion of the substrate 8 extending between the source region 732 and the drain region 738, and a gate structure 750. The semiconductor channel 735 may include a single-crystal semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source region 732, and a drain-side metal-semiconductor alloy region 748 may be formed on each drain region 738.

[0063] One or more field-effect transistors 701 in the CMOS circuit 900 may include a semiconductor channel 735, which includes a portion of a semiconductor material layer 9 in the substrate 8. In embodiments where the semiconductor material layer 9 includes a single-crystal semiconductor material (e.g., single-crystal silicon), the semiconductor channel 735 of each field-effect transistor 701 in the CMOS circuit 900 may include a single-crystal semiconductor channel, such as a single-crystal silicon channel.

[0064] In one embodiment, substrate 8 may include a monocrystalline silicon substrate, and field-effect transistor 701 may include portions of the monocrystalline silicon substrate as semiconductor channels. As used herein, a "semiconductor" device may refer to a device having a dielectric material with a dielectric material ... -5 S / m to 1.0×10 5 Devices with conductivity in the S / m range. As used herein, "semiconductor material" can mean a material having a conductivity of less than 1.0 S / m in the absence of electrical dopant, and capable of being produced with conductivity between 1.0 S / m and 1.0 × 10⁻⁶ S / m after appropriate doping with electrical dopant. 7 Doped materials with conductivity in the S / m range. As used herein, dielectric or insulating materials refer to materials with conductivity less than 1.0 × 10⁻⁶. -5 Materials with a conductivity of S / m. Conductive materials refer to materials with a conductivity greater than 1.0 × 10⁻⁶. 5 S / m conductivity or other materials explicitly identified as conductive materials in this disclosure. All measurements were performed under standard conditions, i.e., 0 degrees Celsius and 1 atmosphere.

[0065] Various metal interconnect structures may subsequently be formed within a dielectric layer above the substrate 8 and the semiconductor device (e.g., field-effect transistor 701) thereon. For example, the dielectric layer may include, for instance, a contact layer dielectric layer 601 surrounding contact structures connected to the source and drain, a first interconnect layer dielectric layer 610, and a second interconnect layer dielectric layer 620. The metal interconnect structures may include a device contact via structure 612 formed within the contact layer dielectric layer 601 and contacting respective components of the CMOS circuit 900, a first metal line structure 618 formed within the first interconnect layer dielectric layer 610, a first metal via structure 622 formed on the lower portion of the second interconnect layer dielectric layer 620, and a second metal line structure 628 formed on the upper portion of the second interconnect layer dielectric layer 620.

[0066] Each dielectric layer (601, 610, 620) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorocarbon, its porous variants, or combinations thereof. Each metal interconnect structure (612, 618, 622, 628) may include at least one conductive material, which may be a combination of a metal barrier liner (e.g., a metal nitride or metal carbide) and a metal filler material. Each metal barrier liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, their alloys, and / or combinations thereof. Other suitable metal barrier liner materials and metal filler materials are within the scope of the disclosure. In one embodiment, the first metal via structure 622 and the second metal wire structure 628 may be formed into an integrated circuit and via structure using a dual damascene process. The dielectric material layers (601, 610, 620) can also be referred to as the lower dielectric material layers (601, 610, 620). The metal interconnect structures (612, 618, 622, 628) formed within the lower dielectric material layers (601, 610, 620) are referred to herein as the lower metal interconnect structures (612, 618, 622, 628).

[0067] In one embodiment, the substrate 8 may include a monocrystalline silicon substrate, and a lower dielectric material layer (601, 610, 620) covering the lower metal interconnect structure (612, 618, 622, 628) may be located on the monocrystalline silicon substrate. A field-effect transistor 701, including a corresponding portion of the monocrystalline silicon substrate as a channel, may be embedded within the lower dielectric material layer (601, 610, 620). The field-effect transistor may then be electrically connected to at least one of the gate, source, and drain of one or more thin-film transistors subsequently formed.

[0068] Although this disclosure is described using one embodiment in which a semiconductor substrate is used as substrate 8, embodiments using an insulating substrate or a conductive substrate as substrate 8 are explicitly contemplated herein.

[0069] Transistors, such as thin-film transistors (TFTs), can be formed in subsequent process steps. The collection of all dielectric layers formed prior to the formation of the TFTs is collectively referred to herein as the lower dielectric material layers (601, 610, 620). The collection of all metal interconnect structures formed within the lower dielectric material layers (601, 610, 620) is referred to herein as the lower metal interconnect structures (612, 618, 622, 628). Typically, the lower metal interconnect structures (612, 618, 622, 628) are formed on a semiconductor material layer 9 in the substrate 8 and embedded within the lower dielectric material layers (601, 610, 620).

[0070] In one embodiment, a planar dielectric layer of uniform thickness may be formed on a lower dielectric material layer (601, 610, 620). This planar dielectric layer is referred to herein as an insulating material layer 635. The insulating material layer 635 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating material layer 635 may range from 30 nm to 300 nm; however, even smaller and larger thicknesses are possible.

[0071] An etch-block dielectric layer 636 may be selectively formed on an insulating material layer 635. The etch-block dielectric layer 636 includes an etch-block dielectric material that provides high etch resistance in a subsequent anisotropic etch process used to etch the dielectric material subsequently deposited on the etch-block dielectric layer 636. For example, the etch-block dielectric layer 636 may include silicon carbide nitride, silicon nitride, silicon oxynitride, or a dielectric metal oxide such as aluminum oxide. The thickness of the etch-block dielectric layer 636 may range from 3 nm to 40 nm, for example, 4 nm to 30 nm, but smaller and larger thicknesses are also possible.

[0072] Reference Figure 2A and Figure 2BThe figure illustrates various device regions (100, 200, 300, 400, 500, 600) that can be formed on the insulating material layer 635. Each device region (100, 200, 300, 400, 500, 600) may include a first device region 100, where a first thin-film transistor device will subsequently be formed; a second device region 200, where a second thin-film transistor device will subsequently be formed; a third device region 300, where a third thin-film transistor device will subsequently be formed; a fourth device region 400, where a fourth thin-film transistor device will subsequently be formed; a fifth device region 500, where a fifth thin-film transistor device will subsequently be formed; and a sixth device region 600, where a sixth thin-film transistor device will subsequently be formed. The six device regions (100, 200, 300, 400, 500, 600) used in this disclosure are exemplary and represent examples of thin-film transistor devices that can be formed according to embodiments of this disclosure. Therefore, it is not necessary to form all six device regions (100, 200, 300, 400, 500, 600). Typically, one or more device regions (100, 200, 300, 400, 500, 600) in the first exemplary structure can be arbitrarily selected for formation in the first exemplary structure.

[0073] According to one aspect of this disclosure, a sequence of material layers may be formed on an insulating material layer 635 and a selectively etch-blocking dielectric layer 636. The sequence of material layers may include, from bottom to top, a first conductive material layer 80L, a first hydrogen-containing dielectric layer 10, a second conductive material layer 80L, a first hydrogen-blocking dielectric layer 30, and a third conductive material layer 80L.

[0074] The first conductive material layer 80L, the second conductive material layer 80L, and the third conductive material layer 80L each comprise and / or are composed of at least one conductive material, which may each be at least one metallic material. In one embodiment, each group of at least one metallic material may comprise a bottom metal barrier liner 80A, a highly conductive metal layer 80B, and a top metal barrier liner 80C as shown in configuration A, or may be composed of a metal layer 80M as shown in configuration B. In embodiments where any conductive material layer 80L uses a stack of a bottom metal barrier liner 80A, a highly conductive metal layer 80B, and a top metal barrier liner 80C, the bottom metal barrier liner 80A and the top metal barrier liner 80C may comprise at least one conductive metal nitride material, such as TiN, TaN, WN, and / or MoN, and the highly conductive metal layer 80B may comprise metals such as Cu, Co, Ru, Mo, W, Ti, and Ta. In embodiments where each conductive material layer 80L is composed of a respective metal layer 80M, the material of the metal layer 80M is selected from heat-resistant metals such as W, Ta, Re, Nb and Mo, or metal nitride materials such as TiN, TaN, WN and / or MoN, so as to minimize the diffusion of metal elements to adjacent dielectric material layers (10, 30).

[0075] The thickness of each conductive material layer 80L can be independently selected from a range of 5 nanometers to 100 nanometers, for example from 10 nanometers to 50 nanometers, although smaller and larger thicknesses are also possible. The thicknesses of the conductive material layers 80L can be the same or different from each other. The conductive material layers 80L can be deposited by chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof.

[0076] The first hydrogen-containing dielectric layer 10 comprises a dielectric material in which the atomic concentration of hydrogen is greater than a first atomic concentration, which may be 100 parts per million (ppm), and preferably greater than 300 ppm, more preferably greater than 1000 ppm. Examples of dielectric materials with a hydrogen atomic concentration greater than 100 ppm include silicon nitride, hydrogenated silicon oxide, silicon oxycarbide, silicon oxynitride, undoped glass silicate, doped glass silicate, organosilicon glass, and hydrogenated alumina. According to one aspect of this disclosure, the hydrogen-barrier dielectric layer 30 may have a lower hydrogen content than the first hydrogen-containing dielectric layer 10. The atomic concentration of hydrogen atoms in the hydrogen-barrier dielectric layer 30 may be less than a second atomic concentration, which may be 30 ppm, and preferably less than 10 ppm, thereby effectively blocking the diffusion of hydrogen atoms.

[0077] Silicon nitride deposited by plasma-enhanced chemical vapor deposition can contain hydrogen atoms ranging from 400 ppm to 2,000 ppm. During the plasma-enhanced chemical vapor deposition process, hydrogen is incorporated into the silicon nitride material and bonds with silicon and nitrogen.

[0078] Hydrogenated silicon oxides, also known as hydrogenated silicate glasses, can contain hydrogen atoms ranging from 1000 ppm to 3000 ppm. They are formed by annealing in a hydrogen-containing environment followed by deposition of silicate glasses using a plasma-enhanced chemical vapor deposition process to decompose precursor materials such as tetraethyl orthosilicate (TEOS). The hydrogen atoms in the hydrogenated silicon oxide passivate the dangling bonds in the silicon oxide material.

[0079] Silicon oxycarbides and silicon oxynitrides may contain hydrogen atoms ranging from 1,000 ppm to 1,500 ppm and can be formed by plasma-enhanced chemical vapor deposition.

[0080] Undoped and doped silicate glasses may contain hydrogen at concentrations ranging from 100 ppm to 500 ppm. Undoped and doped silicate glasses can be formed by decomposing precursor gases such as tetraethyl orthosilicate (TEOS) in a plasma-enhanced chemical vapor deposition process. Doping gases such as diborane, phosphine, arsine, and / or fluorine can flow simultaneously with the precursor gas flow rate to deposit the doped silicate glass.

[0081] Organosilicon glass can contain hydrogen at concentrations ranging from 100 ppm to 300 ppm and can be formed by plasma-enhanced chemical vapor deposition. Other dielectric materials such as alumina can also be used, provided that the dielectric material can be hydrogenated to contain a high concentration of hydrogen atoms above 100 ppm.

[0082] The thickness of the first hydrogen-containing dielectric layer 10 can be in the range of 5 nm to 100 nm, for example, 10 nm to 50 nm, but smaller and larger thicknesses can also be used.

[0083] The first hydrogen-barrier dielectric layer 30 comprises a dielectric material that is substantially free of hydrogen atoms or contains a low atomic concentration of hydrogen atoms, such as below a second atomic concentration (which may be 30 ppm or lower, preferably 10 ppm or lower, more preferably 3 ppm or lower). Furthermore, the dielectric material of the first hydrogen-barrier dielectric layer 30 is selected from dielectric materials that can effectively block the diffusion of hydrogen atoms. Due to the small size and high diffusivity of hydrogen atoms, only a small fraction of dielectric materials can effectively block hydrogen atoms. Examples of such dielectric materials include alkaline earth metal oxides, such as magnesium oxide, calcium oxide, and strontium oxide. In one embodiment, the first hydrogen-barrier dielectric layer 30 comprises and / or is primarily composed of at least one alkaline earth metal oxide material. In one embodiment, the first hydrogen-barrier dielectric layer 30 is composed of magnesium oxide, calcium oxide, or alloys or stacks thereof.

[0084] The first hydrogen-barrier dielectric layer 30 can be deposited by pulsed layer deposition, wherein a high-power laser ablates a target containing source material; electron beam physical vapor deposition, wherein an electron beam evaporates a target containing source material; atomic layer deposition; or other deposition methods known in the art. The thickness of the first hydrogen-barrier dielectric layer 30 can be in the range of 5 nm to 100 nm, for example 10 nm to 50 nm, although smaller and larger thicknesses can also be used.

[0085] Reference Figure 3A and Figure 3B The first photoresist layer 71 can be applied to a stack of conductive material layer 80L, first hydrogen-containing dielectric layer 10, and first hydrogen-barrier dielectric layer 30. The first photoresist layer 71 can be patterned using photolithography to cover one or more of a first group of device regions (100, 200, 300, 400, 500, 600), but not cover one or more of a second group of device regions (100, 200, 300, 400, 500, 600) that are complementary to the first group. In the example, the first photoresist layer 71 can cover the first device region 100, the second device region 200, the third device region 300, and the fifth device region 500, but not the fourth device region 400 or the sixth device region 600. The first photoresist layer 71 can be used as an etching mask to perform an anisotropic etching process to etch portions of the uppermost conductive material layer 80L and the first hydrogen-barrier dielectric layer 30 that are not masked by the first photoresist layer 71. The final step of the anisotropic etching process can selectively etch the material of the first hydrogen-barrier dielectric layer 30, but not the material of the lower conductive material layer 80L. The first photoresist layer 71 can then be removed, for example, by ashing.

[0086] Reference Figure 4A and Figure 4BThe second hydrogen-containing dielectric layer 10 and the fourth conductive material layer 80L can be sequentially deposited on the underlying layer stack (80L, 10, 30). The second hydrogen-containing dielectric layer 10 can contain any material used in the first hydrogen-containing dielectric layer 10. The second hydrogen-containing dielectric layer 10 can have any thickness used in the first hydrogen-containing dielectric layer 10. The material composition of the second hydrogen-containing dielectric layer 10 can be the same as or different from that of the first hydrogen-containing dielectric layer 10. The thickness of the second hydrogen-containing dielectric layer 10 can be the same as or different from that of the first hydrogen-containing dielectric layer 10.

[0087] The fourth conductive material layer 80L may comprise any material that can be used in the first, second, and third conductive material layers 80L described above. The fourth conductive material layer 80L may have any thickness that can be used in the first, second, and third conductive material layers 80L. The material composition of the fourth conductive material layer 80L may be the same as or different from the material composition of any one of the first, second, and third conductive material layers 80L. The thickness of the fourth conductive material layer 80L may be the same as or different from the thickness of any one of the first, second, and third conductive material layers 80L.

[0088] Reference Figure 5A and Figure 5B The second photoresist layer 72 can be coated on a stack of conductive material layer 80L, hydrogen-containing dielectric layer 10, and first hydrogen-barrier dielectric layer 30. The second photoresist layer 72 can be patterned using photolithography to cover one or more of a third group of device regions (100, 200, 300, 400, 500, 600), but not one or more of a fourth group of device regions (100, 200, 300, 400, 500, 600), which is a complementary group to the third group. The selection of the third group can be independent of the composition of the first group described above. In the example shown, the second photoresist layer 72 can cover the first device region 100, the second device region 200, the fourth device region 400, the fifth device region 500, and the sixth device region 600, but not the third device region 300. The second photoresist layer 72 can be used as an etching mask to perform an anisotropic etching process to etch the unmasked portions of the uppermost conductive material layer 80L (fourth conductive material layer 80L) and the lower dielectric layer (e.g., the second hydrogen-containing dielectric layer 10). The final step of the anisotropic etching process can selectively etch the material of the second hydrogen-containing dielectric layer 10 without etching the material of the lower conductive material layer 80L (e.g., the third conductive material layer 80L). The second photoresist layer 72 can then be removed, for example, by ashing.

[0089] Reference Figure 6A and Figure 6BThe second hydrogen-barrier dielectric layer 30 and the fifth conductive material layer 80L can be sequentially deposited on the underlying layer stack (80L, 10, 30). The second hydrogen-barrier dielectric layer 30 can contain any material used in the first hydrogen-barrier dielectric layer 30. The second hydrogen-barrier dielectric layer 30 can have any thickness used in the first hydrogen-barrier dielectric layer 30. The material composition of the second hydrogen-barrier dielectric layer 30 can be the same as or different from that of the first hydrogen-barrier dielectric layer 30. The thickness of the second hydrogen-barrier dielectric layer 30 can be the same as or different from that of the first hydrogen-barrier dielectric layer 30.

[0090] The fifth conductive material layer 80L may comprise any material that can be used in the first, second, third, and fourth conductive material layers 80L described above. The fifth conductive material layer 80L may have any thickness that can be used in the first, second, third, and fourth conductive material layers 80L. The material composition of the fifth conductive material layer 80L may be the same as or different from the material composition of any of the first, second, third, and fourth conductive material layers 80L. The thickness of the fifth conductive material layer 80L may be the same as or different from the thickness of any of the first, second, third, and fourth conductive material layers 80L.

[0091] Reference Figure 7A and Figure 7B The third photoresist layer 73 can be coated on the stack of conductive material layer 80L, hydrogen-containing dielectric layer 10, and hydrogen-barrier dielectric layer 30. The third photoresist layer 73 can be patterned using photolithography to cover one or more of the fifth group in the device regions (300, 200, 300, 400, 500, 600), but not one or more of the sixth group in the device regions (300, 200, 300, 400, 500, 600), said sixth group being a complementary group to the fifth group. The selection of the fifth group can be independent of the composition of the third group and can be independent of the composition of the first group. In the example shown, the third photoresist layer 73 can cover the first device region 100, the third device region 300, the fourth device region 400, and the sixth device region 600, but not the second device region 200 or the fifth device region 500. A third photoresist layer 73 can be used as an etching mask to perform an anisotropic etching process to etch the unmasked portions of the uppermost conductive material layer 80L (the fifth conductive material layer 80L) and the lower dielectric layer (e.g., the second hydrogen barrier dielectric layer 30). The final step of the anisotropic etching process can selectively etch the material of the second hydrogen barrier dielectric layer 30 without etching the material of the lower conductive material layer 80L (e.g., the fourth or third conductive material layer 80L). The third photoresist layer 73 can then be removed, for example, by ashing.

[0092] Typically, vertical stacks (80L, 10, 30) are formed in each device region (100, 200, 300, 400, 500, 600). Each vertical stack (80L, 10, 30) includes, from bottom to top or from top to bottom, a first conductive material layer 80L, a first insulating material layer containing a hydrogen-containing dielectric material (e.g., hydrogen-containing dielectric layer 10), a second conductive material layer 80L, a second insulating material layer containing a hydrogen-blocking dielectric material (e.g., hydrogen-blocking dielectric layer 30), and a third conductive material layer 80L. One or more vertical stacks (80L, 10, 30) may also include at least one additional insulating material layer, which may include an additional hydrogen-containing dielectric layer 10 and / or an additional hydrogen-blocking dielectric layer 30. One or more vertical stacks (80L, 10, 30) may also include at least one conductive material layer 80L.

[0093] Each vertical stack (80L, 10, 30) in each device region (100, 200, 300, 400, 500, 600) may include a sequence of vertically alternating conductive material layers 80L and dielectric layers (10, 30). The types of dielectric layers (10, 30) in each vertical stack (80L, 10, 30) can be selected in any order. In other words, the implementation of the invention is not limited by the order of the types of dielectric layers (10, 30) in each vertical stack (80L, 10, 30). Typically, if (N+1) conductive material layers 80L and N dielectric layers (10, 30) are deposited and patterned, 2N–1 types of vertical stacks (80L, 10, 30) can be formed, such that each vertical stack (80L, 10, 30) includes one or more dielectric layers (10, 30) selected from the N dielectric layers (10, 30).

[0094] Reference Figure 8A and Figure 8B A patterned etch mask layer can be formed, and a patterning process can be performed to form a vertically extending via cavity 19. For example, a first photoresist layer 74 can be applied to the vertical stack (80L, 10, 30) and patterned using lithography to form discrete openings in the region where the vertical channel of the first thin-film transistor will subsequently form. The horizontal cross-sectional shape of the discrete openings in the first photoresist layer 74 can be circular, elliptical, rectangular, rounded rectangle, or any two-dimensional shape with a closed perimeter. A first anisotropic etching process can be performed to transfer the pattern of the discrete openings in the first photoresist layer 74 through a first subset of layers in the vertical stack (80L, 10, 30). The first photoresist layer 74 can then be removed, for example, by ashing. Alternatively, an ion beam etching process with a patterned hard mask layer can be used to form the vertically extending via cavity 19 instead of an anisotropic etching process.

[0095] In the illustrated example, a first anisotropic etching process transfers a pattern of discrete openings in the first photoresist layer 74 through two conductive material layers 80L and two dielectric layers (10, 30). Vertically extending via cavities 19 may be formed beneath each discrete opening in the first photoresist layer 74. A surface portion of the top surface of the conductive material layer 80L may be physically exposed beneath each vertically extending via cavity 19. The lateral dimension (e.g., diameter at the top) of each vertically extending via cavity 19 may range from 20 nm to 300 nm, for example from 30 nm to 100 nm, although smaller and larger lateral dimensions may also be used.

[0096] Reference Figure 9A and Figure 9B A patterned etch mask layer can be formed, and a patterning process can be performed to form additional vertically extending via cavities 19. For example, a second photoresist layer 75 can be applied to the vertical stack (80L, 10, 30) and can be patterned using photolithography to form discrete openings in the region where the vertical channel of the second thin-film transistor will subsequently form. The horizontal cross-sectional shape of the discrete openings in the second photoresist layer 75 can be circular, elliptical, rectangular, rounded rectangle, or any two-dimensional shape with a closed perimeter. A second anisotropic etching process can be performed to transfer the pattern of the discrete openings in the second photoresist layer 75 through a second subset layer in the vertical stack (80L, 10, 30). The second photoresist layer 75 can then be removed, for example, by ashing. Alternatively, an ion beam etching process with a patterned hard mask layer can be used to form the vertically extending via cavities 19 instead of an anisotropic etching process.

[0097] In the illustrated example, a second anisotropic etching process transfers the pattern of discrete openings in the second photoresist layer 75 through three conductive material layers 80L and three dielectric layers (10, 30). A vertically extending via 19 is formed beneath each discrete opening in the second photoresist layer 75. A surface portion of the top surface of the conductive material layer 80L is physically exposed beneath each vertically extending via 19. The lateral dimension (e.g., diameter at the top) of each vertically extending via 19 can range from 20 nm to 300 nm, for example from 30 nm to 100 nm, although smaller and larger lateral dimensions are also possible.

[0098] Reference Figure 10A and Figure 10BA patterned etch mask layer can be formed, and a patterning process can be performed to form additional vertically extending via cavities 19. For example, a third photoresist layer 76 can be coated on the vertical stack (80L, 10, 30) and can be patterned using photolithography to form discrete openings in the region where the vertical channel of the third thin-film transistor will subsequently form. The horizontal cross-sectional shape of the discrete openings in the third photoresist layer 76 can be circular, elliptical, rectangular, rounded rectangle, or any two-dimensional shape with a closed perimeter. A third anisotropic etching process can be performed to transfer the pattern of the discrete openings in the third photoresist layer 76 through a subset of the third layers in the vertical stack (80L, 10, 30). The third photoresist layer 76 can then be removed, for example, by ashing. Alternatively, an ion beam etching process using a patterned hard mask layer can be used to form the vertically extending via cavities 19 instead of anisotropic etching.

[0099] In the illustrated example, a third anisotropic etching process transfers the pattern of discrete openings in the third photoresist layer 76 through four conductive material layers 80L and four dielectric layers (10, 30). A vertically extending via cavities 19 are formed beneath each discrete opening in the third photoresist layer 76. A surface portion of the top surface of the conductive material layer 80L is physically exposed beneath each vertically extending via cavity 19. The lateral dimension (e.g., diameter at the top) of each vertically extending via cavity 19 can range from 20 nm to 300 nm, for example from 30 nm to 100 nm, although smaller and larger lateral dimensions are also possible.

[0100] Reference Figures 8A to 10B At least one anisotropic etching process can be performed to pattern vertical stacks (80L, 10, 30) using each etch mask (e.g., each patterned photoresist layer 74, 75, 76). Each anisotropic etching process forms at least one vertically extending via cavity 19 that passes through each vertical stack (80L, 10, 30) such that the at least one vertically extending via cavity 19 extends through at least one pair of conductive material layers 80L and dielectric layers (10, 30), the dielectric layers being either hydrogen-containing dielectric layer 10 or hydrogen-barrier dielectric layer 30.

[0101] A spatially extended surface sequence comprises vertically stacked surface segments (80L, 10, 30) that may be formed around each vertically extended via cavity 19. In one embodiment, the spatially extended surface sequence may include, from one end to the other, a first conductive surface (e.g., a sidewall of one of the conductive material layers 80L), a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10), a second conductive surface (e.g., a sidewall of another conductive material layer 80L), a second type of insulating surface (e.g., the surface of the hydrogen-barrier dielectric layer 30), and a third conductive surface (e.g., a sidewall of an additional conductive material layer 80L). The first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is the surface of the hydrogen-containing dielectric material containing a hydrogen atom concentration greater than a first atomic concentration, which, as described above, may be greater than 100 ppm. The second type of insulating surface (e.g., the surface of the hydrogen-barrier dielectric layer 30) is a hydrogen-impermeable surface of the hydrogen-barrier dielectric material.

[0102] In one embodiment, each vertical stack (80L, 10, 30) may be patterned such that each layer in the vertical stack (80L, 10, 30) has its own sidewall. In one embodiment, a first conductive surface is a sidewall of a first conductive material layer 80L; a second conductive surface is a sidewall of a second conductive material layer 80L; and a third conductive surface is a sidewall of a third conductive material layer 80L. The hydrogen-barrier dielectric layer 30 has a significantly lower hydrogen concentration than the hydrogen-containing dielectric layer 10 and prevents hydrogen atoms from diffusing through the layer. The atomic concentration of hydrogen atoms in the hydrogen-barrier dielectric layer 30 may be less than the second atomic concentration (which may be 30 ppm or less, and preferably 10 ppm or less, and more preferably 3 ppm or less).

[0103] In one embodiment, the first conductive surface, the second conductive surface, and the third conductive surface are mutually perpendicularly overlapping surface segments of the vertically extending via cavity 19. As used herein, multiple surfaces are considered to be mutually perpendicularly overlapping if they overlap vertically or lie in a vertical plane or substantially vertically. As used herein, a Euclidean plane having an angle of less than 10 degrees with respect to the vertical direction is considered substantially vertical.

[0104] Generally, a combination of a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) can be formed on the substrate 8. The first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is the surface of a hydrogen-containing dielectric material, wherein the concentration of hydrogen atoms is greater than a first atomic concentration (as described above, possibly at least 100 ppm), while the second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is a hydrogen-impermeable surface of a hydrogen-blocking dielectric material.

[0105] In one embodiment, a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is formed between a first conductive surface of a first conductive material portion (e.g., conductive material layer 80L) and a second conductive surface of a second conductive material portion (e.g., another conductive material layer 80L). A second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is formed between the second conductive surface and a third conductive surface of a third conductive material portion (e.g., another conductive material layer 80L).

[0106] In one embodiment, the first conductive material portion, the second conductive material portion, and the third conductive material portion 80 each include their respective source / drain. In other words, the conductive material layer 80L adjacent to the first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and the second type of insulating surface (e.g., the surface of the hydrogen-barrier dielectric layer 30) can constitute the source / drain of the subsequently formed thin-film transistor.

[0107] Reference Figure 11A and Figure 11B The amorphous metal oxide layer 20L can be compliantly deposited on a spatially extended sequence of surfaces, said surface sequence including at least a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30). In one embodiment, the amorphous metal oxide layer 20L can be compliantly deposited in each vertically extending via 19 and on the physically exposed top surface of the conductive material layer 80L. The amorphous metal oxide layer 20L can be deposited by physical vapor deposition, atomic layer deposition, or suitable alternative deposition processes. The thickness of the amorphous metal oxide layer 20L can range from 2 nm to 30 nm, for example, 3 nm to 10 nm, although smaller and larger thicknesses can also be used.

[0108] According to one aspect of this disclosure, the material of the amorphous metal oxide layer 20L is selected from materials whose conductivity type (i.e., p-type or n-type) can be modulated by the oxygen content therein. These materials include tin oxide and titanium oxide. In these embodiments, the n-type metal oxide material can be formed by promoting hydrogen diffusion from the hydrogen-containing dielectric layer to a portion of the amorphous metal oxide semiconductor layer. For example, in the case where the amorphous metal oxide layer includes tin oxide, the annealing process may be accompanied by a chemical reaction. This chemical process can be performed using SnO. x +δH2→SnO x-δ +H2O represents a value where x has a value greater than 1.0+δ and less than 2.0, and δ is in the range of 0.05 to 0.5.

[0109] Tin oxide (SnO) is a compound semiconductor material that, under appropriate conditions (which can be achieved by depositing amorphous tin oxide followed by a crystallization annealing process to obtain a crystalline form), can exhibit p-type conductivity. P-type conductivity means that the dominant charge carriers in the material are "holes," which are essentially places lacking electrons, allowing the movement of positive charges. The stoichiometry, or oxygen-to-tin ratio, plays a crucial role in determining the properties of tin oxide as a p-type semiconductor. The ideal stoichiometry for tin oxide with p-type conductivity is a 1:1 oxygen-to-tin ratio, corresponding to the stoichiometric composition of SnO. In its crystalline form, SnO has a tetragonal crystal structure, with each tin atom linearly coordinated to two oxygen atoms. This structure favors hole formation, which occurs when a tin atom has fewer than expected adjacent oxygen atoms, resulting in incomplete electron shells and the generation of holes.

[0110] Generally, the electrical properties of tin oxide materials are highly dependent on the atomic ratio of oxygen to tin (O:Sn). For p-type tin oxide semiconductors, the O:Sn value can range from 0.95 to 1.15. When O:Sn is within this range, tin vacancies create holes that act as charge carriers, resulting in p-type conductivity. Lower O:Sn values ​​below 0.95 lead to the formation of metallic tin. Higher values ​​above 1.15 result in the filling of oxygen vacancies, leading to a transformation into n-type tin oxide.

[0111] In detail, the conductivity of tin oxide materials varies with the atomic ratio of oxygen to tin, as described below. In stoichiometric tin oxide, the conductivity is around 10. -3 The baseline value is in the range of S / m to 0.1 S / m. This state corresponds to a relatively low hole density as charge carriers in stoichiometric tin oxide. The hole mobility in SnO is also generally lower than the electron mobility in SnO2. Substoichiometric tin oxide (SnO) with y values ​​in the range of 0.95 to 1.0... y In this context, tin oxide materials may still remain p-type semiconductors. As the y-value decreases from 1.0 to 0.95, and before the formation of metallic tin grains, the conductivity may increase with the number of holes until it becomes too non-stoichiometric and begins to lose its p-type properties. For materials with a SnO composition... x For tin oxide materials with x values ​​between 1.0 and 1.15, the conductivity initially decreases as the x value increases from 1.0 due to a decrease in hole density. When the x value further increases to a transition value of approximately 1.15, the tin oxide material changes its crystal structure phase, entering the tin dioxide phase, thus becoming an n-type tin oxide material with high conductivity provided by free electrons.

[0112] Typically, the conductivity of stoichiometric tin oxide (SnO) without any external doping is around 10. -3 Within the range of S / m to 0.1 S / m, although lower and higher conductivity can also be achieved by adjusting deposition conditions. In one embodiment, the amorphous metal oxide layer 20L comprises and / or is primarily composed of an amorphous tin oxide material having an atomic oxygen to tin ratio in the range of 0.95 to 1.15, and preferably in the range of 0.98 to 1.10. Therefore, where the crystallization of the amorphous tin oxide material is promoted by an annealing process performed at a high temperature, typically ranging from 200°C to 400°C, the annealing process causes the initially crystalline tin oxide material of the amorphous metal oxide layer 20L to transform into a crystalline form without changing the material composition. As a result of the annealing process, a p-type doped tin oxide material is obtained.

[0113] Titanium dioxide is a material whose conductivity type (either p-type or n-type) can be altered by adjusting the concentration of oxygen vacancies. Stoichiometric and near-stoichiometric titanium dioxide can behave as an n-type semiconductor. In other words, the majority of charge carriers in stoichiometric or near-stoichiometric titanium dioxide are electrons. Oxygen vacancies in titanium dioxide generally contribute to n-type conductivity because they act as electron donors. When oxygen atoms are removed as ions, free electrons are left behind, increasing the electron concentration and thus enhancing n-type conductivity.

[0114] Providing p-type conductivity in titanium dioxide can be achieved by introducing p-type dopant atoms. Nitrogen, fluorine, or boron atoms can be used as p-type dopants (i.e., acceptor dopants) for titanium dioxide. Therefore, when acceptor atoms are present in the titanium dioxide material at a sufficient atomic concentration, the titanium dioxide material can function as a p-type metal oxide semiconductor material.

[0115] Modulating the conductivity type in titanium dioxide can be achieved by providing a doped titanium dioxide material comprising a sufficiently high concentration of acceptor dopant, causing the doped titanium dioxide to exhibit p-type conductivity. n-type conductivity can be induced by increasing the oxygen vacancy concentration. A small increase in oxygen vacancy concentration maintains the p-type conductivity of the doped titanium dioxide, while a sufficient increase in oxygen vacancy concentration leads to n-type conductivity. Typically, oxygen vacancies act as electron donors because the removal of oxygen ions in a positively charged state leaves behind free electrons. A decrease in oxygen vacancies leads to a decrease in free electrons; therefore, the conductivity type of the doped titanium dioxide may shift to p-type conductivity.

[0116] Generally speaking, any amorphous metal oxide material can be used for amorphous metal oxide layer 20L, as long as the conductivity type of the amorphous metal oxide material can be switched between p-type and n-type according to the oxygen vacancy concentration through subsequent annealing of the amorphous metal oxide material.

[0117] Reference Figure 12A and Figure 12B The gate dielectric layer 50L can be deposited conformally on the amorphous metal oxide layer 20L. The gate dielectric layer 50L can include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, dielectric metal oxide (e.g., aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, etc.) or stacks thereof. In non-limiting illustrative embodiments, the gate dielectric layer 50L can include and / or can be substantially composed of at least one dielectric metal oxide material (e.g., aluminum oxide, hafnium oxide, titanium oxide, tantalum oxide, lanthanum oxide, hafnium silicate, etc.), silicon oxide, silicon nitride, ONO stack, or other gate dielectric materials known in the art. The gate dielectric layer 50L can be deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The thickness of the gate dielectric layer 50L can be in the range of 1 nm to 20 nm, for example, 5 nm to 10 nm, although smaller and larger thicknesses can also be used.

[0118] Reference Figure 13A and Figure 13B An annealing process can be performed to transform the amorphous metal oxide layer 20L into a crystalline metal oxide layer. The annealing process can be performed in an oxygen-free or oxygen-containing environment. Typically, the choice between an oxygen-containing and oxygen-free environment depends on whether additional oxygen needs to be supplied to the amorphous metal oxide layer 20L during crystallization to induce the formation of both types of metal oxide semiconductor materials. An oxygen-free environment can be used during the annealing process if the amorphous metal oxide layer 20L contains a sufficient concentration of oxygen atoms to crystallize into an n-type metal oxide semiconductor material. For example, a nitrogen-containing environment can be used in the annealing process. An oxygen-containing environment can be used during the annealing process if the concentration of oxygen atoms in the amorphous metal oxide layer 20L is insufficient to crystallize into an n-type metal oxide semiconductor material. For example, oxygen can be introduced into the process chamber during the annealing process. The temperature of the annealing process can range from 200 degrees Celsius to 400 degrees Celsius, although lower and higher temperatures can also be used. The duration of the annealing process at elevated temperatures can range from 1 minute to 120 minutes, although shorter and longer durations can also be used.

[0119] During the annealing process, the hydrogen-containing dielectric layer 10 acts as an oxygen absorbing layer, absorbing oxygen atoms from the adjacent portion of the amorphous metal oxide layer 20L. Therefore, a portion of the amorphous metal oxide layer 20L adjacent to the hydrogen-containing dielectric layer 10 loses oxygen atoms, gains excess free electrons, and transforms into an n-type metal oxide semiconductor layer 22 with n-type conductivity, i.e., containing free electrons as free charge carriers.

[0120] The hydrogen-blocking dielectric layer 30 acts as a hydrogen barrier, preventing hydrogen atoms from diffusing through it. The hydrogen-blocking dielectric layer 30 does not absorb any oxygen atoms from the amorphous metal oxide layer 20L. Therefore, the portion of the amorphous metal oxide layer 20L adjacent to the hydrogen-blocking dielectric layer 30 does not lose oxygen atoms and transforms into a p-type metal oxide semiconductor layer 21 with p-type conductivity, i.e., containing holes as free charge carriers. Typically, a pn junction can be formed at the interface between the p-type metal oxide semiconductor layer 21 and the n-type metal oxide semiconductor layer 22 of each contact pair.

[0121] In one embodiment, an oxidizing environment is used during the annealing process, and the partial pressure of oxygen atoms is controlled during the annealing process such that the number of oxygen atoms diffusing from the oxygen environment through the gate dielectric layer 50L into the amorphous metal oxide layer 20L is less than the number of oxygen atoms lost to the hydrogen-containing dielectric layer 10 in the portion of the amorphous metal oxide layer 20L adjacent to the hydrogen-containing dielectric layer 10. Therefore, the portion of the amorphous metal oxide layer 20L adjacent to the hydrogen-containing dielectric layer 10 loses enough oxygen atoms and transforms into an n-type metal oxide semiconductor layer 22 with n-type conductivity. Using an oxidizing environment during the annealing process generally helps to form a p-type metal oxide semiconductor layer 21 by reducing the oxygen vacancy concentration in the portion of the amorphous metal oxide layer 20L adjacent to the hydrogen-blocking dielectric layer 30.

[0122] Typically, during the annealing process at elevated temperatures, the hydrogen-containing dielectric layer 10 acts as an oxygen-absorbing layer, absorbing oxygen atoms from the adjacent portion of the amorphous metal oxide layer 20L. Therefore, the portion of the amorphous metal oxide layer 20L adjacent to the hydrogen-containing dielectric layer 10 loses oxygen atoms and thus gains excess free electrons during the transition from an amorphous to a crystalline state. This portion of the amorphous metal oxide layer 20L, having gained excess free electrons, is converted into an n-type metal oxide semiconductor layer 22, exhibiting n-type conductivity due to the presence of free electrons as charge carriers. In contrast, the hydrogen-blocking dielectric layer 30 acts as a hydrogen diffusion barrier layer, inhibiting the diffusion of hydrogen atoms through it. Therefore, the hydrogen-blocking dielectric layer 30 does not absorb any oxygen atoms from the amorphous metal oxide layer 20L. As a result, during the transition from an amorphous to a crystalline state during the annealing process, the portion of the amorphous metal oxide layer 20L adjacent to the hydrogen-blocking dielectric layer 30 retains oxygen atoms. This portion of the amorphous metal oxide layer 20L, retaining oxygen atoms, is converted into a p-type metal oxide semiconductor layer 21, exhibiting p-type conductivity due to the presence of holes as the primary charge carriers. Typically, during the annealing process, a first portion of the amorphous metal oxide layer 20L contacting a first type insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is converted to an n-type metal oxide semiconductor layer 22 due to the loss of oxygen to hydrogen atoms in the hydrogen-containing dielectric material. Around each vertically extending via 19, a second portion of the amorphous metal oxide layer 20L contacting a second type insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is converted to a p-type metal oxide semiconductor layer 21 during the annealing process. In one embodiment, the first portion of the amorphous metal oxide layer 20L converted to an n-type metal oxide semiconductor layer 22 may extend between a first conductive surface (e.g., the sidewall of the conductive material layer 80L) and a second conductive surface (e.g., the sidewall of another conductive material layer 80L); and the second portion of the amorphous metal oxide layer 20L converted to a p-type metal oxide semiconductor layer 21 may extend between a second conductive surface and a third conductive surface (e.g., the sidewall of an additional conductive material layer 80L). Each p-type metal-oxide-semiconductor layer 21 may include a channel of its respective n-type thin-film transistor; and each n-type metal-oxide-semiconductor layer 22 may include a channel of its respective n-channel thin-film transistor.

[0123] Reference Figure 14A and Figure 14B A gate material layer comprising at least one conductive gate material is deposited within each vertically extending via cavity 19. The at least one conductive gate material may include, for example, a metallic barrier liner material (such as TiN, TaN, and / or WN) and / or a metallic filler material (such as Cu, W, Mo, Co, Ru, etc.). The gate material layer may be deposited by chemical vapor deposition or physical vapor deposition. The gate material layer 55 may completely fill the remaining space of the vertically extending via cavity 19.

[0124] An etch mask layer (not shown) can be coated on the gate material layer and can be photolithographically patterned in a plan view, such as a top view, to cover the area surrounding the vertically extending via cavity 19. A reactive ion etching process or an ion beam etching process can be performed to etch the unmasked portions of the gate material layer. Each patterned portion of the gate material layer includes a gate 55, which may have a plug shape, a vertically extending portion located in each vertically extending cavity 19, and a head covering each vertically extending cavity 19 and having a lateral extent larger than the vertically extending portion. The etch mask layer can then be removed.

[0125] At least one vertical thin-film transistor group may be formed within each device region (100, 200, 300, 400, 500, 600). The type of thin-film transistors within each at least one vertical thin-film transistor group may vary depending on the device region (100, 200, 300, 400, 500, 600). In some device regions (100, 200, 300, 400, 500, 600), at least one vertical thin-film transistor group may include multiple vertical thin-film transistor groups. Each plurality of vertical thin-film transistor groups may be formed inside and around each vertical extension cavity 19. Each transistor includes a respective vertical semiconductor channel comprising a portion of each of a p-type metal-oxide-semiconductor layer 21 and an n-type metal-oxide-semiconductor layer 22. A pair of adjacent conductive material portions 80 serve as a pair of source / drain electrodes, i.e., a source and a drain. Each plurality of vertical thin-film transistor groups located inside and around each vertical extension cavity 19 share a common gate 55. The portion of the gate dielectric layer 50L between the common gate 55 and the sidewall of the vertical extension cavity 19 constitutes the common gate dielectric for multiple vertical thin-film transistor groups.

[0126] Reference Figure 15A and Figure 15B A series of patterning processes can be performed to electrically isolate at least one pair of laterally adjacent vertical thin-film transistors. For example, a combination of photolithography masking and etching processes can be used to pattern each conductive material layer 80L that is in direct contact with any p-type MOSFET layer 21 and n-type MOSFET layer 22, unless electrical connections between electrical nodes of adjacent vertical field-effect transistors at the same level are desired to provide circuit connectivity. Thus, at least one pair of vertical thin-film transistors located inside and around each vertically extending via cavity 19 can be electrically isolated from each other unless lateral electrical connections between adjacent pairs of vertical thin-film transistors are desired.

[0127] Each patterned portion of the conductive material layer 80L includes a conductive material portion 80, which serves as a source / drain. Each source / drain can function as either a source or a drain depending on the electrical bias conditions used to operate the corresponding thin-film transistor. In each device region (100, 200, 300, 400, 500, 600), various types of series connection of vertical thin-film transistors sharing a common gate 55 can be formed. For example, the first device region 100 may include a first n-channel thin-film transistor, a first p-channel thin-film transistor, a second n-channel thin-film transistor, and a second p-channel thin-film transistor connected in series from bottom to top. The second device region 200 may include a first n-channel thin-film transistor, a p-channel thin-film transistor, and a second n-channel thin-film transistor connected in series from bottom to top. The third device region 300 may include an n-channel thin-film transistor, a first p-channel thin-film transistor, and a second p-channel thin-film transistor connected in series from bottom to top. The fourth device region 400 may include a first n-channel thin-film transistor, a second n-channel thin-film transistor, and a p-channel thin-film transistor connected in series from bottom to top. The fifth device region 500 may include p-channel and n-channel thin-film transistors connected in series from bottom to top. The sixth device region 600 may include n-channel and p-channel thin-film transistors connected in series from bottom to top. The stack of thin-film transistors in the fifth and sixth device regions 500 can serve as an inverter circuit. The function of an inverter circuit is well known in the art.

[0128] Generally, embodiments utilizing this disclosure can form any sequence of p-channel and n-channel thin-film transistors connected in series. Alternatively, a single thin-film transistor can be formed using a vertically extending via cavity that extends only between a pair of vertically adjacent conductive material layers 80L. Such variations are explicitly considered herein.

[0129] Reference Figure 16A and Figure 16B The contact dielectric layer 90 can be deposited on the vertical stack of the vertical thin-film transistors. Various contact cavities can be formed in the contact dielectric layer 90, located above the conductive structure embodying the electrical nodes of the vertical thin-film transistors. Various contact hole structures (98, 95) can be formed in various contact hole cavities. The various contact hole structures (98, 95) may include: source / drain contact hole structures 98 contacting respective conductive material portions 80 (which serve as source / drain), and gate contact hole structures 95 contacting respective gates 55.

[0130] Reference Figure 17A and Figure 17B An exemplary layout of a contact hole structure (98, 95) in the second device region 200 that contacts an electrical node in a vertical stack of vertical thin-film transistors is shown. Figure 17A and Figure 17BThe section X-X' in the middle corresponds to Figure 16A A cross-section of the vertical stack of thin-film transistors in the second device region 200. For illustrative purposes, in Figure 16A , Figure 17A and Figure 17B In the second device region 200, the conductive material portions 80 in the vertical thin-film transistor are labeled with reference numbers 81, 82, 83, and 84 from top to bottom. In other words, the conductive material portions 80 in the vertical thin-film transistor in the second device region 200 include, from top to bottom, a top conductive material layer 80L, a second top conductive material layer 82, a third top conductive material layer 83, and a bottom conductive material layer 84. Typically, each conductive material portion 80 in the vertical thin-film transistor can be patterned to form a respective contact hole structure for electrically connecting the respective conductive material portion 80.

[0131] Reference Figures 1 to 17B The semiconductor structure includes: a pn junction located at the interface between a p-type metal oxide semiconductor layer 21 and an n-type metal oxide semiconductor layer 22; a hydrogen-containing dielectric material portion having a hydrogen atom concentration greater than a first atomic concentration (as described above, it can be at least 100 ppm) and having a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) contacting the n-type metal oxide semiconductor layer 22; and a hydrogen-blocking dielectric material portion including a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) contacting the p-type metal oxide semiconductor layer 21, wherein the second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is a hydrogen-impermeable surface.

[0132] In one embodiment, the semiconductor structure further includes: a first conductive material portion 80 contacting a first portion of the p-type metal-oxide-semiconductor layer 21; a second conductive material portion 80 contacting a second portion of the p-type metal-oxide-semiconductor layer 21 and a first portion of the n-type metal-oxide-semiconductor layer 22; and a third conductive material portion 80 contacting a second portion of the n-type metal-oxide-semiconductor layer 22. In one embodiment, the first conductive material portion 80, the second conductive material portion 80, and the third conductive material portion 80 comprise three conductive material layers 80L that are perpendicularly spaced from each other in a direction perpendicular to the top surface of the substrate 8.

[0133] In one embodiment, the p-type metal-oxide-semiconductor layer 21 includes a channel of a p-channel thin-film transistor; the n-type metal-oxide-semiconductor layer 22 includes a channel of an n-channel thin-film transistor; and the first conductive material portion 80, the second conductive material portion 80, and the third conductive material portion 80 include source / drain electrodes 80 of the n-type thin-film transistor and the n-channel thin-film transistor combination. In one embodiment, the semiconductor structure includes at least one gate structure (50, 55), which includes a respective gate dielectric layer 50 and a respective gate electrode, wherein the p-type metal-oxide-semiconductor layer 21 and the n-type metal-oxide-semiconductor layer 22 are each in contact with the at least one gate structure (50, 55).

[0134] Reference Figure 18 According to one embodiment of this disclosure, a region of a second exemplary structure is shown. The second exemplary structure can be achieved by forming a hydrogen-containing dielectric layer 10 on the top surface of the etch-block dielectric layer 636, thereby... Figure 1 The first exemplary structure shown is derived from this one. The second exemplary structure may include a p-channel transistor region 700, where a p-channel thin-film transistor will subsequently be formed, and an n-channel transistor region 800, where an n-channel thin-film transistor will subsequently be formed. The hydrogen-containing dielectric layer 10 in the second exemplary structure may have any material composition as described with reference to the hydrogen-containing dielectric layer 10 in the first exemplary structure. The thickness of the hydrogen-containing dielectric layer 10 in the second exemplary structure may be in the range of 50 nm to 500 nm, for example from 100 nm to 300 nm, although smaller and larger thicknesses may also be used.

[0135] Reference Figure 19 The recessed region 29 can be selectively formed by vertically recessing the upper portion of the hydrogen-containing dielectric layer 10. The recessed area of ​​the upper portion of the hydrogen-containing dielectric layer 10 corresponds to the region where a p-type metal-oxide-semiconductor layer will subsequently be formed. For example, the recessed region 29 may be formed around the central region of the p-channel transistor region 700, but not around the central region of the n-channel transistor region 800. One of the recessed regions 29 may be formed in the peripheral region of the n-channel transistor region 800.

[0136] In one embodiment, a photoresist layer (not shown) may be applied to the top surface of the hydrogen-containing dielectric layer 10 and may be patterned using lithography to form openings in the region where a p-type metal-oxide-semiconductor layer is desired to form. An etching process may be performed to vertically etch down the unmasked portions of the hydrogen-containing dielectric layer 10. A wet etching process or a reactive ion etching process may be performed. The recess depth of the recessed region 29 may be in the range of 5 nm to 100 nm, for example, 10 nm to 50 nm, although smaller and larger recess depths may also be used. The photoresist layer may then be removed, for example, by ashing.

[0137] Reference Figure 20Hydrogen-blocking dielectric material may be deposited in the recessed region 29. The hydrogen-blocking dielectric material may include any hydrogen-blocking dielectric material that can be used in the hydrogen-blocking dielectric layer 30 in the first exemplary structure. The thickness of the hydrogen-blocking dielectric material may be approximately equal to or greater than the recess depth of the recessed region 29. Excess portions of the hydrogen-blocking dielectric material may be removed from outside the region of the recessed region 29. For example, a patterned photoresist layer may be formed to cover portions of the hydrogen-blocking dielectric material located within the region of the recessed region 29. Portions of the hydrogen-blocking dielectric material located outside the region of the recessed region 29 may be removed by performing an etching process. The photoresist layer may then be removed, for example, by ashing. Alternatively, excess portions of the hydrogen-blocking dielectric material may be removed from outside the region of the recessed region 29 by performing a planarization process. In this embodiment, the planarization process may include a chemical mechanical polishing process.

[0138] A hydrogen-blocking dielectric layer 30 may be formed in each recessed region 29. The hydrogen-blocking dielectric layer 30 in the second exemplary structure may have the same material composition as any hydrogen-blocking dielectric layer 30 that may be used in the first exemplary structure. To reiterate, each hydrogen-blocking dielectric layer 30 of this disclosure may comprise a dielectric material that is substantially free of hydrogen atoms, or contain hydrogen atoms at a low atomic concentration, such as below a second atomic concentration (which may be 30 ppm or less, preferably 10 ppm or less, more preferably 3 ppm or less). Furthermore, the dielectric material of the hydrogen-blocking dielectric layer 30 is selected from dielectric materials that effectively block the diffusion of hydrogen atoms. Examples of such dielectric materials include alkaline earth metal oxides, such as magnesium oxide, calcium oxide, and strontium oxide. In one embodiment, the hydrogen-blocking dielectric layer 30 comprises and / or is substantially composed of at least one alkaline earth metal oxide material. In one embodiment, the hydrogen-blocking dielectric layer 30 is composed of magnesium oxide, calcium oxide, or alloys or stacks thereof. The thickness of the hydrogen barrier dielectric layer 30 can range from 5 nm to 100 nm, for example from 10 nm to 50 nm, although smaller and larger recess depths can also be used. The top surface of the hydrogen barrier dielectric layer 30 can be coplanar with the horizontal plane including the top surface of the hydrogen-containing dielectric layer 10, and can protrude above the horizontal plane or be recessed below the horizontal plane.

[0139] A combination of a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) can be formed. The first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) includes the remaining portion of the top surface of the hydrogen-containing dielectric layer 10. The second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) includes a portion of the top surface of the hydrogen-blocking dielectric material, i.e., the top surface of the hydrogen-blocking dielectric layer 30.

[0140] Generally, a combination of a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) can be formed on the substrate 8. The first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is the surface of a hydrogen-containing dielectric material, wherein the concentration of hydrogen atoms is greater than a first atomic concentration (as described above, possibly at least 100 ppm), while the second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is a hydrogen-impermeable surface of a hydrogen-blocking dielectric material.

[0141] Reference Figure 21 A photoresist layer (not shown) may be applied to a combination of an insulating layer (e.g., hydrogen-containing dielectric layer 10) and a portion of a hydrogen-barrier dielectric material (e.g., hydrogen-barrier dielectric layer 30). The photoresist layer may be patterned using lithography to form a pair of elongated openings in each region, wherein the source / drain electrodes of the thin-film transistor will subsequently be formed. Adjacent pairs of elongated openings may be laterally spaced by their respective uniform lateral spacing, which is the channel length of the respective thin-film transistor to be formed subsequently. The channel length may be in the range of 5 nm to 300 nm, for example, 10 nm to 50 nm, although smaller and larger channel lengths may also be used. In one embodiment, the elongated openings in the photoresist layer may be formed on a subset of the non-horizontal boundary between the hydrogen-containing dielectric layer 10 and the hydrogen-barrier dielectric layer 30.

[0142] An anisotropic etching process can be performed to transfer the pattern of the extended openings through the dielectric layer 10. The source / drain cavity 79 can be formed by a combination of the hydrogen-containing dielectric layer 10 and the hydrogen-barrier dielectric layer 30 beneath the extended openings in the photoresist layer. In one embodiment, a surface portion of the top surface of the etched barrier dielectric layer 636 can be physically exposed beneath each source / drain cavity 79. Typically, the depth of the source / drain cavity 79 can be the same as or less than the maximum thickness of the hydrogen-containing dielectric layer 10. The photoresist layer can then be removed, for example, by ashing.

[0143] At least one conductive material, such as at least one metallic material, may be deposited in the source / drain cavity 79 and on the combination of the hydrogen-containing dielectric layer 10 and the hydrogen-blocking dielectric layer 30. The at least one conductive material may include a metal barrier liner comprising a metal barrier liner material and a metal filler layer comprising a metal filler material. The metal barrier liner material may include conductive metal nitrides or conductive metal carbides, such as TiN, TaN, WN, TiC, TaC, and / or WC. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, their alloys, and / or combinations thereof.

[0144] A portion of the at least one metallic material may be removed from the outside of the source / drain cavity 79 by a planarization process, which may employ chemical mechanical polishing (CMP) and / or recess etching. Each remaining portion of the at least one conductive material filling the source / drain cavity constitutes a conductive material portion 80, which is a source / drain electrode. In one embodiment, each source / drain electrode 80 may include a metallic barrier liner 80A, which is the remaining portion of the metallic barrier liner material, and a metallic filler portion 80F, which is the remaining portion of the metallic filler material.

[0145] Typically, a spatially extended surface sequence can be formed. This spatially extended surface sequence can be arranged horizontally and can sequentially include, from one end to the other, a first conductive surface, a first type of insulating surface (e.g., the surface of hydrogen-containing dielectric layer 10), a second conductive surface, a second type of insulating surface (e.g., the surface of hydrogen-blocking dielectric layer 30), and a third conductive surface. The first type of insulating surface (e.g., the surface of hydrogen-containing dielectric layer 10) is the surface of a hydrogen-containing dielectric material containing hydrogen atoms at a concentration greater than a first atomic concentration (as described above, at least 100 ppm), and the second type of insulating surface (e.g., the surface of hydrogen-blocking dielectric layer 30) is a hydrogen-impermeable surface of the hydrogen-blocking dielectric material.

[0146] In one embodiment, a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is formed between the first conductive surface of the first conductive material portion 80 and the second conductive surface of the second conductive material portion 80. In another embodiment, a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is formed between the second conductive surface and the third conductive surface of the third conductive material portion 80. The conductive material portions can be formed by filling the source / drain cavity 79 with at least one conductive material. The first conductive material portion 80, the second conductive material portion 80, and the third conductive material portion 80 may include corresponding portions of at least one conductive material filling the respective cavities in the source / drain cavity 79. In one embodiment, the first conductive material portion 80, the second conductive material portion 80, and the third conductive material portion 80 each include a corresponding source / drain electrode 80 of a subsequently formed thin-film transistor.

[0147] Reference Figure 23 Executable reference Figure 11A and Figure 11B The processing steps described herein are for depositing an amorphous metal oxide layer 20L. The material composition and thickness range of the amorphous metal oxide layer 20L in the second exemplary structure may be the same as those in the first exemplary structure. The amorphous metal oxide layer 20L in the second exemplary structure does not need to conform to the deposition process because the amorphous metal oxide layer 20L is formed on a plane.

[0148] Reference Figure 12A and Figure 12B The aforementioned process steps can be used to form the gate dielectric layer 50L. In the second exemplary structure, the material composition and thickness range of the gate dielectric layer 50L may be the same as those of the gate dielectric layer 50L in the first exemplary structure.

[0149] Reference Figure 24 Executable reference Figure 13A and Figure 13B The annealing process described herein transforms the amorphous metal oxide layer 20L into a combination of a p-type metal oxide semiconductor layer 21 and an n-type metal oxide semiconductor layer 22. In this process step, the annealing process conditions can be referenced. Figure 13A and Figure 13B The annealing process conditions are the same.

[0150] During the annealing process at elevated temperatures, the first portion of the amorphous metal oxide layer 20L that contacts a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) transforms into an n-type metal oxide semiconductor layer 22 due to the loss of oxygen by hydrogen atoms into the hydrogen-containing dielectric material in the hydrogen-containing dielectric layer 10 during the annealing process. The second portion of the amorphous metal oxide layer 20L that contacts a second type of insulating surface (e.g., the surface of the hydrogen-barrier dielectric layer 30) transforms into a p-type metal oxide semiconductor layer 21 during the annealing process.

[0151] In one embodiment, a first portion of the amorphous metal oxide layer 20L is converted into an n-type metal oxide semiconductor layer 22, the first portion extending between a first conductive surface (e.g., the top surface of the first conductive material portion 80) and a second conductive surface (e.g., the top surface of the second conductive material portion 80); and a second portion of the amorphous metal oxide layer 20L is converted into a p-type metal oxide semiconductor layer 21, the second portion extending between a second conductive surface and a third conductive surface (e.g., the top surface of the third conductive material portion 80). In one embodiment, the p-type metal oxide semiconductor layer 21 includes channels of p-channel thin-film transistors, and the n-type metal oxide semiconductor layer 22 includes channels of n-channel thin-film transistors.

[0152] Typically, the conductivity type of the crystalline portion of the amorphous metal oxide layer 20L is determined by whether or not it is in contact with the hydrogen-blocking dielectric layer 30 at or around the crystalline portion. Each crystalline portion of the amorphous metal oxide layer 20L in contact with the hydrogen-containing dielectric layer 10 transforms into an n-type metal oxide semiconductor layer 22 due to the loss of oxygen atoms and the accumulation of free electrons. Each crystalline portion of the amorphous metal oxide layer 20L in contact with the hydrogen-blocking dielectric layer 30 transforms into a p-type metal oxide semiconductor layer 21. A portion of the crystalline portion of the amorphous metal oxide layer 20L that is not in contact with either the hydrogen-containing dielectric layer 10 or the hydrogen-blocking dielectric layer 30 may transform into a portion of either the n-type metal oxide semiconductor layer 22 or the p-type metal oxide semiconductor layer 21, depending on the relative proximity of the hydrogen-containing dielectric layer 10 and the hydrogen-blocking dielectric layer 30.

[0153] In one embodiment, the top surface of the conductive material portion 80 is located between a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30), and a pn junction may be formed on the top surface of the conductive material portion 80.

[0154] Reference Figure 25 A gate electrode material layer 55L may be deposited on the gate dielectric layer 50L. The gate electrode material layer 55L comprises at least one conductive gate electrode material. The at least one conductive gate electrode material may include, for example, a metal barrier substrate material (such as TiN, TaN, and / or WN) and a metal filler material (such as Cu, W, Mo, Co, Ru, etc.). The gate electrode material layer 55L may be deposited by chemical vapor deposition or physical vapor deposition. The thickness of the gate electrode material layer 55L may range from 20 nm to 200 nm, although smaller and larger thicknesses are also possible.

[0155] Reference Figure 26 The gate electrode material layer 55L and the gate dielectric layer 50L can be patterned to form gate structures (50, 55). Each gate structure (50, 55) may include a combination of a gate dielectric layer 50 and a gate electrode 55. Each gate dielectric layer 50 is a patterned portion of the gate dielectric layer 50L. Each gate electrode 55 is a patterned portion of the gate electrode material layer 55L. Each gate structure (50, 55) may extend laterally between an adjacent pair of conductive material portions 80, which are source / drain electrodes. In one embodiment, the gate dielectric layer 50 may contact the top edge of the pn junction between an adjacent pair of p-type metal-oxide-semiconductor layers 21 and n-type metal-oxide-semiconductor layers 22.

[0156] A p-channel thin-film transistor is formed in a p-channel transistor region 700, and an n-channel thin-film transistor is formed in an n-channel transistor region 800. A continuous group of at least one p-type metal-oxide-semiconductor layer 21 and at least one n-type metal-oxide-semiconductor layer 22 is formed. In some embodiments, one or more conductive material portions 80 (which are source / drain electrodes) may contact a pn junction between adjacent pairs of p-type metal-oxide-semiconductor layers 21 and n-type metal-oxide-semiconductor layers 22. The continuous group of at least one p-type metal-oxide-semiconductor layer 21 and at least one n-type metal-oxide-semiconductor layer 22 may be optically patterned to provide electrical isolation from adjacent thin-film transistor pairs. Furthermore, for adjacent thin-film transistor pairs where electrical connection between source / drain electrodes is desired, a common source / drain electrode (including conductive material portions 80) may be used. In this embodiment, the combination of p-type metal-oxide-semiconductor layers 21 and n-type metal-oxide-semiconductor layers 22, having a pn junction therebetween, can be used to form a series connection of an n-channel thin-film transistor and a p-channel thin-film transistor. The pn junction may contact the top surface of the common source / drain electrode.

[0157] Reference Figure 27 The contact dielectric layer 90 may be deposited on the thin-film transistor. Multiple contact cavities may be formed above the contact dielectric layer 90, located on the conductive structure constituting the electrical node of the thin-film transistor. Multiple contact hole structures may be formed in multiple contact cavities. The multiple contact hole structures may include source / drain contact hole structures (not shown) that contact their respective electrically conductive material portions 80 (which serve as source / drain electrodes), and gate contact hole structures 95 that contact their respective gate electrodes 55.

[0158] Reference Figure 28 According to one embodiment of this disclosure, an alternative configuration of a second exemplary structure is shown. This alternative configuration illustrates an embodiment in which the gate dielectric layer 50 and the gate electrode 55 are shared between adjacent pairs of n-channel and p-channel thin-film transistors. This configuration embodies an inverter circuit whose function is well known in the art.

[0159] According to various embodiments of this disclosure, reference is made to Figure 1 and Figures 18 to 28A semiconductor structure is provided. The semiconductor structure includes: a pn junction located at the interface between a p-type metal oxide semiconductor layer 21 and an n-type metal oxide semiconductor layer 22; a hydrogen-containing dielectric material portion containing a hydrogen atom concentration greater than a first atomic concentration (as described above, it can be at least 100 ppm) and having a first type of insulating surface (e.g., the surface of a hydrogen-containing dielectric layer 10) in contact with the n-type metal oxide semiconductor layer 22; and a hydrogen-blocking dielectric material portion including a second type of insulating surface (e.g., the surface of a hydrogen-blocking dielectric layer 30) in contact with the p-type metal oxide semiconductor layer 21, wherein the second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is a hydrogen-impermeable surface.

[0160] In one embodiment, the semiconductor structure includes: a first conductive material portion 80 contacting a first portion of a p-type metal-oxide-semiconductor layer 21; a second conductive material portion 80 contacting a second portion of the p-type metal-oxide-semiconductor layer 21 and a first portion of an n-type metal-oxide-semiconductor layer 22; and a third conductive material portion 80 contacting a second portion of the n-type metal-oxide-semiconductor layer 22. In one embodiment, the first conductive material portion 80, the second conductive material portion 80, and the third conductive material portion 80 comprise three conductive material portions 80, which are laterally spaced from each other in a horizontal direction parallel to the top surface of the substrate 8.

[0161] In one embodiment, the p-type metal-oxide-semiconductor layer 21 includes a channel of a p-channel thin-film transistor; the n-type metal-oxide-semiconductor layer 22 includes a channel of an n-channel thin-film transistor; and the first conductive material portion 80, the second conductive material portion 80, and the third conductive material portion 80 include source / drain electrodes 80 of the n-type thin-film transistor and the n-channel thin-film transistor combination. In one embodiment, the semiconductor structure includes at least one gate structure (50, 55), including a respective gate dielectric layer 50 and a respective gate 55. The p-type metal-oxide-semiconductor layer 21 and the n-type metal-oxide-semiconductor layer 22 are each in contact with the at least one gate structure (50, 55).

[0162] Reference Figure 29 The illustration shows a region of a third exemplary structure according to an embodiment of the present disclosure. The third exemplary structure may be derived from the first exemplary structure by forming a dielectric substrate layer 108 on an etch-block dielectric layer 636. The dielectric substrate layer 108 may contain any material that can be used with reference to the hydrogen-containing dielectric layer 10 described with reference to the first exemplary structure. In one embodiment, the dielectric substrate layer 108 may contain undoped silicate glass or doped silicate glass. The thickness of the dielectric substrate layer 108 may range from 100 nm to 400 nm, although smaller and larger thicknesses may also be used.

[0163] A third exemplary structure may include an n-channel transistor region 800 and a p-channel transistor region 700. A gate cavity is formed in each of the n-channel transistor region 800 and the p-channel transistor region 700. The gate cavity is then filled with at least one gate electrode material to form a gate electrode 55. In one embodiment, the at least one gate electrode material may include a metal barrier liner material (e.g., TiN, TaN, and / or WN) and a metal filler material (e.g., Cu, W, Mo, Co, Ru, etc.). Excess portions of the at least one gate electrode material are removed from a horizontal plane including the top surface of the dielectric substrate layer 108 using a planarization process. The planarization process may include a chemical mechanical polishing process and / or a trench etching process. Each continuous portion of the at least one gate electrode material filling the respective gate cavity constitutes a gate electrode 55. In one embodiment, each gate electrode 55 may include a gate electrode liner 53 consisting of the remaining portion of the metal barrier liner material and a gate electrode filler material portion 54 consisting of the remaining portion of the metal filler material. The top surface of the gate electrode 55 may be formed in a horizontal plane including the top surface of the dielectric substrate layer 108. In one embodiment, the first gate 55 and the second gate 55 are respectively embedded in the dielectric substrate layer 108 in the n-channel transistor region 800 and the p-channel transistor region 700 above the substrate 8.

[0164] Reference Figure 30 A first gate dielectric component layer 51 and a second gate dielectric component layer 52 may be deposited. The first gate dielectric component layer 51 may comprise silicon dioxide, aluminum oxide, or a transition metal oxide, and its thickness may be in the range of 1 nm to 6 nm, for example, 1.5 nm to 3 nm. According to one embodiment of the present disclosure, the second gate dielectric component layer 52 comprises a hydrogen barrier dielectric layer 30.

[0165] The hydrogen-barrier dielectric layer 30 in the third exemplary structure can have any material composition that can be used in the hydrogen-barrier dielectric layer 30 in the first exemplary structure. Therefore, the hydrogen-barrier dielectric layer 30 comprises a dielectric material that is substantially free of hydrogen atoms, or contains hydrogen atoms at a low atomic concentration, such as below a second atomic concentration (which may be 30 ppm or less, and preferably 10 ppm or less, and more preferably 3 ppm or less). Furthermore, the dielectric material of the hydrogen-barrier dielectric layer 30 is selected from dielectric materials that can effectively block the diffusion of hydrogen atoms. Examples of such dielectric materials include alkaline earth metal oxides, such as magnesium oxide, calcium oxide, and strontium oxide. In one embodiment, the hydrogen-barrier dielectric layer 30 comprises and / or is primarily composed of at least one alkaline earth metal oxide material. In one embodiment, the hydrogen-barrier dielectric layer 30 is composed of magnesium oxide, calcium oxide, or alloys or stacks thereof. The thickness of the hydrogen-barrier dielectric layer 30 can range from 1 nm to 6 nm, for example, 1.5 nm to 3 nm, although smaller and larger thicknesses are also possible.

[0166] Reference Figure 31 A first photoresist layer 57 may be applied onto the second gate dielectric component layer 52 (i.e., the hydrogen barrier dielectric layer 30) and may be patterned using lithography to cover the p-channel transistor region 700 but not the n-channel transistor region 800. A selective etching process may be performed to etch the material of the hydrogen barrier dielectric layer 30 without etching the material of the first gate dielectric component layer 51. The selective etching process removes the unmasked portions of the second gate dielectric component layer 52 (i.e., the hydrogen barrier dielectric layer 30). The first photoresist layer 57 may then be removed, for example, by ashing.

[0167] Reference Figure 32 The hydrogen-containing dielectric layer 10 can be deposited as a third gate dielectric component layer. The hydrogen-containing dielectric layer 10 can contain any material suitable as a gate dielectric material, selected from the hydrogen-containing dielectric materials discussed in the first exemplary structure. For example, the hydrogen-containing dielectric layer 10 in the third exemplary structure can contain silicon dioxide, or a dielectric metal oxide material deposited in a hydrogen-containing environment or deposited using a hydrogen-containing precursor gas. The thickness of the hydrogen-containing dielectric layer 10 can range from 1 nm to 6 nm, for example, 1.5 nm to 3 nm, although smaller and larger thicknesses are also possible.

[0168] Reference Figure 33 The second photoresist layer 59 can be applied to the hydrogen-containing dielectric layer 10 and can be patterned using lithography to cover the n-channel transistor region 800 but not the p-channel transistor region 700. A selective etching process can be performed to etch the material of the hydrogen-containing dielectric layer 10 without etching the material of the hydrogen-blocking dielectric layer 30. The unmasked portions of the hydrogen-containing dielectric layer 10 are removed by the selective etching process. The second photoresist layer 59 can then be removed, for example, by ashing.

[0169] After removing the second photoresist layer 59, a combination of a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is formed on the substrate 8. The first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is the surface of the hydrogen-containing dielectric material, wherein the concentration of hydrogen atoms is greater than the first atomic concentration (as described above, possibly at least 100 ppm), while the second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is the hydrogen-free surface of the hydrogen-blocking dielectric material.

[0170] The portion of the first gate dielectric component layer 51 in the n-channel transistor region 800, combined with the hydrogen-containing dielectric layer 10, comprises a first type gate dielectric 50A. The first type gate dielectric 50A is formed on a first gate 55 located in the n-channel transistor region 800. The portion of the first gate dielectric component layer 51 in the p-channel transistor region 700, combined with the hydrogen-blocking dielectric layer 30, comprises a second type gate dielectric 50B. The second type gate dielectric 50B is formed on a second gate 55 located in the p-channel transistor region 700. In one embodiment, a first type insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is the top surface of the first type gate dielectric 50A, and a second type insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is the top surface of the second type gate dielectric 50B.

[0171] Reference Figure 34 Executable reference Figure 11A and Figure 11B The processing steps described herein are for depositing an amorphous metal oxide layer 20L. The material composition and thickness range of the amorphous metal oxide layer 20L in the third exemplary structure may be the same as those in the first exemplary structure. The amorphous metal oxide layer 20L in the third exemplary structure does not need to conform to the deposition process because it is formed on a planar surface. The amorphous metal oxide layer 20L is deposited on a first-type insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second-type insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30). In some embodiments, the top surface of a portion of the hydrogen-containing dielectric layer 10 covering the edge portion of the hydrogen-blocking dielectric layer 30 may have a vertically projecting bump segment. The covered portion of the top surface of the amorphous metal oxide layer 20L may have a bump segment protruding above a horizontal extension of the top surface of the amorphous metal oxide layer 20L.

[0172] Reference Figure 35 The amorphous metal oxide layer 20L can be patterned to provide the electrical insulation required for the subsequently formed thin-film transistor. The patterned amorphous metal oxide layer 20 can be formed.

[0173] Reference Figure 36 Executable reference Figure 13A and Figure 13BThe annealing process is used to transform each patterned amorphous metal oxide layer 20 into a corresponding group of at least one crystalline metal oxide semiconductor layer. Since the surface of the patterned amorphous metal oxide layer 20 is exposed to the environment during the annealing process and is susceptible to oxygen diffusion during annealing, the annealing process may preferably be performed in an oxygen-free environment to avoid excessive oxygen diffusion into the patterned amorphous metal oxide layer 20 during annealing. In one embodiment, the patterned amorphous metal oxide layer 20 may be transformed into a combination comprising at least one n-type metal oxide semiconductor layer 22 and at least one p-type metal oxide semiconductor layer 21.

[0174] When the annealing process is performed at an elevated temperature, the first portion of the patterned amorphous metal oxide layer 20 that contacts a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) transforms into an n-type metal oxide semiconductor layer 22 due to the loss of oxygen by hydrogen atoms into the hydrogen-containing dielectric material in the hydrogen-containing dielectric layer 10 during the annealing process. The second portion of the patterned amorphous metal oxide layer 20 that contacts a second type of insulating surface (e.g., the surface of the hydrogen-barrier dielectric layer 30) transforms into a p-type metal oxide semiconductor layer 21 during the annealing process. In one embodiment, the p-type metal oxide semiconductor layer 21 contains channels of p-channel thin-film transistors, and the n-type metal oxide semiconductor layer 22 contains channels of n-channel thin-film transistors.

[0175] Finish Figure 13A and Figure 13B Following the annealing process described herein, portions of the amorphous metal oxide layer 20L undergo a phase transition to a crystalline state. The conductivity type of the newly crystallized metal oxide material portion depends on whether each metal oxide material portion is in contact with the hydrogen-containing dielectric layer 10 or the hydrogen-barrier dielectric layer 30. Each portion of the amorphous metal oxide layer 20L in contact with the hydrogen-containing dielectric layer 10 transforms into an n-type metal oxide semiconductor layer 22 due to the loss of oxygen atoms and the accumulation of free electrons, while each portion of the amorphous metal oxide layer 20L in contact with the hydrogen-barrier dielectric layer 30 transforms into a p-type metal oxide semiconductor layer 21. Specifically, each crystallized portion of the amorphous metal oxide layer 20L in contact with the hydrogen-containing dielectric layer 10 transforms into an n-type metal oxide semiconductor layer 22 due to the loss of oxygen atoms and the accumulation of free electrons. Each crystallized portion of the amorphous metal oxide layer 20L in contact with the hydrogen-barrier dielectric layer 30 generally transforms into a p-type metal oxide semiconductor layer 21, except for the peripheral region adjacent to the hydrogen-containing dielectric layer 10. The pn junction between the p-type metal oxide semiconductor layer 21 and the n-type metal oxide semiconductor layer 22 can be formed at or near the interface between the hydrogen-containing dielectric layer 10 and the hydrogen-blocking dielectric layer 30.

[0176] Reference Figure 37A passivation dielectric layer 62 may be selectively deposited above and around the p-type metal-oxide-semiconductor layer 21 and the n-type metal-oxide-semiconductor layer 22, and on the physically exposed portions of the top surfaces of the hydrogen-containing dielectric layer 10 and the hydrogen-barrier dielectric layer 30. If used, the passivation dielectric layer 62 may contain a dielectric material that functions as a diffusion barrier material. For example, the passivation dielectric layer 62 may contain silicon nitride, silicon carbide, or silicon oxynitride.

[0177] A dielectric material, such as undoped or doped silicate glass, may be deposited on the passivation dielectric layer 62. A planarization process, such as chemical mechanical planarization, may be performed to planarize the top surface of the deposited dielectric material. The remaining portion of the deposited dielectric material is referred to herein as the contact dielectric layer 90.

[0178] A photoresist layer (not shown) may be applied onto the contact dielectric layer 90, and discrete openings therein may be formed using a photolithography process. The pattern of the discrete openings in the photoresist layer may be transferred through the contact dielectric layer 90 and the passivation dielectric layer 62 by an anisotropic etching process to form source / drain cavities 79. A pair of source / drain cavities 79 may be formed over the end portion of each semiconductor channel covering a respective gate 55. The photoresist layer may then be removed, for example, by ashing.

[0179] Reference Figure 38 At least one conductive material may be deposited in the source / drain cavity 79 and on the contact dielectric layer 90. The at least one conductive material may include a metal barrier liner, comprising a metal barrier liner material, and a metal filler layer, comprising a metal filler material. The metal barrier liner material may include conductive metal nitrides or conductive metal carbides, such as TiN, TaN, WN, TiC, TaC, and / or WC. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, their alloys, and / or combinations thereof. Excess portions of the at least one conductive material above a horizontal plane including the top surface of the contact dielectric layer may be removed by a planarization process, which may use chemical mechanical polishing (CMP) and / or trench etching. Each remaining portion of the at least one conductive material filling the source / drain cavity 79 constitutes a source / drain 80, which is the conductive material portion 80. In one embodiment, each source / drain 80 may include a metal barrier liner 80A, which is the remaining portion of the metal barrier liner material, and a metal filler portion 80F, which is the remaining portion of the metal filler material. Generally, the source / drain 80 may be formed on corresponding portions of the P-type metal oxide semiconductor layer 21 and the N-type metal oxide semiconductor layer 22 via contact layer dielectric layers 90.

[0180] Reference Figure 39The illustration shows a region of a fourth exemplary structure according to an embodiment of the present disclosure. The fourth exemplary structure may be derived from... Figure 29 The third exemplary structure shown is derived by depositing a first gate dielectric component layer 51 and a hydrogen-containing dielectric layer 10. The hydrogen-containing dielectric layer 10 may be deposited as a gate dielectric component layer. The hydrogen-containing dielectric layer 10 may comprise any material suitable as a gate dielectric material, selected from hydrogen-containing dielectric materials discussed with reference to the first exemplary structure. For example, the hydrogen-containing dielectric layer 10 in the fourth exemplary structure may comprise silicon oxide, or a dielectric metal oxide material deposited in a hydrogen-containing environment or using a hydrogen-containing precursor gas. The thickness of the hydrogen-containing dielectric layer 10 may range from 1 nm to 6 nm, for example from 1.5 nm to 3 nm, although smaller and larger thicknesses may also be used.

[0181] A first photoresist layer 57 may be applied onto the hydrogen-containing dielectric layer 10 and may be patterned using lithography to cover the n-channel transistor region 800 but not the p-channel transistor region 700. A selective etching process may be performed to etch the material of the hydrogen-containing dielectric layer 10 without etching the material of the first gate dielectric component layer 51. The selective etching process removes the unmasked portions of the second gate dielectric component layer 52 (i.e., the hydrogen-blocking dielectric layer 30). The first photoresist layer 57 may then be removed, for example, by ashing.

[0182] Reference Figure 40 A second gate dielectric component layer 52 can be deposited. According to one embodiment of this disclosure, the second gate dielectric component layer 52 includes a hydrogen-blocking dielectric layer 30. The hydrogen-blocking dielectric layer 30 in the fourth exemplary structure may have any material composition that can be used in the hydrogen-blocking dielectric layer 30 in the first exemplary structure. Therefore, the hydrogen-blocking dielectric layer 30 includes a dielectric material that is substantially free of hydrogen atoms, or contains hydrogen atoms at a low atomic concentration (e.g., an atomic concentration below the second atomic concentration, which may be 30 ppm or less, preferably 10 ppm or less, more preferably 3 ppm or less). Furthermore, the dielectric material of the hydrogen-blocking dielectric layer 30 is selected from dielectric materials that effectively block the diffusion of hydrogen atoms through it. Examples of such dielectric materials include alkaline earth metal oxides, such as magnesium oxide, calcium oxide, and strontium oxide. In one embodiment, the hydrogen-blocking dielectric layer 30 comprises and / or is substantially composed of at least one alkaline earth metal oxide material. In one embodiment, the hydrogen-blocking dielectric layer 30 is composed of magnesium oxide, calcium oxide, or alloys or stacks thereof. The thickness of the hydrogen barrier dielectric layer 30 can be in the range of 1 nm to 6 nm, for example from 1.5 nm to 3 nm, although smaller and larger thicknesses can also be used.

[0183] Reference Figure 41The second photoresist layer 59 can be applied onto the hydrogen-blocking dielectric layer 30 and can be patterned using lithography to cover the p-channel transistor region 700 but not the n-channel transistor region 800. A selective etching process can be performed to etch the material of the hydrogen-blocking dielectric layer 30 without etching the material of the hydrogen-containing dielectric layer 10. The unmasked portions of the hydrogen-blocking dielectric layer 30 are removed by the selective etching process. The second photoresist layer 59 can then be removed, for example, by ashing.

[0184] After removing the second photoresist layer 59, a combination of a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is formed on the substrate 8. The first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is the surface of the hydrogen-containing dielectric material, wherein the concentration of hydrogen atoms is greater than the first atomic concentration (as described above, possibly at least 100 ppm), while the second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is the hydrogen-free surface of the hydrogen-blocking dielectric material.

[0185] The portion of the first gate dielectric component layer 51 in the n-channel transistor region 800, combined with the hydrogen-containing dielectric layer 10, comprises a first type gate dielectric 50A. The first type gate dielectric 50A is formed on a first gate 55 located in the n-channel transistor region 800. The portion of the first gate dielectric component layer 51 in the p-channel transistor region 700, combined with the hydrogen-blocking dielectric layer 30, comprises a second type gate dielectric 50B. The second type gate dielectric 50B is formed on a second gate 55 located in the p-channel transistor region 700. In one embodiment, a first type insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is the top surface of the first type gate dielectric 50A, and a second type insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is the top surface of the second type gate dielectric 50B.

[0186] Reference Figure 42 Executable reference Figure 11A and Figure 11B The processing steps described herein are for depositing an amorphous metal oxide layer 20L. The material composition and thickness range of the amorphous metal oxide layer 20L in the fourth exemplary structure may be the same as those in the first exemplary structure. The amorphous metal oxide layer 20L in the fourth exemplary structure does not need to conform to the deposition process because it is formed on a planar surface. The amorphous metal oxide layer 20L is deposited on a first-type insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second-type insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30). In some embodiments, the top surface of a portion of the hydrogen-blocking dielectric layer 30 covering the edge portion of the hydrogen-containing dielectric layer 10 may have a vertically projecting protrusion. The covered portion of the top surface of the amorphous metal oxide layer 20L may have a protrusion protruding above a horizontal extension of the top surface of the amorphous metal oxide layer 20L.

[0187] Reference Figure 43 The amorphous metal oxide layer 20L can be patterned to provide the electrical insulation required for the subsequently formed thin-film transistor. The patterned amorphous metal oxide layer 20 can be formed.

[0188] Reference Figure 44 Executable reference Figure 13A and Figure 13B The annealing process transforms each patterned amorphous metal oxide layer 20 into a corresponding at least one crystalline metal oxide semiconductor layer group. Since the surface of the patterned amorphous metal oxide layer 20 is exposed to the environment during the annealing process and readily absorbs oxygen, the annealing process may preferably employ an oxygen-free environment to avoid excessive oxygen absorption into the patterned amorphous metal oxide layer 20 during the annealing process. In one embodiment, the patterned amorphous metal oxide layer 20 may be transformed into a combination comprising at least one n-type metal oxide semiconductor layer 22 and at least one p-type metal oxide semiconductor layer 21.

[0189] When the annealing process is performed at an elevated temperature, the first portion of the patterned amorphous metal oxide layer 20 that contacts a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) transforms into an n-type metal oxide semiconductor layer 22 due to the loss of oxygen by hydrogen atoms into the hydrogen-containing dielectric material in the hydrogen-containing dielectric layer 10 during the annealing process. The second portion of the patterned amorphous metal oxide layer 20 that contacts a second type of insulating surface (e.g., the surface of the hydrogen-barrier dielectric layer 30) transforms into a p-type metal oxide semiconductor layer 21 during the annealing process. In one embodiment, the p-type metal oxide semiconductor layer 21 contains channels of p-channel thin-film transistors, and the n-type metal oxide semiconductor layer 22 contains channels of n-channel thin-film transistors.

[0190] As described above, the conductivity type of each crystalline metal oxide portion originating from the amorphous metal oxide layer 20L is determined by whether or not it is in contact with the hydrogen-blocking dielectric layer 30 at or around each crystalline metal oxide portion. Each portion of the amorphous metal oxide layer 20L in contact with the hydrogen-containing dielectric layer 10 crystallizes into an n-type metal oxide semiconductor layer 22 due to the loss of oxygen atoms and the accumulation of free electrons. Each portion of the amorphous metal oxide layer 20L in contact with the hydrogen-blocking dielectric layer 30 typically crystallizes into a p-type metal oxide semiconductor layer 21, except for the peripheral region adjacent to the hydrogen-containing dielectric layer 10. The pn junction between the p-type metal oxide semiconductor layer 21 and the n-type metal oxide semiconductor layer 22 may be formed at or near the interface between the hydrogen-containing dielectric layer 10 and the hydrogen-blocking dielectric layer 30.

[0191] Reference Figure 45A passivation dielectric layer 62 may be selectively deposited above and around the p-type metal-oxide-semiconductor layer 21 and the n-type metal-oxide-semiconductor layer 22, and on the physically exposed portions of the top surfaces of the hydrogen-containing dielectric layer 10 and the hydrogen-barrier dielectric layer 30. If used, the passivation dielectric layer 62 may contain a dielectric material that functions as a diffusion barrier material. For example, the passivation dielectric layer 62 may contain silicon nitride, silicon carbide, or silicon oxynitride.

[0192] A dielectric material, such as undoped or doped silicate glass, may be deposited on the passivation dielectric layer 62. A planarization process, such as chemical mechanical planarization, may be performed to planarize the top surface of the deposited dielectric material. The remaining portion of the deposited dielectric material is referred to herein as the contact dielectric layer 90.

[0193] A photoresist layer (not shown) may be applied onto the contact dielectric layer 90, and discrete openings therein may be formed using a photolithography process. The pattern of the discrete openings in the photoresist layer may be transferred through the contact dielectric layer 90 and the passivation dielectric layer 62 by an anisotropic etching process to form source / drain cavities 79. A pair of source / drain cavities 79 may be formed over the end portion of each semiconductor channel covering a respective gate 55. The photoresist layer may then be removed, for example, by ashing.

[0194] Reference Figure 46 At least one conductive material may be deposited in the source / drain cavity 79 and on the contact dielectric layer 90. The at least one conductive material may include a metal barrier liner, comprising a metal barrier liner material, and a metal filler layer, comprising a metal filler material. The metal barrier liner material may include conductive metal nitrides or conductive metal carbides, such as TiN, TaN, WN, TiC, TaC, and / or WC. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, their alloys, and / or combinations thereof. Excess portions of the at least one conductive material above a horizontal plane including the top surface of the contact dielectric layer may be removed by a planarization process, which may use chemical mechanical polishing (CMP) and / or trench etching. Each remaining portion of the at least one conductive material filling the source / drain cavity 79 constitutes a source / drain 80, which is the conductive material portion 80. In one embodiment, each source / drain 80 may include a metal barrier liner 80A, which is the remainder of the metal barrier liner material, and a metal filler portion 80F, which is the remainder of the metal filler material. Generally, the source / drain 80 may be formed in the contact dielectric layer 90 and located on corresponding portions of the P-type metal oxide semiconductor layer 21 and the N-type metal oxide semiconductor layer 22.

[0195] Various embodiments based on this disclosure and referenced herein Figure 1 and Figures 29 to 46A semiconductor structure is provided. The semiconductor structure includes: a pn junction located at the interface between a p-type metal oxide semiconductor layer 21 and an n-type metal oxide semiconductor layer 22; a hydrogen-containing dielectric material portion having a hydrogen atom concentration greater than a first atomic concentration (as described above, it can be at least 100 ppm) and having a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) contacting the n-type metal oxide semiconductor layer 22; and a hydrogen-blocking dielectric material portion including a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) contacting the p-type metal oxide semiconductor layer 21, wherein the second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is a hydrogen-impermeable surface.

[0196] In one embodiment, the semiconductor structure includes: a first conductive material portion 80 contacting a first portion of a p-type metal oxide semiconductor layer 21; a second conductive material portion 80 contacting a second portion of the p-type metal oxide semiconductor layer 21 and a first portion of an n-type metal oxide semiconductor layer 22; and a third conductive material portion 80 contacting a second portion of the n-type metal oxide semiconductor layer 22.

[0197] In one embodiment, the first conductive material portion 80, the second conductive material portion 80, and the third conductive material portion 80 comprise three conductive material portions 80 laterally spaced from each other in a horizontal direction parallel to the top surface of the substrate 8. In one embodiment, the p-type metal-oxide-semiconductor layer 21 comprises a channel of a p-channel thin-film transistor; the n-type metal-oxide-semiconductor layer 22 comprises a channel of an n-channel thin-film transistor; and the first conductive material portion 80, the second conductive material portion 80, and the third conductive material portion 80 comprise a source / drain 80 of a combination of a p-channel thin-film transistor and an n-channel thin-film transistor. In one embodiment, the semiconductor structure comprises at least one gate structure (50, 55), comprising a respective gate dielectric layer 50 and a respective gate electrode, wherein the p-type metal-oxide-semiconductor layer 21 and the n-type metal-oxide-semiconductor layer 22 are each in contact with the at least one gate structure (50, 55).

[0198] Reference Figure 47 This illustrates the first exemplary structure after performing additional processing steps (see reference). Figures 1 to 17B discuss). Figure 47 The first exemplary structure shown can be constructed by forming a second metal via structure 632 that passes through the stack of insulating material layer 635, etch-block dielectric layer 636, and contact dielectric layer 90, thereby allowing access from... Figure 16A , Figure 16B , Figure 17A and Figure 17B This is derived from the first exemplary structure shown. The second metal through-hole structure 632 may be formed on the top surface of the second metal wire structure 628.

[0199] A third insulating layer 637 may be formed on top of the insulating layer 40. A third metal wire structure 638 may be formed in the third insulating layer 637, located on the top surface of various contact hole structures (95, 98) and the second metal hole structure 632. The combination of the insulating material layer 635, the etch-blocking dielectric layer 636, the contact layer dielectric layer 90, and the third insulating layer 637 constitutes the third interconnect dielectric layer 630. Although Figure 47 Only the first device region 100 and the second device region 200 are explicitly shown, but various device regions (100, 200, 300, 400, 500, 600) can be located within the third interconnect dielectric layer 630.

[0200] The fourth interconnect dielectric layer 640 is embedded in the third metal via structure 642 and the fourth metal line 648, and may be formed on the third interconnect dielectric layer 630. Additional metal interconnect structures (not shown) are embedded in additional dielectric material layers (not shown), which may be subsequently formed on the fourth interconnect dielectric layer 640 as needed.

[0201] Figure 48 The second, third, or fourth exemplary structures are schematically shown after performing additional processing steps. Figure 48 The second, third, or fourth exemplary structure shown can be derived from... Figure 27 and Figure 28 The second exemplary structure shown Figure 38 The third exemplary structure shown or Figure 46 The fourth exemplary structure shown is derived from it, in a manner as follows: Figure 27 , Figure 28 , Figure 38 or Figure 46 The stacking of the insulating material layer 635, the etch-block dielectric layer 636, and all other dielectric material layers formed on the etch-block dielectric layer 636 forms a second metal via structure 632. The second metal via structure 632 may be formed on the top surface of the second metal wire structure 628.

[0202] A third line layer insulating layer 637 may be formed on the contact layer dielectric layer 90. A third metal line structure 638 may be formed in the third line layer insulating layer 637, located on the top surface of each contact hole structure (in the embodiment of the second exemplary structure) or on the top surface of the source / drain electrode 80, and on the top surface of the second metal via structure 632. The insulating material layer 635, the etch-stop dielectric layer 636, the third line layer insulating layer 637, and the combination of all insulating material layers between the etch-stop dielectric layer 636 and the third line layer insulating layer 637 constitute the third interconnect layer dielectric layer 630. The p-channel transistor region 700 and the n-channel transistor region 800 may be located within the third interconnect layer dielectric layer 630.

[0203] The fourth interconnect dielectric layer 640 is embedded in the third metal via structure 642 and the fourth metal line 648, and may be formed on the third interconnect dielectric layer 630. Additional metal interconnect structures (not shown) are embedded in additional dielectric material layers (not shown), which may be subsequently formed on the fourth interconnect dielectric layer 640 as needed.

[0204] Figure 49 This is the first flowchart, which illustrates the general processing steps for manufacturing the semiconductor device of this disclosure.

[0205] Refer to step 4910 and Figures 1 to 10B , Figures 18 to 22 29 to Figure 33 and 39 to Figure 41 A combination of a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) can be formed on the substrate 8. The first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is the surface of the hydrogen-containing dielectric material, wherein the concentration of hydrogen atoms is greater than the first atomic concentration (as described above, possibly at least 100 ppm), while the second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is the hydrogen-free surface of the hydrogen-blocking dielectric material.

[0206] Refer to step 4920 and Figure 11A , Figure 11B , Figure 23 , Figure 34 and Figure 42 The amorphous metal oxide layer 20L can be deposited on a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) and a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30).

[0207] Refer to step 4930 and Figures 12A to 17B , Figures 24 to 28 35 to Figure 38 and 43 to Figure 48 The annealing process can be performed at elevated temperatures. During the annealing process, a first portion of the amorphous metal oxide layer 20L that contacts a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) transforms into an n-type metal oxide semiconductor layer 22 by losing oxygen to hydrogen atoms in the hydrogen-containing dielectric material, while a second portion of the amorphous metal oxide layer 20L that contacts a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) transforms into a p-type metal oxide semiconductor layer 21 during the annealing process.

[0208] Figure 50 The second flowchart illustrates the general processing steps for manufacturing the semiconductor device of this disclosure.

[0209] Refer to step 5010 and Figures 1 to 10B and Figures 18 to 22 This can form a spatially extended sequence of surfaces, which, from one end to the other, sequentially include a first conductive surface, a first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10), a second conductive surface, a second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30), and a third conductive surface. The first type of insulating surface (e.g., the surface of the hydrogen-containing dielectric layer 10) is the surface of the hydrogen-containing dielectric material, wherein the concentration of hydrogen atoms is greater than the first atomic concentration (as described above, possibly at least 100 ppm), while the second type of insulating surface (e.g., the surface of the hydrogen-blocking dielectric layer 30) is the hydrogen-free surface of the hydrogen-blocking dielectric material.

[0210] Refer to step 5020 and Figure 11A , Figure 11B and Figure 23 Amorphous metal oxide layers 20L can be deposited on spatially extended surface sequences.

[0211] Refer to step 5030 and Figures 12A to 17B , Figures 24 to 28 , Figure 47 and Figure 48 The annealing process can be performed at elevated temperatures. A first portion of the amorphous metal oxide layer 20L is transformed into a p-type metal oxide semiconductor layer 21 extending between the first conductive surface and the second conductive surface, and a second portion of the amorphous metal oxide layer 20L is transformed into an n-type metal oxide semiconductor layer 22 extending between the second conductive surface and the third conductive surface.

[0212] Various embodiments disclosed herein can be used to provide a combination of a p-type metal oxide semiconductor layer 21 and an n-type metal oxide semiconductor layer 22 by depositing an amorphous metal oxide layer 20L and by modulating the oxygen vacancy concentration to give different regions of the amorphous metal oxide layer 20L different characteristics after annealing. Modulation of the oxygen vacancy concentration can be achieved by a combination of a hydrogen-containing dielectric layer 10 and a hydrogen-blocking dielectric layer 30. An alkaline earth metal oxide layer can be used as the hydrogen-blocking dielectric layer 30.

[0213] As described in more detail above, one embodiment of this disclosure discloses a method for forming a semiconductor structure, comprising: forming a combination of a first type insulating surface and a second type insulating surface on a substrate, wherein the first type insulating surface is a surface of a hydrogen-containing dielectric material containing hydrogen atoms at a first atomic concentration, and the second type insulating surface is a hydrogen-impermeable surface of a hydrogen-barrier dielectric material containing hydrogen atoms at a second atomic concentration, the second atomic concentration being lower than the first atomic concentration; depositing an amorphous metal oxide layer on the first type insulating surface and the second type insulating surface; and performing an annealing process at an elevated temperature, wherein a first portion of the amorphous metal oxide layer contacts the first type insulating surface and is transformed into an n-type metal oxide semiconductor layer during the annealing process, and a second portion of the amorphous metal oxide layer contacts the second type insulating surface and is transformed into a p-type metal oxide semiconductor layer during the annealing process.

[0214] In some embodiments, the first type of insulating surface is formed between the first conductive surface of the first conductive material portion and the second conductive surface of the second conductive material portion; and the second type of insulating surface is formed between the second conductive surface and the third conductive surface of the third conductive material portion. In some embodiments, each of the first conductive material portion, the second conductive material portion, and the third conductive material portion includes a respective source / drain electrode; the p-type metal-oxide-semiconductor layer includes a channel of a p-channel thin-film transistor; and the n-type metal-oxide-semiconductor layer includes a channel of an n-channel thin-film transistor. In some embodiments, the method further includes: forming a vertical stack that sequentially includes, from bottom to top or from top to bottom, a first conductive material layer, a first insulating material layer including the hydrogen-containing dielectric material, a second conductive material layer, a second insulating material layer including the hydrogen-blocking dielectric material, and a third conductive material layer; and patterning the vertical stack such that each layer in the vertical stack has a respective sidewall, wherein: the first conductive surface is a sidewall of the first conductive material layer; the second conductive surface is a sidewall of the second conductive material layer; and the third conductive surface is a sidewall of the third conductive material layer. In some embodiments, the method includes forming a vertically extending via cavity through the vertical stack, wherein the first conductive surface, the second conductive surface, and the third conductive surface are surface portions of the vertically extending via cavity that overlap each other in the vertical direction. In some embodiments, the combination of the first type insulating surface and the second type insulating surface is formed by: forming an insulating layer on a substrate, the insulating layer comprising a hydrogen-containing dielectric material; forming a recessed region by vertically recessing a portion of the top surface of the insulating layer; and filling the recessed region with a portion of a hydrogen-resistant dielectric material, wherein: the first type insulating surface comprises the remaining portion of the top surface of the insulating layer; and the second type insulating surface comprises the top surface of the portion of the hydrogen-resistant dielectric material. In some embodiments, the method further includes: forming a cavity in the combination comprising the portion of the insulating layer and the hydrogen-resistant dielectric material; and filling the cavity with at least one conductive material, wherein the first conductive material portion, the second conductive material portion, and the third conductive material portion comprise respective portions of the at least one conductive material filling the cavity. In some embodiments, the method further includes depositing a gate dielectric layer on the amorphous metal oxide layer, wherein the annealing process is performed after depositing the gate dielectric layer. In some embodiments, the method further includes: depositing a gate electrode material layer on the gate dielectric layer; and patterning the gate electrode material layer and the gate dielectric layer into at least one gate electrode and at least one gate dielectric.In some embodiments, the method further includes: forming a first gate and a second gate embedded within a dielectric substrate layer on the substrate; forming a first type of gate dielectric on the first gate and a second type of gate dielectric on the second gate, wherein: the first type of insulating surface is the top surface of the first type of gate dielectric; and the second type of insulating surface is the top surface of the second type of gate dielectric. In some embodiments, the method further includes: forming a contact layer dielectric layer over the p-type metal-oxide-semiconductor layer and the n-type metal-oxide-semiconductor layer; and forming source / drain electrodes through the contact layer dielectric layer on respective portions of the p-type metal-oxide-semiconductor layer and the n-type metal-oxide-semiconductor layer.

[0215] As described in more detail above, one embodiment of this disclosure discloses a method for forming a semiconductor structure, comprising: forming a spatially extended sequence of surfaces, sequentially comprising a first conductive surface, a first type insulating surface, a second conductive surface, a second type insulating surface, and a third conductive surface from one end to the other, wherein the first type insulating surface is a surface of a hydrogen-containing dielectric material, the hydrogen-containing dielectric material comprising hydrogen atoms at a concentration greater than a first atomic concentration, and the second type insulating surface is a hydrogen-impermeable surface of a hydrogen-blocking dielectric material; depositing an amorphous metal oxide layer on the spatially extended sequence of surfaces; and performing an annealing process at an elevated temperature, wherein a first portion of the amorphous metal oxide layer is converted into an n-type metal oxide semiconductor layer extending between the first conductive surface and the second conductive surface, and a second portion of the amorphous metal oxide layer is converted into a p-type metal oxide semiconductor layer extending between the second conductive surface and the third conductive surface.

[0216] In some embodiments, the spatially extended surface sequence is formed by: forming a vertical stack comprising, from bottom to top or top to bottom, a first conductive material layer, a first insulating material layer comprising the hydrogen-containing dielectric material, a second conductive material layer, a second insulating material layer comprising the hydrogen-blocking dielectric material, and a third conductive material layer; and performing an anisotropic etching process on the vertical stack using an etching mask to pattern the vertical stack. In some embodiments, the anisotropic etching process forms a vertically extending via cavity in the structure of the vertical stack; and the spatially extended surface sequence includes a surface portion of the vertical stack surrounding the vertically extending via cavity. In some embodiments, the process further includes: depositing a gate dielectric layer on the amorphous metal oxide layer, wherein the annealing process is performed after depositing the gate dielectric layer; and forming a gate on the gate dielectric layer.

[0217] As described in more detail above, in one embodiment of this disclosure, a semiconductor structure is disclosed, comprising: a p-type metal oxide semiconductor layer and an n-type metal oxide semiconductor layer; a hydrogen-containing dielectric material portion having a first type insulating surface in contact with the n-type metal oxide semiconductor layer; and a hydrogen-blocking dielectric material portion including a second type insulating surface in contact with the p-type metal oxide semiconductor layer, the second type insulating surface being a hydrogen-impermeable surface.

[0218] In some embodiments, the method further includes: a first conductive material portion contacting a first portion of the p-type metal-oxide-semiconductor layer; a second conductive material portion contacting a second portion of the p-type metal-oxide-semiconductor layer and a first portion of the n-type metal-oxide-semiconductor layer; and a third conductive material portion contacting a second portion of the n-type metal-oxide-semiconductor layer. In some embodiments, the first, second, and third conductive material portions comprise three conductive material layers, which are perpendicularly spaced apart from each other in a direction perpendicular to the top surface of the substrate. In some embodiments, the p-type metal-oxide-semiconductor layer comprises a channel of a p-channel thin-film transistor; the n-type metal-oxide-semiconductor layer comprises a channel of an n-channel thin-film transistor; and the first, second, and third conductive material portions comprise source / drain electrodes of a combination of the p-channel and n-channel thin-film transistors. In some embodiments, the method further includes at least one gate structure, each gate structure comprising a respective gate dielectric layer and a respective gate electrode, wherein both the p-type and n-type metal-oxide-semiconductor layers are in contact with the at least one gate structure.

[0219] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Each embodiment described using the term "comprises" is also inherently disclosed in some embodiments as potentially replacing the term "consists essentially of" or "consists of," unless otherwise expressly stated herein. In some embodiments, the inclusion of a Markush Group, which lists two or more elements as alternatives, may also be implicitly disclosed whenever two or more elements are listed in the same or different paragraphs. Whenever the auxiliary verb "can" is used in this disclosure to describe the formation or processing of an element, in some embodiments, embodiments in which such an element or processing step is not performed are also explicitly contemplated, provided that the resulting apparatus or device provides an equivalent result. Therefore, the auxiliary verb "can" used to describe the execution of a component forming or processing step should also be interpreted as "may" or "may, or may not," provided that omitting the component forming or processing step provides the same or equivalent result, including slightly superior and slightly inferior results. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: p-type metal-oxide-semiconductor layer and n-type metal-oxide-semiconductor layer; The hydrogen-containing dielectric material portion has a first-type insulating surface that contacts the n-type metal oxide semiconductor layer; as well as The hydrogen-barrier dielectric material portion includes a second type insulating surface that contacts the p-type metal oxide semiconductor layer, the second type insulating surface being a hydrogen-impermeable surface.

2. The semiconductor structure according to claim 1, characterized in that, Further includes: The first conductive material portion is in contact with the first portion of the p-type metal oxide semiconductor layer; The second conductive material portion contacts the second portion of the p-type metal oxide semiconductor layer and the first portion of the n-type metal oxide semiconductor layer; as well as The third conductive material portion contacts the second portion of the n-type metal oxide semiconductor layer.

3. The semiconductor structure according to claim 2, characterized in that, The first conductive material portion, the second conductive material portion, and the third conductive material portion each comprise three conductive material layers, which are perpendicularly spaced apart from each other along a direction perpendicular to the top surface of the substrate.

4. The semiconductor structure according to claim 2, characterized in that, The p-type metal-oxide-semiconductor layer includes a channel of a p-channel thin-film transistor; The n-type metal-oxide-semiconductor layer includes a channel of an n-channel thin-film transistor; as well as The first conductive material portion, the second conductive material portion, and the third conductive material portion include a source / drain electrode of a combination of the p-channel thin-film transistor and the n-channel thin-film transistor.

5. The semiconductor structure according to claim 1, characterized in that, It also includes at least one gate structure, each gate structure comprising a respective gate dielectric layer and a respective gate electrode, wherein both the p-type metal oxide semiconductor layer and the n-type metal oxide semiconductor layer are in contact with the at least one gate structure.

6. The semiconductor structure according to claim 5, characterized in that, The gate dielectric layer is deposited on the p-type metal oxide semiconductor layer and the n-type metal oxide semiconductor layer.

7. The semiconductor structure according to claim 6, characterized in that, The thickness of the gate dielectric layer is less than 20 nm.

8. The semiconductor structure according to claim 1, characterized in that, The hydrogen atom concentration of the first type of insulating surface is a first atomic concentration, and the hydrogen atom concentration of the second type of insulating surface is a second atomic concentration, wherein the second atomic concentration is lower than the first atomic concentration.

9. The semiconductor structure according to claim 2, characterized in that, The first conductive material portion, the hydrogen-containing dielectric material portion, the second conductive material portion, the hydrogen-blocking dielectric material portion, and the third conductive material portion constitute a vertical stack, wherein the semiconductor structure further includes a through-hole cavity extending vertically in the vertical stack.

Images