Bump cushion structure and semiconductor package structure

Abstract

The utility model discloses a kind of bump buffer structure and semiconductor packaging structure, the bump buffer structure includes bump, buffer sleeve and wafer, the bump includes several and is located on the wafer, the buffer sleeve includes several and is provided with opening, the buffer sleeve is set on the wafer, and it is correspondingly sleeved on the outer periphery of the bump by the opening.In the utility model, by only setting buffer sleeve at corresponding position on wafer and bump, thereby reducing the coverage area ratio of polymer for buffering on wafer, so that the thermal stress generated when polymer for buffering solidifies and shrinks is greatly reduced, and then the wafer warping degree is reduced, and reliability is improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing, and in particular to bump buffer structures and semiconductor packaging structures. Background Technology

[0002] In advanced packaging, polymer buffer layers are crucial structures for ensuring chip reliability, effectively preventing bump cracking and brittle failure of silicon chips. Current technologies often employ full-coverage buffer layers (coverage exceeding 90%), but this design suffers from significant wafer warpage. This is primarily due to the substantial difference in thermal expansion coefficients between silicon wafers (approximately 2.6 ppm / °C) and the polymer materials used in buffer layers (typically 40-60 ppm / °C). This difference causes shrinkage stress generated by the polymer during curing and cooling, which pulls on the wafer, leading to concave warpage.

[0003] Furthermore, as advanced packaging evolves towards 2.5D / 3D heterogeneous integration, the thinning and enlargement of chips further exacerbates the cumulative thermal stress effect caused by multi-material stacking. The industry has attempted to alleviate warpage by adding fillers with low thermal expansion coefficients or developing low-temperature curing polymers. However, the former increases material brittleness, leading to cracking risks, while the latter, due to incomplete cyclization reactions, impairs the material's mechanical properties and reliability. Clearly, these material-level improvements are impractical and cannot effectively solve the problem of excessive wafer warpage. Utility Model Content

[0004] The technical problem to be solved by this utility model is to provide a bump buffer structure and a semiconductor packaging structure to solve the problem of excessive wafer warpage caused by the curing of polymer buffer layers in existing advanced packaging.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows: a bump buffer structure, which includes bumps, buffer sleeves and wafers. The bumps include a plurality of bumps and are disposed on the wafer. The buffer sleeves include a plurality of bumps and are provided with openings. The buffer sleeves are disposed on the wafer and are fitted onto the outer periphery of the bumps one by one through the openings.

[0006] Furthermore, in the bump buffer structure described in this utility model, the buffer sleeve is an annular structure, with its inner side enclosing to form the opening.

[0007] Furthermore, in the bump buffer structure described in this utility model, the bump includes a lower metallization layer and a solder cap. The lower metallization layer includes an embedded portion and a covering portion connected to each other. The embedded portion is embedded in the opening, and the covering portion covers a portion of the upper surface of the buffer sleeve and exposes the outer peripheral portion of the buffer sleeve. The solder cap is located above the covering portion.

[0008] Furthermore, the bump buffer structure described in this utility model also includes a metal pad, which is located between the wafer and the embedded portion.

[0009] Furthermore, in the bump buffer structure described in this utility model, the buffer sleeve includes a first buffer portion and a second buffer portion connected to each other. The upper surface of the first buffer portion is flush with the upper surface of the second buffer portion. The first buffer portion covers the metal pad, and the second buffer portion covers the wafer.

[0010] Furthermore, in the bump buffer structure described in this utility model, the overlap width of the overlapping area between the upper surface of the first buffer part and the lower surface of the covering part is a first width d1, and the first width d1 satisfies: 13.5um≤d1≤20um.

[0011] Furthermore, in the bump buffer structure described in this utility model, the overlap width of the overlapping area between the lower surface of the second buffer portion and the upper surface of the wafer is the second width d2, and the second width d2 satisfies: d2≥15um.

[0012] Furthermore, in the bump buffer structure described in this utility model, the wafer is provided with through-silicon vias, and the through-silicon vias are correspondingly arranged with the opening.

[0013] Furthermore, in the bump buffer structure described in this utility model, the coverage width of the upper surface of the buffer sleeve covered by the bump is the third width d3, and the width of the upper surface of the buffer sleeve not covered by the bump is the fourth width d4. The third width d3 satisfies: d3≥13.5um, and the fourth width d4 satisfies: 20um<d4≤50um.

[0014] This invention also proposes a semiconductor packaging structure, which includes the bump buffer structure described above.

[0015] The beneficial effects of this invention are as follows: This invention designs an advanced encapsulated polymer buffer sleeve. Unlike traditional full-coverage structures, this invention uses a buffer sleeve around the periphery of each bump on the wafer, allowing a portion of the polymer to remain only on the wafer surface at the location corresponding to the bump. This significantly reduces the proportion of the polymer coverage area. Since the wafer warpage is proportional to the area of ​​the buffer polymer covering the surface, by placing the buffer sleeve only at the location corresponding to the bump on the wafer, the proportion of the buffer polymer coverage area on the wafer is reduced. This greatly reduces the force exerted by the buffer polymer on the wafer when it shrinks due to heat, thus reducing the thermal stress generated by the buffer polymer after curing, thereby reducing wafer warpage and improving reliability. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of the bump buffer structure described in this utility model from one perspective in one embodiment.

[0017] Figure 2 This is a top view of one embodiment of the bump buffer structure described in this utility model.

[0018] Figure 3 for Figure 1 The diagram shows a cross-sectional view of the bump buffer structure after the hidden portion of the structure is shown.

[0019] Figure 4 This is a cross-sectional view of the bump buffer structure described in this utility model from another perspective in another embodiment.

[0020] Figure 5 This is a top view of another embodiment of the bump buffer structure described in this utility model.

[0021] Figure 6 This is a cross-sectional view of the bump buffer structure described in this utility model from another perspective in another embodiment.

[0022] Figure 7 This is a top view of another embodiment of the bump buffer structure described in this utility model.

[0023] Label Explanation: 1. Buffer sleeve; 11. First buffer section; 12. Second buffer section; 13. Opening; 2. Protrusion; 21. Embedded part; 22. Cover part; 23. Weld cap; 3. Wafers; 4. Metal pads; 5. Through-silicon vias. Detailed Implementation

[0024] To explain in detail the technical content, objectives, and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0025] In advanced packaging technology, the buffer layer beneath the bumps (also known as a stress buffer layer, dielectric layer, passivation layer, or polymer layer) is a key guarantee of reliability, and its main functions are as follows: (1) Stress buffering / mechanical stress relief: This is the most important function of the buffer layer. Due to the large difference in the coefficients of thermal expansion between the chip (such as a silicon chip) and the underlying substrate (such as an organic substrate, ceramic, or another chip), the expansion and contraction of the two are different when the temperature changes, which will generate huge shear stress at the connection point (i.e., bump). The buffer layer is much softer and has a much lower elastic modulus than the silicon chip and bump, which can absorb and dissipate these thermomechanical stresses and prevent the stress from being directly transmitted to the fragile silicon chip. Without this buffer layer, repeated thermal cycling will cause fatigue cracking of the bumps, and in more serious cases, it will cause the silicon chip itself to crack (especially the low-k dielectric layer), resulting in device failure.

[0026] (2) Mechanical support and flattening: Provide a flat and stable mechanical support platform for the metal redistribution layer and bumps constructed above.

[0027] (3) Electrical insulation: As a dielectric layer, it isolates different metal pads on the chip surface, thereby preventing short circuits between different metal pads.

[0028] (4) Protect the underlying structure: This buffer layer can protect the passivation layer and fragile low-k dielectric material on the chip surface from physical and chemical damage from subsequent processes (such as electroplating, bump placement) or external environment.

[0029] In practical applications, the selection of buffer layer materials requires a comprehensive balance of factors such as stress buffering capacity, adhesion, thermal stability, dielectric properties, process compatibility, hygroscopicity, and cost. Currently, the most common materials used in buffer layers are polymer dielectric materials, mainly including the following three types: (1) Polyimide (PI): Polyimide has excellent high temperature stability, good mechanical strength, excellent stress buffering performance, mature process, good adhesion and low dielectric constant. It is one of the most traditional and widely used materials in advanced packaging.

[0030] (2) Polybenzoxazole (PBO): Polybenzoxazole has extremely high thermal stability, excellent adhesion, good mechanical strength, excellent stress buffering ability, low moisture absorption and good chemical stability. Its comprehensive performance is excellent and it is widely used in high-end packaging. It is especially suitable for applications that require stronger mechanical protection or higher heat resistance.

[0031] (3) Benzocyclobutene (BCB): Benzocyclobutene has extremely low dielectric constant, extremely low dielectric loss, excellent thermal stability, extremely low hygroscopicity, low stress during curing, excellent planarization ability and good chemical stability, making it increasingly popular in advanced packaging, especially in applications requiring high frequency performance.

[0032] However, the inventors have learned that buffer layers made of polymer dielectric materials suffer from significant wafer warpage degradation, primarily due to the following reasons: (1) CTE (Coefficient of Thermal Expansion) mismatch: The silicon wafer has a low CTE (approximately 2.6 ppm / °C), while the polymer material used in the buffer layer has a high CTE (typically 40–60 ppm / °C). During the cooling process after curing, the shrinkage rate of the polymer buffer layer is much greater than that of the silicon substrate, which causes the buffer layer to exert tensile stress on the wafer, causing the wafer to bend towards the side covered by the polymer buffer layer (i.e., front-side concave warping).

[0033] (2) Chemical shrinkage and curing stress: During the curing process, the polymer buffer layer undergoes a cross-linking reaction, the molecular structure becomes denser and accompanied by volume shrinkage (the chemical shrinkage rate can reach 5-10%). This internal shrinkage stress is not uniformly distributed within the polymer buffer layer, especially at the edges or in areas with dense patterns, which exacerbates local warping.

[0034] Moreover, as advanced packaging evolves towards 2.5D / 3D heterogeneous integration, the thinning and enlarging of chips further exacerbates the thermal stress accumulation effect caused by multi-material stacking, leading to a more significant wafer warpage problem.

[0035] To reduce wafer warpage, the industry has attempted to mitigate the problem by adding fillers with low coefficients of thermal expansion or developing low-temperature curing polymers. However, the former increases the brittleness of the material, leading to a risk of cracking; the latter, due to incomplete cyclization reactions, impairs the material's mechanical properties and reliability. Clearly, these material-level improvements cannot effectively solve the problem of excessive wafer warpage.

[0036] Furthermore, the inventors understand that current industry practices commonly employ a full-coverage structure for buffer layers, meaning the buffer layer covers the entire wafer surface, with openings only at locations requiring electrical connections. This structure results in the buffer layer's actual coverage area typically exceeding 90%, while wafer warpage is directly proportional to factors such as the buffer layer's thickness, area, and curing temperature. Therefore, with a full-coverage structure, wafer warpage is prone to becoming excessive.

[0037] Therefore, please refer to Figure 1 , Figure 4 as well as Figure 6This utility model discloses a bump buffer structure, including a bump 2, a buffer sleeve 1 and a wafer 3. The bump 2 includes a plurality of bumps and is disposed on the wafer 3. The buffer sleeve 1 includes a plurality of bumps and is provided with an opening 13. The buffer sleeve 1 is disposed on the wafer 3 and is fitted onto the outer periphery of the bump 2 one by one through the opening 13.

[0038] As can be seen from the above description, the beneficial effects of this utility model are as follows: This utility model designs an advanced encapsulated polymer buffer sleeve. Unlike the traditional full-coverage structure, this utility model uses a buffer sleeve 1 to cover the outer periphery of each bump 2 on the wafer 3, so that only a portion of the polymer is retained on the upper surface of the wafer 3 at the position corresponding to the bump 2. This significantly reduces the coverage area of ​​the polymer. Since the warpage of the wafer 3 is proportional to the area of ​​the buffer polymer covering the surface, by setting the buffer sleeve 1 only at the position corresponding to the bump 2 on the wafer 3, the coverage area of ​​the buffer polymer on the wafer 3 is reduced. This greatly reduces the force that the buffer polymer pulls on the wafer 3 when it shrinks due to heat, which in turn reduces the thermal stress generated by the buffer polymer after curing, thereby reducing the warpage of the wafer 3 and improving reliability.

[0039] Furthermore, such as Figure 3 As shown, the buffer sleeve 1 has a ring-shaped structure, with its inner sides enclosing to form the opening 13. In practical applications, the structure of the buffer sleeve 1 can be any ring shape, such as a circular ring, a square ring, or an octagonal ring, without limitation. For example, the most suitable ring geometry can be selected based on the actual situation of the layout, shape, and spatial constraints of the bumps on the chip (such as a circle for dense arrangement and a polygon for specific arrays), thereby optimizing space utilization, stress distribution, and process compatibility, and improving the flexibility and applicability of the design.

[0040] Furthermore, such as Figure 1 , Figure 4 as well as Figure 6 As shown, in the bump buffer structure of this utility model, the bump 2 includes an under bump metallization (UBM) layer and a solder cap 23. The under bump metallization layer includes an embedded part 21 and a covering part 22 connected to each other. The embedded part 21 is embedded in the opening 13. The covering part 22 covers part of the upper surface of the buffer sleeve 1 and exposes the outer peripheral part of the buffer sleeve 1. The solder cap 23 is located above the covering part 22.

[0041] As described above, the metallization layer under the bump is designed in layers. The embedded part 21 of the embedded opening 13 ensures the stability of the electrical connection and ensures a stable electrical connection with the underlying metal (such as Cu pads). At the same time, based on the covering part 22 that supports the bump 2 on the buffer sleeve 1, the stress is transferred to the polymer layer for absorption, avoiding stress concentration at the root of the bump 2, which could lead to cracking or delamination.

[0042] In practical applications, the annular structure buffer sleeve 1 of this utility model can be applied to a variety of different packaging process scenarios. Two different application scenarios are listed below.

[0043] Application Scenario 1: The buffer sleeve 1 has a metal pad 4 (such as a copper pad) below it and a bump above it, such as WLCSP (Wafer Level Chip Scale Package) or fan-out package.

[0044] Obviously, in application scenario one, the corresponding metal pad 4 needs to be set accordingly, such as Figure 1 as well as Figure 4 As shown, the metal pad 4 can be located between the wafer 3 and the embedded part 21. By setting the metal pad 4 between the wafer 3 and the embedded part 21, the location of key electrical connection nodes is established, facilitating electrical connection. Meanwhile, in application scenario one, the aforementioned annular buffer sleeve 1 needs to meet the following requirements: Furthermore, such as Figure 1 as well as Figure 4 As shown, in the bump buffer structure of this utility model, the buffer sleeve 1 includes a first buffer portion 11 and a second buffer portion 12 connected to each other. The upper surface of the first buffer portion 11 is flush with the upper surface of the second buffer portion 12. The first buffer portion 11 covers the metal pad 4, and the second buffer portion 12 covers the wafer 3. Figure 1 as well as Figure 4 As shown, the buffer sleeve 1 can be considered to consist of two parts: a first buffer part 11 and a second buffer part 12. The dividing line between these two parts can be... Figure 1 as well as Figure 4 The dashed line in the middle.

[0045] As described above, by covering part of the buffer sleeve 1 on the metal pad 4 and part of the buffer sleeve 1 on the wafer 3, the buffer sleeve 1 can effectively cover the interface area between the metal pad 4 and the wafer 3, preventing delamination or interface failure in this stress-sensitive area and improving the overall packaging reliability.

[0046] Furthermore, such as Figure 2 as well as Figure 5As shown, in the bump buffer structure of this utility model, the overlap width of the overlapping area between the upper surface of the first buffer part 11 and the lower surface of the covering part 22 is the first width d1, and the first width d1 satisfies: 13.5um≤d1≤20um.

[0047] As described above, the overlap width d1 between the covering part 22 and the buffer sleeve 1 is greater than or equal to 13.5 μm to ensure sufficient contact area for the buffer sleeve 1 to effectively absorb thermomechanical stress and guarantee the buffering effect of the polymer. Simultaneously, the overlap width d1 between the covering part 22 and the buffer sleeve 1 is less than or equal to 20 μm to avoid stress interference or impact on other structures that may result from excessive coverage.

[0048] Furthermore, such as Figure 2 as well as Figure 5 As shown, in the bump buffer structure of this utility model, the overlap width of the overlapping area between the lower surface of the second buffer part 12 and the upper surface of the wafer 3 is the second width d2, and the second width d2 satisfies: d2≥15um.

[0049] As described above, the overlap width d2 of the overlapping area between the lower surface of the second buffer portion 12 and the upper surface of the wafer 3 is greater than or equal to 15um, thereby ensuring that the buffer sleeve 1 can effectively wrap and protect the edge of the metal pad 4, preventing it from being exposed and becoming the starting point of delamination, and effectively ensuring that the area above the metal pad 4 and the sidewalls bonded to the polymer will not delaminate.

[0050] Application Scenario 2: The area below the buffer sleeve 1 is flat silicon or a large area of ​​metal, such as the area on the back of the 2.5D package interposer where the TSV (Through-Silicon Via) and C4 bump are connected.

[0051] In this application scenario two, such as Figure 6 as well as Figure 7 As shown, a through-silicon via (TSV) 5 can be correspondingly formed on the wafer. The TSV 5 is positioned corresponding to the opening 13, and the TSV 5 is not covered by the buffer sleeve 1. By ensuring that the TSV 5 is not covered by the buffer sleeve 1, it is ensured that the electrical connection point (exposed copper area) on the top of the TSV is not blocked by the buffer sleeve 1, thus avoiding problems such as poor electrical connection that may be caused by the buffer sleeve 1 covering the TSV 5. In application scenario two, the annular buffer sleeve 1 needs to meet the following requirements: Furthermore, such as Figure 7As shown, in the bump buffer structure of the present utility model, the covering width of the upper surface of the buffer sleeve 1 covered by the bump 2 is the third width d3, and the width of the upper surface of the buffer sleeve 1 not covered by the bump 2 is the fourth width d4. Among them, the third width d3 satisfies: d3≥13.5um, and the fourth width d4 satisfies: 20um<d4≤50um.

[0052] From the above description, on the one hand, making the overlapping area width d3 between the buffer sleeve 1 and the bump 2 ≥13.5um ensures that there is a large enough area of polymer to cover the periphery of the TSV, so as to effectively absorb the stress transmitted by the bump 2 and ensure the stress buffering ability of the polymer. It should be noted that the maximum value of the overlapping area width d3 needs to satisfy not touching the copper-exposed position of the through-silicon via. On the other hand, controlling the radial extension width d4 of the part of the buffer sleeve 1 not covered by the bump 2 within the range of 20um < d4 ≤ 50um. This value range can not only ensure that the buffer sleeve 1 extends a sufficient distance outward from the edge of the bump 2 to provide effective support and buffering, but also strictly limit its maximum extension width to avoid obvious warping of the wafer 3 again due to excessive covering area. Therefore, by precisely controlling the covering area, both the buffering effect of the polymer buffer layer can be ensured and the warping degree will not be too large.

[0053] The present utility model also proposes a semiconductor packaging structure, which includes the above-mentioned bump buffer structure. Since this semiconductor packaging structure adopts the above technical solution, it at least has all the technical effects brought by the above technical solution, which will not be elaborated here one by one.

[0054] Please refer to Figure 1 and Figure 4 , Embodiment 1 of the present utility model is: a bump buffer structure, which sequentially includes a wafer 3, a metal pad 4, a buffer sleeve 1, and a bump 2 from bottom to top. There are several buffer sleeves 1 and bumps 2, and the two are arranged in one-to-one correspondence. Specifically: an opening 13 is provided on the buffer sleeve 1, and the buffer sleeve 1 is correspondingly sleeved on the outer periphery of the bump 2 through the opening 13. The following specifically discusses one buffer sleeve 1 and one bump 2, as Figure 1 and Figure 4 As shown, on the upper surface of the wafer 3, there are a metal pad 4 and a buffer sleeve 1, and the buffer sleeve 1 covers the outer peripheral edge of the metal pad 4. A circular opening 13 is provided at the central position of the buffer sleeve 1, so that it can form an overall circular ring structure. In this bump buffer structure, the buffer sleeve 1 covers part of the wafer 3, so that in the thickness direction of the wafer 3, the sum of the projected areas of the buffer sleeve 1 and the opening 13 on the wafer 3 is smaller than the upper surface area of the wafer 3. As Figure 2 and Figure 5As shown, viewed from the direction perpendicular to the upper surface of wafer 3 (i.e., the thickness direction), the projected area of ​​buffer sleeve 1 on wafer 3 is much smaller than the area of ​​the upper surface of wafer 3. In practical applications, the coverage of all buffer sleeves 1 on wafer 3 can be less than 20%.

[0055] In this embodiment, as Figure 1 as well as Figure 4 As shown, the buffer sleeve 1 includes a first buffer part 11 and a second buffer part 12 connected to each other. The upper surface of the first buffer part 11 is flush with the upper surface of the second buffer part 12. The first buffer part 11 is located on the upper surface of the metal pad 4, and the outer side wall of the first buffer part 11 is flush with the outer side wall of the metal pad 4. The second buffer part 12 is located above the wafer 3 and is tightly attached to the outer side wall of the metal pad 4.

[0056] In this embodiment, Figure 1 as well as Figure 4 As shown, the bump 2 includes a lower metallization layer and a solder cap 23, which is located above the lower metallization layer. The lower metallization layer covers a portion of the metal pad 4 and a portion of the buffer sleeve 1. The lower metallization layer can be divided into two parts: an embedded portion 21 and a covering portion 22 connected to each other. The covering portion 22 is located above the embedded portion 21, and the width (i.e., radius) of the covering portion 22 is greater than the width of the embedded portion 21. Figure 1 as well as Figure 4 As shown, the insert 21 is inserted into the opening 13 of the buffer sleeve 1, and the cover 22 extends beyond the lower surface of the insert 21 and covers a portion of the upper surface of the buffer sleeve 1. A welding cap 23 is also provided on the cover 22, such as... Figure 1 as well as Figure 2 As shown, the welding cap 23 is cylindrical, as... Figure 4 as well as Figure 5 As shown, the welding cap 23 is spherical.

[0057] In practical applications, Figure 2 as well as Figure 5 As shown, the overlap width of the overlapping area between the upper surface of the first buffer part 11 and the lower surface of the covering part 22 is the first width d1, which satisfies: 13.5um≤d1≤20um; the overlap width of the overlapping area between the lower surface of the second buffer part 12 and the upper surface of the wafer 3 is the second width d2, which satisfies: d2≥15um.

[0058] Please refer to Figure 6 as well as Figure 7The second embodiment of this utility model is as follows: a bump buffer structure, which includes a wafer 3, a buffer sleeve 1, and bumps 2 from bottom to top. Several buffer sleeves 1 and bumps 2 are provided, and they are arranged in a one-to-one correspondence. Specifically, an opening 13 is provided on the buffer sleeve 1, and the buffer sleeve 1 is fitted onto the outer periphery of the bump 2 through the opening 13. The following describes one of the buffer sleeves 1 and bumps 2 in detail. A through-silicon via (TSV) 5 is provided on the wafer 3. The buffer sleeve 1 is located on the upper surface of the wafer 3, and a circular opening 13 is provided in its center to present a circular shape. That is, the buffer sleeve 1 is a hollow cylinder. The opening 13 is coaxially arranged with the TSV 5, and the radius of the TSV 5 is smaller than the radius of the opening 13, so that the TSV 5 is not covered by the buffer sleeve 1. Figure 6 As shown, in this bump buffer structure, the buffer sleeve 1 covers a portion of the wafer 3 such that, in the thickness direction of the wafer 3, the sum of the projected areas of the buffer sleeve 1 and the opening 13 on the wafer 3 is less than the area of ​​the upper surface of the wafer 3. Viewed from the direction perpendicular to the upper surface of the wafer 3 (i.e., the thickness direction), the projected area of ​​the buffer sleeve 1 on the wafer 3 is much smaller than the area of ​​the upper surface of the wafer 3. In practical applications, the coverage rate of all buffer sleeves 1 on the wafer 3 can be less than 20%. In this embodiment, as Figure 6 As shown, the bump 2 includes a lower metallization layer and a solder cap 23. The solder cap 23 is located above the lower metallization layer and is cylindrical. The lower metallization layer covers a portion of the wafer 3 and a portion of the buffer sleeve 1. The lower metallization layer can be divided into two parts: an embedded portion 21 and a covering portion 22 connected to each other. The covering portion 22 is located above the embedded portion 21, and the width (radius) of the covering portion 22 is greater than the width of the embedded portion 21. Figure 6 As shown, the insert 21 is inserted into the opening 13 of the buffer sleeve 1 to completely cover the bottom of the opening 13, and the lower peripheral surface of the cover 22 covers part of the upper surface of the buffer sleeve 1.

[0059] In practical applications, such as Figure 7 As shown, the width of the upper surface of the buffer sleeve 1 covered by the protrusion 2 is the third width d3, which satisfies: d3≥13.5um; the width of the upper surface of the buffer sleeve 1 not covered by the protrusion 2 is the fourth width d4, which satisfies: 20um<d4≤50um.

[0060] In summary, the bump buffer structure and semiconductor packaging structure provided by this utility model are as follows: (1) This utility model provides an advanced packaging buffer polymer structure design to reduce the thermal stress generated by the buffer polymer after curing, thereby reducing the warpage of wafer 3 and improving the reliability problem caused by polymer delamination and solder joint cracking. That is, it aims to solve the problem of wafer 3 warpage caused by excessive thermal stress after curing of the current buffer polymer. (2) The buffer polymer of this utility model is different from the traditional full-coverage structure. This utility model only retains a ring-shaped buffer polymer under the bump 2, and the buffer polymer in other parts is completely removed by development, so that the coverage of the buffer polymer on the wafer 3 is less than 20%, which greatly reduces the stress influence generated by the polymer during curing shrinkage, thereby effectively controlling the warpage of wafer 3. Compared with the traditional full-coverage structure, in practical applications, the warpage of wafer 3 of this utility model can be reduced by 50% to 70%, thereby reducing the risk of polymer delamination and improving reliability.

[0061] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent modifications made based on the content of this utility model specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of this utility model.

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