Arc suppression device grounding fault point current inhibition capability test circuit and device

Abstract

The utility model relates to arc suppression device inhibits the circuit and device of ability test of ground fault point current, and its circuit includes: the waveform storage unit for storing a variety of fault current waveforms, with the waveform storage unit connection, the information transmission unit for outputting one kind of fault current waveform, with the information transmission unit connection, the conversion unit for converting the fault current waveform of information transmission unit output into analog signal, with the conversion unit connection, the power amplifier unit for connecting the measured arc suppression device to amplify the fault current waveform after conversion and input the amplified fault current waveform to the measured arc suppression device, with the conversion unit connection, the edge calculation unit for connecting the measured arc suppression device to detect the current inhibition parameter of measured arc suppression device. The utility model can simulate and generate the ground fault current under multiple scenes, and send to the measured arc suppression device to detect, improve performance detection efficiency and reduce detection cost.

Description

Technical Field

[0001] This utility model relates to the field of power equipment testing technology, and in particular to a test circuit and device for the ability of an arc suppression device to suppress ground fault current. Background Technology

[0002] Single-phase grounding faults in power grids frequently lead to accidents such as forest fires, electrical equipment burnout, and electric shocks. In particular, arc grounding faults are highly prone to causing secondary accidents such as ferroresonance and phase-to-phase short circuits. Furthermore, the fault current of permanent grounding faults causes step voltages near the fault point, posing a significant threat to the safety of people and livestock.

[0003] Currently, widely used arc suppression devices include arc suppression coils and arc suppression cabinets. After a ground fault occurs, the neutral point voltage is applied to the arc suppression coil, causing it to generate an inductive current that cancels the capacitive current at the ground fault point, making the fault point current less than the arc reignition value, thus achieving the arc suppression effect. However, due to limitations in component characteristics, it can only compensate for the fundamental reactive component and cannot compensate for the active and harmonic components in the ground fault current. The working principle of the arc suppression cabinet is to directly ground the faulty phase through a fast switch, suppressing the ground fault point voltage and making it difficult for the arc at the fault point to reignite. Therefore, whether the performance of the arc suppression device meets the usage requirements is particularly important. Since there is currently a lack of tools that can simulate the fault current during a real-world fault scenario, to ensure safety, arc suppression devices usually need to be sent to a specialized testing institution for performance testing before installation on-site. However, this method has drawbacks such as long testing time, low testing efficiency, and high testing costs. Utility Model Content

[0004] The technical problem to be solved by this utility model is to provide a test circuit and device for the ability of an arc-suppressing device to suppress ground fault current.

[0005] The technical solution adopted by this utility model to solve its technical problem is: constructing a test circuit for the ability of an arc-suppressing device to suppress ground fault current, including: Waveform storage unit for storing various fault current waveforms; An information transmission unit connected to the waveform storage unit for outputting one of the fault current waveforms; A conversion unit connected to the information transmission unit for converting the fault current waveform output by the information transmission unit into an analog signal; Connected to the conversion unit, used to connect to the arc suppression device under test to amplify the converted fault current waveform and input the amplified fault current waveform to the power amplification unit of the arc suppression device under test; An edge computing unit connected to the conversion unit and used to connect the arc suppression device under test to detect the current suppression parameters of the arc suppression device under test.

[0006] Preferably, the waveform storage unit includes multiple storage chip banks; each storage chip bank is used to store one of the fault current waveforms.

[0007] Preferably, the information transmission unit includes a multiplexer U1, a first switch K1, and a second switch K2; the multiple channel input terminals of the multiplexer U1 are connected one-to-one to each of the memory chip banks, the first channel selection terminal of the multiplexer U1 is connected to a set DC voltage via the first switch K1, the second channel selection terminal of the multiplexer U1 is connected to the set DC voltage via the second switch K2, and the output terminal of the multiplexer U1 is connected to the conversion unit.

[0008] Preferably, the number of memory chip banks is three, and the various fault current waveforms include metallic single-phase ground fault current waveform, intermittent arc ground fault current waveform, and high-resistance ground fault current waveform.

[0009] Preferably, the information transmission unit further includes a network communication unit; the network communication unit is connected between the output terminal of the multiplexer U1 and the conversion unit, and the network communication unit is used to send the fault current waveform output by the information transmission unit to the conversion unit.

[0010] Preferably, the conversion unit includes a digital signal conversion module of model Q68AD-GA / D; and / or The power amplification unit includes a power amplification module with model number PCU-100K-AC-4Q-360V-370A.

[0011] Preferably, the edge computing unit includes a sampling module; The sampling module is connected to the conversion unit and the arc suppression device under test. The sampling module is used to acquire the fault current waveform output by the conversion unit and to acquire the compensation current waveform of the arc suppression device under test, so as to obtain the current suppression parameter by subtracting the fault current waveform from the compensation current waveform.

[0012] Preferably, the sampling module includes a first analog-to-digital converter U2, a second analog-to-digital converter U3, a signal converter U4, and a processor U5; The first analog-to-digital converter U2 is connected to the conversion unit, and the first analog-to-digital converter U2 is used to convert the fault current waveform output by the conversion unit into a digital signal; The second analog-to-digital converter U3 is connected to the arc suppression device under test, and the second analog-to-digital converter U3 is used to convert the compensation current waveform into a digital signal; The signal converter U4 is connected to the first analog-to-digital converter U2 and the second analog-to-digital converter U3. The signal converter U4 is used to convert the compensation current waveform and the fault current waveform output by the conversion unit into an LVDS signal. The processor U5 is connected to the signal converter U4. The processor U5 is used to receive the LVDS signal and calculate the current suppression parameter by subtracting the fault current waveform from the compensation current waveform.

[0013] Preferably, the edge computing unit further includes a power supply module; The power supply module includes a first DC power supply S1, a second DC power supply S2, a first varistor RV1, a second varistor RV2, a third varistor RV3, a discharge tube GD, and a capacitor C. The first and second AC input terminals of the first DC power supply S1 are respectively connected to the mains power, and the DC output terminal of the first DC power supply S1 is respectively connected to the first analog-to-digital converter U2, the second analog-to-digital converter U3, the signal converter U4 and the processor U5; The first AC input terminal of the first DC power supply S1 is grounded through the first varistor RV1 and the discharge tube GD. The second AC input terminal of the first DC power supply S1 is connected to one end of the second varistor RV2. The other end of the second varistor RV2 is connected to the node after the first varistor RV1 and the discharge tube GD are connected. The first AC input terminal of the first DC power supply S1 is also connected to the second AC input terminal of the first DC power supply S1 through the third varistor RV3. The capacitor C is connected in parallel with the discharge tube GD. The first AC input terminal of the second DC power supply S2 is connected to the first AC input terminal of the first DC power supply S1, the second AC input terminal of the second DC power supply S2 is connected to the second AC input terminal of the first DC power supply S1, and the DC output terminal of the second DC power supply S2 is connected to the analog power supply terminal of the first analog-to-digital converter U2 and the analog power supply terminal of the second analog-to-digital converter U3.

[0014] This utility model also constructs a test device for the ability of an arc-suppressing device to suppress ground fault current, including the above-described test circuit for the ability of an arc-suppressing device to suppress ground fault current.

[0015] The present invention has the following advantages: it can simulate and generate ground fault currents in multiple scenarios and send them to the arc suppression device under test for detection. It eliminates the need to transport the arc suppression device to the testing institution, and can perform pre-shipment verification or on-site application verification of the arc suppression device under test, which helps to improve the efficiency of performance testing and reduce testing costs. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a circuit structure block diagram of the arc suppression device's ability to suppress ground fault current in some embodiments of this utility model; Figure 2 This is a circuit diagram of the information transmission unit in some embodiments of this utility model; Figure 3 This is a circuit diagram of the sampling module in some embodiments of this utility model; Figure 4 This is a circuit diagram of the power supply module in some embodiments of this utility model. Detailed Implementation

[0017] To provide a clearer understanding of the technical features, objectives, and effects of this utility model, the specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0018] In the following description, it should be understood that the orientations or positional relationships indicated by terms such as "front," "rear," "up," "down," "left," "right," "longitudinal," "horizontal," "vertical," "horizontal," "top," "bottom," "inner," "outer," "head," and "tail" are based on the orientations or positional relationships shown in the accompanying drawings, and are constructed and operated in a specific orientation. They are only for the convenience of describing this technical solution and do not indicate that the device or component referred to must have a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0019] Figure 1 This is a circuit block diagram of a test circuit for the ability of an arc-suppressing device to suppress ground fault current in some embodiments of this utility model. This test circuit can simulate and generate ground fault currents under various scenarios and send them to the arc-suppressing device under test for detection. It eliminates the need to transport the arc-suppressing device to a testing facility, allowing for pre-shipment verification or on-site application verification of the device, thus improving performance testing efficiency and reducing testing costs. The arc-suppressing device can be an existing arc-suppressing device such as an arc-suppressing coil or an arc-suppressing cabinet.

[0020] like Figure 1 As shown, the test circuit for the ability of the arc suppression device to suppress ground fault current may include a waveform storage unit 1, an information transmission unit 2, a conversion unit 3, a power amplification unit 4, and an edge computing unit 5.

[0021] Waveform storage unit 1 is used to store various fault current waveforms. These waveforms can include ground fault currents from scenarios such as metallic single-phase ground fault current waveforms, intermittent arcing ground fault current waveforms, and high-resistance ground fault current waveforms. Taking the metallic single-phase ground fault current waveform as an example, it refers to the fault current waveform corresponding to a metallic single-phase ground fault. The fault current waveforms can be stored in waveform storage unit 1 in digital signal form. It should be noted that each fault current waveform can include information on the change in fault current over a certain period before and after the ground fault occurs. The fault current waveforms can be obtained by recording the current waveform when a real ground fault occurs in the power supply system.

[0022] In some embodiments, such as Figure 2 As shown, the waveform storage unit 1 may include multiple memory chip banks, each used to store a specific fault current waveform. In this embodiment, storing one fault current waveform per memory chip bank facilitates the management and updating of the fault current waveform, and also allows the information transmission unit 2 to select the corresponding fault current waveform for output. Furthermore, the memory chip bank can be a non-volatile memory such as FLASH.

[0023] like Figure 1 As shown, the information transmission unit 2 is connected to the waveform storage unit 1. The information transmission unit 2 is used to output one of the fault current waveforms according to the user's operation.

[0024] In some embodiments, such as Figure 2 As shown, the information transmission unit 2 may include a multiplexer U1, a first switch K1, and a second switch K2. The multiple channel input terminals of the multiplexer U1 are connected one-to-one to each memory chip BANK. The first channel selection terminal of the multiplexer U1 is connected to a set DC voltage via the first switch K1, and the second channel selection terminal of the multiplexer U1 is connected to the set DC voltage via the second switch K2. The output terminal of the multiplexer U1 is connected to the conversion unit 3.

[0025] In this embodiment, the multiplexer U1 can be a CD4051 multiplexer U1. The user can close or open the first switch K1 and / or the second switch K2 to set the level of the first and second channel selection terminals of the multiplexer U1, so that one of the channel input terminals of the multiplexer U1 is connected to its output terminal, thereby connecting one of the memory chips BANK to the conversion unit 3, so that the corresponding digital signal of one of the fault current waveforms is sent to the conversion unit 3.

[0026] In some embodiments, the number of memory chip banks can be three, storing ground fault currents in scenarios such as metallic single-phase ground fault current waveforms, intermittent arc ground fault current waveforms, and high-resistance ground fault current waveforms in a one-to-one manner. Since the multiplexer U1 in this embodiment only uses three input channels, the selection of the three input channels can be achieved simply by operating the first switch K1 and the second switch K2. Therefore, as... Figure 2 The third channel selection terminal of the multiplexer U1 shown can be grounded.

[0027] In some embodiments, the information transmission unit 2 may further include a network communication unit. The network communication unit is connected between the output of the multiplexer U1 and the conversion unit 3, and is used to send the fault current waveform output by the information transmission unit 2 to the conversion unit 3. The network communication unit may include a network interface card (NIC) of model F1002E-BP. Since the testing process involves high current and high voltage signals, posing a risk to the personal safety of personnel, this embodiment conveniently places the first switch K1, the second switch K2, and the waveform storage unit 1 in the monitoring room, while the conversion unit 3, the power amplification unit 4, and the edge computing unit 5 can be placed in the testing room. This allows personnel to operate the first switch K1 and the second switch K2, and update the fault current waveform in the waveform storage unit 1, from the monitoring room, thus achieving remote testing.

[0028] Furthermore, in some embodiments, the information transmission unit 2 may also include an encryption module of model MTL831C, which can improve the security of data transmission.

[0029] like Figure 1 As shown, conversion unit 3 is connected to information transmission unit 2. Conversion unit 3 is used to convert the fault current waveform output by information transmission unit 2 into an analog signal. Understandably, the function of conversion unit 3 is to restore the fault current waveform to an analog signal, preparing for the simulation to generate the fault current waveform.

[0030] In some embodiments, the conversion unit 3 may include a digital signal conversion module of model Q68AD-GA / D. Utilizing the high accuracy of the Q68AD-GA / D, it can reproduce the waveform of a real ground fault as closely as possible, thus improving test accuracy. Of course, the signal conversion module can also be replaced by other signal conversion modules.

[0031] like Figure 1As shown, power amplifier unit 4 is connected to conversion unit 3. Power amplifier unit 4 is used to connect to the arc suppression device under test to amplify the converted fault current waveform and input the amplified fault current waveform to the arc suppression device under test. During ground faults, the fault current is large, and the output power of conversion unit 3 is low. It can only simulate the changing shape of the fault current waveform, but cannot simulate the power of the fault current waveform. The function of power amplifier unit 4 is to amplify the current of the fault current waveform after it has been converted into an analog signal, thereby simulating the output of the fault current waveform.

[0032] In some embodiments, the power amplification unit 4 may include a power amplification module of model PCU-100K-AC-4Q-360V-370A. This model of power amplification module not only meets the high current requirements of the fault current waveform, but also has the advantage of high output accuracy, which helps to highly reproduce the current waveform when a real ground fault occurs.

[0033] like Figure 1 As shown, the edge computing unit 5 is connected to the conversion unit 3. The edge computing unit 5 is used to connect to the arc suppression device under test to detect the current suppression parameters of the arc suppression device. Specifically, some arc suppression devices will feed back a compensation current waveform to characterize the magnitude of its output compensation current when they are working. The closer the compensation current is to the fault current, the better the arc suppression effect. The current suppression parameter can be used to characterize the deviation between the compensation current waveform and the fault current waveform, that is, the current suppression parameter can characterize the arc suppression effect of the arc suppression device under test.

[0034] In some embodiments, the edge computing unit 5 may include a sampling module and a power supply module. The sampling module is connected to the conversion unit 3 and the arc suppression device under test. The sampling module is used to acquire the fault current waveform output by the conversion unit 3 and to acquire the compensation current waveform of the arc suppression device under test, so as to obtain the current suppression parameter by subtracting the fault current waveform from the compensation current waveform. The power supply module is connected to the sampling module to supply power to the sampling module.

[0035] In some embodiments, such as Figure 3 As shown, the sampling module may include a first analog-to-digital converter U2, a second analog-to-digital converter U3, a signal converter U4, and a processor U5.

[0036] The first analog-to-digital converter U2 is connected to the conversion unit 3, and is used to convert the fault current waveform output by the conversion unit 3 into a digital signal. The first analog-to-digital converter U2 can be an ADC7606.

[0037] The second analog-to-digital converter U3 is connected to the arc suppression device under test. U3 is used to convert the compensation current waveform into a digital signal. U3 can be an ADC7606 analog-to-digital converter.

[0038] Signal converter U4 is connected to the first analog-to-digital converter U2 and the second analog-to-digital converter U3. Signal converter U4 converts the compensation current waveform and the fault current waveform output by conversion unit 3 into LVDS signals. Signal converter U4 can be a differential line driver of model ADN4663. Since both the fault current waveform and the compensation current waveform are analog signals, their anti-interference capability is poor and they are easily affected by noise. The function of signal converter U4 is to transmit the compensation current waveform and the fault current waveform to processor U5 in the form of differential signals, which can effectively improve the anti-interference capability of the signal transmission circuit, thereby improving the signal-to-noise ratio.

[0039] For ease of calculation, in some embodiments, the fault current waveform output by the conversion unit 3 is converted to the compensation current waveform output by the arc extinguishing device under test and set to the same sampling rate, which can be from 128 points / cycle to 1024 points / cycle.

[0040] Processor U5 is connected to signal converter U4. Processor U5 receives LVDS signals and calculates the current suppression parameters by subtracting the fault current waveform from the compensation current waveform. In this embodiment, processor U5 can be an existing microprocessor or MCU. It should be noted that the addition and subtraction operations between current waveforms are mature program algorithms, and specific details can be found in existing technologies.

[0041] In some embodiments, such as Figure 4 As shown, the power supply module may include a first DC power supply S1 and a second DC power supply S2, a first varistor RV1, a second varistor RV2, a third varistor RV3, a discharge tube GD, and a capacitor C.

[0042] The first and second AC input terminals of the first DC power supply S1 are connected to the mains power supply, respectively. The DC output terminal of the first DC power supply S1 is connected to the first analog-to-digital converter U2, the second analog-to-digital converter U3, the signal converter U4, and the processor U5, respectively. The first AC input terminal of the first DC power supply S1 is grounded through a varistor RV1 and a discharge tube GD. The second AC input terminal of the first DC power supply S1 is connected to one end of the second varistor RV2. The other end of the second varistor RV2 is connected to the node where the first varistor RV1 and the discharge tube GD are connected. The first AC input terminal of the first DC power supply S1 is also connected to the second AC input terminal of the first DC power supply S1 through a third varistor RV3. The capacitor C is connected in parallel with the discharge tube GD. The first AC input terminal of the second DC power supply S2 is connected to the first AC input terminal of the first DC power supply S1. The second AC input terminal of the second DC power supply S2 is connected to the second AC input terminal of the first DC power supply S1. The DC output terminal of the second DC power supply S2 is connected to the analog power supply terminal of the first analog-to-digital converter U2 and the analog power supply terminal of the second analog-to-digital converter U3. The AC side grounding terminals of the first DC power supply S1 and the second DC power supply S2 are connected to the node after the first varistor RV1 is connected to the discharge tube GD.

[0043] In this embodiment, the first DC power supply S1 and the second DC power supply S2 can be existing AD-DC conversion power supplies. The first DC power supply S1 is used to provide a stable 3.3V DC voltage, and the second DC power supply S2 is used to provide a stable 5V DC voltage (i.e., the set DC voltage). The first varistor RV1, the second varistor RV2, and the third varistor RV3 constitute a structure to prevent the power supply module from being damaged by overvoltage of the input mains power. The capacitor C acts as a filter, filtering out noise superimposed on the mains power and sending it to ground. The discharge tube GD is used to improve the surge current protection performance of the power supply module, preventing surge currents (such as lightning strikes, electromagnetic interference, etc.) from damaging the power supply module.

[0044] In some embodiments, the arc suppression device's ability to suppress ground fault current testing apparatus may further include a display device for displaying current suppression parameters. The display device may be installed in a monitoring room, and the edge computing unit 5 may also be connected to the display device via a network communication unit to feed back the current suppression parameters to the display device.

[0045] This utility model also provides a test device for the ability of an arc-suppressing device to suppress ground fault current, including the test circuit for the ability of an arc-suppressing device to suppress ground fault current provided in the embodiments of this utility model.

[0046] It is understood that the above embodiments only illustrate preferred embodiments of the present utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present utility model patent. It should be noted that for those skilled in the art, the above technical features can be freely combined, and several modifications and improvements can be made without departing from the concept of the present utility model, all of which fall within the protection scope of the present utility model. Therefore, all equivalent transformations and modifications made within the scope of the claims of the present utility model should fall within the coverage of the claims of the present utility model.

Claims

1. A test circuit for the ability of an arc-suppressing device to suppress ground fault current, characterized in that, include: Waveform storage unit for storing various fault current waveforms; An information transmission unit connected to the waveform storage unit for outputting one of the fault current waveforms; A conversion unit connected to the information transmission unit for converting the fault current waveform output by the information transmission unit into an analog signal; Connected to the conversion unit, used to connect to the arc suppression device under test to amplify the converted fault current waveform and input the amplified fault current waveform to the power amplification unit of the arc suppression device under test; An edge computing unit connected to the conversion unit and used to connect the arc suppression device under test to detect the current suppression parameters of the arc suppression device under test.

2. The arc suppression device's ability to suppress ground fault current test circuit according to claim 1, characterized in that, The waveform storage unit includes multiple storage chips (BANK); each storage chip (BANK) is used to store one of the fault current waveforms.

3. The arc suppression device's ability to suppress ground fault current test circuit according to claim 2, characterized in that, The information transmission unit includes a multiplexer U1, a first switch K1, and a second switch K2; the multiple channel input terminals of the multiplexer U1 are connected one-to-one to each of the memory chips BANK, the first channel selection terminal of the multiplexer U1 is connected to a set DC voltage via the first switch K1, the second channel selection terminal of the multiplexer U1 is connected to a set DC voltage via the second switch K2, and the output terminal of the multiplexer U1 is connected to the conversion unit.

4. The arc suppression device's ability to suppress ground fault current test circuit according to claim 3, characterized in that, The number of storage chip banks is 3, and the various fault current waveforms include metallic single-phase ground fault current waveform, intermittent arc ground fault current waveform, and high-resistance ground fault current waveform.

5. The arc suppression device's ability to suppress ground fault current test circuit according to claim 3, characterized in that, The information transmission unit further includes a network communication unit; the network communication unit is connected between the output terminal of the multiplexer U1 and the conversion unit, and the network communication unit is used to send the fault current waveform output by the information transmission unit to the conversion unit.

6. The arc suppression device's ability to suppress ground fault current test circuit according to claim 1, characterized in that, The conversion unit includes a digital signal conversion module of model Q68AD-GA / D; and / or The power amplification unit includes a power amplification module with model number PCU-100K-AC-4Q-360V-370A.

7. The test circuit for the ability of the arc-suppressing device to suppress ground fault current according to any one of claims 3 to 6, characterized in that, The edge computing unit includes a sampling module; The sampling module is connected to the conversion unit and the arc suppression device under test. The sampling module is used to acquire the fault current waveform output by the conversion unit and to acquire the compensation current waveform of the arc suppression device under test, so as to obtain the current suppression parameter by subtracting the fault current waveform from the compensation current waveform.

8. The arc suppression device's ability to suppress ground fault current test circuit according to claim 7, characterized in that, The sampling module includes a first analog-to-digital converter U2, a second analog-to-digital converter U3, a signal converter U4, and a processor U5; The first analog-to-digital converter U2 is connected to the conversion unit, and the first analog-to-digital converter U2 is used to convert the fault current waveform output by the conversion unit into a digital signal; The second analog-to-digital converter U3 is connected to the arc suppression device under test, and the second analog-to-digital converter U3 is used to convert the compensation current waveform into a digital signal; The signal converter U4 is connected to the first analog-to-digital converter U2 and the second analog-to-digital converter U3. The signal converter U4 is used to convert the compensation current waveform and the fault current waveform output by the conversion unit into an LVDS signal. The processor U5 is connected to the signal converter U4. The processor U5 is used to receive the LVDS signal and calculate the current suppression parameter by subtracting the fault current waveform from the compensation current waveform.

9. The arc suppression device's ability to suppress ground fault current test circuit according to claim 8, characterized in that, The edge computing unit also includes a power supply module; The power supply module includes a first DC power supply S1, a second DC power supply S2, a first varistor RV1, a second varistor RV2, a third varistor RV3, a discharge tube GD, and a capacitor C. The first and second AC input terminals of the first DC power supply S1 are respectively connected to the mains power, and the DC output terminal of the first DC power supply S1 is respectively connected to the first analog-to-digital converter U2, the second analog-to-digital converter U3, the signal converter U4 and the processor U5; The first AC input terminal of the first DC power supply S1 is grounded through the first varistor RV1 and the discharge tube GD. The second AC input terminal of the first DC power supply S1 is connected to one end of the second varistor RV2. The other end of the second varistor RV2 is connected to the node after the first varistor RV1 and the discharge tube GD are connected. The first AC input terminal of the first DC power supply S1 is also connected to the second AC input terminal of the first DC power supply S1 through the third varistor RV3. The capacitor C is connected in parallel with the discharge tube GD. The first AC input terminal of the second DC power supply S2 is connected to the first AC input terminal of the first DC power supply S1, the second AC input terminal of the second DC power supply S2 is connected to the second AC input terminal of the first DC power supply S1, and the DC output terminal of the second DC power supply S2 is connected to the analog power supply terminal of the first analog-to-digital converter U2 and the analog power supply terminal of the second analog-to-digital converter U3.

10. A testing device for the ability of an arc-suppressing device to suppress ground fault current, characterized in that, Includes a test circuit for the ability of an arc-suppressing device to suppress ground fault current as described in any one of claims 1 to 9.

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