A test fixture

Abstract

This utility model discloses a test fixture, including an FPGA module, a DA module, an AD module, a power supply module, a serial communication module, a test interface module, and a chip test module. The FPGA module includes an FPGA chip and connected to it a main wave sampling circuit, an active crystal oscillator, a temperature sampling chip, a voltage reference chip, an SPI flash memory, and a P signal input circuit. The serial communication module includes RS-422, RS-232, and RS-485, which are respectively connected to the FPGA chip. The chip test module includes MSOP-0.65, SOP, and SOIC-1.27 test chip pads. The AD module includes an AD conversion chip and its associated voltage reference chip. The test interface module includes a MOSFET driver and interfaces for connecting the circuits in the FPGA module, DA module, AD module, serial communication module, and chip test module to the outside world. The power supply module steps down the external power supply and converts it into the DC power required by each module circuit.

Description

Technical Field

[0001] This utility model belongs to the field of digital circuit testing technology, and specifically relates to a testing fixture. Background Technology

[0002] In the research and development and production of electronic devices today, due to the heterogeneous nature of peripheral device communication interfaces, engineers often need to design dedicated communication interfaces and chips in various package forms for different technical specifications. This process involves complex hardware adaptation and multiple rounds of verification. The traditional testing approach, which involves building a separate test system for each communication interface and chip package, significantly increases the time cost and resource consumption of equipment development.

[0003] In today's electronic devices and production processes, the testing methods, testing pathways, and communication protocols required for each product are different. In this situation, the experimental objectives can only be achieved by designing circuits multiple times. Therefore, test fixtures that can achieve multiple functions are becoming increasingly urgent.

[0004] Patent 202323203902.9 is an FPGA-based 1553B bus automated integrated test system. The FPGA system is connected to the host computer via an Ethernet interface circuit, to a remote interrupt bus monitor via a 1553B bus interface circuit, and to the product under test via a multi-channel analog-to-digital converter. It is applicable to testing large batches of 1553B products and has good practicality.

[0005] Patent 202420714574.4 provides a tool for functional testing of display modules in display products, including a main control module, a power supply module, a serial communication module, a buzzer module, a button module, and a communication interface module. The tool connects to the module under test through the test fixture to measure and analyze the quality of the module. It can also be used for multiple purposes and is small, portable, and easy to operate.

[0006] Patent 202322940979.8 provides an application solution that is compatible with RS-485 circuits and TTL communication circuits. By using a multi-channel switch and optocoupler, the RS-485 circuit and TTL circuit are combined into one, which can achieve the simultaneous satisfaction of the two communication methods by only manufacturing one tooling board.

[0007] Traditional equipment typically only supports a single specific method and cannot simultaneously implement multiple common communication protocols such as RS-422, RS-232, RS-485, and TTL. It cannot simultaneously test multiple external devices such as screens, buttons, and motors, nor can it simultaneously detect multiple common package types such as MSOP-0.65, SOP, and SOIC-1.27.

[0008] Therefore, the need for efficient and accurate testing of multi-channel communication and chips in different packages is becoming increasingly urgent, and a multi-functional testing fixture needs to be designed to meet this need. Utility Model Content

[0009] This invention addresses the shortcomings of existing technologies by providing a testing fixture based on a highly compatible architecture, capable of simultaneously conducting comprehensive testing on multi-channel communication circuits.

[0010] This utility model achieves this objective through the following technical solution:

[0011] A test fixture includes an FPGA module, a DA module, an AD module, a power supply module, a serial communication module, a test interface module, and a chip test module. The FPGA module includes an FPGA chip and connected main wave sampling circuit, an active crystal oscillator, a temperature sampling chip, a voltage reference chip, an SPI flash memory, and a P signal input circuit. The serial communication module includes RS-422, RS-232, and RS-485 connectors, which are respectively connected to the FPGA chip. The chip test module includes MSOP-0.65, SOP, and SOIC-1.27 test chip pads. The AD module includes an AD conversion chip and its associated voltage reference chip. The test interface module includes a MOSFET driver and interfaces connecting the circuits in the FPGA module, DA module, AD module, serial communication module, and chip test module to external devices. The power supply module steps down the external power supply to convert it into the DC power required by each module circuit.

[0012] Furthermore, the main wave sampling circuit of the FPGA module includes a PDXF sampling circuit and a PD sampling circuit. In the PDXF sampling circuit, the external input differential signals PDXF+ and PDXF- are connected to the primary side of the transformer through current-limiting resistors, and the secondary side of the transformer is grounded and outputs a single-ended signal to the FPGA chip, respectively. In the PD sampling circuit, the external input signal PD+ is connected to the FPGA chip through the first capacitor and the first resistor, and the other path is connected to the digital ground through the second resistor. The external input signal PD- is connected to the power supply through the third resistor, and the other path is connected to the digital ground through the second capacitor.

[0013] Furthermore, the transformer model for the main wave sampling circuit is CMW2012-361T2.

[0014] Furthermore, in the P signal input circuit of the FPGA module, the externally input P SIGXF+ and P SIGXF- are connected to the input side of the optocoupler, respectively, and the output side of the optocoupler outputs the P SIG signal to the FPGA chip and ground, respectively.

[0015] Furthermore, the FPGA chip model is EF2L45LG144B.

[0016] Furthermore, the DA converter chip in the DA module is model TPC116S8-TR.

[0017] Furthermore, the AD conversion chip in the AD module is model MS5135N.

[0018] Furthermore, the voltage reference source chip model is RS431AYSF3.

[0019] Furthermore, the MOSFET driver model is UCC27324.

[0020] Furthermore, the SPI flash memory model is GD25Q80.

[0021] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0022] The technical solution provided by this utility model can cover multiple common communication protocols such as RS-422, RS-232, RS-485, and TTL. It can simultaneously test the functions of chips in various common package types, including MSOP-0.65, SOP, and SOIC-1.27. The designed chip test package allows for soldering and testing of different numbers of pins with the same pin pitch, and test points are reserved. This utility model is based on a highly compatible architecture, which can simultaneously conduct comprehensive testing on multiple communication links, covering 3 RS-422 circuits, 3 RS-232 circuits, 2 RS-485 circuits, and 1 TTL circuit, as well as other common communication protocols. It can simultaneously test multiple external devices such as screens, buttons, and motors. It can also test the functions of chips with common package types such as MSOP-0.65, SOP, and SOIC-1.27 by connecting the pins of the chip test module to the reserved IO port of the test interface module. It is also compatible with MSOP4, MSOP8, MSOP16, SOP4, SOP8, and SOP16 chips. Furthermore, it has 8 DA outputs and 2 differential AD acquisition functions, making it a multi-purpose device that saves testing costs and time. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of this utility model;

[0024] Figure 2 This is the circuit diagram of the power module of this utility model;

[0025] Figure 3 This is the peripheral circuit diagram of the FPGA module circuit of this utility model;

[0026] Figure 4 This is the circuit diagram of the FPGA chip for the FPGA module circuit of this utility model;

[0027] Figure 5This is the circuit diagram of the DA module of this utility model;

[0028] Figure 6 This is the circuit diagram of the AD module of this utility model;

[0029] Figure 7 This is the circuit diagram of the serial communication module of this utility model;

[0030] Figure 8 This is the circuit diagram of the test interface module of this utility model;

[0031] Figure 9 This is the circuit diagram of the chip testing module of this utility model. Detailed Implementation

[0032] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art. It should be noted that, without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] This utility model provides a testing fixture, such as Figure 1 As shown, it includes an FPGA module, a DA module, an AD module, a power supply module, a serial communication module, a test interface module, and a chip test module.

[0034] Power module circuit reference Figure 2 It is used to provide the DC power required by each circuit, including a 24V switching power supply module N1, a 12V linear regulator N2, 5V linear regulators V1 and V3, a 3.3V linear regulator V2, and a 1.8V linear regulator U1; the 24V switching power supply module is connected to the 12V linear regulator, the 12V linear regulator is connected to the 5V linear regulator, the 5V linear regulator is connected to the 3.3V linear regulator, and the 3V linear regulator is connected to the 1.8V linear regulator.

[0035] When operating in a specific environment, the input voltage is 24V-28V. The DC24 power supply is then regulated by four linear voltage regulators to output DC power of +12V, +5V, +3.3V, and +1.8V respectively.

[0036] FPGA module circuits such as Figure 3 and Figure 4 This includes the FPGA chip and its peripheral circuits. The FPGA chip U2 model is EF2L45LG144B.

[0037] Pins 7, 16, 30, 36, 37, 51, 66, 72, 79, 88, 102, 108, 123, 129, 135, and 144 of FPGA chip U2 are all connected to a +3.3V power supply.

[0038] Pins 8, 18, 29, 46, 53, 63, 64, 80, 90, 101, 116, 124, and 134 of FPGA chip U2 are all connected to DGND.

[0039] Pins 6, 9, 10, and 11 of FPGA chip U2 are connected to pins 1, 2, 6, and 3 of SPI flash memory U3, respectively. The model of SPI flash memory U3 is GD25Q80.

[0040] Pin 110 of FPGA chip U2 is connected to a +3.3V power supply through resistor R12.

[0041] Pin 120 of FPGA chip U2 is connected to a +3.3V power supply through resistor R13.

[0042] Pins 130, 131, 136, and 137 of FPGA chip U2 are connected to pins 1, 2, 3, and 4 of connector XS1 via resistors R26, R27, R29, and R30, respectively.

[0043] Pins 12, 13, 14, 15, 17, 19, 20, 21, 26, 27, 35, and 59 of the FPGA chip U2 are connected to pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of the header J1 of the interface test module via resistors R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, and R78, respectively.

[0044] Pins 31 and 32 of FPGA chip U2 are connected to pins 4 and 2 of MOSFET driver U7 of interface test module, respectively.

[0045] Pins 33 and 34 of the FPGA chip U2 are connected to pins 4 and 2 of the MOSFET driver U8 of the interface test module, respectively.

[0046] Pins 140 and 141 of the FPGA chip U2 are connected to pins 4 and 2 of the MOSFET driver U6 of the interface test module, respectively.

[0047] Pins 142 and 143 of FPGA chip U2 are connected to pins 4 and 2 of MOSFET driver U9 of interface test module, respectively.

[0048] Pin 28 of FPGA chip U2 is connected to pin 3 of crystal oscillator X1 through resistor R11.

[0049] Pins 22, 23, 24, and 25 of FPGA chip U2 are connected to pins 2 of temperature sensing chips Q2, Q3, Q4, and Q5, respectively.

[0050] Pins 109 and 119 of FPGA chip U2 are connected to the +3.3V power supply through resistors R28 and R31, respectively, and are connected to DGND through capacitors C49 and C50.

[0051] Pins 96 and 97 of FPGA chip U2 are connected to pin C of voltage reference chip V4 through resistor R4, and to pin A of voltage reference chip V4 through capacitor C33.

[0052] Pin 60 of FPGA chip U2 is connected to pin 3 of transformer L4 and resistor R38 respectively. PDXF+ and PDXF- are connected to pin 4 and pin 1 of transformer L4 respectively through resistors R32 and R33. Signal CY0 is output through pin 3 of transformer L4. Pin 2 of transformer L4 is connected to DGND.

[0053] PD+ and PD- are input through pins 1 and 2 of RF connector Q1. PD- is connected to the +5V power supply through resistor R37 and to DGND through capacitor C52. PD+ is connected to DGND through resistor R39. The output signal CY0 is sent to pin 60 of FPGA chip U2 through capacitor C51 and resistor R38.

[0054] Pin 73 of FPGA chip U2 is connected to pin 3 of optocoupler N3. At the same time, pin 3 of optocoupler N3 is connected to the negative terminal of LED D2 through resistor R35. The positive terminal of LED D2 is connected to the +5V power supply. Pin 4 of optocoupler N3 is connected to DGND. Pin 1 of optocoupler N3 is connected to one end of resistor R34 and resistor R36. Pin 2 of optocoupler N3 is connected to the other end of resistor R36 and P SIGXF-. The other end of resistor R34 is connected to P SIGXF+.

[0055] Pin 1 of crystal oscillator X1 is connected to the +3.3V power supply through resistor R10, and pin 2 and DGND are connected through capacitor C35. Pin 4 is connected to the +3.3V power supply. The first end of capacitor C34 is connected to the +3.3V power supply and the second end is connected to DGND. Pin 3 of crystal oscillator X1 is connected to pin 28 of FPGA chip U2 through resistor R11.

[0056] See DA module circuit. Figure 5 The DA converter chip U4 is model TPC116S8-TR.

[0057] Pin 1 of chip U4 is connected to pin 3 of FPGA chip U2, pin 2 of chip U4 is connected to pin 4 of FPGA chip U2, pin 9 of chip U4 is connected to pin 5 of FPGA chip U2, pin 15 of chip U4 is connected to pin 2 of FPGA chip U2, and pin 16 of chip U4 is connected to pin 1 of FPGA chip U2.

[0058] Pins 4, 5, 6, 7, 13, 12, 11, and 10 of chip U4 are connected to pins 1, 2, 3, 4, 5, 6, 7, and 8 of connector XS2, respectively; pins 3 and 8 of chip U4 are connected to the +3.3V power supply, and pin 14 is connected to DGND.

[0059] The AD module circuit is shown below. Figure 6 As shown, the AD conversion chip U5 in the AD module is model MS5135N, and the voltage reference source chip V5 is model RS431AYSF3.

[0060] Pins 1, 6, 19, 24, 25, 28, 29, and 32 of chip U5 are all connected to a 3.3V power supply. Pin 33 of chip U5 is connected to DGND. Pin 21 of chip U5 is connected to DGND through capacitors C53 and C54 respectively. Pin 23 of chip U5 is connected to DGND through resistor R44. Pin 2 of chip U5 is connected to pin 114 of chip U2 in the FPGA module circuit. Pin 3 of chip U5 is connected to pin 107 of chip U2 in the FPGA module circuit. Pin 4 of chip U5 is connected to pin 106 of chip U2 in the FPGA module circuit. Pin 5 of chip U5 is connected to pin 105 of chip U2 in the FPGA module circuit. Pin 7 of chip U5 is connected to pin 104 of chip U2 in the FPGA module circuit. Pin 8 of chip U5 is connected to pin 103 of chip U2 in the FPGA module circuit. Pin 9 of chip U5 is connected to pin 104 of chip U2 in the FPGA module circuit. Pin 100 of chip U2 in module A is connected to pin 99 of chip U2 in FPGA module A, pin 11 of chip U5 is connected to pin 86 of chip U2 in FPGA module A, pin 12 of chip U5 is connected to pin 85 of chip U2 in FPGA module A, pin 13 of chip U5 is connected to pin 82 of chip U2 in FPGA module A, pin 14 of chip U5 is connected to pin 81 of chip U2 in FPGA module A, pin 15 of chip U5 is connected to pin 78 of chip U2 in FPGA module A, pin 16 of chip U5 is connected to pin 77 of chip U2 in FPGA module A, pin 18 of chip U5 is connected to pin 75 of chip U2 in FPGA module A, and pin 20 of chip U5 is connected to pin 74 of chip U2 in FPGA module A.

[0061] The C terminal of chip V5 is connected to pin 21 of chip U5 through resistor R46. The R terminal of chip V5 is connected to the +5V power supply through resistors R47 and R45, and to DGND through resistor R48. The A terminal of chip V5 is connected to the C terminal of chip V5 through capacitor C55.

[0062] See serial communication module Figure 7 As shown, it includes RSM232 chips U10, U15, and U16, RSM485 chips U11 and U13, and RSM422 chips U12, U14, and U17.

[0063] Pin 1 of chips U10, U11, U12, U13, U14, U15, U16, and U17 is connected to the +5V_1 power supply. Pin 2 of chips U10, U11, U12, U13, U14, U15, U16, and U17 is connected to DGND. Pin 5 of chips U12, U14, and U17 is connected to the +3.3V power supply. Pin 6 of chips U12, U14, and U17 is connected to DGND. Pin 7 of chips U12, U14, and U17 is connected to RGND. Pin 8 of chips U10, U15, and U16 is connected to RGND.

[0064] The two ends of capacitors C62, C65, C69, C60, C66, C68, C61, and C64 are connected to pins 1 and 2 of chips U12, U14, U17, U10, U15, U16, U11, and U13, respectively. The two ends of capacitors C63, C67, and C70 are connected to pins 5 and 6 of chips U12, U14, and U17, respectively. The two ends of resistors R61, R63, and R65 are connected to pins 11 and 10 of chips U12, U14, and U17, respectively. The two ends of resistors R62, R64, and R66 are connected to pins 8 and 9 of chips U12, U14, and U17, respectively.

[0065] See the test interface module. Figure 8 As shown, it includes MOSFET driver chips U7, U8, and U9, connectors XS1-XS11, pin headers J1-J10, RF connector Q1, and MOSFET driver model UCC27324.

[0066] Pins 2 and 4 of chip U7 are connected to pins 32 and 31 of FPGA chip U2, respectively; pins 2 and 4 of chip U6 are connected to pins 141 and 140 of FPGA chip U2, respectively; pins 2 and 4 of chip U8 are connected to pins 34 and 33 of FPGA chip U2, respectively; pins 2 and 4 of chip U9 are connected to pins 143 and 142 of FPGA chip U2, respectively; and pins 5 and 7 of chip U7 are connected to pins 4 and 3 of connector XS9 through resistors R52 and R50, respectively. Pins 5 and 7 of chip U6 are connected to pins 8 and 7 of connector XS9 via resistors R51 and R49, respectively. Pins 5 and 7 of chip U8 are connected to pins 2 and 1 of connector XS9 via resistors R57 and R55, respectively. Pins 5 and 7 of chip U9 are connected to pins 6 and 5 of connector XS9 via resistors R58 and R56, respectively. Pin 3 of chips U6, U7, U8, and U9 is connected to DGND, and pin 6 of chips U6, U7, U8, and U9 is connected to the +5V power supply.

[0067] Pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of header J1 are connected to pins 12, 13, 14, 15, 17, 19, 20, 21, 26, 27, 35, and 59 of FPGA chip U2 via resistors R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, and R78, respectively. Pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of header J2 are connected to pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of connector XS8, respectively. Pins 11 and 12; pins 1, 2, and 3 of header J3 are connected to pins 65, 62, and 61 of FPGA chip U2, respectively; pins 4, 5, 6, 7, 8, 9, 10, 11, and 12 of header J3 are connected to pins 1, 2, 3, 4, 5, 6, 7, 8, and 9 of connector XS9, respectively; pins 1, 2, 3, 4, and 5 of header J4 are connected to pins 93, 92, 91, 89, and 87 of FPGA chip U2 through resistors R85, R84, R83, R82, and R81, respectively; pin 7 of header J4 is connected to pin 26 of chip U5 through resistors R79 and R42; pin 6 of header J4 is connected to pin 27 of chip U5 through resistors R80 and R43.

[0068] Pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of connector XS8 are connected to the first terminals of resistors R24, R23, R22, R25, R19, R14, R20, R21, R15, R16, and R18, respectively. The second terminals of resistors R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, and R25 are connected to capacitors C37, C38, and C39, respectively. C40, C41, C42, C43, C44, C45, C46, ​​C47, and C48 are connected to DGND. The second ends of resistors R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, and R25 are respectively connected to pins 112, 125, 126, 127, 128, 111, 115, 117, 94, 84, 83, and 98 of FPGA chip U2.

[0069] Pins 1, 2, and 3 of connector XS3 are connected to pins 8, 7, and 6 of serial communication module U16, respectively. Pins 4, 5, and 6 of connector XS3 are connected to pins 8, 7, and 6 of serial communication module U15, respectively. Pins 7, 8, and 9 of connector XS3 are connected to pins 8, 7, and 6 of serial communication module U10, respectively.

[0070] Pins 1, 2, and 3 of connector XS4 are connected to pins 10, 9, and 8 of serial communication module U13, respectively. Pins 4, 5, and 6 of connector XS4 are connected to pins 10, 9, and 8 of serial communication module U11, respectively. Pins 7 and 8 of connector XS4 are connected to pins 57 and 58 of FPGA chip U2, respectively. Pin 9 of connector XS4 is connected to DGND.

[0071] Pins 1, 2, 3, 4, and 5 of connector XS5 are connected to pins 7, 8, 9, 10, and 11 of serial communication module U14, respectively. Pins 6, 7, 8, 9, and 10 of connector XS5 are connected to pins 7, 8, 9, 10, and 11 of serial communication module U12, respectively.

[0072] Pins 1, 2, 3, 4, and 5 of connector XS6 are connected to pins 7, 8, 9, 10, and 11 of serial communication module U17, respectively.

[0073] Pins 1 and 2 of connector XS7 are connected to the PDXF+ and PDXF- signal output terminals respectively, pins 3 and 4 are connected to the P SIGXF+ and P SIGXF- signal output terminals respectively, and pins 5 to 9 are connected to DGND.

[0074] Pin 1 of connector XS10 is connected to the line output terminal of power module DGND, pin 2 is connected to the +3.3V power output terminal of power module, pin 3 is connected to the +5V power output terminal of power module, and pin 4 is connected to the +12V power output terminal of power module.

[0075] Pin 1 of connector XS11 is connected to the GDN in connection line of the power module, and pin 2 is connected to the VIN+ connection terminal of the power module.

[0076] Pin 1 and pin 2 of RF connector Q1 are connected to the output terminals of PD+ and PD- in the circuit, respectively.

[0077] See chip testing module Figure 9As shown, it includes SOIC-1.27 test chip pad U18, MSOP-0.65 test chip pad U19, and SOP test chip pad U20.

[0078] Chip pad U18 corresponds to pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of the SOIC-1.27 test chip, which are connected to pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of header J5, respectively. Chip pad U18 corresponds to pins 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, and 24 of the SOIC-1.27 test chip, which are connected to pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of header J6, respectively.

[0079] Chip pad U19 corresponds to pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of the MSOP-0.65 test chip, which are connected to pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of header J7, respectively. Chip pad U19 corresponds to pins 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, and 24 of the MSOP-0.65 test chip, which are connected to pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 of header J8, respectively.

[0080] Chip pad U20 corresponds to pins 1, 2, 3, 4, 5, 6, 7, and 8 of the SOP test chip, which are connected to pins 8, 7, 6, 5, 4, 3, 2, and 1 of header J9, respectively. Chip pad U20 corresponds to pins 9, 10, 11, 12, 13, 14, 15, and 16 of the SOP test chip, which are connected to pins 8, 7, 6, 5, 4, 3, 2, and 1 of header J10, respectively.

[0081] The testing fixture of this utility model is used as follows:

[0082] The test demonstration chip is the XDA5541, which is packaged in SOP8. The chip was soldered to pad U20. Referring to the chip's datasheet, its pin definitions are VOUT, AGND, REF, CS, SCLK, DIN, DGND, and VDD. Specifically, pin 1 of pad U20 is VOUT, pin 2 is AGND, pin 3 is REF, pin 4 is CS, pin 13 is SCLK, pin 14 is DIN, pin 15 is DGND, and pin 16 is VDD.

[0083] Connect pin 2 of J9 to pin 6 of XS7 using external cables, connect pin 3 of J9 to pin 2 of XS10, connect pin 4 of J9 to pin 2 of XS10, connect pin 1 of J10 to pin 2 of XS10, connect pin 2 of J10 to pin 7 of XS7, connect pin 3 of J10 to pin 2 of J1, and connect pin 4 of J10 to pin 3 of J1. Test the chip's functionality through FPGA programming.

[0084] The SOIC-1.27-TEST pad U18 can hold chips packaged in SOIC-8, SOIC-14, SOIC-16, and SOIC-24; the MSOP-0.65-TEST pad U19 can hold chips packaged in MSOP8, MSOP10, MSOP14, and MSOP24; and the SOP16-W2.54-TEST pad U20 can hold chips packaged in SOP8, SOP16, and SOP4. Pads U18, U19, and U20 can each hold chips in different packages and perform tests simultaneously.

[0085] This invention enables testing of chips in various common package types, including MSOP-0.65, SOP, and SOIC-1.27, by connecting the pins of the chip test module to the reserved I / O port of the test interface module. It allows for soldering and testing of chips with different pin numbers and pin pitches of the same type, and provides reserved test points. It covers multiple common communication protocols such as RS-422, RS-232, RS-485, and TTL. To overcome the limitations of traditional testing methods, this invention develops an integrated, multi-dimensional testing platform. Its innovation is reflected in three aspects: First, it can simultaneously conduct comprehensive testing on multiple communication links, covering 3 RS-422 circuits, 3 RS-232 circuits, 2 RS-485 circuits, and 1 TTL circuit, among other common communication protocols. It can achieve parallel testing of multiple devices such as display drivers, button testing, and motor control, significantly improving testing efficiency compared to traditional single-function test benches. Second, for testing needs of different packages, it can also interconnect with chip testing modules through programmable I / O interfaces, enabling testing of various common package types such as MSOP-0.65, SOP, and SOIC-1.27, and is compatible with the functions of chips such as MSOP4, MSOP8, MSOP16, SOP4, SOP8, and SOP16. Finally, it also features 8 DA outputs and 2 differential AD acquisition functions, allowing for multiple uses in one machine and saving testing costs and time.

[0086] The present invention has been described in detail above through embodiments, but the content described is only an exemplary embodiment of the present invention and should not be considered as limiting the scope of implementation of the present invention. The protection scope of the present invention is defined by the claims. Any technical solutions designed by those skilled in the art using the technical solutions described in the present invention, or designed by those skilled in the art under the inspiration of the technical solutions of the present invention, within the substance and protection scope of the present invention, to achieve the above-mentioned technical effects, or equivalent changes and improvements made to the scope of the application, should still fall within the patent protection scope of the present invention. It should be noted that, for clarity, descriptions of some components and processes that are not directly and obviously related to the protection scope of the present invention but are known to those skilled in the art have been omitted in the description of the present invention.

Claims

1. A testing fixture, characterized in that, It includes an FPGA module, a DA module, an AD module, a power supply module, a serial communication module, a test interface module, and a chip test module. The FPGA module includes an FPGA chip and its connected main wave sampling circuit, active crystal oscillator, temperature sampling chip, voltage reference chip, SPI flash memory, and P signal input circuit. The serial communication module includes RS-422, RS-232, and RS-485, which are connected to the FPGA chip. The chip test module includes MSOP-0.65, SOP, and SOIC-1.27 test chip pads. The AD module includes an AD conversion chip and its associated voltage reference chip. The test interface module includes MOSFET drivers and interfaces for connecting the circuits in the FPGA module, DA module, AD module, serial communication module, and chip test module to the outside world. The power supply module steps down the external power supply and converts it into the DC power required by each module circuit.

2. The testing fixture according to claim 1, characterized in that, The main wave sampling circuit of the FPGA module includes a PDXF sampling circuit and a PD sampling circuit. In the PDXF sampling circuit, the external input differential signals PDXF+ and PDXF- are connected to the primary side of the transformer through current-limiting resistors, respectively. The secondary side of the transformer is grounded and outputs a single-ended signal to the FPGA chip, respectively. In the PD sampling circuit, the external input signal PD+ is connected to the FPGA chip through the first capacitor and the first resistor, and the other path is connected to the digital ground through the second resistor. The external input signal PD- is connected to the power supply through the third resistor, and the other path is connected to the digital ground through the second capacitor.

3. The testing fixture according to claim 1, characterized in that, The transformer model for the main wave sampling circuit is CMW2012-361T2.

4. The testing fixture according to claim 1, characterized in that, In the P signal input circuit of the FPGA module, the externally input P SIGXF+ and P SIGXF- are connected to the input side of the optocoupler, respectively, and the output side of the optocoupler outputs the P SIG signal to the FPGA chip and ground, respectively.

5. The testing fixture according to claim 1, characterized in that, The FPGA chip model is EF2L45LG144B.

6. The testing fixture according to claim 5, characterized in that, The DA converter chip in the DA module is model TPC116S8-TR.

7. A testing fixture according to claim 6, characterized in that, The AD conversion chip in the AD module is model MS5135N.

8. A test fixture according to claim 7, characterized in that, The voltage reference source chip model is RS431AYSF3.

9. A testing fixture according to claim 8, characterized in that, The MOSFET driver model is UCC27324.

10. A testing fixture according to claim 9, characterized in that, The SPI flash memory model is GD25Q80.

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