A testing system and equipment for power switching devices

Abstract

This disclosure relates to a testing system and equipment for power switching devices. The testing system includes a testing module and a device-under-test (DUT) mounting assembly. The DUT mounting assembly includes a DUT base and at least one anti-interference unit. A first output terminal and a first detection terminal of the testing module are connected to a first end of the DUT base; a second output terminal and a second detection terminal of the testing module are connected to a second end of the DUT base; and a third output terminal and a third detection terminal of the testing module are connected to a third end of the DUT base. At least one of multiple output terminals and multiple detection terminals of the testing module is connected to the DUT base via the anti-interference unit. The anti-interference unit is used to filter out interference information between the testing module and the DUT mounting assembly. This disclosure can eliminate interference information between the testing module and the DUT caused by a long test path through the anti-interference unit, thereby ensuring the accuracy of the testing process for the DUT.

Description

Technical Field

[0001] This disclosure relates to the field of power switching device testing technology, and in particular to a testing system and equipment for power switching devices. Background Technology

[0002] During the testing of power switching devices, any parasitic inductance and capacitance in the test circuit can cause waveform oscillations and voltage spikes in the signal applied to the device under test, thus affecting the accuracy of the test results and even damaging the device. Therefore, how to reduce interference factors during the testing of power switching devices to improve test accuracy has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0003] To solve the above-mentioned technical problems, or at least partially solve them, this disclosure provides a test system and equipment for power switching devices. The test system provided in this disclosure can eliminate interference information between the test module and the device under test caused by the long test path through an anti-interference unit, thereby ensuring the accuracy of the test process for the device under test.

[0004] This disclosure provides a test system for power switching devices, the test system including: a test module and a device under test mounting assembly; The test module includes a first output terminal, a second output terminal, a third output terminal, a first detection terminal, a second detection terminal, and a third detection terminal; the test module is used to detect the performance parameters of the device under test. The device under test (DUT) mounting assembly includes a DUT base and at least one anti-interference unit. The first output terminal and the first detection terminal are connected to the first end of the base of the device under test, the second output terminal and the second detection terminal are connected to the second end of the base of the device under test, and the third output terminal and the third detection terminal are connected to the third end of the base of the device under test. At least one of the multiple output terminals and multiple detection terminals of the test module is connected to the base of the device under test through an anti-interference unit; The device under test (DUT) base is used to house the DUT, and the anti-interference unit is used to filter out interference information between the test module and the DUT mounting components.

[0005] Optionally, at least one anti-interference unit includes at least one of an inductor, a variable resistor, and a variable capacitor.

[0006] Optionally, the anti-interference unit includes at least one inductor; At least one of the multiple output terminals and multiple detection terminals of the test module is connected to the base of the device under test via an inductor. The inductor is used to filter out interference signals between the test module and the device under test on the transmission path.

[0007] Optionally, the inductive device includes at least one of a ferrite bead and a ferrite ring.

[0008] Optionally, the anti-interference unit includes a variable resistor; the first end of the variable resistor is connected to the first output terminal, and the second end of the variable resistor is connected to the first end of the base of the device under test. The first end of the device under test (DUT) base is used to connect to the gate of the DUT; the variable resistor is used to adjust the resistance value in response to the resistance adjustment signal.

[0009] Optionally, the variable resistor device includes a first switching unit, at least one second switching unit, and at least one fixed resistor; the second switching unit corresponds one-to-one with the fixed resistor. The device under test assembly also includes a first control unit; The control terminals of the first and second switching units are connected to the first control unit. The first terminal of the first switching unit is connected to the first output terminal, and the second terminal of the first switching unit is connected to the first terminal of the base of the device under test. The first terminal of the second switching unit is connected to the first output terminal, and the second terminal of the second switching unit is connected to the first terminal of the fixed resistor. The second terminal of the fixed resistor is connected to the first terminal of the base of the device under test. The first control unit is used to provide resistance adjustment signals to the control terminals of the first and second switching units to control the on and off states of the first and second switching units.

[0010] Optionally, the anti-interference unit includes at least one variable capacitor element; The variable capacitor is connected between the first end of the base of the device under test and the second end of the base of the device under test, and / or the variable capacitor is connected between the second end of the base of the device under test and the third end of the base of the device under test. The first end of the device under test (DUT) base is used to connect to the gate of the DUT, the second end of the DUT base is used to connect to the source of the DUT, and the third end of the DUT base is used to connect to the drain of the DUT.

[0011] Optionally, the variable capacitor includes at least one third switching unit and at least one first capacitor; The device under test assembly also includes a second control unit; The control terminal of the third switching unit is connected to the second control unit, and the second terminal of the third switching unit is connected to the first terminal of the first capacitor. The first end of the third switching unit is connected to the first end of the base of the device under test, and the second end of the first capacitor is connected to the second end of the base of the device under test; or, the first end of the third switching unit is connected to the second end of the base of the device under test, and the second end of the first capacitor is connected to the third end of the base of the device under test. The second control unit is used to control the on and off of the third switching unit.

[0012] Optionally, the device under test (DUT) mounting assembly may also include a power module; the power module is used to supply power to the DUT.

[0013] This disclosure also provides a test apparatus for power switching devices, including any of the test systems described above.

[0014] This disclosure provides a testing system and equipment for power switching devices. The testing system includes a testing module and a device-under-test (DUT) mounting assembly. The testing module includes a first output terminal, a second output terminal, a third output terminal, a first detection terminal, a second detection terminal, and a third detection terminal. The testing module is used to detect the performance parameters of the DUT. The DUT mounting assembly includes a DUT base and at least one anti-interference unit. The first output terminal and the first detection terminal are connected to a first end of the DUT base, the second output terminal and the second detection terminal are connected to a second end of the DUT base, and the third output terminal and the third detection terminal are connected to a third end of the DUT base. At least one of the multiple output terminals and multiple detection terminals of the testing module is connected to the testing module through the anti-interference unit. The DUT base is used to accommodate the DUT, and the anti-interference unit is used to filter out interference information between the testing module and the DUT mounting assembly. The test module detects the first pin of the device under test (DUT) through the first output terminal and the first detection terminal, detects the second pin of the DUT through the second output terminal and the second detection terminal, and detects the third pin of the DUT through the third output terminal and the third detection terminal. Furthermore, multiple output terminals and multiple detection terminals of the test module can be connected to the DUT base through an anti-interference unit. The anti-interference unit can filter out interference information between the test module and the DUT mounting components. Therefore, the test system provided in this disclosure can eliminate interference information between the test module and the DUT caused by the long test path through the anti-interference unit, thereby ensuring the accuracy of the DUT testing process. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a test system for a power switching device provided in an embodiment of this disclosure.

[0017] Figure 2 This is a schematic diagram of the structure of a test system for another power switching device provided in an embodiment of this disclosure.

[0018] Figure 3 This is a waveform diagram provided for an embodiment of the present disclosure.

[0019] Figure 4 This is a schematic diagram of the structure of a test system for another power switching device provided in an embodiment of this disclosure.

[0020] Figure 5 This is yet another waveform diagram provided for an embodiment of the present disclosure.

[0021] Figure 6 This is a schematic diagram of the structure of a test system for another power switching device provided in an embodiment of this disclosure.

[0022] Figure 7 This is yet another waveform diagram provided for an embodiment of the present disclosure.

[0023] Figure 8 This is a schematic diagram of the structure of a preferred power switching device test system provided in an embodiment of this disclosure. Detailed Implementation

[0024] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description in order to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples thereof.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The embodiments will now be described in detail with reference to the accompanying drawings.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0027] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0028] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0029] In the embodiments of this application, the term "electrical connection" can refer to two components being directly electrically connected, or it can refer to two components being electrically connected via one or more other components.

[0030] In the embodiments of this application, the first node, the second node, and the third node are defined only for the convenience of describing the circuit structure, and the first node, the second node, and the third node are not actual circuit units.

[0031] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0032] During the testing of power switching devices, any parasitic inductance and capacitance in the test circuit can cause waveform oscillations and voltage spikes in the signal applied to the device under test, thus affecting the accuracy of the test results and even damaging the device. Therefore, how to reduce interference factors during the testing of power switching devices to improve test accuracy has become a technical problem that urgently needs to be solved by those skilled in the art.

[0033] Based on the above-mentioned technical problems, this application provides a testing system and equipment for power switching devices. The embodiments of this application will be described below with reference to the accompanying drawings.

[0034] Figure 1 This is a schematic diagram of the structure of a test system for a power switching device provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the test system for power switching devices includes: a test module 10 and a device under test mounting assembly 20.

[0035] The test module 10 includes a first output terminal 101, a second output terminal 102, a third output terminal 103, a first detection terminal 104, a second detection terminal 105, and a third detection terminal 106.

[0036] The test module 10 is used to detect the performance parameters of the device under test 30.

[0037] For example, the device under test 30 may be a silicon carbide metal oxide semiconductor field-effect transistor (SiCMosFET), and the test module 10 is used to perform avalanche breakdown testing on the SiC MosFET.

[0038] The device under test mounting assembly 20 includes a device under test base 210 and at least one anti-interference unit 220.

[0039] The first output terminal 101 and the first detection terminal 104 are connected to the first end of the device under test (DUT) base 210, the second output terminal 102 and the second detection terminal 105 are connected to the second end of the DUT base 210, and the third output terminal 103 and the third detection terminal 106 are connected to the third end of the DUT base 210. The DUT base 210 is used to accommodate the device under test (DUT) 30.

[0040] For example, the device under test 30 can be mounted on the device under test base 210 by direct plug-in or by soldering. The first output terminal 101, the second output terminal 102, and the third output terminal 103 are used to output test signals to the first, second, and third terminals of the device under test base 210, respectively. The first detection terminal 104, the second detection terminal 105, and the third detection terminal 106 are used to collect the signals output from the first, second, and third terminals of the device under test base 210, respectively, thereby realizing the detection of the performance parameters of the device under test 30.

[0041] At least one of the multiple output terminals and multiple detection terminals of the test module 10 is connected to the base 210 of the device under test through the anti-interference unit 220.

[0042] The anti-interference unit 220 is used to filter out interference information between the test module 10 and the device under test mounting assembly 20.

[0043] For example, the first output terminal 101, the second output terminal 102, the third output terminal 103, the first detection terminal 104, the second detection terminal 105, and the third detection terminal 106 of the test module 10 can all be connected to the device under test (DUT) base 210 through the anti-interference unit 220. Alternatively, one of the first output terminal 101, the second output terminal 102, the third output terminal 103, the first detection terminal 104, the second detection terminal 105, and the third detection terminal 106 can be connected to the DUT base 210 through the anti-interference unit 220. Alternatively, the first output terminal 101 and the first detection terminal 104 can be connected to the DUT base 210 through the anti-interference unit 220, the second output terminal 102 and the second detection terminal 105 can be connected to the DUT base 210 through the anti-interference unit 220, and the third output terminal 103 and the third detection terminal 106 can be connected to the DUT base 210 through the anti-interference unit 220, etc. Figure 1Taking the connection of the first output terminal 101 and the first detection terminal 104 to the device under test (DUT) base 210 via the anti-interference unit 220 as an example, since there is a long test path between the test module 10 and the DUT mounting assembly 20, there are unavoidable parasitic capacitances and inductances along the test path. Therefore, the test signal output from the first output terminal 101 to the first end of the DUT base 210 will oscillate due to the parasitic capacitances and inductances, carrying abnormal interference information. This disclosure provides an anti-interference unit 220 in the DUT mounting assembly 20, which is close to the DUT 30. This allows the anti-interference unit 220 to filter out the interference information caused by waveform oscillations in the test path from the test module 10 to the DUT 30, thereby enabling the DUT mounting assembly 20 to receive accurate test signals. Furthermore, each detection terminal of the test module 10 is connected to a filtering unit, thereby filtering out interference information that also exists in the signals collected from each pin of the device under test (DUT) mounting assembly 20, ensuring that each detection terminal of the test module 10 can receive accurate signals. Therefore, the test system provided in this disclosure can eliminate interference information between the test module 10 and the DUT 30 caused by the long test path through the anti-interference unit 220, thereby ensuring the accuracy of the test process of the DUT 30.

[0044] It should be noted that, Figure 1 The first output terminal 101 and the first detection terminal 104 are shown as examples, connected to the device under test base 210 through the anti-interference unit 220. Other output terminals and detection terminals of the test module 10 can also be connected to the device under test base 210 through the anti-interference unit 220, and no specific limitation is made here.

[0045] In some embodiments, at least one anti-interference unit 220 includes at least one of an inductor, a variable resistor, and a variable capacitor.

[0046] For example, if three anti-interference units 220 are provided, the three anti-interference units 220 can be an inductor, a variable resistor, and a variable capacitor, or they can be two inductors and one variable resistor, or two inductors and one variable capacitor. For example, if two anti-interference units 220 are provided, the two anti-interference units 220 can be an inductor and a variable capacitor, or they can be an inductor and a variable resistor, or they can be a variable resistor and a variable capacitor.

[0047] It should be noted that the number of anti-interference units 220, and the specific type of each anti-interference unit 220 (inductor, variable resistor, or variable capacitor), need to be set according to the actual situation, and no specific limitation is made here.

[0048] In some embodiments, the anti-interference unit 220 includes at least one inductor.

[0049] At least one of the multiple output terminals and multiple detection terminals of the test module 10 is connected to the base 210 of the device under test via an inductor.

[0050] The inductor is used to filter out interference signals between the test module 10 and the device under test 30 on the transmission path.

[0051] For example, taking the multiple output terminals and multiple detection terminals of the test module 10 as examples, all of which are connected to the base 210 of the device under test via inductors, Figure 2 This is a schematic diagram of the structure of a test system for another power switching device provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the first output terminal 101 is connected to the first end of the device under test base 210 through the first inductor 2211, the second output terminal 102 is connected to the second end of the device under test base 210 through the second inductor 2212, the third output terminal 103 is connected to the third end of the device under test base 210 through the third inductor 2213, the first detection terminal 104 is connected to the first end of the device under test base 210 through the fourth inductor 2214, the second detection terminal 105 is connected to the second end of the device under test base 210 through the fifth inductor 2215, and the third detection terminal 106 is connected to the third end of the device under test base 210 through the sixth inductor 2216.

[0052] The first end of the device under test (DUT) base 210 is connected to the gate of the DUT 30, the second end of the DUT base 210 is connected to the source of the DUT 30, and the third end of the DUT base 210 is connected to the drain of the DUT 30. Because self-conduction by free electrons occurs between the source and drain of the DUT 30, it suffers from poor stability and strong Miller feedback. Therefore, this disclosure provides a second inductor 2212 between the second output terminal 102 and the second terminal of the device under test (DUT) base 210, a third inductor 2213 between the third output terminal 103 and the third terminal of the DUT base 210, a fifth inductor 2215 between the second detection terminal 105 and the second terminal of the DUT base 210, and a sixth inductor 2216 between the third detection terminal 106 and the third terminal of the DUT base 210. This enables the effective reduction of electromagnetic interference in the DUT 30 during avalanche testing, thereby improving the DUT 30's immunity to electromagnetic interference and reducing signal oscillations during avalanche testing, thus preventing damage to the DUT 30 due to signal oscillations. Furthermore, this disclosure can also eliminate Miller oscillations of the gate of the device under test 30 by providing a first inductor 2211 between the first output terminal 101 and the first end of the device under test base 210, and a fourth inductor 2214 between the first detection terminal 104 and the first end of the device under test base 210. Figure 3 A waveform diagram provided for an embodiment of this disclosure, such as... Figure 3 As shown, when no inductor is placed between the test module 10 and the device under test (DUT) base 210, referring to the waveform diagram marked A in the attached figure, oscillating waveforms are present in the gate-source voltage VGS, source-drain voltage VDS, and drain current ID. However, when an inductor is placed between the test module 10 and the DUT base 210, referring to the waveform diagram marked B in the attached figure, no oscillating waveforms are present in the gate-source voltage VGS, source-drain voltage VDS, and drain current ID. Therefore, the test system provided in this disclosure can eliminate interference information caused by the long test path between the test module 10 and the DUT 30 through the inductor, thereby ensuring the accuracy of the test process of the DUT 30.

[0053] It should be noted that the connection of multiple output terminals and multiple detection terminals of the test module 10 to the base 210 of the device under test via inductors is only an example. The specific number of inductors connected needs to be set according to the actual situation, and no specific limit is made here.

[0054] In some embodiments, the inductor includes at least one of a magnetic bead and a magnetic ring.

[0055] For example, the inductor can be a ferrite bead, and the output and detection terminals of the test module 10 can be connected in series to the base 210 of the device under test via the ferrite bead. Alternatively, the inductor can be a magnetic ring, and the output and detection terminals of the test module 10 can be connected to the base 210 of the device under test via the magnetic ring. The inductor can also include both a ferrite bead and a magnetic ring; that is, some output and detection terminals of the test module 10 are connected in series to the base 210 of the device under test via the ferrite bead, while other output and detection terminals are connected to the base 210 of the device under test via the magnetic ring.

[0056] In some embodiments, Figure 4 This is a schematic diagram of the structure of a test system for another power switching device provided in an embodiment of this disclosure, as shown below. Figure 4 As shown, the anti-interference unit 220 includes a variable resistor 222; the first end of the variable resistor 222 is connected to the first output terminal 101, and the second end of the variable resistor 222 is connected to the first end of the base 210 of the device under test.

[0057] The first end of the device under test base 210 is used to connect to the gate of the device under test 30; the variable resistor 222 is used to adjust the resistance value in response to the resistance adjustment signal.

[0058] For example, if the gate-source voltage VGS of the device under test 30 oscillates excessively, the gate resistance of the device under test 30 can be increased by the variable resistor 222 to eliminate the strong Miller oscillation. Furthermore, the variable resistor 222 can adjust its resistance value according to a resistance adjustment signal. Therefore, the resistance value can be adjusted multiple times during the testing process to determine the most suitable resistance value to eliminate the strong Miller oscillation. Additionally, the resistance value of the variable resistor 222 can be adjusted to meet the needs of different devices under test 30 in eliminating the strong Miller oscillation. Figure 5 Another waveform diagram provided for an embodiment of this disclosure, such as Figure 5 As shown, when no variable resistor 222 is provided between the test module 10 and the first end of the device under test (DUT) base 210, referring to the waveform diagram marked C, oscillating waveforms are present in the gate-source voltage VGS, source-drain voltage VDS, and drain current ID. However, when a variable resistor 222 is provided between the test module 10 and the first end of the DUT base 210, referring to the waveform diagram marked D, no oscillating waveforms are present in the gate-source voltage VGS, source-drain voltage VDS, and drain current ID. Therefore, in the test system provided in this disclosure, the variable resistor 222 can eliminate interference information and Miller oscillations caused by the long test path between the test module 10 and the DUT 30, thereby ensuring the accuracy of the test process of the DUT 30.

[0059] In some embodiments, see continue to see Figure 4 The variable resistor device 222 includes a first switching unit K1, at least one second switching unit K2, and at least one fixed resistor R; the second switching unit K2 corresponds one-to-one with the fixed resistor R.

[0060] The device under test mounting assembly 20 also includes a first control unit 230.

[0061] The control terminals of the first switching unit K1 and the second switching unit K2 are connected to the first control unit 230. The first end of the first switching unit K1 is connected to the first output terminal 101, and the second end of the first switching unit K1 is connected to the first end of the base 210 of the device under test. The first end of the second switching unit K2 is connected to the first output terminal 110, and the second end of the second switching unit K2 is connected to the first end of the fixed resistor R. The second end of the fixed resistor R is connected to the first end of the base 210 of the device under test.

[0062] The first control unit 230 is used to provide resistance adjustment signals to the control terminals of the first switching unit K1 and the second switching unit K2 to control the on and off of the first switching unit K1 and the second switching unit K2.

[0063] For example, Figure 4 An exemplary diagram illustrates at least four second switching units K2 and at least four fixed resistors R. The four second switching units K2 are connected in series with their respective fixed resistors R, and the resistance values ​​of the four fixed resistors R can be different. When no additional resistance is required at the gate of the device under test 30, the first control unit 230 controls the first switching unit K1 to be turned on, and all second switching units K2 to be turned off. When additional resistance is required at the gate of the device under test 30, the first control unit 230 controls the first switching unit K1 to be turned off. Depending on the required resistance value, the corresponding second switching unit K2 can be turned on. Furthermore, additional resistance values ​​other than those corresponding to the four fixed resistors R can be added to the gate of the device under test 30 by connecting the fixed resistors R in parallel.

[0064] In some embodiments, Figure 6 This is a schematic diagram of the structure of a test system for another power switching device provided in an embodiment of this disclosure, as shown below. Figure 6 As shown, the anti-interference unit 220 includes at least one variable capacitor 223.

[0065] The variable capacitor 223 is connected between the first end of the device under test (DUT) base 210 and the second end of the DUT base 210, and / or, the variable capacitor 223 is connected between the second end of the DUT base 210 and the third end of the DUT base 210.

[0066] The first end of the device under test (DUT) base 210 is used to connect to the gate of the DUT 30, the second end of the DUT base 210 is used to connect to the source of the DUT 30, and the third end of the DUT base 210 is used to connect to the drain of the DUT 30.

[0067] For example, the anti-interference unit 220 may include a variable capacitor 223 connected between a first end and a second end of the device under test (DUT) base 210, thereby filtering the gate and source of the DUT 30 to eliminate oscillations and absorbing gate-source energy when the DUT 30 is turned off. The variable capacitor 223 may also be connected between a second end and a third end of the DUT base 210, thereby filtering the source and drain of the DUT 30 to eliminate oscillations and absorbing source-drain energy when the DUT 30 is turned off. Figure 6 An exemplary drawing shows a variable capacitor 223 connected between the first end of the device under test (DUT) base 210 and the second end of the DUT base 210.

[0068] The anti-interference unit 220 may also include two variable capacitors 223. One variable capacitor 223 is connected between the first end of the device under test (DUT) base 210 and the second end of the DUT base 210, and the other variable capacitor 223 is connected between the second end of the DUT base 210 and the third end of the DUT base 210. This enables filtering between the gate and source of the DUT 30 and between the source and drain to eliminate oscillations, as well as absorption of gate-source energy and source-drain energy when the DUT 30 is turned off.

[0069] The variable capacitor 223 may also be disposed between the first output terminal 101 and the second output terminal 102, or between the first detection terminal 104 and the second detection terminal 105, or between the second output terminal 102 and the third output terminal 103, or between the second detection terminal 105 and the third detection terminal 106.

[0070] Figure 7 Another waveform diagram provided for an embodiment of this disclosure, such as Figure 7As shown, when the device under test (DUT) base 210 is not equipped with the variable capacitor 223, referring to the waveform diagram marked E in the attached figure, oscillating waveforms are present in the gate-source voltage VGS, source-drain voltage VDS, and drain current ID. However, when the DUT base 210 is equipped with the variable capacitor 223, referring to the waveform diagram marked F in the attached figure, no oscillating waveforms are present in the gate-source voltage VGS, source-drain voltage VDS, and drain current ID. Therefore, the test system provided in this disclosure can eliminate interference information and strong Miller oscillations caused by the long test path between the test module 10 and the DUT 30 through the variable capacitor 223, thereby ensuring the accuracy of the test process of the DUT 30.

[0071] In some embodiments, see continue to see Figure 5 The variable capacitor 223 includes at least one third switching unit K3 and at least one first capacitor C.

[0072] The device under test assembly also includes a second control unit 240.

[0073] The control terminal of the third switch unit K3 is connected to the second control unit 240, and the second terminal of the third switch unit K3 is connected to the first terminal of the first capacitor C.

[0074] The first end of the third switching unit K3 is connected to the first end of the device under test base 210, and the second end of the first capacitor C is connected to the second end of the device under test base 210; or, the first end of the third switching unit K3 is connected to the second end of the device under test base 210, and the second end of the first capacitor C is connected to the third end of the device under test base 210.

[0075] The second control unit 240 is used to control the turning on and off of the third switching unit K3.

[0076] For example, Figure 5 An exemplary diagram shows at least one third switching unit K3 comprising three third switching units K3, and at least one first capacitor C comprising three first capacitors C. The third switching unit K3 and the first capacitor C are connected in series in a one-to-one correspondence. The capacitance values ​​of the three first capacitors C can be different. Therefore, when it is necessary to set an additional capacitor to eliminate the oscillation waveform between the gate and the source or between the source and the drain, the corresponding third switching unit K3 can be turned on by the second control unit 240 according to different capacitance value requirements. Furthermore, the capacitance values ​​other than the capacitance values ​​corresponding to the three first capacitors C can be set between the gate and the source or between the source and the drain by connecting the first capacitors C in parallel.

[0077] Figure 8 This is a schematic diagram of the structure of a preferred power switching device test system provided in an embodiment of the present disclosure, as shown below. Figure 8 As shown, the test system for power switching devices includes: a test module 10 and a device under test mounting assembly 20.

[0078] The test module 10 includes a first output terminal 101, a second output terminal 102, a third output terminal 103, a first detection terminal 104, a second detection terminal 105, and a third detection terminal 106.

[0079] The device under test mounting assembly 20 includes a device under test base 210, a first inductor 2211, a second inductor 2212, a third inductor 2213, a fourth inductor 2214, a fifth inductor 221, a sixth inductor 2216, a first control unit 230, a second control unit 240, a variable resistor 222, and a variable capacitor 223.

[0080] The first output terminal 101 is connected to the first end of the device under test (DUT) base 210 via the first inductor 2211; the second output terminal 102 is connected to the second end of the DUT base 210 via the second inductor 2212; the third output terminal 103 is connected to the third end of the DUT base 210 via the third inductor 2213; the first detection terminal 104 is connected to the first end of the DUT base 210 via the fourth inductor 2214; the second detection terminal 105 is connected to the second end of the DUT base 210 via the fifth inductor 2215; and the third detection terminal 106 is connected to the third end of the DUT base 210 via the sixth inductor 2216.

[0081] For example, the first end of the device under test (DUT) base 210 is connected to the gate of the DUT 30, the second end of the DUT base 210 is connected to the source of the DUT 30, and the third end of the DUT base 210 is connected to the drain of the DUT 30. Because self-conduction by free electrons occurs between the source and drain of the DUT 30, there are problems of poor stability and strong Miller feedback. Therefore, this disclosure provides a second inductor 2212 between the second output terminal 102 and the second terminal of the device under test (DUT) base 210, a third inductor 2213 between the third output terminal 103 and the third terminal of the DUT base 210, a fifth inductor 2215 between the second detection terminal 105 and the second terminal of the DUT base 210, and a sixth inductor 2216 between the third detection terminal 106 and the third terminal of the DUT base 210. This enables the effective reduction of electromagnetic interference in the DUT 30 during avalanche testing, thereby improving the DUT 30's immunity to electromagnetic interference and reducing signal oscillations during avalanche testing, thus preventing damage to the DUT 30 due to signal oscillations. Furthermore, this disclosure can also eliminate Miller oscillations of the gate of the device under test 30 by providing a first inductor 2211 between the first output terminal 101 and the first end of the device under test base 210, and a fourth inductor 2214 between the first detection terminal 104 and the first end of the device under test base 210.

[0082] The variable resistor device 222 includes a first switching unit K1, four second switching units K2, and four fixed resistors R.

[0083] The control terminals of the first switching unit K1 and the second switching unit K2 are connected to the first control unit 230. The first end of the first switching unit K1 is connected to the first output terminal 101, and the second end of the first switching unit K1 is connected to the first end of the base 210 of the device under test. The first end of the second switching unit K2 is connected to the first output terminal 110, and the second end of the second switching unit K2 is connected to the first end of the fixed resistor R. The second end of the fixed resistor R is connected to the first end of the base 210 of the device under test.

[0084] The second switching unit K2 is connected in series with each of the four fixed resistors R, and the resistance values ​​of the four fixed resistors R can be different. When no additional resistance is needed at the gate of the device under test 30, the first control unit 230 controls the first switching unit K1 to be turned on, and all the second switching units K2 to be turned off. When an additional resistance is needed at the gate of the device under test 30, the first control unit 230 controls the first switching unit K1 to be turned off, and can control the corresponding second switching unit K2 to be turned on according to different resistance requirements. Furthermore, the fixed resistors R can be connected in parallel to add a resistance value to the gate of the device under test 30 that is not equal to the resistance values ​​corresponding to the four fixed resistors R.

[0085] The variable capacitor 223 includes a third switching unit K3 and three first capacitors C.

[0086] The variable capacitor 223 is connected between the first end of the device under test (DUT) base 210 and the second end of the DUT base 210, and / or, the variable capacitor 223 is connected between the second end of the DUT base 210 and the third end of the DUT base 210.

[0087] The third switching unit K3 is connected in series with the first capacitor C in a one-to-one correspondence. The capacitance values ​​of the three first capacitors C can be different. Therefore, if it is necessary to set an additional capacitor to eliminate the oscillation waveform between the gate and the source or between the source and the drain, the corresponding third switching unit K3 can be turned on by the second control unit 240 according to the different capacitance value requirements. In addition, the capacitance values ​​other than the capacitance values ​​corresponding to the three first capacitors C can be set between the gate and the source or between the source and the drain by connecting the first capacitors C in parallel.

[0088] This disclosure includes an anti-interference unit 220 in the device under test (DUT) mounting assembly 20, located close to the DUT 30. This anti-interference unit 220 filters out interference caused by waveform oscillations in the test path from the test module 10 to the DUT 30, ensuring the DUT mounting assembly 20 receives accurate test signals. Furthermore, each detection terminal of the test module 10 is connected to a filtering unit, which filters out interference also present in the signals collected from each pin of the DUT mounting assembly 20, ensuring each detection terminal of the test module 10 receives accurate signals. Therefore, the test system provided by this disclosure can eliminate interference caused by the long test path between the test module 10 and the DUT 30 through the anti-interference unit 220, thereby ensuring the accuracy of the DUT 30 testing process.

[0089] In some embodiments, the device under test (DUT) mounting assembly further includes a power module.

[0090] Specifically, the power module is connected to the base of the device under test (DUT) and is used to supply power to the DUT so that it can function properly.

[0091] In some embodiments, the device under test mounting assembly further includes a filtering unit.

[0092] Specifically, the filtering unit is used to eliminate interference signals between various circuit components in the assembly of the device under test.

[0093] This disclosure also provides a test device for power switching devices, which includes the test system provided in any of the above embodiments.

[0094] It is understood that the test equipment for power switching devices provided in this application embodiment can achieve the corresponding beneficial effects of the test system for power switching devices provided in the above embodiments, which will not be elaborated here.

[0095] The above are merely specific embodiments of this disclosure, enabling those skilled in the art to understand or implement this disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A testing system for power switching devices, characterized in that, include: The test module includes a first output terminal, a second output terminal, a third output terminal, a first detection terminal, a second detection terminal, and a third detection terminal; wherein, the test module is used to detect the performance parameters of the device under test; The device under test (DUT) mounting assembly includes a DUT base and at least one anti-interference unit. The first output terminal and the first detection terminal are connected to the first end of the base of the device under test, the second output terminal and the second detection terminal are connected to the second end of the base of the device under test, and the third output terminal and the third detection terminal are connected to the third end of the base of the device under test. At least one of the multiple output terminals and multiple detection terminals of the test module is connected to the base of the device under test through the anti-interference unit. The device under test (DUT) base is used to accommodate the DUT, and the anti-interference unit is used to filter out interference information between the test module and the DUT mounting assembly.

2. The testing system according to claim 1, characterized in that, At least one of the anti-interference units includes at least one of an inductor, a variable resistor, and a variable capacitor.

3. The testing system according to claim 2, characterized in that, The anti-interference unit includes at least one of the aforementioned inductors; At least one of the multiple output terminals and multiple detection terminals of the test module is connected to the base of the device under test through the inductor. The inductor is used to filter out interference signals between the test module and the device under test on the transmission path.

4. The testing system according to claim 3, characterized in that, The inductor includes at least one of a magnetic bead and a magnetic ring.

5. The testing system according to claim 2, characterized in that, The anti-interference unit includes the variable resistor device; the first end of the variable resistor device is connected to the first output terminal, and the second end of the variable resistor device is connected to the first end of the base of the device under test. The first end of the device under test (DUT) base is used to connect to the gate of the DUT; the variable resistor is used to adjust the resistance value in response to the resistance adjustment signal.

6. The testing system according to claim 5, characterized in that, The variable resistor device includes a first switching unit, at least one second switching unit, and at least one fixed resistor; the second switching unit corresponds one-to-one with the fixed resistor. The device under test mounting assembly also includes a first control unit; The control terminals of the first and second switching units are connected to the first control unit. The first terminal of the first switching unit is connected to the first output terminal, and the second terminal of the first switching unit is connected to the first terminal of the base of the device under test. The first terminal of the second switching unit is connected to the first output terminal, and the second terminal of the second switching unit is connected to the first terminal of the fixed resistor. The second terminal of the fixed resistor is connected to the first terminal of the base of the device under test. The first control unit is used to provide resistance adjustment signals to the control terminals of the first switching unit and the second switching unit to control the opening and closing of the first switching unit and the second switching unit.

7. The testing system according to claim 2, characterized in that, The anti-interference unit includes at least one variable capacitor; The variable capacitor is connected between the first end of the base of the device under test and the second end of the base of the device under test, and / or the variable capacitor is connected between the second end of the base of the device under test and the third end of the base of the device under test. The first end of the device under test (DUT) base is used to connect to the gate of the DUT, the second end of the DUT base is used to connect to the source of the DUT, and the third end of the DUT base is used to connect to the drain of the DUT.

8. The testing system according to claim 7, characterized in that, The variable capacitor includes at least one third switching unit and at least one first capacitor; The device under test mounting assembly also includes a second control unit; The control terminal of the third switching unit is connected to the second control unit, and the second terminal of the third switching unit is connected to the first terminal of the first capacitor. The first terminal of the third switching unit is connected to the first terminal of the base of the device under test, and the second terminal of the first capacitor is connected to the second terminal of the base of the device under test. Alternatively, the first end of the third switching unit is connected to the second end of the base of the device under test, and the second end of the first capacitor is connected to the third end of the base of the device under test. The second control unit is used to control the on and off states of the third switching unit.

9. The testing system according to claim 1, characterized in that, The device under test (DUT) mounting assembly also includes a power module; the power module is used to supply power to the DUT.

10. A testing device for a power switching device, characterized in that, Includes the test system as described in any one of claims 1-9.

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