A segmented temperature-compensated bandgap reference circuit with adjustable low-temperature drift

Abstract

This utility model relates to the field of analog integrated circuit design technology, specifically disclosing a segmented temperature-compensated bandgap reference circuit with adjustable low temperature drift. It includes a startup circuit, a first-order temperature compensation voltage circuit, a first-order temperature compensation current circuit, and a segmented temperature compensation voltage circuit. The startup circuit injects a target current into the first-order temperature compensation voltage circuit upon power-up, causing the first-order temperature compensation voltage circuit to move away from its degeneracy point. The first-order temperature compensation voltage circuit provides the bandgap reference voltage and provides bias current to both the first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit. The first-order temperature compensation current circuit provides a reference current and provides bias current to the segmented temperature compensation voltage circuit. The segmented temperature compensation voltage circuit superimposes the generated compensation voltage onto the bandgap reference voltage to further reduce the temperature coefficient of the bandgap reference voltage. This utility model can reduce the temperature drift of the bandgap reference voltage.

Description

Technical Field

[0001] This utility model relates to the field of analog integrated circuit design technology, and more specifically, to a segmented temperature-compensated bandgap reference circuit with adjustable low-temperature drift. Background Technology

[0002] Bandgap reference circuits, as an important component of analog integrated circuit systems, are widely used in various high-precision chips, such as power management chips, high-precision sensor chips, and high-precision ADCs, because they can provide a bandgap reference voltage independent of power supply voltage and temperature. Bandgap reference circuits typically provide a high-precision reference voltage for other modules; therefore, the accuracy of the bandgap reference voltage affects the accuracy of other modules. Traditional bandgap references usually employ a first-order temperature compensation method. The basic principle is to add a negative temperature coefficient voltage to a weighted, adjustable positive temperature coefficient voltage to eliminate the first-order temperature term, thereby obtaining a bandgap reference voltage that is approximately independent of temperature.

[0003] In reality, because the negative temperature coefficient voltage of a device is not an ideal first-order negative temperature coefficient voltage, but rather exhibits higher-order curvature, the resulting bandgap reference voltage has a higher-order temperature coefficient, affecting the accuracy of the bandgap reference. To improve the accuracy of the bandgap reference, higher-order compensation is required in the circuit design. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a segmented temperature-compensated bandgap reference circuit with adjustable low-temperature drift. Based on first-order temperature compensation, the bandgap reference voltage is compensated in segments at high and low temperatures, thereby improving the accuracy of the bandgap reference voltage through temperature correction and achieving lower temperature drift.

[0005] As a first aspect of this utility model, a segmented temperature-compensated bandgap reference circuit with adjustable low temperature drift is provided. The segmented temperature-compensated bandgap reference circuit with adjustable low temperature drift includes a startup circuit, a first-order temperature compensation voltage circuit, a first-order temperature compensation current circuit, and a segmented temperature compensation voltage circuit. The startup circuit is connected to the first-order temperature compensation voltage circuit. The first-order temperature compensation voltage circuit is connected to both the first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit. The first-order temperature compensation current circuit is connected to the segmented temperature compensation voltage circuit. The startup circuit is used to inject a target current into the first-order temperature compensation voltage circuit when it is powered on, so that the first-order temperature compensation voltage circuit is removed from the degeneracy point. The first-order temperature compensation voltage circuit is used to provide a bandgap reference voltage that has been offset by the first-order temperature coefficient, and to provide PTAT bias current for the first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit, respectively. The first-order temperature compensation current circuit is used to provide a reference current that has offset the first-order temperature coefficient and to provide a low-temperature drift bias current for the segmented temperature compensation voltage circuit. The segmented temperature compensation voltage circuit is used to generate a compensation voltage and superimpose the compensation voltage onto the bandgap reference voltage to further reduce the temperature coefficient of the bandgap reference voltage.

[0006] Further, the startup circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, and a second resistor R2. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to the power supply voltage VREF. The gate of the first PMOS transistor MP1 is connected to the power supply ground GND. The drain of the first PMOS transistor MP1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the drain of the first NMOS transistor MN1. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected and... Furthermore, it is connected to the drain of the first NMOS transistor MN1, the source of the first NMOS transistor MN1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the power ground GND, the source of the second NMOS transistor MN2 is connected to the first-order temperature compensation voltage circuit, the second PMOS transistor MP2 and the third PMOS transistor MP3 form a current mirror, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 are connected and connected to the drain of the second PMOS transistor MP2, and the drain of the third PMOS transistor MP3 is connected to the first-order temperature compensation voltage circuit.

[0007] Further, the first-order temperature compensation voltage circuit includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first transistor QN1, a second transistor QN2, a third transistor QN3, a third resistor R3, a trimming resistor Rtrim, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7. The fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 form a current mirror. The source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5, and the first PMOS transistor MP7... The drains of all five NMOS transistors MN5 are connected to the power supply voltage VREF. The drain of the fourth PMOS transistor MP4 is connected to the source of the sixth PMOS transistor MP6. The drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7. The gates of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are connected to each other and to the drain of the seventh PMOS transistor MP7. The drain of the sixth PMOS transistor MP6 is connected to the drain of the third NMOS transistor MN3 and to the drain of the third PMOS transistor MP3. The drain of the seventh PMOS transistor MP7 is connected to the drain of the fourth NMOS transistor MN4. The first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit are connected to each other respectively. The gate of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5, and the drain of the third NMOS transistor MN3 are connected together. The source of the third NMOS transistor MN3 is connected to the collector of the first transistor QN1. The emitter, base, and collector of the third transistor QN3 are connected together and connected to the collector of the first transistor QN1. The source of the fourth NMOS transistor MN4 is connected to the collector of the second transistor QN2. The base of the first transistor QN1 is connected to the base of the second transistor QN2 and connected to the source of the fifth NMOS transistor MN5. The emitter of transistor QN1 is connected to the second end of the third resistor R3. The emitter of the second transistor QN2 is connected to the first end of the third resistor R3 and to the source of the second NMOS transistor MN2. The second end of the third resistor R3 is connected to the first end of the trimming resistor Rtrim. The second end of the trimming resistor Rtrim is connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to the power ground GND. The source of the fifth NMOS transistor MN5 is connected to the first end of the fifth resistor R5. The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6. The second end of the sixth resistor R6 is connected to the first end of the seventh resistor R7. The second end of the seventh resistor R7 is connected to the power ground GND.

[0008] Furthermore, the area ratio of the emitter of the first transistor QN1 to the emitter of the second transistor QN2 is 1:8, and the third transistor QN3 is introduced into the collector of the first transistor QN1, so the area ratio of the emitter of the first transistor QN1 to the emitter of the third transistor QN3 is 1:7.

[0009] Furthermore, the bandgap reference voltage provided by the first-order temperature compensation voltage circuit for: ; In the formula, This is the difference between the base-emitter voltage of the first transistor QN1 and the base-emitter voltage of the second transistor QN2. This is the voltage between the base and emitter of the first transistor QN1. To adjust the resistance value of resistor Rtrim, This is the resistance value of the fourth resistor, R4. This is the resistance value of the third resistor, R3.

[0010] Furthermore, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 constitute a voltage divider resistor, which is used to divide the bandgap reference voltage. Perform voltage division and convert the divided voltage to voltage. and voltage The output is sent to the segmented temperature compensation voltage circuit; the current mirror composed of the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 is used to provide the bias voltage. Its gate is connected to several sets of current mirrors to generate the PTAT bias current.

[0011] Further, the first-order temperature compensation current circuit includes an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, and an eighth resistor R8. The sources of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both connected to the power supply voltage VREF. The drain of the eighth PMOS transistor MP8 is connected to the source of the tenth PMOS transistor MP10. The gate of the eighth PMOS transistor MP8 is connected to the gate of the tenth PMOS transistor MP10 and also connected to the drain of the seventh PMOS transistor MP7. The collector of the fourth transistor QN4, the base of the sixth transistor QN6, the base of the seventh transistor QN7, and the drain of the tenth PMOS transistor MP10 are connected... The emitters of the fourth transistor QN4 and the fifth transistor QN5, and the second terminal of the eighth resistor R8 are all connected to the power supply ground GND. The bases of the fourth transistor QN4 and the fifth transistor QN5, the first terminal of the eighth resistor R8, and the emitter of the sixth transistor QN6 are connected together. The collector of the fifth transistor QN5 is connected to the emitter of the seventh transistor QN7. The collectors of the sixth transistor QN6 and the seventh transistor QN7, and the drain of the eleventh PMOS transistor MP11 are connected together. The drain of the ninth PMOS transistor MP9 is connected to the source of the eleventh PMOS transistor MP11. The gates of the ninth PMOS transistor MP9, the gates of the eleventh PMOS transistor MP11, and the drain of the eleventh PMOS transistor MP11 are connected together and connected to the segmented temperature compensation voltage circuit.

[0012] Furthermore, the reference current provided by the first-order temperature compensation current circuit for: ; In the formula, This is the PTAT bias current. This is the voltage between the base and emitter of the fourth transistor QN4. This is the resistance value of the eighth resistor, R8; The current mirror formed by the ninth PMOS transistor MP9 and the eleventh PMOS transistor MP11 is used to provide the bias voltage. Its gate is connected to several sets of current mirrors to generate the reference current. .

[0013] Further, the segmented temperature compensation voltage circuit includes a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a twenty-first PMOS transistor MP21, and a ninth resistor R9. The sources of the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, and the sixteenth PMOS transistor MP16 are also mentioned. All are connected to the power supply voltage VREF. The drain of the twelfth PMOS transistor MP12 is connected to the source of the fourteenth PMOS transistor MP14. The drain of the thirteenth PMOS transistor MP13 is connected to the source of the fifteenth PMOS transistor MP15. The drain of the sixteenth PMOS transistor MP16 is connected to the source of the seventeenth PMOS transistor MP17. The gates of the twelfth PMOS transistor MP12, the fourteenth PMOS transistor MP14, the thirteenth PMOS transistor MP13, and the fifteenth PMOS transistor MP15 are all connected to the gate of the seventh PMOS transistor MP7. The gates of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17 are both connected to the gate of the eleventh PMOS transistor MP11. The drain of the fourteenth PMOS transistor MP14 is connected to the source of the eighteenth PMOS transistor MP18. The drain of the fifteenth PMOS transistor MP15 is connected to the first terminal of the ninth resistor R9. The drain of the seventeenth PMOS transistor MP17 is connected to the source of the twentieth PMOS transistor MP20. The source of the eighteenth PMOS transistor MP18 is connected to the source of the nineteenth PMOS transistor MP19. The twentieth PMOS transistor MP20... The source of the transistor is connected to the source of the twenty-first PMOS transistor MP21. The gate of the eighteenth PMOS transistor MP18 is connected to the first end of the sixth resistor R6. The gates of the nineteenth PMOS transistor MP19 and the twentieth PMOS transistor MP20 are both connected to the first end of the ninth resistor R9. The drains of the eighteenth PMOS transistor MP18 and the twentieth PMOS transistor MP20 are both connected to the first end of the fourth resistor R4. The drains of the nineteenth PMOS transistor MP19, the twenty-first PMOS transistor MP21, and the second end of the ninth resistor R9 are all connected to the power supply ground GND.

[0014] Furthermore, the compensation voltage generated by the segmented temperature compensation voltage circuit for: ; In the formula, To compensate for the current, This is the resistance value of the fourth resistor, R4; The compensation voltage Superimposed on the bandgap reference voltage The corrected bandgap reference voltage is obtained from the above. for: .

[0015] The segmented temperature-compensated bandgap reference circuit with adjustable low temperature drift provided by this utility model has the following advantages: By using a segmented temperature-compensated voltage circuit, a parabolic temperature characteristic voltage with an upward opening is superimposed on the first-order compensation downward-opening parabolic temperature characteristic voltage, which is used to further reduce the temperature coefficient of the bandgap reference voltage, thereby reducing the temperature drift of the bandgap reference voltage. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the following detailed description to explain the present invention, but do not constitute a limitation thereof.

[0017] Figure 1 This is a schematic diagram of the structure of this utility model.

[0018] Figure 2 This is a schematic diagram of the voltage characteristics of this utility model.

[0019] Figure 3 This is a schematic diagram of the output of the bandgap reference voltage of this invention under the TT process angle.

[0020] Figure 4 This is a schematic diagram of the output of the bandgap reference voltage of this invention after adjustment at the FF process angle.

[0021] Figure 5 This is a schematic diagram of the output of the bandgap reference voltage of this invention after adjustment under the SS process angle. Detailed Implementation

[0022] To further illustrate the technical means and effects adopted by this utility model to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a segmented temperature compensation bandgap reference circuit with adjustable low-temperature drift proposed according to this utility model. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the protection scope of this utility model.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the utility model described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0024] In explaining this utility model, it should be noted that the terms "installation," "connection," and "linking" should be interpreted broadly unless otherwise specified. For example, a connection can be a fixed connection, a connection through a special interface, or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0025] This embodiment provides a segmented temperature-compensated bandgap reference circuit with adjustable low-temperature drift, such as... Figure 1 As shown, the adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit includes a startup circuit 1, a first-order temperature compensation voltage circuit 2, a first-order temperature compensation current circuit 3, and a segmented temperature compensation voltage circuit 4. The startup circuit 1 is connected to the first-order temperature compensation voltage circuit 2. The first-order temperature compensation voltage circuit 2 is connected to both the first-order temperature compensation current circuit 3 and the segmented temperature compensation voltage circuit 4. The first-order temperature compensation current circuit 3 is connected to the segmented temperature compensation voltage circuit 4. The output terminal of the segmented temperature compensation voltage circuit 4 is connected to the first-order temperature compensation voltage circuit 2. The starting circuit 1 is used to inject a target current into the first-order temperature compensation voltage circuit 2 when powered on. This causes the first-order temperature compensation voltage circuit 2 to move away from the degeneracy point; The first-order temperature compensation voltage circuit 2 is used to provide a bandgap reference voltage that has compensated for the first-order temperature coefficient. The first-order temperature compensation current circuit 2 provides PTAT bias current to the first-order temperature compensation current circuit 3 and the segmented temperature compensation voltage circuit 4, respectively; wherein, the first-order temperature compensation voltage circuit 2 provides PTAT bias current to the first-order temperature compensation current circuit 3. The first-order temperature compensation voltage circuit 2 provides the PTAT bias current to the segmented temperature compensation voltage circuit 4. and PTAT bias current ; The first-order temperature compensation current circuit 3 is used to provide a reference current that has compensated for the first-order temperature coefficient. And provide a low-temperature drift bias current for the segmented temperature compensation voltage circuit 4. ; The segmented temperature compensation voltage circuit 4 is used to generate a compensation voltage and superimpose the compensation voltage onto the bandgap reference voltage to further reduce the bandgap reference voltage. Temperature coefficient.

[0026] Preferably, the startup circuit 1 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, and a second resistor R2. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to the power supply voltage VREF. The gate of the first PMOS transistor MP1 is connected to the power supply ground GND. The drain of the first PMOS transistor MP1 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the drain of the first NMOS transistor MN1. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected... The first NMOS transistor MN1 is connected to its drain. The source of the first NMOS transistor MN1 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the power ground GND. The source of the second NMOS transistor MN2 is connected to the first-order temperature compensation voltage circuit 2. The second PMOS transistor MP2 and the third PMOS transistor MP3 form a current mirror. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2. The gate of the second PMOS transistor MP2 is connected to the gate of the third PMOS transistor MP3 and is also connected to the drain of the second PMOS transistor MP2. The drain of the third PMOS transistor MP3 is connected to the first-order temperature compensation voltage circuit 2.

[0027] It should be noted that in startup circuit 1, if the first-order temperature compensation voltage circuit 2 is at its degeneracy point when the power supply voltage VREF is applied, then as follows: Figure 1 shown As the power supply ground, when the power supply voltage VREF > VTHN1, since the second resistor R2 is very small, the current flowing through the first resistor R1 is... for: ; Wherein, VTHN1 is the threshold voltage of the first NMOS transistor MN1; It is the gate-source voltage of the first NMOS transistor MN1; because As the power supply ground, the second resistor R2 is very small. The first NMOS transistor MN1 and the second NMOS transistor MN2 are approximately equivalent to current mirrors, and the width-to-length ratio of the first NMOS transistor MN1 and the second NMOS transistor MN2 is the same. Since the second PMOS transistor MP2 and the third PMOS transistor MP3 form a current mirror, then: ; The target current for the first-order temperature compensation voltage circuit 2 is: When the target current is injected When a certain value is reached, the first-order temperature compensation voltage circuit 2 is removed from the degeneracy point, and then... The rise causes the second NMOS transistor MN2 to turn off, thereby increasing the target current. The value is zero, so it has no additional effect on the first-order temperature compensation voltage circuit 2.

[0028] Preferably, the first-order temperature compensation voltage circuit 2 includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first transistor QN1, a second transistor QN2, a third transistor QN3, a third resistor R3, a trimming resistor Rtrim, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7. The fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 form a current mirror. The source of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5... The source of the fourth PMOS transistor MP4 and the drain of the fifth PMOS transistor MP5 are both connected to the power supply voltage VREF. The drain of the fourth PMOS transistor MP4 is connected to the source of the sixth PMOS transistor MP6. The drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7. The gates of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are connected to the gate and the drain of the seventh PMOS transistor MP7. The drain of the sixth PMOS transistor MP6 is connected to the drain of the third NMOS transistor MN3 and the drain of the third PMOS transistor MP3. The drain of the seventh PMOS transistor MP7 is connected to the source of the fourth PMOS transistor MP4. The drain of NMOS transistor MN4 is connected to the first-order temperature compensation current circuit 3 and the segmented temperature compensation voltage circuit 4, respectively. The gates of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the drain of the third NMOS transistor MN3 are connected together. The source of the third NMOS transistor MN3 is connected to the collector of the first transistor QN1. The emitter, base, and collector of the third transistor QN3 are connected together and connected to the collector of the first transistor QN1. The source of the fourth NMOS transistor MN4 is connected to the collector of the second transistor QN2. The connection between the base of the first transistor QN1 and the base of the second transistor QN2 is connected to the fifth NMOS transistor MN5. The source of the S-MOSFET MN5 is connected. The emitter of the first transistor QN1 is connected to the second terminal of the third resistor R3. The emitter of the second transistor QN2 is connected to the first terminal of the third resistor R3 and also connected to the source of the second NMOS transistor MN2. The second terminal of the third resistor R3 is connected to the first terminal of the adjustment resistor Rtrim. The second terminal of the adjustment resistor Rtrim is connected to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is connected to the power ground GND. The source of the fifth NMOS transistor MN5 is connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the first terminal of the seventh resistor R7.The second terminal of the seventh resistor R7 is connected to the power ground GND.

[0029] Specifically, in the first-order temperature compensation voltage circuit 2, QN1, QN2, R3, Rtrim, and R4 constitute the traditional Brokaw reference structure. MP4, MP5, MP6, and MP7 form a current mirror to ensure that the current flowing through transistors QN1 and QN2 is the same. The area ratio of the emitter of the first transistor QN1 to the emitter of the second transistor QN2 is 1:8. The leakage current of the reverse-biased diodes from the collectors of both transistors QN1 and QN2 to the substrate increases with increasing temperature. Since the emitter area of ​​the first transistor QN1 is different from that of the second transistor QN2, the collector current loss of the two transistors QN1 and QN2 is also different. In order to match the current flowing through the emitters of the two transistors QN1 and QN2, the third transistor QN3 is introduced into the collector of the first transistor QN1. The area ratio of the emitter of the first transistor QN1 to the emitter of the third transistor QN3 is 1:7, that is, the emitter area ratio of the transistors is QN1:QN2:QN3=1:8:7.

[0030] Specifically, according to Figure 1 Circuit analysis shows that the first-order temperature compensation voltage circuit 2 provides a bandgap reference voltage. for: ; because, = ,but: ; In the formula, This is the difference between the base-emitter voltage of the first transistor QN1 and the base-emitter voltage of the second transistor QN2. This is the voltage between the base and emitter of the first transistor QN1 (a voltage with a negative temperature coefficient). To adjust the resistance value of resistor Rtrim, This is the resistance value of the fourth resistor, R4. R3 is the resistance value of the third resistor; N2:N1 is the ratio of the emitter area of ​​transistor QN2 to the emitter area of ​​transistor QN1. It should be noted that the voltage between the base and emitter of any transistor... ,have: ; In the formula, At reference temperature The bandgap voltage is approximately 1.2V. At reference temperature voltage under , It is thermal voltage (constant). It is a process-related constant; m is related to the temperature coefficient of the current flowing through the transistor. When the current flowing through the transistor is PTAT current, m=1; when the current flowing through the transistor is CTAT current, m=-1; when the current flowing through the transistor is a temperature-independent current, m=0.

[0031] From the above equation, it can be seen that the bandgap reference voltage At reference temperature After performing a Taylor expansion and eliminating the first-order terms, it can be simplified to: The voltage is a parabola opening downwards; therefore, only a parabola opening upwards is needed for the temperature-voltage curve. With first-order bandgap reference voltage By adding them together, a bandgap reference voltage with smaller temperature drift can be obtained. The segmented temperature compensation voltage circuit 4 of this utility model achieves this function.

[0032] Specifically, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 constitute a voltage divider resistor, which is used to divide the bandgap reference voltage. Perform voltage division and convert the divided voltage to voltage. and voltage The output is sent to the segmented temperature compensation voltage circuit 4; the current mirror composed of the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 is used to provide the bias voltage. Its gate is connected to several sets of current mirrors to generate the PTAT bias current.

[0033] Preferably, the first-order temperature compensation current circuit 3 includes an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, and an eighth resistor R8. The sources of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both connected to the power supply voltage VREF. The drain of the eighth PMOS transistor MP8 is connected to the source of the tenth PMOS transistor MP10. The gate of the eighth PMOS transistor MP8 is connected to the gate of the tenth PMOS transistor MP10 and also connected to the drain of the seventh PMOS transistor MP7. The collector of the fourth transistor QN4, the base of the sixth transistor QN6, the base of the seventh transistor QN7, and the drain of the tenth PMOS transistor MP10 are connected... Together, the emitter of the fourth transistor QN4, the emitter of the fifth transistor QN5, and the second terminal of the eighth resistor R8 are all connected to the power ground GND. The base of the fourth transistor QN4, the base of the fifth transistor QN5, the first terminal of the eighth resistor R8, and the emitter of the sixth transistor QN6 are connected together. The collector of the fifth transistor QN5 is connected to the emitter of the seventh transistor QN7. The collector of the sixth transistor QN6, the collector of the seventh transistor QN7, and the drain of the eleventh PMOS transistor MP11 are connected together. The drain of the ninth PMOS transistor MP9 is connected to the source of the eleventh PMOS transistor MP11. The gate of the ninth PMOS transistor MP9, the gate of the eleventh PMOS transistor MP11, and the drain of the eleventh PMOS transistor MP11 are connected together and connected to the segmented temperature compensation voltage circuit 4.

[0034] Specifically, according to Figure 1 Circuit analysis shows that in the first-order temperature compensation current circuit 3, the PTAT bias current is replicated through a current mirror composed of PMOS transistors MP8 and MP9. Obtain the PTAT bias current Then, the PTAT bias current is replicated through transistors QN4 and QN5. and with current having a negative temperature coefficient The summation yields the reference current provided by the first-order temperature compensation current circuit 3. for: ; In the formula, The PTAT bias current (positive temperature coefficient current) is replicated by a current mirror formed by PMOS transistors MP8 and MP9. And came; This is the voltage between the base and emitter of the fourth transistor QN4 (the voltage with a negative temperature coefficient). This is the resistance value of the eighth resistor, R8; By using the eighth resistor R8, which has a lower temperature coefficient, a current with a negative temperature coefficient can be obtained. By adjusting the resistance value of the eighth resistor R8, a reference current with a lower temperature coefficient can be obtained. N2:N1 is the ratio of the emitter area of ​​transistor QN2 to that of transistor QN1; coefficient k1 is the ratio between the width-to-length ratio of the current mirror formed by MP8 and MP10 and the width-to-length ratio of the current mirror formed by MP5 and MP7; where the positive temperature coefficient of the current... Adding a current with a negative temperature coefficient By adjusting the resistance value of the eighth resistor R8, a first-order compensated low-temperature-coefficient reference current can be obtained. .

[0035] The current mirror formed by the ninth PMOS transistor MP9 and the eleventh PMOS transistor MP11 is used to provide the bias voltage. Its gate is connected to several sets of current mirrors to generate the reference current. .

[0036] Preferably, the segmented temperature compensation voltage circuit 4 includes a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a twenty-first PMOS transistor MP21, and a ninth resistor R9. The sources of the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, and the sixteenth PMOS transistor MP16 are... All are connected to the power supply voltage VREF. The drain of the twelfth PMOS transistor MP12 is connected to the source of the fourteenth PMOS transistor MP14. The drain of the thirteenth PMOS transistor MP13 is connected to the source of the fifteenth PMOS transistor MP15. The drain of the sixteenth PMOS transistor MP16 is connected to the source of the seventeenth PMOS transistor MP17. The gates of the twelfth PMOS transistor MP12, the fourteenth PMOS transistor MP14, the thirteenth PMOS transistor MP13, and the fifteenth PMOS transistor MP15 are all connected to the gate of the seventh PMOS transistor MP7. The gates of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17 are both connected to the gate of the eleventh PMOS transistor MP11. The drain of the fourteenth PMOS transistor MP14 is connected to the source of the eighteenth PMOS transistor MP18. The drain of the fifteenth PMOS transistor MP15 is connected to the first terminal of the ninth resistor R9. The drain of the seventeenth PMOS transistor MP17 is connected to the source of the twentieth PMOS transistor MP20. The source of the eighteenth PMOS transistor MP18 is connected to the source of the nineteenth PMOS transistor MP19. The twentieth PMOS transistor MP20... The source of the transistor is connected to the source of the twenty-first PMOS transistor MP21. The gate of the eighteenth PMOS transistor MP18 is connected to the first end of the sixth resistor R6. The gates of the nineteenth PMOS transistor MP19 and the twentieth PMOS transistor MP20 are both connected to the first end of the ninth resistor R9. The drains of the eighteenth PMOS transistor MP18 and the twentieth PMOS transistor MP20 are both connected to the first end of the fourth resistor R4. The drains of the nineteenth PMOS transistor MP19, the twenty-first PMOS transistor MP21, and the second end of the ninth resistor R9 are all connected to the power supply ground GND.

[0037] Specifically, according to Figure 1 Circuit analysis in segmented temperature compensation voltage circuit 4: PTAT bias current To replicate the PTAT bias current through a current mirror formed by PMOS transistors MP12 and MP14 Therefore, coefficient k2 is the ratio between the aspect ratio of the current mirror formed by MP12 and MP14 and the aspect ratio of the current mirror formed by MP5 and MP7, that is: ; PTAT bias current The PTAT bias current I is replicated by a current mirror formed by PMOS transistors MP13 and MP15. PTAT Therefore, coefficient k3 is the ratio between the aspect ratio of the current mirror formed by MP13 and MP15 and the aspect ratio of the current mirror formed by MP5 and MP7, that is: ; Low temperature drift bias current To replicate the reference current using a current mirror constructed from PMOS transistors MP16 and MP17 Therefore, coefficient k4 is the ratio between the aspect ratio of the current mirror formed by MP16 and MP17 and the aspect ratio of the current mirror formed by MP5 and MP7, that is: ; Therefore, we can conclude that: ; In the above formula, and The current has a positive temperature coefficient. For current with a low temperature coefficient, It is a voltage with a positive temperature coefficient. and It is the bandgap reference voltage The partial voltage, compared to The temperature coefficient can be approximately ignored; PMOS transistors MP18 and MP19 operate in the subthreshold region, according to the subthreshold current expression. The current can be obtained. , The expression is: ; ; In the above formula, Gate-source voltage; Characteristic current under specific processes and dimensions; This is the subthreshold slope factor; From the above formula, we can obtain that , scaling + = From this, we can obtain: ; Similarly, it can be deduced that PMOS transistors MP20 and MP21 operate in the subthreshold region, and the current can be obtained. The expression is: ; Therefore, we can conclude that: ; Therefore, we can conclude that: , As can be seen from the above formula, with increasing temperature, Increase - Decrease, therefore It increases with increasing temperature. - Increase, therefore It decreases as temperature increases; resistance R4 has a low temperature coefficient, therefore Voltage with a positive temperature coefficient Voltage with a negative temperature coefficient; when T < hour, Approaching zero, and Dominant; when T > hour, Approaching zero, and Dominant; Temperature-voltage curves as follows Figure 2 As shown, it is approximately equivalent to an upward-opening parabola; wherein, the compensation voltage generated by the segmented temperature compensation voltage circuit 4... for: ; In the formula, To compensate for the current, This is the resistance value of the fourth resistor, R4; The compensation voltage Superimposed on the bandgap reference voltage The corrected bandgap reference voltage is obtained from the above. for: .

[0038] It should be noted that choosing appropriate k2, k4, , and To generate a suitable compensation voltage This compensates for the bandgap reference voltage. The corrected bandgap reference voltage is obtained. ;like Figure 2 As shown, The temperature-voltage curve is approximately equivalent to a downward-opening parabola, which is then superimposed with an upward-opening parabolic voltage. A voltage function resembling a fourth-order function is obtained. This reduces the temperature drift of the bandgap reference voltage.

[0039] Specifically, due to non-ideal factors in the manufacturing process, resistor mismatch, and BJT saturation circuit I... S Variations in characteristics can introduce errors into the output voltage of a bandgap reference circuit. To counteract the adverse effects of process variations in chip manufacturing, a resistor trimming method is employed in this example. Figure 3 This is a schematic diagram illustrating the variation of the bandgap reference voltage with temperature under ideal conditions. Figure 4 The temperature coefficient of the bandgap reference voltage is reduced by adding a trimming resistor at the FF process corner. Figure 5 The temperature coefficient of the bandgap reference voltage is reduced by decreasing the trimming resistor at the SS process corner. Figure 4 and Figure 5 It can be seen that a good temperature coefficient of the bandgap reference voltage can be obtained by adjusting the resistance.

[0040] The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit provided by this utility model generates an upward-opening temperature-voltage parabolic curve through a segmented temperature compensation voltage circuit, which is superimposed with a downward-opening temperature-voltage parabolic curve generated by a first-order temperature compensation voltage circuit, so as to further reduce the temperature coefficient of the bandgap reference voltage.

[0041] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A segmented temperature-compensated bandgap reference circuit with adjustable low-temperature drift, characterized in that, The adjustable low-temperature drift segmented temperature compensation bandgap reference circuit includes a startup circuit (1), a first-order temperature compensation voltage circuit (2), a first-order temperature compensation current circuit (3), and a segmented temperature compensation voltage circuit (4). The startup circuit (1) is connected to the first-order temperature compensation voltage circuit (2). The first-order temperature compensation voltage circuit (2) is connected to the first-order temperature compensation current circuit (3) and the segmented temperature compensation voltage circuit (4) respectively. The first-order temperature compensation current circuit (3) is connected to the segmented temperature compensation voltage circuit (4). The starting circuit (1) is used to inject a target current into the first-order temperature compensation voltage circuit (2) when it is powered on, so that the first-order temperature compensation voltage circuit (2) is removed from the degeneracy point. The first-order temperature compensation voltage circuit (2) is used to provide a bandgap reference voltage that has been offset by the first-order temperature coefficient, and to provide PTAT bias current for the first-order temperature compensation current circuit (3) and the segmented temperature compensation voltage circuit (4), respectively. The first-order temperature compensation current circuit (3) is used to provide a reference current that has been offset by the first-order temperature coefficient and to provide a low-temperature drift bias current for the segmented temperature compensation voltage circuit (4). The segmented temperature compensation voltage circuit (4) is used to generate a compensation voltage and superimpose the compensation voltage onto the bandgap reference voltage to further reduce the temperature coefficient of the bandgap reference voltage.

2. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 1, characterized in that, The startup circuit (1) includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, and a second resistor R2. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to the power supply voltage VREF. The gate of the first PMOS transistor MP1 is connected to the power supply ground GND. The drain of the first PMOS transistor MP1 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the drain of the first NMOS transistor MN1. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected and connected to the power supply ground GND. The drain of the first NMOS transistor MN1 is connected, the source of the first NMOS transistor MN1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the power ground GND, the source of the second NMOS transistor MN2 is connected to the first-order temperature compensation voltage circuit (2), the second PMOS transistor MP2 and the third PMOS transistor MP3 form a current mirror, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 are connected and connected to the drain of the second PMOS transistor MP2, and the drain of the third PMOS transistor MP3 is connected to the first-order temperature compensation voltage circuit (2).

3. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 2, characterized in that, The first-order temperature compensation voltage circuit (2) includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first transistor QN1, a second transistor QN2, a third transistor QN3, a third resistor R3, a trimming resistor Rtrim, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7. The fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 form a current mirror. The source of the fourth PMOS transistor MP4 and the source of the fifth PMOS transistor MP5 are... The drain of the fifth NMOS transistor MN5 is connected to the power supply voltage VREF. The drain of the fourth PMOS transistor MP4 is connected to the source of the sixth PMOS transistor MP6. The drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7. The gates of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are connected to the gate of the seventh PMOS transistor MP7 and also to the drain of the seventh PMOS transistor MP7. The drain of the sixth PMOS transistor MP6 is connected to the drain of the third NMOS transistor MN3 and also to the drain of the third PMOS transistor MP3. The drain of the seventh PMOS transistor MP7 is connected to the drain of the fourth NMOS transistor MP6. The drain of MN4 is connected to the first-order temperature compensation current circuit (3) and the segmented temperature compensation voltage circuit (4) respectively. The gate of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5, and the drain of the third NMOS transistor MN3 are connected together. The source of the third NMOS transistor MN3 is connected to the collector of the first transistor QN1. The emitter, base, and collector of the third transistor QN3 are connected together and connected to the collector of the first transistor QN1. The source of the fourth NMOS transistor MN4 is connected to the collector of the second transistor QN2. The connection between the base of the first transistor QN1 and the base of the second transistor QN2 is connected to the fifth NMOS transistor MN4. The source of the first NMOS transistor MN5 is connected to the source. The emitter of the first transistor QN1 is connected to the second terminal of the third resistor R3. The emitter of the second transistor QN2 is connected to the first terminal of the third resistor R3 and also connected to the source of the second NMOS transistor MN2. The second terminal of the third resistor R3 is connected to the first terminal of the adjustment resistor Rtrim. The second terminal of the adjustment resistor Rtrim is connected to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is connected to the power ground GND. The source of the fifth NMOS transistor MN5 is connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the first terminal of the seventh resistor R7.The second terminal of the seventh resistor R7 is connected to the power ground GND.

4. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 3, characterized in that, The area ratio of the emitter of the first transistor QN1 to the emitter of the second transistor QN2 is 1:

8. The third transistor QN3 is introduced into the collector of the first transistor QN1, and the area ratio of the emitter of the first transistor QN1 to the emitter of the third transistor QN3 is 1:

7.

5. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 3, characterized in that, The bandgap reference voltage provided by the first-order temperature compensation voltage circuit (2) for: ； In the formula, This is the difference between the base-emitter voltage of the first transistor QN1 and the base-emitter voltage of the second transistor QN2. This is the voltage between the base and emitter of the first transistor QN1. To adjust the resistance value of resistor Rtrim, This is the resistance value of the fourth resistor, R4. This is the resistance value of the third resistor, R3.

6. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 5, characterized in that, The fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 constitute a voltage divider resistor, which is used to divide the bandgap reference voltage. Perform voltage division and convert the divided voltage to voltage. and voltage The output is sent to the segmented temperature compensation voltage circuit (4); the current mirror composed of the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 is used to provide the bias voltage. Its gate is connected to several sets of current mirrors to generate the PTAT bias current.

7. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 3, characterized in that, The first-order temperature compensation current circuit (3) includes an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, and an eighth resistor R8. The sources of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both connected to the power supply voltage VREF. The drain of the eighth PMOS transistor MP8 is connected to the source of the tenth PMOS transistor MP10. The gate of the eighth PMOS transistor MP8 is connected to the gate of the tenth PMOS transistor MP10 and also to the drain of the seventh PMOS transistor MP7. The collector of the fourth transistor QN4, the base of the sixth transistor QN6, the base of the seventh transistor QN7, and the drain of the tenth PMOS transistor MP10 are connected to a resistor R8. The emitter of the fourth transistor QN4, the emitter of the fifth transistor QN5, and the second end of the eighth resistor R8 are all connected to the power ground GND. The base of the fourth transistor QN4, the base of the fifth transistor QN5, the first end of the eighth resistor R8, and the emitter of the sixth transistor QN6 are connected together. The collector of the fifth transistor QN5 is connected to the emitter of the seventh transistor QN7. The collector of the sixth transistor QN6, the collector of the seventh transistor QN7, and the drain of the eleventh PMOS transistor MP11 are connected together. The drain of the ninth PMOS transistor MP9 is connected to the source of the eleventh PMOS transistor MP11. The gate of the ninth PMOS transistor MP9, the gate of the eleventh PMOS transistor MP11, and the drain of the eleventh PMOS transistor MP11 are connected together and connected to the segmented temperature compensation voltage circuit (4).

8. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 7, characterized in that, The reference current provided by the first-order temperature compensation current circuit (3) for: ； In the formula, This is the PTAT bias current. This is the voltage between the base and emitter of the fourth transistor QN4. This is the resistance value of the eighth resistor, R8; The current mirror formed by the ninth PMOS transistor MP9 and the eleventh PMOS transistor MP11 is used to provide the bias voltage. Its gate is connected to several sets of current mirrors to generate the reference current. .

9. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 7, characterized in that, The segmented temperature compensation voltage circuit (4) includes the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, the fifteenth PMOS transistor MP15, the sixteenth PMOS transistor MP16, the seventeenth PMOS transistor MP17, the eighteenth PMOS transistor MP18, the nineteenth PMOS transistor MP19, the twentieth PMOS transistor MP20, the twenty-first PMOS transistor MP21, and the ninth resistor R9. The sources of the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, and the sixteenth PMOS transistor MP16 are all... Connected to the power supply voltage VREF, the drain of the twelfth PMOS transistor MP12 is connected to the source of the fourteenth PMOS transistor MP14, the drain of the thirteenth PMOS transistor MP13 is connected to the source of the fifteenth PMOS transistor MP15, and the drain of the sixteenth PMOS transistor MP16 is connected to the source of the seventeenth PMOS transistor MP17. The gates of the twelfth PMOS transistor MP12, the fourteenth PMOS transistor MP14, the thirteenth PMOS transistor MP13, and the fifteenth PMOS transistor MP15 are all connected to the gate of the seventh PMOS transistor MP7. The gates of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17 are both connected to the gate of the eleventh PMOS transistor MP11. The drain of the fourteenth PMOS transistor MP14 is connected to the source of the eighteenth PMOS transistor MP18. The drain of the fifteenth PMOS transistor MP15 is connected to the first terminal of the ninth resistor R9. The drain of the seventeenth PMOS transistor MP17 is connected to the source of the twentieth PMOS transistor MP20. The source of the eighteenth PMOS transistor MP18 is connected to the source of the nineteenth PMOS transistor MP19. The twentieth PMOS transistor MP20... The source of the transistor is connected to the source of the twenty-first PMOS transistor MP21. The gate of the eighteenth PMOS transistor MP18 is connected to the first end of the sixth resistor R6. The gates of the nineteenth PMOS transistor MP19 and the twentieth PMOS transistor MP20 are both connected to the first end of the ninth resistor R9. The drains of the eighteenth PMOS transistor MP18 and the twentieth PMOS transistor MP20 are both connected to the first end of the fourth resistor R4. The drains of the nineteenth PMOS transistor MP19, the twenty-first PMOS transistor MP21, and the second end of the ninth resistor R9 are all connected to the power supply ground GND.

10. A segmented temperature-compensated bandgap reference circuit with adjustable low-temperature drift according to claim 9, characterized in that, The compensation voltage generated by the segmented temperature compensation voltage circuit (4) for: ； In the formula, To compensate for the current, This is the resistance value of the fourth resistor, R4; The compensation voltage Superimposed on the bandgap reference voltage The corrected bandgap reference voltage is obtained from the above. for: 。

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