A dual reset circuit and electronic device

Abstract

This application discloses a dual reset circuit, including a first processor and a second processor, with a first reset line and a second reset line respectively connecting them. The first reset line is connected to the reset terminal of the second processor for resetting the second processor by the first processor, and the second reset line is connected to the reset terminal of the first processor for resetting the first processor by the second processor. A bidirectional communication data line is also provided between the first processor and the second processor. The technical solution of this application effectively solves the unreliability issues inherent in traditional CPU reset methods.

Description

Technical Field

[0001] This application belongs to the field of circuit technology, and in particular relates to a dual reset circuit and electronic device. Background Technology

[0002] A reset operation refers to the restart of a program during CPU operation due to a fault or other reason. It typically includes hardware reset and software reset methods. Hardware reset utilizes a timer circuit whose timing output is connected to the CPU's reset pin. The program running in the CPU clears the timer within a certain time range (such as a preset timing period). Therefore, when the program is running normally, the timer never overflows and thus does not generate a reset signal. If a program malfunctions and fails to clear the timer within the timing period, the timer overflows, generating a reset signal and restarting the CPU. Software reset works on the same principle, but replaces the hardware timer with the CPU's internal timer. This simplifies hardware circuit design, but its reliability is not as good as that of a hardware timer.

[0003] In existing technologies, many electronic products based on Linux and Android systems use software reset. However, the reliability of software reset is not as good as that of hardware timer reset. For example, if the internal timer of the system itself malfunctions, it cannot be detected. Secondly, the system startup time of existing electronic products based on Linux and Android systems is often greater than 40 seconds, while hardware circuit reset must be completed within 1.6 seconds. Therefore, it is not feasible to directly add a hardware timer as a hardware reset circuit. Utility Model Content

[0004] The main technical problem addressed by this application is to provide a dual reset circuit and electronic device, thereby resolving the unreliability issues inherent in the CPU reset methods of the prior art.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is to provide a dual reset circuit, including a first processor and a second processor, and a first reset line and a second reset line respectively connected between the first processor and the second processor, wherein the first reset line is connected to the reset terminal of the second processor for the first processor to reset the second processor, and the second reset line is connected to the reset terminal of the first processor for the second processor to reset the first processor; a bidirectional communication data line is also provided between the first processor and the second processor.

[0006] In some embodiments, the bidirectional communication data line includes an asynchronous serial communication data line.

[0007] In some embodiments, the bidirectional communication data line includes an SPI data line.

[0008] In some embodiments, the second processor includes a GPIO interface for connecting to an expansion device.

[0009] In some embodiments, the first processor has a built-in LINUX system, Android system, iOS system, or HarmonyOS system.

[0010] In some embodiments, the second processor includes an 8-bit, 16-bit, or 32-bit microcontroller.

[0011] Based on the same concept, this application also provides an electronic device including the aforementioned dual reset circuit.

[0012] The beneficial effects of this application are as follows: This application discloses a dual reset circuit, including a first processor and a second processor, and a first reset line and a second reset line respectively connected between the two. The first reset line is connected to the reset terminal of the second processor for resetting the second processor by the first processor, and the second reset line is connected to the reset terminal of the first processor for resetting the first processor by the second processor. A bidirectional communication data line is also provided between the first processor and the second processor. Through the technical solution of this application, the unreliability risks existing in the CPU reset method can be effectively solved. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the circuit composition in one embodiment of this application; Figure 2 This is a schematic diagram of another circuit configuration in one embodiment of this application; Figure 3 This is a circuit diagram of the second processor gate in one embodiment of this application. Detailed Implementation

[0014] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0015] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0016] The embodiments will now be described in detail with reference to the accompanying drawings.

[0017] For ease of explanation, Figure 1 A first embodiment is shown, which includes a first processor 1 and a second processor 2, and a first reset line 11 and a second reset line 12 respectively connected between the first processor 1 and the second processor 2. The first reset line 11 is connected to the reset terminal of the second processor 2 and is used by the first processor 1 to reset the second processor 2. The second reset line 12 is connected to the reset terminal of the first processor 1 and is used by the second processor 2 to reset the first processor 1.

[0018] Specifically, the first processor 1 typically refers to the core processor installed in electronic products such as mobile phones and wearable devices. It runs commercially popular operating systems such as Linux, Android, iOS, and HarmonyOS. The second processor 2 is a cost-effective MCU, such as an 8-bit, 16-bit, or 32-bit microcontroller.

[0019] In addition, a bidirectional communication data line 13 is provided between the first processor 1 and the second processor 2 for information exchange between the first processor 1 and the second processor 2.

[0020] The first processor 1 accesses the second processor 2 once via bidirectional communication data line 13 at a first time interval, such as two minutes (the first time interval can be changed, but cannot be less than the startup time of the Android system and the LINUX system). The second processor 2 accesses the first processor 1 once via bidirectional communication data line 13 at a second time interval, such as every 100ms (the time cannot exceed 1 second).

[0021] When the program of the first processor 1 encounters a problem and fails to access the second processor 2 via the bidirectional communication data line 13 for a period of time exceeding the first time interval, the second processor 2 resets the first processor 1 via the second reset line 12. Conversely, when the program of the second processor 2 encounters a problem and fails to access the first processor 1 via the bidirectional communication data line 13 for a period of time exceeding the second time interval, the first processor 1 resets the second processor 2 via the first reset line 11.

[0022] Therefore, the technical solution of this application can realize bidirectional circuit reset, ensuring that both the first processor 1 and the second processor 2 can reliably perform reset operation. Both have hardware reset implementation methods, and the reset time interval of the first processor 1 can be reasonably set according to the characteristics of the operating system installed in the first processor 1, thereby enhancing the flexibility and versatility of the application.

[0023] Specifically, the bidirectional communication data line 13 can be two data lines for implementing asynchronous serial communication UART, namely the receive data line RDX and the transmit data line TDX. The bidirectional communication data line 13 can also be an SPI interface data line, including a clock line, two data lines, and a chip select line.

[0024] Furthermore, such as Figure 2 As shown, the second processor 2 also includes a GPIO (General Purpose Input / Output) interface for connecting the expansion device 3 via an expansion data line 21. When the second processor 2 controls the expansion device 3 via the expansion data line 21, it can also receive control commands from the first processor 1 via the bidirectional communication data line 13. This is equivalent to the first processor 1 indirectly controlling the expansion device 3, effectively utilizing the GPIO interface of the second processor 2 for expansion device control, thus enhancing the peripheral expansion capabilities of the first processor 1. Furthermore, the type of microcontroller can be selected based on the required number of GPIO interfaces.

[0025] like Figure 3 As shown, this is an embodiment of the second processor 2, which uses an 8-bit microcontroller STM8S003F3P6 with 14 GPIO interfaces, connected via asynchronous serial communication UART. Figure 3 The MCU-UART-RXD and MCU-UART-TXD in the microcontroller communicate bidirectionally with the first processor. Here, the STM8S003F3P6 microcontroller accesses the first processor once every 100ms (the time cannot exceed 1 second) via the asynchronous serial communication UART connection. This is to prevent the first processor from resetting the microcontroller in time if there is a problem with the STM8S003F3P6, i.e., if it does not access the first processor for more than 100ms. The first processor can connect to the reset terminal NRST of the STM8S003F3P6 via the first reset line to reset the microcontroller in time.

[0026] Based on the same inventive concept, this application also includes electronic devices with the aforementioned dual reset circuit.

[0027] Therefore, this application discloses a dual reset circuit, including a first processor and a second processor, with a first reset line and a second reset line respectively connecting them. The first reset line is connected to the reset terminal of the second processor for resetting the second processor by the first processor, and the second reset line is connected to the reset terminal of the first processor for resetting the first processor by the second processor. A bidirectional communication data line is also provided between the first processor and the second processor. The technical solution of this application can effectively solve the unreliability issues inherent in traditional CPU reset methods.

[0028] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A dual reset circuit, characterized in that, The system includes a first processor and a second processor, with a first reset line and a second reset line respectively connecting the first processor and the second processor. The first reset line is connected to the reset terminal of the second processor for the first processor to reset the second processor, and the second reset line is connected to the reset terminal of the first processor for the second processor to reset the first processor. A bidirectional communication data line is also provided between the first processor and the second processor.

2. The dual reset circuit according to claim 1, characterized in that, The bidirectional communication data line includes an asynchronous serial communication data line.

3. The dual reset circuit according to claim 1, characterized in that, The bidirectional communication data line includes an SPI data line.

4. The dual reset circuit according to claim 1, characterized in that, The second processor includes a GPIO interface for connecting expansion devices.

5. The dual reset circuit according to claim 1, characterized in that, The first processor has a built-in LINUX system, Android system, iOS system or HarmonyOS system.

6. The dual reset circuit according to claim 1, characterized in that, The second processor includes an 8-bit, 16-bit, or 32-bit microcontroller.

7. An electronic device, characterized in that, Includes the dual reset circuit as described in any one of claims 1-6.

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