A dual-pin chip adapter with built-in connectivity detection, connectivity detection circuit, adapter, and chip connectivity detection system.

Abstract

This utility model discloses a dual-pin chip adapter with built-in connectivity detection, a connectivity detection circuit, an adapter, and a chip connectivity detection system. The adapter includes a chip adapter body, which comprises a base and a limiting frame. The limiting frame forms multiple probe contact holes corresponding to the pin positions of the chip. It also includes multiple probe units, each with a position corresponding to a probe contact hole, and the probe contact holes corresponding to the pin positions of the chip. The top of each probe unit extends from the probe contact hole. At least one probe unit includes a probe group, which includes a first probe and a second probe. This utility model, a dual-pin chip adapter with built-in connectivity detection, a connectivity detection circuit, an adapter, and a chip connectivity detection system, solves the problem of ensuring connectivity detection for any pin requiring detection, guaranteeing a normal connection between the chip and the adapter, and ensuring correct data programming.

Description

Technical Field

[0001] This utility model belongs to the technical field of chip programming devices, and particularly relates to a dual-pin chip adapter with built-in connectivity detection, a connectivity detection circuit, an adapter, and a chip connectivity detection system. Background Technology

[0002] Current chip adapters are single-pin structures, making connectivity testing impossible through the adapter itself. Existing technology requires a host computer to power on the chip for connectivity testing, but this is limited by the chip itself and peripheral circuitry, preventing testing of power pins and certain pins related to peripheral circuitry. If the power pins are not connected correctly, the chip to be programmed may be abnormally powered by other pins. In this case, the programmer may not report an error and may complete the programming process normally. However, due to this abnormal power supply, the programmed chip may pose a risk during use, such as insufficient programming leading to data loss. Conversely, if some pins related to peripheral circuitry are not connected correctly, but there are actual connectivity issues, the host computer may fail to detect these problems, leading to errors during subsequent programming. Summary of the Invention

[0003] To address the shortcomings of the existing technology, this utility model aims to provide a dual-pin chip adapter with built-in connectivity detection, a connectivity detection circuit, an adapter, and a chip connectivity detection system. This solves the problem of ensuring connectivity detection for any pin that needs to be detected, guaranteeing a normal connection between the chip and the adapter, and ensuring correct data programming.

[0004] To achieve the above objectives, this utility model provides a dual-pin chip adapter with built-in connectivity detection, comprising a chip adapter body, the chip adapter body including a base and a limiting frame for placing the chip; the limiting frame forms a plurality of probe contact holes corresponding to the pin positions of the chip; the limiting frame is mounted on the base; it also includes a plurality of probe units, the probe units being mounted on the base and located below the limiting frame, the positions of the probe units corresponding one-to-one with the probe contact holes, the positions of the probe contact holes corresponding one-to-one with the pin positions of the chip, and the top end of the probe unit extending from the probe contact hole; at least one of the probe units includes a probe group, the probe group including a first probe and a second probe.

[0005] In one implementation, the tip shapes of the first probe and the second probe are matched with the shapes of the pins of the corresponding chip.

[0006] In one implementation, the first probe and the second probe are arranged along the pin extension direction of the chip.

[0007] In one implementation, the tip of the first probe is inclined downward in a direction away from the second probe to form a first slope; the tip of the second probe is inclined downward in a direction away from the first probe to form a second slope.

[0008] In one implementation, the probe contact hole corresponding to the probe group is an elongated hole.

[0009] This utility model provides a connectivity detection circuit, comprising:

[0010] Voltage input terminal;

[0011] Detect voltage input terminal;

[0012] A comparison circuit is provided, wherein the voltage input terminal and the detection voltage input terminal are connected to the comparison circuit; the comparison circuit is used to compare the voltage signal at the voltage input terminal and the voltage signal at the detection voltage input terminal to obtain a comparison result signal;

[0013] A connection error triggering and latching circuit is used to determine whether the current pin connection status of the chip is normal based on the comparison result signal, and to issue an error signal when the status is abnormal, and to keep it from being reset.

[0014] The signal switch / selection circuit is used to connect the host computer signal when the status is normal and to stop working after receiving an abnormal signal.

[0015] In one embodiment, the comparison circuit includes:

[0016] A first resistor, the first end of which is connected to the voltage input terminal;

[0017] A second resistor, the first end of which is connected to the detection voltage input terminal;

[0018] A comparator, wherein the negative input terminal of the comparator is connected to the first resistor, and the positive input terminal of the comparator is connected to the second resistor;

[0019] A third resistor is connected between the output terminal of the comparator and the positive power supply terminal of the comparator;

[0020] A fourth resistor, the first end of which is connected to the output terminal of the comparator, and the second end of which is connected to the negative power supply terminal of the comparator and grounded;

[0021] A fifth resistor and a sixth resistor; the fifth resistor and the sixth resistor are connected in series between the negative input terminal of the comparator and the negative power supply terminal of the comparator;

[0022] A first capacitor, the first end of which is connected to the positive power supply terminal of the comparator, and the second end of which is grounded.

[0023] As one implementation, the connection exception triggering and latching circuit includes:

[0024] A power supply, which is connected to the positive power supply terminal of the comparator;

[0025] A trigger, wherein the VCC terminal of the trigger is connected to the power supply, and the GND terminal of the trigger is grounded;

[0026] A seventh resistor, the first end of which is connected to the power supply, and the second end of which is connected to the D terminal of the trigger;

[0027] An eighth resistor is provided, the first end of which is connected to the output of the comparator, and the second end of which is connected to the PRE terminal of the flip-flop.

[0028] A ninth resistor is connected between the output of the comparator and the CLK terminal of the flip-flop;

[0029] A tenth resistor, the first end of which is connected to the power supply, and the second end of which is connected between the CLR terminals of the trigger.

[0030] A second capacitor, the first terminal of which is connected to the CLR terminal of the trigger, and the second terminal of which is grounded;

[0031] A third capacitor, the first terminal of which is connected to the VCC terminal of the trigger, and the second terminal of which is grounded;

[0032] A twelfth resistor is connected between the positive output terminal of the trigger and the ground terminal.

[0033] As one implementation, it also includes a host computer port, which is connected to the positive output terminal of the trigger.

[0034] As one implementation, a status indication circuit is also included, the status indication circuit including a status display device; the first terminal of the status indication circuit is connected to the positive output terminal of the trigger, and the second terminal of the status indication circuit is grounded.

[0035] As one implementation, the signal switch / selection circuit includes:

[0036] The fourteenth resistor;

[0037] The fifteenth resistor;

[0038] An analog switch is provided, wherein the NC terminal of the analog switch is connected to the host computer through the fourteenth resistor, the IN terminal of the analog switch is connected to the positive output terminal of the trigger through the fifteenth resistor, the COM terminal of the analog switch is connected to the chip, the GND terminal of the analog switch is grounded, and the VCC terminal of the analog switch is connected to the power supply.

[0039] A fourth capacitor, the first terminal of which is connected to the VCC terminal of the analog switch, and the second terminal of which is grounded;

[0040] An eleventh resistor is connected between the COM terminal and the GND terminal of the analog switch.

[0041] An adapter according to this utility model includes the connectivity detection circuit described in this utility model.

[0042] The present invention provides a chip connectivity testing system, comprising a dual-pin chip adapter with built-in connectivity testing, a circuit board, and a connectivity testing circuit.

[0043] The probe unit of the dual-needle chip adapter with built-in connectivity detection is electrically connected to the circuit board through the pad unit of the circuit board; the pad unit corresponding to the position of the probe group includes a first pad and a second pad, and the positions of the first pad and the second pad correspond to the positions of the first probe and the second probe, respectively.

[0044] The first probe is electrically connected to the voltage input terminal of the connectivity detection circuit;

[0045] The second probe is electrically connected to the detection voltage input terminal of the connectivity detection circuit.

[0046] Because of the adoption of the above technical solution, this utility model has the following beneficial effects:

[0047] The dual-probe structure of the chip adapter allows for the detection of a proper connection between the chip and the adapter when the chip is placed in the limiting frame. At least one pin of the chip corresponds to a first probe and a second probe. This, combined with a connectivity detection circuit, enables the verification of the connection between the chip and the adapter without affecting the existing system software. The top shapes of the first and second probes match the shapes of the corresponding chip pins, ensuring sufficient contact and guaranteeing normal circuit operation and detection quality. The first and second probes are arranged along the pin extension direction of the chip, resulting in a more rational layout and smaller space usage. The tops of the first and second probes feature a first bevel and a second bevel, respectively, ensuring good contact with the chip pins. The probe contact holes corresponding to the probe group are elongated holes for easy installation of the first and second probes. The connectivity detection circuit structure enables reliable connection detection of the chip pins, eliminating potential quality issues caused by connectivity problems with the chip power pins, ensuring a normal connection between the chip and the adapter, and guaranteeing correct data programming. The inclusion of a host computer port allows for the transmission of comparison results to the host computer. The use of a status display device can provide prompts for comparison results. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a perspective view of a dual-pin chip adapter with built-in connectivity detection according to an embodiment of this application.

[0050] Figure 2 This is a top view of a dual-pin chip adapter with built-in connectivity detection according to an embodiment of this application;

[0051] Figure 3 This is a schematic diagram of the probe group structure of the dual-needle chip adapter with built-in connectivity detection according to an embodiment of this application.

[0052] Figure 4 This is a schematic diagram of the probe group installation structure of the dual-needle chip adapter with built-in connectivity detection according to an embodiment of this application.

[0053] Figure 5 This is a circuit diagram of the connectivity detection circuit according to an embodiment of this application;

[0054] Figure 6 This is a schematic diagram of the pad structure of the circuit board according to an embodiment of this application.

[0055] Explanation of icon numbers:

[0056] 1-Base;

[0057] 2-Limiting frame;

[0058] 21-Probe contact hole;

[0059] 3-Probe unit;

[0060] 31-First probe; 311-First inclined plane; 32-Second probe; 321-Second inclined plane;

[0061] 4- Comparator circuit;

[0062] 5-Connection exception trigger and latch circuit;

[0063] 6-Signal switch / selection circuit;

[0064] 7-Circuit board;

[0065] 71-Pad unit; 711-First pad, 712-Second pad. Detailed Implementation

[0066] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0067] In the description of this utility model, it should be noted that the terms "upper," "lower," "left," "right," "center," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this utility model and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0068] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," "linking," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0069] Example 1

[0070] Please see Figures 1-6 According to Embodiment 1 of this utility model, a dual-needle chip adapter with built-in connectivity detection includes a chip adapter body, which includes a base 1 and a limiting frame 2 for placing the chip; the limiting frame 2 forms a plurality of probe contact holes 21 corresponding to the pin positions of the chip; the limiting frame 2 is mounted on the base 1; it also includes a plurality of probe units 3, which are mounted on the base 1 and located below the limiting frame 2. The positions of the probe units 3 correspond one-to-one with the probe contact holes 21, and the positions of the probe contact holes 21 correspond one-to-one with the pin positions of the chip. The top of the probe unit 3 extends out from the probe contact hole 21; each probe unit 3 includes a probe group, which includes a first probe 31 and a second probe 32.

[0071] The dual-probe structure of the chip adapter allows the chip to be placed in the limiting frame 2. At least one pin of the chip has a first probe 31 and a second probe 32. This can be used in conjunction with a connectivity detection circuit to detect whether the connection between the chip and the adapter is normal, without affecting the original software operation of the system. The original software can work normally.

[0072] In this embodiment, the top shapes of the first probe 31 and the second probe 32 are matched with the shapes of the corresponding chip pins to ensure sufficient contact between the first probe 31 and the second probe 32 and the chip pins, thereby ensuring the normal operation of the circuit and the quality of the detection.

[0073] The first probe 31 and the second probe 32 are arranged along the pin extension direction of the chip, making the layout of the first probe 31 and the second probe 32 more reasonable and occupying less space.

[0074] The tip of the first probe 31 is inclined downward in a direction away from the second probe 32 to form a first inclined surface 311; the tip of the second probe 32 is inclined downward in a direction away from the first probe 31 to form a second inclined surface 321; this ensures that the first probe 31 and the second probe 32 have good contact with the chip pins.

[0075] In this embodiment, the probe type of the first probe 31 and the second probe 32 is Kelvin pin.

[0076] In this embodiment, the probe contact hole 21 corresponding to the probe group is an elongated hole, which facilitates the installation of the first probe 31 and the second probe 32.

[0077] A connectivity detection circuit according to an embodiment of the present invention includes: a voltage input terminal V_IN, a detection voltage input terminal V_DETECT, a comparison circuit 4, a connection abnormality triggering and latching circuit 5, and a signal switch / selection circuit 6.

[0078] The voltage input terminal V_IN and the detection voltage input terminal V_DETECT are connected to the comparison circuit 4; the comparison circuit 4 is used to compare the voltage signal at the voltage input terminal V_IN and the voltage signal at the detection voltage input terminal V_DETECT to obtain a comparison result signal;

[0079] The connection abnormality triggering and latching circuit 5 is used to determine whether the current pin connection status of the chip is normal based on the comparison result signal, and to issue an abnormal signal when the status is abnormal, and to keep it from being reset.

[0080] The signal switch / selection circuit 6 is used to connect the host computer signal when the status is normal and to stop working after receiving an abnormal signal.

[0081] The use of a connectivity detection circuit enables reliable connectivity detection of chip pins, eliminating potential quality issues caused by connectivity problems of chip power pins, ensuring normal connection between the chip and the adapter, and ensuring correct data programming.

[0082] In this embodiment, the comparison circuit 4 includes:

[0083] A first resistor R1, the first end of which is connected to the voltage input terminal V_IN;

[0084] A second resistor R2, the first end of which is connected to the detection voltage input terminal V_DETECT;

[0085] A comparator U1 is provided, with its negative input terminal connected to the first resistor R1 and its positive input terminal connected to the second resistor R2. In this embodiment, a low-voltage, rail-to-rail input single-channel comparator U1 of model TL331LV is used. In other embodiments, other models of comparator U1 may also be used.

[0086] A third resistor R3 is connected between the output terminal of the comparator U1 and the positive power supply terminal of the comparator U1.

[0087] A fourth resistor R4 is provided, with its first end connected to the output terminal of the comparator U1 and its second end connected to the negative power supply terminal of the comparator U1 and grounded.

[0088] A fifth resistor R5 and a sixth resistor R6; the fifth resistor R5 and the sixth resistor R6 are connected in series between the negative input terminal of the comparator U1 and the negative power supply terminal of the comparator U1.

[0089] A first capacitor C1 is provided, with its first end connected to the positive power supply terminal of the comparator U1 and its second end grounded.

[0090] During testing, a high level at the output of comparator U1 indicates normal contact, while a low level indicates abnormal contact.

[0091] In this embodiment, the connection anomaly triggering and latching circuit 5 includes:

[0092] A power supply VCC is connected to the positive power supply terminal of the comparator U1.

[0093] A trigger U2 is provided, wherein the VCC terminal of the trigger U2 is connected to the power supply VCC, and the GND terminal of the trigger U2 is grounded; in this embodiment, a single-channel positive edge triggered D-type trigger of model SN74LVC1G74 is used. In other embodiments, other models of trigger U2 may also be used.

[0094] A seventh resistor R7, the first end of which is connected to the power supply VCC, and the second end of which is connected to the D terminal of the trigger U2;

[0095] An eighth resistor R8 is provided, with its first end connected to the output of the comparator U1 and its second end connected to the PRE terminal of the flip-flop U2.

[0096] A ninth resistor R9 is connected between the output of the comparator U1 and the CLK terminal of the flip-flop U2;

[0097] A tenth resistor R10, the first end of which is connected to the power supply VCC, and the second end of which is connected between the CLR terminals of the trigger U2;

[0098] A second capacitor C2 is provided, with its first terminal connected to the CLR terminal of the trigger U2 and its second terminal grounded.

[0099] A third capacitor C3 is provided, with its first terminal connected to the VCC terminal of the trigger U2 and its second terminal grounded.

[0100] A twelfth resistor R12 is connected between the positive output terminal of the flip-flop U2 and the ground terminal.

[0101] In this embodiment, when the positive output of trigger U2 is low, it indicates normal contact; when the positive output is high, it indicates abnormal contact.

[0102] In this embodiment, the signal switch / selection circuit 6 includes:

[0103] The fourteenth resistor, R14;

[0104] The fifteenth resistor is R15;

[0105] An analog switch U3 is provided. The NC terminal of the analog switch U3 is connected to the host computer through the fourteenth resistor R14. The IN terminal of the analog switch U3 is connected to the positive output terminal of the trigger U2 through the fifteenth resistor R15. The COM terminal of the analog switch U3 is connected to the chip. The GND terminal of the analog switch U3 is grounded. The VCC terminal of the analog switch U3 is connected to the power supply VCC. In this embodiment, a single-channel, single-pole single-throw analog switch of model TS5A3167 is used, which has low power consumption, low on-resistance and excellent signal integrity. In other embodiments, other models of analog switch U3 can also be used.

[0106] A fourth capacitor C4, the first end of which is connected to the VCC terminal of the analog switch U3, and the second end of which is grounded;

[0107] An eleventh resistor R11 is connected between the COM terminal and the GND terminal of the analog switch U3.

[0108] In this embodiment, when the positive output of trigger U2 is low, indicating normal contact, the voltage signal of the chip programming terminal XRES is equal to the voltage signal of the host computer input terminal RST, and the chip works normally at this time; when the positive output of trigger U2 is high, indicating abnormal contact, the analog switch is opened, the chip programming terminal XRES is low, and the chip stops working.

[0109] In other embodiments, the comparison circuit 4, the connection exception triggering and latching circuit 5, and the signal switch / selection circuit 6 may also employ other specific circuit structures that can achieve the relevant functions.

[0110] An adapter according to an embodiment of the present invention includes the connectivity detection circuit described in this embodiment.

[0111] A chip connectivity detection system according to an embodiment of the present invention includes a dual-pin chip adapter with built-in connectivity detection, a circuit board 7, and a connectivity detection circuit as described in this embodiment.

[0112] The probe unit 3 of the dual-needle chip adapter with built-in connectivity detection is electrically connected to the circuit board 7 through the pad unit 71 of the circuit board 7; the pad unit 71 corresponding to the position of the probe group includes a first pad 711 and a second pad 712, and the positions of the first pad 711 and the second pad 712 correspond to the positions of the first probe 31 and the second probe 32, respectively.

[0113] The first probe 31 is electrically connected to the voltage input terminal V_IN of the connectivity detection circuit;

[0114] The second probe 32 is electrically connected to the detection voltage input terminal V_DETECT of the connectivity detection circuit.

[0115] Example 2

[0116] The structure of the dual-needle chip adapter with built-in connectivity detection in Embodiment 2 of this utility model is basically the same as that in Embodiment 1. The difference is that the probes of the first probe 31 and the second probe 32 are spring pins.

[0117] Example 3

[0118] The structure of the dual-needle chip adapter with built-in connectivity detection in Embodiment 3 of this utility model is basically the same as that in Embodiment 1. The difference is that the top of the first probe 31 and the top of the second probe 32 are arc surfaces.

[0119] Example 4

[0120] The structure of the dual-needle chip adapter with built-in connectivity detection in Embodiment 4 of this utility model is basically the same as that in Embodiment 1. The difference is that the probe contact hole 21 corresponding to the probe group is rectangular or irregular in shape.

[0121] Example 5

[0122] The structure of the dual-needle chip adapter with built-in connectivity detection in Embodiment 5 of this utility model is basically the same as that in Embodiment 1. The difference is that the multiple probe units 3 each include a probe group.

[0123] An adapter according to Embodiment 5 of this utility model is basically the same as that in Embodiment 1, except that it includes multiple connectivity detection circuits or the connectivity detection circuits can realize multiple detections.

[0124] Example 6

[0125] The connectivity detection circuit of Embodiment Six of this utility model is basically the same as that of Embodiment One, except that it further includes a host computer port STATUS, which is connected to the positive output terminal of the trigger U2; the use of the host computer port STATUS can realize the transmission of comparison results to the host computer.

[0126] Example 7

[0127] The connectivity detection circuit of Embodiment 7 of this utility model is basically the same as that of Embodiment 1, except that it further includes a status indication circuit. The status indication circuit includes a light-emitting diode D1 and a thirteenth resistor R13. The first terminal of the status indication circuit is connected to the positive output terminal of the trigger U2, and the second terminal of the status indication circuit is grounded. In this embodiment, the light-emitting diode D1 serves as a status display device.

[0128] The use of a status display device can provide comparison results, allowing users to intuitively understand the current connection status of the chip.

[0129] The present invention has been described in detail above with reference to the accompanying drawings and embodiments. Those skilled in the art can make various modifications to the present invention based on the above description. Therefore, certain details in the embodiments should not be construed as limiting the present invention, and the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A dual-pin chip adapter with built-in connectivity detection, comprising a chip adapter body, the chip adapter body including a base and a limiting frame for placing a chip; the limiting frame forming a plurality of probe contact holes corresponding to the pin positions of the chip; the limiting frame being mounted on the base; characterized in that, It also includes multiple probe units, which are mounted on the base and located below the limiting frame. The positions of the probe units correspond one-to-one with the probe contact holes, and the positions of the probe contact holes correspond one-to-one with the pin positions of the chip. The top of the probe unit extends out from the probe contact hole. At least one of the probe units includes a probe group, the probe group including a first probe and a second probe.

2. The dual-pin chip adapter with built-in connectivity detection according to claim 1, characterized in that, The tip shapes of the first probe and the second probe match the shapes of the corresponding pins of the chip.

3. The dual-pin chip adapter with built-in connectivity detection according to claim 1, characterized in that, The first probe and the second probe are arranged along the pin extension direction of the chip.

4. The dual-pin chip adapter with built-in connectivity detection according to claim 1, characterized in that, The tip of the first probe slopes downward in a direction away from the second probe to form a first slope; the tip of the second probe slopes downward in a direction away from the first probe to form a second slope.

5. The dual-pin chip adapter with built-in connectivity detection according to claim 1, characterized in that, The probe contact hole corresponding to the probe group is an elongated hole.

6. A connectivity detection circuit, characterized in that, include: Voltage input terminal; Detect voltage input terminal; The voltage input terminal and the detection voltage input terminal are connected to the comparison circuit; The comparison circuit is used to compare the voltage signal at the voltage input terminal and the voltage signal at the detection voltage input terminal to obtain a comparison result signal; A connection error triggering and latching circuit is used to determine whether the current pin connection status of the chip is normal based on the comparison result signal, and to issue an error signal when the status is abnormal, and to keep it from being reset. The signal switch / selection circuit is used to connect the host computer signal when the status is normal and to stop working after receiving an abnormal signal.

7. The connectivity detection circuit according to claim 6, characterized in that, The comparison circuit includes: A first resistor, the first end of which is connected to the voltage input terminal; A second resistor, the first end of which is connected to the detection voltage input terminal; A comparator, wherein the negative input terminal of the comparator is connected to the first resistor, and the positive input terminal of the comparator is connected to the second resistor; A third resistor is connected between the output terminal of the comparator and the positive power supply terminal of the comparator; A fourth resistor, the first end of which is connected to the output terminal of the comparator, and the second end of which is connected to the negative power supply terminal of the comparator and grounded; A fifth resistor and a sixth resistor; the fifth resistor and the sixth resistor are connected in series between the negative input terminal of the comparator and the negative power supply terminal of the comparator; A first capacitor, the first end of which is connected to the positive power supply terminal of the comparator, and the second end of which is grounded.

8. The connectivity detection circuit according to claim 7, characterized in that, The connection anomaly triggering and latching circuit includes: A power supply, which is connected to the positive power supply terminal of the comparator; A trigger, wherein the VCC terminal of the trigger is connected to the power supply, and the GND terminal of the trigger is grounded; A seventh resistor, the first end of which is connected to the power supply, and the second end of which is connected to the D terminal of the trigger; An eighth resistor is provided, the first end of which is connected to the output of the comparator, and the second end of which is connected to the PRE terminal of the flip-flop. A ninth resistor is connected between the output of the comparator and the CLK terminal of the flip-flop; A tenth resistor, the first end of which is connected to the power supply, and the second end of which is connected between the CLR terminals of the trigger. A second capacitor, the first terminal of which is connected to the CLR terminal of the trigger, and the second terminal of which is grounded; A third capacitor, the first terminal of which is connected to the VCC terminal of the trigger, and the second terminal of which is grounded; A twelfth resistor is connected between the positive output terminal of the trigger and the ground terminal.

9. The connectivity detection circuit according to claim 8, characterized in that, It also includes a host computer port, which is connected to the positive output terminal of the trigger.

10. The connectivity detection circuit according to claim 8, characterized in that, It also includes a status indication circuit, which includes a status display device; the first terminal of the status indication circuit is connected to the positive output terminal of the trigger, and the second terminal of the status indication circuit is grounded.

11. The connectivity detection circuit according to claim 8, characterized in that, The signal switch / selection circuit includes: The fourteenth resistor; The fifteenth resistor; An analog switch is provided, wherein the NC terminal of the analog switch is connected to the host computer through the fourteenth resistor, the IN terminal of the analog switch is connected to the positive output terminal of the trigger through the fifteenth resistor, the COM terminal of the analog switch is connected to the chip, the GND terminal of the analog switch is grounded, and the VCC terminal of the analog switch is connected to the power supply. A fourth capacitor, the first terminal of which is connected to the VCC terminal of the analog switch, and the second terminal of which is grounded; An eleventh resistor is connected between the COM terminal and the GND terminal of the analog switch.

12. An adapter, characterized in that, Includes the connectivity detection circuit as described in any one of claims 6 to 11.

13. A chip connectivity detection system, characterized in that, Includes the dual-pin chip adapter with built-in connectivity detection as described in any one of claims 1 to 5, a circuit board, and the connectivity detection circuit as described in any one of claims 6 to 11; The probe unit of the dual-needle chip adapter with built-in connectivity detection is electrically connected to the circuit board through the pad unit of the circuit board; the pad unit corresponding to the position of the probe group includes a first pad and a second pad, and the positions of the first pad and the second pad correspond to the positions of the first probe and the second probe, respectively. The first probe is electrically connected to the voltage input terminal of the connectivity detection circuit; The second probe is electrically connected to the detection voltage input terminal of the connectivity detection circuit.

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