Gate driving circuit, display panel and display device

Abstract

This utility model provides a gate driving circuit, a display panel, and a display device, relating to the field of display technology, for improving signal output stability and narrowing the bezel width of display products. The display panel includes a substrate and a gate driving circuit disposed on the substrate. The gate driving circuit includes cascaded multi-stage shift registers, each shift register including a second output control node, a first node control transistor, a second node control transistor, and a third node control transistor. The active layers of the second node control transistor, the third node control transistor, and the first node control transistor are arranged along a first direction. A first conductive connection portion serves as the second output control node, with its first end coupled to the second electrodes of the second and third node control transistors, and its second end coupled to the first electrode of the first node control transistor.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, more and more display products are integrating gate drive circuits in the bezel area. This integration method helps improve the driving performance of display products. The layout of the gate drive circuit not only determines the bezel width of the display product, but also the stability of the output signal of the gate drive circuit. Therefore, how to better layout the gate drive circuit to improve signal output stability and narrow the bezel width of display products has become an urgent technical problem to be solved. Utility Model Content

[0003] The purpose of this invention is to provide a gate driving circuit, a display panel, and a display device to improve signal output stability and narrow the bezel width of display products.

[0004] To achieve the above objectives, this utility model provides the following technical solution:

[0005] The first aspect of this utility model provides a display panel, including a substrate and a gate driving circuit disposed on the substrate. The gate driving circuit includes a cascaded multi-stage shift register, and the shift register includes a second output control node, a first node control transistor, a second node control transistor, and a third node control transistor.

[0006] The active layer of the second node control transistor, the active layer of the third node control transistor, and the active layer of the first node control transistor are arranged along a first direction.

[0007] The shift register further includes a first conductive connection portion, which serves as the second output control node. The first conductive connection portion includes at least a portion extending along a first direction. A first end of the first conductive connection portion is coupled to the second pole of the second node control transistor and the second pole of the third node control transistor. A second end of the first conductive connection portion is coupled to the first pole of the first node control transistor.

[0008] Optionally, the active layer of the second node control transistor extends along the first direction, and the active layer of the third node control transistor extends along the first direction.

[0009] The portion of the active layer of the second node control transistor used to form the second electrode of the second node control transistor is coupled to the portion of the active layer of the third node control transistor used to form the second electrode of the third node control transistor, forming a first common connection terminal of an integral structure; the first end of the first conductive connection portion is coupled to the first common connection terminal.

[0010] Optionally, the active layer of the first node control transistor extends along a first direction, and the active layer of the first node control transistor and the active layer of the third node control transistor are offset along a second direction, which intersects with the first direction; the portion of the active layer of the first node control transistor used to form the second electrode of the first node control transistor is closer to the active layer of the third node control transistor than the portion of the active layer of the first node control transistor used to form the first electrode of the first node control transistor.

[0011] The second end of the first conductive connection portion is coupled to the portion of the active layer of the first node control transistor used to form the second electrode of the first node control transistor.

[0012] Optionally, the display panel further includes at least one second-level signal line; the shift register further includes a second gating output transistor and a first capacitor; the second plate of the first capacitor and the first electrode of the second gating output transistor are coupled to the same second-level signal line, or the second plate of the first capacitor and the first electrode of the second gating output transistor are coupled to different second-level signal lines; the second electrode of the second gating output transistor is coupled to the gate drive signal output terminal;

[0013] When the second plate of the first capacitor and the first plate of the second gate output transistor are coupled to the same second level signal line, the shift register further includes a first gate connection portion, and the first gate connection portion, the first plate of the first capacitor and the gate of the second gate output transistor are coupled sequentially along the second direction; the second end of the first conductive connection portion is also coupled to the first gate connection portion.

[0014] Optionally, the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the second level signal line coupled to it on the substrate at least partially overlap.

[0015] Optionally, the first conductive connection portion further includes a connection body portion connected between the first end and the second end, the connection body portion extending along a first direction; at least a portion of the orthographic projection of the active layer of the third node control transistor on the substrate is located between the orthographic projection of the connection body portion on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate.

[0016] Both the first end and the second end extend along the second direction, and at least a portion of the orthographic projection of the active layer of the third node control transistor onto the substrate is located between the orthographic projection of the first end onto the substrate and the orthographic projection of the second end onto the substrate.

[0017] Optionally, the display panel includes a first gate metal layer, a second gate metal layer, and a third gate metal layer sequentially stacked along a direction away from the substrate.

[0018] The first node control transistor includes an oxide transistor, an oxide active layer, and at least one of a top gate layer and a bottom gate layer. The top gate layer is located on the side of the oxide active layer facing away from the substrate, and the bottom gate layer is located on the side of the oxide active layer facing the substrate. The bottom gate layer is disposed in the same layer and with the same material as the first gate metal layer or the second gate metal layer. The top gate layer is disposed in the same layer and with the same material as the second gate metal layer or the third gate metal layer.

[0019] Optionally, the bottom gate layer and the top gate layer are coupled together; or, the bottom gate layer and the top gate layer are independent of each other.

[0020] Optionally, the display panel further includes a first first level signal line; the shift register further includes a second capacitor and a first gating output transistor, the first plate of the second capacitor is coupled to the gate of the first gating output transistor, the second plate of the second capacitor is coupled to the gate drive signal output terminal, the first terminal of the first gating output transistor is coupled to the first first level signal line, and the second terminal of the first gating output transistor is coupled to the gate drive signal output terminal.

[0021] The first electrode of the second capacitor is disposed in the same layer and made of the same material as the first gate metal layer, the second gate metal layer, or the third gate metal layer; the second electrode of the second capacitor is disposed in the same layer and made of the same material as the first gate metal layer, the second gate metal layer, or the third gate metal layer; the first electrode of the second capacitor and the second electrode of the second capacitor are disposed in different layers.

[0022] Optionally, the shift register further includes a second gate connection portion, wherein the second gate connection portion, the first plate of the second capacitor, and the gate of the first gating output transistor are sequentially coupled along the second direction;

[0023] The shift register further includes a second conductive connection portion coupled to the second gate connection portion and coupled to at least one of the top gate layer and the bottom gate layer of the first node control transistor.

[0024] Optionally, the display panel further includes a first first level signal line; the shift register further includes a second capacitor and a first gating output transistor, the first plate of the second capacitor is coupled to the gate of the first gating output transistor, the second plate of the second capacitor is coupled to the gate drive signal output terminal, the first terminal of the first gating output transistor is coupled to the first first level signal line, and the second terminal of the first gating output transistor is coupled to the gate drive signal output terminal.

[0025] The first electrode of the second capacitor includes a first sub-electrode and a second sub-electrode disposed opposite to each other. The first sub-electrode is disposed in the same layer and with the same material as the first gate metal layer, and the second sub-electrode is disposed in the same layer and with the same material as the third gate metal layer. The second electrode of the second capacitor is located between the first sub-electrode and the second sub-electrode, and the second electrode of the second capacitor is disposed in the same layer and with the same material as the second gate metal layer.

[0026] Optionally, the shift register further includes a second gate connection portion, and the gates of the second gate connection portion, the first sub-plate, and the first gating output transistor are sequentially coupled along the second direction;

[0027] The shift register further includes a second conductive connection portion coupled to the second gate connection portion and coupled to at least one of the top gate layer and the bottom gate layer of the first node control transistor.

[0028] Optionally, the display panel further includes a first first level signal line; the shift register further includes a second capacitor and a first gating output transistor, the first plate of the second capacitor is coupled to the gate of the first gating output transistor, the second plate of the second capacitor is coupled to the gate drive signal output terminal, the first terminal of the first gating output transistor is coupled to the first first level signal line, and the second terminal of the first gating output transistor is coupled to the gate drive signal output terminal.

[0029] The first electrode of the second capacitor includes a first sub-electrode and a second sub-electrode disposed opposite to each other. The second electrode of the second capacitor is located between the first sub-electrode and the second sub-electrode. The second sub-electrode or the second electrode of the second capacitor is disposed in the same layer and with the same material as the oxide active layer.

[0030] Optionally, the shift register further includes a compensation capacitor, the first plate of which is coupled to the first plate of the second capacitor, the second plate of which is coupled to the second plate of the second capacitor, and the second plate of which is also coupled to the gate drive signal output terminal of the shift register.

[0031] The orthographic projection of the active layer of the first gated output transistor on the substrate and the orthographic projection of the first plate of the compensation capacitor on the substrate are arranged along a first direction.

[0032] Optionally, the shift register further includes a fourth conductive connection portion, which is coupled to the second plate of the compensation capacitor; the fourth conductive connection portion also serves as an input signal terminal coupled to the input transistor in the adjacent N-stage shift register, where N is an integer greater than or equal to 1.

[0033] Optionally, the fourth conductive connection portion is disposed in the same layer and made of the same material as the second gate metal layer.

[0034] Optionally, the display panel further includes at least two clock signal lines and a second first-level signal line; the shift register further includes an input transistor and a transmission transistor, the gate of the input transistor is coupled to the corresponding clock signal line, the first terminal of the input transistor is coupled to an input signal terminal, and the second terminal of the input transistor and the first terminal of the transmission transistor are both coupled to the input node in the shift register; the gate of the transmission transistor is coupled to the second first-level signal line, and the second terminal of the transmission transistor is coupled to a first output control node;

[0035] The portion of the active layer of the input transistor used to form the second electrode of the input transistor is coupled to the portion of the active layer of the transmission transistor used to form the first electrode of the transmission transistor, forming a second common connection terminal of an integral structure.

[0036] The shift register further includes a third conductive connection portion, which serves as the input node and is coupled to the second common connection terminal.

[0037] Optionally, the orthographic projection of the third conductive connection portion on the substrate and the orthographic projection of the active layer of the third node control transistor on the substrate are arranged along a second direction, and the third conductive connection portion is coupled to the gate of the third node control transistor.

[0038] Optionally, the display panel further includes a second first-level signal line; the shift register further includes a first pull-down transistor, the gate of the first pull-down transistor is coupled to the second gate connection portion, the first electrode of the first pull-down transistor is coupled to the second first-level signal line, and the second electrode of the first pull-down transistor is coupled to the second conductive connection portion.

[0039] Optionally, the display panel further includes multiple sub-pixels, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit being coupled to a light emission control signal input terminal, a reset signal input terminal, and a scan signal input terminal respectively; the gate driving signal output terminal of the shift register serves as the light emission control signal input terminal, the reset signal input terminal, or the scan signal input terminal.

[0040] Based on the above-described display panel technical solution, the second aspect of this utility model provides a display device.

[0041] Based on the above-mentioned display panel technical solution, the third aspect of this utility model provides a gate driving circuit, which is applied to the above-mentioned display panel; the gate driving circuit includes: a plurality of cascaded shift registers, each shift register including a first output control node, a first gating output sub-circuit, a pull-down sub-circuit, and a gate driving signal output terminal;

[0042] The first gating output sub-circuit is coupled to the first output control node, the first first level signal input terminal and the gate drive signal output terminal respectively, and is used to control the electrical connection between the first first level signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the first output control node.

[0043] The pull-down sub-circuit is coupled to the control signal input terminal and the pull-down signal input terminal respectively, and the pull-down sub-circuit is also coupled to the first output control node or the gate drive signal output terminal; it is used to control the potential of the first output control node according to the pull-down signal input terminal under the control of the control signal input terminal; or, according to the pull-down signal input terminal, control the potential of the gate drive signal output terminal.

[0044] Optionally, the pull-down sub-circuit includes a first pull-down transistor, the gate of which is coupled to the control signal input terminal, the first terminal of which is coupled to the pull-down signal input terminal, and the second terminal of which is coupled to the first output control node or the gate drive signal output terminal.

[0045] Optionally, the pull-down signal input terminal includes a second first-level signal input terminal; the potential of the second first-level signal input terminal is the same as or different from that of the first first-level signal input terminal.

[0046] Optionally, the shift register further includes an input sub-circuit and an input node. The input sub-circuit is coupled to a first clock signal input terminal, an input signal terminal, and the input node, respectively, and is used to control the electrical connection between the input signal terminal and the input node to be turned on or off under the control of the first clock signal input terminal.

[0047] When the pull-down sub-circuit is coupled to the first output control node, the input node or the first output control node is multiplexed as the control signal input terminal.

[0048] Optionally, the shift register further includes an input sub-circuit and an input node. The input sub-circuit is coupled to a first clock signal input terminal, an input signal terminal, and the input node, respectively, and is used to control the electrical connection between the input signal terminal and the input node to be turned on or off under the control of the first clock signal input terminal.

[0049] The shift register further includes a second gating output sub-circuit and a second output control node. The second gating output sub-circuit is coupled to the second output control node, the gate drive signal output terminal, and the second level signal input terminal, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the second output control node.

[0050] When the pull-down sub-circuit is coupled to the gate drive signal output terminal: the input node, the first output control node, or the second output control node is multiplexed as the control signal input terminal; or, the gate drive signal output terminal of the adjacent next-stage shift register is multiplexed as the pull-down signal input terminal coupled to the pull-down sub-circuit in the current-stage shift register.

[0051] Optionally, the pull-down sub-circuit includes a second pull-down transistor and a coupling capacitor. The gate of the second pull-down transistor is coupled to the control signal input terminal, the first terminal of the second pull-down transistor is coupled to the pull-down signal input terminal, the second terminal of the second pull-down transistor is coupled to the first plate of the coupling capacitor, and the second plate of the coupling capacitor is coupled to the first output control node.

[0052] Optionally, the control signal input terminal includes the first output control node, and the pull-down signal input terminal includes a second clock signal input terminal.

[0053] Optionally, the shift register further includes: a second gating output sub-circuit and a second output control node, wherein the second gating output sub-circuit is coupled to the second output control node, the gate drive signal output terminal and the second level signal input terminal respectively, and is used to control the electrical connection between the gate drive signal output terminal and the second level signal input terminal to be turned on or off under the control of the second output control node;

[0054] The shift register further includes a first node control sub-circuit, which is coupled to the second output control node, the second first level signal input terminal and the first output control node respectively, and is used to control the electrical connection between the second output control node and the second first level signal input terminal to be turned on or off under the control of the first output control node.

[0055] Optionally, the shift register further includes: a second gating output sub-circuit and a second output control node, wherein the second gating output sub-circuit is coupled to the second output control node, the gate drive signal output terminal and the second level signal input terminal respectively, and is used to control the electrical connection between the gate drive signal output terminal and the second level signal input terminal to be turned on or off under the control of the second output control node;

[0056] The shift register further includes an input sub-circuit and an input node. The input sub-circuit is coupled to a first clock signal input terminal, an input signal terminal, and the input node, respectively, and is used to control the electrical connection between the input signal terminal and the input node to be turned on or off under the control of the first clock signal input terminal.

[0057] The shift register further includes a first node control sub-circuit, which is coupled to the second output control node, the second first level signal input terminal and the input node respectively, and is used to control the electrical connection between the second output control node and the second first level signal input terminal to be turned on or off under the control of the input node.

[0058] Optionally, the shift register further includes a second gating output sub-circuit and a second output control node. The second gating output sub-circuit is coupled to the second output control node, the gate drive signal output terminal, and the local brush control signal input terminal, respectively, and is used to control the electrical connection between the gate drive signal output terminal and the local brush control signal input terminal to be turned on or off under the control of the second output control node.

[0059] Optionally, the shift register further includes a first cascaded output sub-circuit and a second cascaded output sub-circuit;

[0060] The first cascaded output sub-circuit is coupled to the first output control node, the first first level signal input terminal and the cascaded signal output terminal respectively, and is used to control the electrical connection between the first first level signal input terminal and the cascaded signal output terminal to be turned on or off under the control of the first output control node.

[0061] The second cascaded output sub-circuit is coupled to the second output control node, the second level signal input terminal, and the cascaded signal output terminal, respectively, and is used to control the electrical connection between the second level signal input terminal and the cascaded signal output terminal to be turned on or off under the control of the second output control node.

[0062] Optionally, the shift register further includes:

[0063] The second node control sub-circuit is coupled to the reset signal input terminal, the second first level signal input terminal, and the second output control node, respectively, and is used to control the electrical connection between the second first level signal input terminal and the second output control node to be turned on or off under the control of the reset signal input terminal.

[0064] The third node control sub-circuit is coupled to the input node, the second level signal input terminal and the second output control node respectively, and is used to control the electrical connection between the second level signal input terminal and the second output control node to be turned on or off under the control of the input node.

[0065] The transmission sub-circuit is coupled to the second first-level signal input terminal, the input node, and the first output control node, respectively, and is used to control the electrical connection between the input node and the first output control node to be turned on or off under the control of the second first-level signal input terminal.

[0066] In the technical solution provided by this utility model, the active layers of the second node control transistor, the third node control transistor, and the first node control transistor are arranged along a first direction. The first conductive connection portion includes at least a portion extending along the first direction, such that the second poles of the second node control transistor and the third node control transistor are coupled together and coupled to the first end of the first conductive connection portion. The second end of the first conductive connection portion is coupled to the first pole of the first node control transistor. This not only reduces the overall layout space occupied by the first conductive connection portion, the first node control transistor, the second node control transistor, and the third node control transistor in the second direction intersecting the first direction, which is beneficial for narrowing the width of the display panel bezel, but also simplifies the structure of the first conductive connection portion, reduces the connection difficulty between the first conductive connection portion and each control transistor, and allows the first conductive connection portion to be located on one side of the control transistor it is coupled to, and adjacent to, the control transistor it is coupled to, avoids the first conductive connection portion from overlapping with other functional structures, better ensures the stability of the first conductive connection portion as the second output control node, and thus effectively improves the stability of the output signal of the gate drive circuit. Attached Figure Description

[0067] The accompanying drawings, which are included to provide a further understanding of the present invention and constitute a part of this invention, illustrate exemplary embodiments of the present invention and, together with the description thereof, serve to explain the present invention and do not constitute an undue limitation thereof. In the drawings:

[0068] Figure 1 A schematic diagram of the first circuit structure of the shift register provided in an embodiment of this utility model;

[0069] Figure 2 A schematic diagram of the second circuit structure of the shift register provided in an embodiment of this utility model;

[0070] Figure 3 A schematic diagram of the third circuit structure of the shift register provided in an embodiment of this utility model;

[0071] Figure 4 The first driving timing diagram of the shift register provided in the embodiment of this utility model;

[0072] Figure 5 A schematic diagram of the fourth circuit structure of the shift register provided in an embodiment of this utility model;

[0073] Figure 6 A schematic diagram of the fifth circuit structure of the shift register provided in an embodiment of this utility model;

[0074] Figure 7The second driving timing diagram of the shift register provided in the embodiment of this utility model;

[0075] Figure 8 A schematic diagram of the sixth circuit structure of the shift register provided in an embodiment of this utility model;

[0076] Figure 9 A schematic diagram of the seventh circuit structure of the shift register provided in an embodiment of this utility model;

[0077] Figure 10 A schematic diagram of the eighth circuit structure of the shift register provided in this embodiment of the utility model;

[0078] Figure 11 A schematic diagram of the ninth circuit structure of the shift register provided in an embodiment of this utility model;

[0079] Figure 12 A schematic diagram of the tenth circuit structure of the shift register provided in this embodiment of the utility model;

[0080] Figure 13 The third driving timing diagram of the shift register provided for an embodiment of this utility model;

[0081] Figure 14 The fourth driving timing diagram of the shift register provided in the embodiment of this utility model;

[0082] Figure 15 A schematic diagram of the eleventh circuit structure of the shift register provided in this embodiment of the utility model;

[0083] Figure 16 A schematic diagram of the first layout of the first active layer and the first gate metal layer in the shift register provided in an embodiment of the present utility model;

[0084] Figure 17 A schematic diagram of the first layout of the second gate metal layer and the second active layer in the shift register provided for an embodiment of this utility model;

[0085] Figure 18 In order to be in Figure 16 Add on the basis Figure 17 Schematic diagram behind the film layer;

[0086] Figure 19 A schematic diagram of the first layout of the third gate metal layer in the shift register provided in an embodiment of this utility model;

[0087] Figure 20 In order to be in Figure 18 Add on the basis Figure 19 Schematic diagram behind the film layer;

[0088] Figure 21A schematic diagram of the first layout of the first source-drain metal layer in the shift register provided in this embodiment of the utility model;

[0089] Figure 22 In order to be in Figure 20 Add on the basis Figure 21 Schematic diagram behind the film layer;

[0090] Figure 23 A schematic diagram of the twelfth circuit structure of the shift register provided in this embodiment of the utility model;

[0091] Figure 24 This is a schematic diagram of the second layout of the second gate metal layer in the shift register provided in an embodiment of the present invention;

[0092] Figure 25 In order to be in Figure 16 Add on the basis Figure 24 membrane and Figure 19 Schematic diagram behind the film layer;

[0093] Figure 26 A schematic diagram of the second layout of the first source-drain metal layer in the shift register provided in an embodiment of this utility model;

[0094] Figure 27 A schematic diagram of the layout of the second source-drain metal layer in the shift register provided in this embodiment of the utility model;

[0095] Figure 28 In order to be in Figure 25 Add on the basis Figure 26 membrane and Figure 27 Schematic diagram behind the film layer;

[0096] Figure 29 A schematic diagram of the circuit structure of the sub-pixel driving circuit provided in an embodiment of this utility model;

[0097] Figure 30 The driving timing diagram of the sub-pixel driving circuit provided in the embodiment of this utility model is shown. Detailed Implementation

[0098] To further illustrate the gate driving circuit, display panel, and display device provided in the embodiments of this utility model, a detailed description is provided below with reference to the accompanying drawings.

[0099] Please see Figures 15 to 28 This utility model provides a display panel, including a substrate and a gate driving circuit disposed on the substrate. The gate driving circuit includes a cascaded multi-stage shift register, and the shift register includes a second output control node N3, a first node control transistor T6, a second node control transistor T7 and a third node control transistor T3.

[0100] The active layer of the second node control transistor T7, the active layer of the third node control transistor T3, and the active layer of the first node control transistor T6 are arranged along a first direction.

[0101] The shift register further includes a first conductive connection portion 31, which serves as the second output control node N3. The first conductive connection portion 31 includes at least a portion extending along a first direction. The first end portion 31b of the first conductive connection portion 31 is coupled to the second pole of the second node control transistor T7 and the second pole of the third node control transistor T3. The second end portion 31c of the first conductive connection portion 31 is coupled to the first pole of the first node control transistor T6.

[0102] It should be noted that, Figures 16 to 22 for Figure 15 The layout corresponding to the circuit structure Figures 24 to 28 for Figure 23 The circuit structure corresponds to the layout layout. In the two layout layouts, the layouts of the first active layer (polysilicon active layer), the first gate metal layer, the second active layer (oxide active layer), and the third gate metal layer are the same and can be referred to each other.

[0103] like Figure 16 The diagram illustrates the active layer and gate of each transistor, specifically as follows: active layer 21 of input transistor T1, gate g1 of input transistor T1; active layer 22 of transmission transistor T2, gate g2 of transmission transistor T2; active layer 23 of third node control transistor T3, gate g3 of third node control transistor T3; active layer 24 of second gating output transistor T4, gate g4 of second gating output transistor T4; active layer 25 of first gating output transistor T5, gate g5 of first gating output transistor T5; active layer 27 of second node control transistor T7, gate g7 of second node control transistor T7; active layer 28 of first pull-down transistor T8, gate g8 of first pull-down transistor T8.

[0104] like Figure 17 and Figure 19 As shown, the active layer 26 of the first node control transistor T6, the bottom gate layer g62 of the first node control transistor T6, and the top gate layer g61 of the first node control transistor T6 are illustrated.

[0105] For example, the display panel includes a display area and a peripheral area surrounding the display area. The peripheral area includes a left border area and a right border area, and the display area is located between the left border area and the right border area. The display panel may include a variety of gate driving circuits. Each gate driving circuit may include one gate driving circuit or two gate driving circuits. When one gate driving circuit is included, the gate driving circuit is located in the left border area or the right border area to achieve single-sided driving of the display panel. When two gate driving circuits are included, one gate driving circuit is located in the left border area and the other gate driving circuit is located in the right border area to achieve dual-sided driving of the display panel.

[0106] For example, the active layer of the first node control transistor T6 includes an oxide active layer, and the active layers of the second node control transistor T7 and the third node control transistor T3 include polysilicon active layers, but are not limited thereto.

[0107] For example, the second terminal of the second node control transistor T7 and the second terminal of the third node control transistor T3 are coupled together and coupled to the first end 31b of the first conductive connection portion 31.

[0108] According to the specific structure of the display panel described above, in the display panel provided by this utility model embodiment, the active layer of the second node control transistor T7, the active layer of the third node control transistor T3, and the active layer of the first node control transistor T6 are arranged along a first direction. The first conductive connection portion 31 includes at least a portion extending along the first direction, such that the second electrode of the second node control transistor T7 and the second electrode of the third node control transistor T3 are coupled together and coupled to the first end 31b of the first conductive connection portion 31, and the second end 31c of the first conductive connection portion 31 is coupled to the first electrode of the first node control transistor T6. This not only reduces the size of the second node control transistor T7 intersecting the first direction but also... In terms of orientation, the layout space occupied by the first conductive connection part 31, the first node control transistor T6, the second node control transistor T7, and the third node control transistor T3 is conducive to narrowing the width of the display panel bezel. It also simplifies the structure of the first conductive connection part 31, reduces the connection difficulty between the first conductive connection part 31 and each control transistor, and allows the first conductive connection part 31 to be located on one side of its coupled control transistor and adjacent to its coupled control transistor. This avoids the first conductive connection part 31 from overlapping with other functional structures, better ensuring the stability of the first conductive connection part 31 as the second output control node N3, thereby effectively improving the stability of the gate drive circuit output signal.

[0109] Please see Figures 15 to 28In some embodiments, the active layer of the second node control transistor T7 extends along a first direction, and the active layer of the third node control transistor T3 extends along the first direction; the portion of the active layer of the second node control transistor T7 used to form the second electrode of the second node control transistor T7 is coupled to the portion of the active layer of the third node control transistor T3 used to form the second electrode of the third node control transistor T3, forming a first common connection terminal 40 of an integral structure; the first end 31b of the first conductive connection portion 31 is coupled to the first common connection terminal 40.

[0110] For example, the active layer of the second node control transistor T7 is a strip pattern extending along the first direction, and the active layer of the third node control transistor T3 is a strip pattern extending along the first direction, but it is not limited to this.

[0111] For example, the portion of the active layer of the second node control transistor T7 used to form the second electrode of the second node control transistor T7 is disposed opposite to the portion of the active layer of the third node control transistor T3 used to form the second electrode of the third node control transistor T3 along a first direction, and is coupled together to form a first common connection terminal 40 of an integral structure.

[0112] The above configuration optimizes the overall layout of the first conductive connection 31, the first node control transistor T6, the second node control transistor T7, and the third node control transistor T3, reducing the overall layout space occupied. At the same time, it reduces the connection difficulty between the first conductive connection 31 and each control transistor, allowing the first conductive connection 31 to be located on one side of its coupled control transistor and adjacent to it. This avoids the first conductive connection 31 overlapping with other functional structures, better ensuring the stability of the first conductive connection 31 as the second output control node N3, thereby effectively improving the stability of the gate drive circuit output signal.

[0113] Please see Figures 15 to 28 In some embodiments, the active layer of the first node control transistor T6 extends along a first direction, and the active layer of the first node control transistor T6 and the active layer of the third node control transistor T3 are offset along a second direction, which intersects with the first direction; the portion of the active layer of the first node control transistor T6 used to form the second electrode of the first node control transistor T6 is closer to the active layer of the third node control transistor T3 than the portion of the active layer of the first node control transistor T6 used to form the first electrode of the first node control transistor T6.

[0114] The second end portion 31c of the first conductive connection portion 31 is coupled to the portion of the active layer of the first node control transistor T6 used to form the second electrode of the first node control transistor T6.

[0115] For example, the first direction includes the longitudinal direction, and the second direction includes the transverse direction, but is not limited thereto.

[0116] The above configuration allows the portion of the active layer of the first node control transistor T6 used to form the second electrode of the first node control transistor T6, as well as the first common connection terminal 40, to be arranged more centrally. This helps to further simplify the structure of the first conductive connection portion 31, reduce the area occupied by the first conductive connection portion 31, and better achieve the narrow bezel design of the display panel.

[0117] like Figures 15 to 28 As shown, in some embodiments, the display panel further includes at least one second-level signal line (e.g., Figure 21 The first second-level signal line VGH10 in the middle, such as Figure 26 The shift register also includes a second gating output transistor T4 and a first capacitor C1; the second plate C12 of the first capacitor C1 and the first electrode of the second gating output transistor T4 are coupled to the same second-level signal line (e.g., the first second-level signal line VGH10 and the second second-level signal line VGH20). Figure 21 The first second-level signal line VGH10 in the first capacitor C1, or the second plate C12 of the first capacitor C1 and the first terminal of the second gating output transistor T4 are coupled to different second-level signal lines (such as...). Figure 26 The first second-level signal line VGH10 and the second second-level signal line VGH20 in the middle); the second terminal of the second gating output transistor T4 is coupled to the gate drive signal output terminal OUT;

[0118] like Figures 15 to 22 As shown, when the second plate C12 of the first capacitor C1 and the first electrode of the second gate output transistor T4 are coupled to the same second level signal line, the shift register further includes a first gate connection portion 41, and the first gate connection portion 41, the first plate C11 of the first capacitor C1 and the gate of the second gate output transistor T4 are sequentially coupled along the second direction; the second end 31c of the first conductive connection portion 31 is also coupled to the first gate connection portion 41.

[0119] like Figures 15 to 22 As shown, exemplarily, the display panel includes a second-level signal line (such as...). Figure 21The first second-level signal line (VGH10) of the first capacitor C1 and the first terminal of the second gating output transistor T4 are coupled to this second-level signal line. It should be noted that, as... Figure 15 As shown, Figure 15 The second-level signal input terminal VGH1, as shown in the diagram, is coupled to the first second-level signal line VGH10.

[0120] like Figures 23 to 28 As shown, exemplarily, the display panel includes two second-level signal lines (such as...). Figure 28 The first second-level signal line VGH10 and the second second-level signal line VGH20 are connected to the first second-level signal line VGH20 via the second plate C12 of the first capacitor C1, and the first terminal of the second select output transistor T4 is connected to the other second-level signal line VGH10. It should be noted that, as... Figure 23 As shown, Figure 23 The first second-level signal input terminal VGH1 is coupled to the first second-level signal line VGH10, and the second second-level signal input terminal VGH2 is coupled to the second second-level signal line VGH20.

[0121] like Figures 15 to 22 As shown, by way of example, the first gate connection portion 41, the first plate C11 of the first capacitor C1 and the gate of the second gate output transistor T4 are formed into a single structure.

[0122] The above configuration allows the first plate C11 of the first capacitor C1 and the gate of the second gate output transistor T4 to be coupled to the first conductive connection portion 31 through the first gate connection portion 41, thereby coupling the first plate C11 of the first capacitor C1 and the gate of the second gate output transistor T4 to the second output control node N3. This configuration, while ensuring the connection relationship, effectively simplifies the overall layout of the first conductive connection portion 31, the first capacitor C1, and the second gate output transistor T4, which is conducive to better achieving a narrow bezel design for the display panel.

[0123] like Figures 15 to 28 As shown, in some embodiments, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate and the orthographic projection of the second level signal line coupled to it on the substrate at least partially overlap.

[0124] The above configuration allows the second plate C12 of the first capacitor C1 to be directly coupled to the second level signal line through a via located in the overlapping area, avoiding the via occupying additional layout space and facilitating a narrower bezel for the display panel.

[0125] like Figures 15 to 28 As shown, in some embodiments, the first conductive connection portion 31 further includes a connection body portion 31a connected between the first end portion 31b and the second end portion 31c, the connection body portion 31a extending along a first direction; at least a portion of the orthographic projection of the active layer of the third node control transistor T3 onto the substrate is located between the orthographic projection of the connection body portion 31a onto the substrate and the orthographic projection of the second electrode plate C12 of the first capacitor C1 onto the substrate.

[0126] Both the first end 31b and the second end 31c extend along the second direction, and at least a portion of the orthographic projection of the active layer of the third node control transistor T3 onto the substrate is located between the orthographic projection of the first end 31b onto the substrate and the orthographic projection of the second end 31c onto the substrate.

[0127] For example, the connecting body 31a, the first end 31b and the second end 31c are formed as an integral structure.

[0128] The above layout allows the first conductive connection part 31, the first node control transistor T6, the second node control transistor T7, the third node control transistor T3, the first capacitor C1, and the second gating output transistor T4 to be arranged in a concentrated manner, which not only effectively reduces the overall layout space occupied by these structures, but also reduces the difficulty of connecting the devices.

[0129] In some embodiments, the display panel includes a first gate metal layer, a second gate metal layer, and a third gate metal layer sequentially stacked along a direction away from the substrate.

[0130] The first node control transistor T6 includes an oxide transistor, an oxide active layer, and at least one of a top gate layer g61 and a bottom gate layer g62. The top gate layer g61 is located on the side of the oxide active layer facing away from the substrate, and the bottom gate layer g62 is located on the side of the oxide active layer facing the substrate. The bottom gate layer g62 is disposed in the same layer and with the same material as the first gate metal layer or the second gate metal layer. The top gate layer g61 is disposed in the same layer and with the same material as the second gate metal layer or the third gate metal layer.

[0131] For example, the first node control transistor T6 adopts a single-gate structure, that is, it includes one of the top gate layer g61 and the bottom gate layer g62.

[0132] For example, the first node control transistor T6 adopts a dual-gate structure, including a top gate layer g61 and a bottom gate layer g62. The top gate layer g61 and the bottom gate layer g62 can be implemented using the following film layers: the bottom gate layer g62 is disposed in the same layer and with the same material as the first gate metal layer, and the top gate layer g61 is disposed in the same layer and with the same material as the third gate metal layer; or, the bottom gate layer g62 is disposed in the same layer and with the same material as the second gate metal layer, and the top gate layer g61 is disposed in the same layer and with the same material as the third gate metal layer.

[0133] For example, the bottom gate layer g62 and the top gate layer g61 are coupled together; or, the bottom gate layer g62 and the top gate layer g61 are independent of each other. More specifically, when the bottom gate layer g62 and the top gate layer g61 are coupled together, both the bottom gate layer g62 and the top gate layer g61 are coupled to the first output control node N2. When the bottom gate layer g62 and the top gate layer g61 are independent of each other, one of the bottom gate layer g62 and the top gate layer g61 is coupled to the first output control node N2, and the other of the bottom gate layer g62 and the top gate layer g61 is coupled to an independent control signal terminal for regulating the threshold voltage of the first node control transistor T6.

[0134] The above configuration allows for flexible layout of the top gate layer g61 and the bottom gate layer g62, enabling the gate driving circuit to adapt to different layout space requirements and making the layout of the gate driving circuit more diverse.

[0135] like Figure 15 and Figure 23 As shown, in some embodiments, the display panel further includes a first first-level signal line VGL10; the shift register further includes a second capacitor C2 and a first gating output transistor T5, the first plate C21 of the second capacitor C2 is coupled to the gate of the first gating output transistor T5, the second plate C22 of the second capacitor C2 is coupled to the gate drive signal output terminal OUT, the first terminal of the first gating output transistor T5 is coupled to the first first-level signal line VGL10, and the second terminal of the first gating output transistor T5 is coupled to the gate drive signal output terminal OUT; the first plate C21 of the second capacitor C2 is disposed in the same layer and with the same material as the first gate metal layer, the second gate metal layer or the third gate metal layer; the second plate C22 of the second capacitor C2 is disposed in the same layer and with the same material as the first gate metal layer, the second gate metal layer or the third gate metal layer; the first plate C21 of the second capacitor C2 and the second plate C22 of the second capacitor C2 are disposed in different layers.

[0136] For example, the first electrode C21 of the second capacitor C2 is disposed in the same layer and with the same material as the first gate metal layer, and the second electrode C22 of the second capacitor C2 is disposed in the same layer and with the same material as the second gate metal layer.

[0137] For example, the first electrode C21 of the second capacitor C2 is disposed in the same layer and with the same material as the second gate metal layer, and the second electrode C22 of the second capacitor C2 is disposed in the same layer and with the same material as the third gate metal layer.

[0138] For example, the first electrode C21 of the second capacitor C2 is disposed in the same layer and with the same material as the first gate metal layer, and the second electrode C22 of the second capacitor C2 is disposed in the same layer and with the same material as the third gate metal layer.

[0139] For example, the first electrode C21 of the second capacitor C2 is disposed in the same layer and with the same material as the third gate metal layer, and the second electrode C22 of the second capacitor C2 is disposed in the same layer and with the same material as the second gate metal layer.

[0140] The above configuration allows the second capacitor C2 to be formed simultaneously with the existing gate metal layer in the display panel in the same patterning process, and allows the second capacitor C2 to be flexibly laid out, enabling the gate driving circuit to adapt to the needs of different layout spaces and making the layout of the gate driving circuit more diverse.

[0141] like Figures 15 to 22 As shown, in some embodiments, the shift register further includes a second gate connection portion 42, wherein the second gate connection portion 42, the first plate C21 of the second capacitor C2, and the gate of the first gating output transistor T5 are sequentially coupled along the second direction; the shift register further includes a second conductive connection portion 32, which is coupled to the second gate connection portion 42 and coupled to at least one of the top gate layer g61 and the bottom gate layer g62 of the first node control transistor T6.

[0142] For example, the second gate connection portion 42, the first plate C21 of the second capacitor C2 and the gate of the first gate output transistor T5 are formed into an integral structure.

[0143] For example, the second conductive connection portion 32 is coupled to the second gate connection portion 42, and is also coupled to both the top gate layer g61 and the bottom gate layer g62 of the first node control transistor T6.

[0144] The above configuration enables the second conductive connection portion 32 to simultaneously achieve coupling with the gate of the first node control transistor T6, the first plate C21 of the second capacitor C2, and the gate of the first gating output transistor T5. This not only ensures connection performance but also reduces the layout difficulty of the device, which is beneficial to saving the overall layout space occupied by the shift register.

[0145] like Figures 15 to 28 As shown, in some embodiments, the display panel further includes a first first-level signal line VGL10; the shift register further includes a second capacitor C2 and a first gating output transistor T5, the first plate C21 of the second capacitor C2 is coupled to the gate of the first gating output transistor T5, the second plate C22 of the second capacitor C2 is coupled to the gate drive signal output terminal OUT, the first terminal of the first gating output transistor T5 is coupled to the first first-level signal line VGL10, and the second terminal of the first gating output transistor T5 is coupled to the gate drive signal output terminal OUT;

[0146] The first electrode C21 of the second capacitor C2 includes a first sub-electrode C211 and a second sub-electrode C212 disposed opposite to each other. The first sub-electrode C211 is disposed in the same layer and with the same material as the first gate metal layer. The second sub-electrode C212 is disposed in the same layer and with the same material as the third gate metal layer. The second electrode C22 of the second capacitor C2 is located between the first sub-electrode C211 and the second sub-electrode C212. The second electrode C22 of the second capacitor C2 is disposed in the same layer and with the same material as the second gate metal layer.

[0147] For example, the second sub-electrode C212 is formed as an integral structure with the top gate layer g61 of the first node control transistor T6.

[0148] For example, the shift register further includes a second gate connection portion 42, and the gates of the first sub-plate C211 and the first gate output transistor T5 are sequentially coupled along the second direction; the shift register further includes a second conductive connection portion 32, which is coupled to the second gate connection portion 42 and coupled to at least one of the top gate layer g61 and the bottom gate layer g62 of the first node control transistor T6.

[0149] The above configuration allows the second capacitor C2 to form a sandwich structure, which increases its charge storage capacity and helps stabilize the signal of the first output control node N2. Furthermore, this configuration enables the second conductive connection portion 32 to simultaneously couple with the gate of the first node control transistor T6, the first plate C21 of the second capacitor C2, and the gate of the first gating output transistor T5. This not only ensures connection performance but also reduces the layout complexity of the devices, saving overall layout space occupied by the shift register.

[0150] In some embodiments, the display panel further includes a first first level signal line VGL10; the shift register further includes a second capacitor C2 and a first gating output transistor T5, the first plate C21 of the second capacitor C2 is coupled to the gate of the first gating output transistor T5, the second plate C22 of the second capacitor C2 is coupled to the gate drive signal output terminal OUT, the first terminal of the first gating output transistor T5 is coupled to the first first level signal line VGL10, and the second terminal of the first gating output transistor T5 is coupled to the gate drive signal output terminal OUT;

[0151] The first electrode C21 of the second capacitor C2 includes a first sub-electrode C211 and a second sub-electrode C212 disposed opposite to each other. The second electrode C22 of the second capacitor C2 is located between the first sub-electrode C211 and the second sub-electrode C212. The second sub-electrode C212 or the second electrode C22 of the second capacitor C2 is disposed in the same layer and with the same material as the oxide active layer.

[0152] It should be noted that when the oxide active layer is made conductive, it can be used not only as the source and drain of the first node control transistor T6, but also as the plates of a capacitor to sequentially fabricate a sandwich-structured capacitor. It is worth noting that the plates of both the first capacitor C1 and the second capacitor C2 can be fabricated using the oxide active layer.

[0153] The above configuration makes the second capacitor C2 form a sandwich structure, which is beneficial to increase the charge storage capacity of the second capacitor C2, stabilize the node signal, and also narrow the bezel of the display panel.

[0154] like Figures 15 to 28As shown, in some embodiments, the shift register further includes a compensation capacitor C4, the first plate C41 of the compensation capacitor C4 being coupled to the first plate C21 of the second capacitor C2, the second plate C42 of the compensation capacitor C4 being coupled to the second plate C22 of the second capacitor C2, and the second plate C42 of the compensation capacitor C4 being coupled to the gate drive signal output terminal OUT of the shift register; the orthographic projection of the active layer of the first gating output transistor T5 on the substrate and the orthographic projection of the first plate C41 of the compensation capacitor C4 on the substrate are arranged along a first direction.

[0155] For example, the first plate C41 of the compensation capacitor C4 is disposed in the same layer and with the same material as the first gate metal layer, and the second plate C42 of the compensation capacitor C4 is disposed in the same layer and with the same material as the second gate metal layer.

[0156] The shift register described above also includes a compensation capacitor C4. The first plate C41 of the compensation capacitor C4 is coupled to the first plate C21 of the second capacitor C2, and the second plate C42 of the compensation capacitor C4 is coupled to the second plate C22 of the second capacitor C2. This allows the compensation capacitor C4 to compensate for the charge storage capacity of the second capacitor C2, which is beneficial for further stabilizing the node signal. Simultaneously, the orthographic projection of the active layer of the first gate output transistor T5 on the substrate and the orthographic projection of the first plate C41 of the compensation capacitor C4 on the substrate are aligned along a first direction, which helps to narrow the bezel width of the display panel.

[0157] like Figures 15 to 28 As shown, in some embodiments, the shift register further includes a fourth conductive connection portion 34, which is coupled to the second plate C42 of the compensation capacitor C4; the fourth conductive connection portion 34 also serves as the input signal terminal STV coupled to the input transistor T1 in the adjacent lower N-stage shift register, where N is an integer greater than or equal to 1.

[0158] For example, the fourth conductive connection portion 34 is disposed in the same layer and with the same material as the second gate metal layer.

[0159] For example, the fourth conductive connection portion 34 is formed as an integral structure with the second electrode plate C42 of the compensation capacitor C4, but it is not limited to this.

[0160] The fourth conductive connection portion 34 is formed by using the second gate metal layer, and is coupled to the input transistor T1 in the adjacent lower N-stage shift register through the fourth conductive connection portion 34, which helps to simplify the wiring layout and save wiring space.

[0161] like Figures 23 to 28As shown, in some embodiments, the display panel further includes at least two clock signal lines (such as a first clock signal line CK0 and a second clock signal line CB0) and a second first level signal line VGL20; the shift register further includes an input transistor T1 and a transmission transistor T2, the gate of the input transistor T1 is coupled to the corresponding clock signal line, the first terminal of the input transistor T1 is coupled to the input signal terminal STV, the second terminal of the input transistor T1 and the first terminal of the transmission transistor T2 are both coupled to the input node N1 in the shift register; the gate of the transmission transistor T2 is coupled to the second first level signal line VGL20, and the second terminal of the transmission transistor T2 is coupled to the first output control node N2;

[0162] The portion of the active layer of the input transistor T1 used to form the second electrode of the input transistor T1 is coupled to the portion of the active layer of the transmission transistor T2 used to form the first electrode of the transmission transistor T2, forming a second common connection terminal 43 of an integral structure; the shift register also includes a third conductive connection portion 33, which serves as the input node N1 and is coupled to the second common connection terminal 43.

[0163] For example, the level value of the first level signal transmitted by the second first level signal line VGL20 may be the same as or different from the level value of the first level signal transmitted by the first first level signal line VGL10. Figure 23 As shown, the second first-level signal line VGL20 is used to connect to the second first-level signal input terminal VGL2, and the first first-level signal line VGL10 is used to connect to the first first-level signal input terminal VGL1.

[0164] For example, the gate drive circuit includes a shift register that, when employing, Figure 6 In the structure shown, the first clock signal input terminal CK of the odd-numbered shift register is coupled to one of the first clock signal line CK0 and the second clock signal line CB0, and the second clock signal input terminal CB of the odd-numbered shift register is coupled to the other of the first clock signal line CK0 and the second clock signal line CB0; the connection of the first clock signal input terminal CK and the second clock signal input terminal CB of the even-numbered shift register to the clock signal lines is the opposite of that of the odd-numbered shift registers.

[0165] For example, the gate drive circuit includes a shift register that, when employing, Figure 3In the structure shown, the first clock signal input terminal CK of the odd-numbered shift register is coupled to one of the first clock signal line CK0 and the second clock signal line CB0, and the first clock signal input terminal CK of the even-numbered shift register is coupled to the other of the first clock signal line CK0 and the second clock signal line CB0.

[0166] For example, the active layer of the input transistor T1 includes a strip pattern extending along a first direction. The active layer of the transmission transistor T2 includes a strip pattern extending along the first direction. The active layers of the input transistor T1 and the active layers of the transmission transistor T2 are arranged along the first direction.

[0167] For example, the orthographic projection of the third conductive connection portion 33 on the substrate and the orthographic projection of the active layer of the third node control transistor T3 on the substrate are arranged along the second direction, and the third conductive connection portion 33 is coupled to the gate of the third node control transistor T3.

[0168] The above configuration integrates the active layer of the input transistor T1 and the active layer of the transmission transistor T2 into a single design, eliminating the need for vias. This reduces the manufacturing complexity of the shift register and improves signal stability.

[0169] like Figures 15 to 28 As shown, in some embodiments, the display panel further includes a second first-level signal line VGL20; the shift register further includes a first pull-down transistor T8, the gate of the first pull-down transistor T8 is coupled to the second gate connection portion 42, the first terminal of the first pull-down transistor T8 is coupled to the second first-level signal line VGL20, and the second terminal of the first pull-down transistor T8 is coupled to the second conductive connection portion 32.

[0170] For example, the active layer of the first pull-down transistor T8 includes a strip pattern extending along a first direction.

[0171] For example, the active layer of the input transistor T1, the active layer of the transmission transistor T2, and the active layer of the pull-down transistor are arranged sequentially along a first direction.

[0172] The above configuration helps to further reduce the bezel width occupied by the shift register along the second direction, which is beneficial for achieving a narrow bezel on the display panel.

[0173] It should be noted that, Figure 21 , Figure 22 , Figure 26 and Figure 28The octagonal black via in the image is a connection hole between the first source / drain metal layer and the film layer located on its bottom layer. The film layer on its bottom layer includes a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, and a third gate metal layer. Figure 27 and Figure 28 The quadrilateral square hole in the middle is the connection hole between the second source / drain metal layer and the first source / drain metal layer.

[0174] As shown in Figure 29, in some embodiments, the display panel further includes a plurality of sub-pixels, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit being coupled to a light emission control signal input terminal, a reset signal input terminal and a scan signal input terminal respectively; the gate driving signal output terminal of the shift register serves as the light emission control signal input terminal, the reset signal input terminal or the scan signal input terminal.

[0175] For example, the plurality of sub-pixels, including the plurality of sub-pixel driving circuits, are divided into multiple rows of sub-pixel driving circuits. Each level of the shift register can correspond to at least one row of sub-pixel driving circuits. The shift register is coupled to each sub-pixel driving circuit in the corresponding at least one row of sub-pixel driving circuits and is used to provide corresponding signals to each sub-pixel driving circuit.

[0176] For example, the sub-pixel driving circuit includes a driving transistor M3, a power control transistor M5, a light emission control transistor M6, a compensation transistor M2, a data writing transistor M4, a first reset transistor M1, a second reset transistor M7, a third reset transistor M8, and a capacitor structure.

[0177] The gate of the first reset transistor M1 is coupled to the first reset signal input terminal Reset1, the first terminal of the first reset transistor M1 is coupled to the first initialization signal input terminal INT1, and the second terminal of the first reset transistor M1 is coupled to the second terminal of the driving transistor M3.

[0178] The gate of the compensation transistor M2 is coupled to the second scan signal input terminal Gate2, the first terminal of the compensation transistor M2 is coupled to the second terminal of the driving transistor M3, and the second terminal of the compensation transistor M2 is coupled to the gate of the driving transistor M3.

[0179] The gate of the data writing transistor M4 is coupled to the first scan signal input terminal Gate1, the first terminal of the data writing transistor M4 is coupled to the data signal input terminal Data, and the second terminal of the data writing transistor M4 is coupled to the first terminal of the driving transistor M3.

[0180] The gate of the power control transistor M5 is coupled to the light emission control signal input terminal EM, the first terminal of the power control transistor M5 is coupled to the power signal input terminal VDD, and the second terminal of the power control transistor M5 is coupled to the first terminal of the driving transistor M3.

[0181] The gate of the light-emitting control transistor M6 is coupled to the light-emitting control signal input terminal EM. The first terminal of the light-emitting control transistor M6 is coupled to the second terminal of the driving transistor M3. The second terminal of the light-emitting control transistor M6 is coupled to the anode of the light-emitting element L included in the sub-pixel. The cathode of the light-emitting element L receives the negative power supply signal VSS.

[0182] The gate of the second reset transistor M7 is coupled to the second reset signal input terminal Reset2, the first terminal of the second reset transistor M7 is coupled to the second initialization signal INIT2, and the second terminal of the second reset transistor M7 is coupled to the anode of the light-emitting element L.

[0183] The gate of the third reset transistor M8 is coupled to the second reset signal input terminal Reset2, the first terminal of the third reset transistor M8 is coupled to the third initialization signal INIT3, and the second terminal of the third reset transistor M8 is coupled to the first terminal of the driving transistor M3.

[0184] For example, the gate drive signal output terminal of the shift register can be: the light emission control signal input terminal EM, the first reset signal input terminal Reset1, the second reset signal input terminal Reset2, the first scan signal input terminal Gate1, or the second scan signal input terminal Gate2.

[0185] like Figure 30 The diagram illustrates the driving timing of the sub-pixel driving circuit. The driving timing is divided into three stages: reset stage Y1, compensation writing stage Y2, and light emission stage Y3. In reset stage Y1, the first reset transistor M1, the second reset transistor M7, and the third reset transistor M8 are used to perform the reset function. In compensation writing stage Y2, data signals are written through data writing transistor M4 and compensation transistor M2, and threshold voltage compensation is performed on the driving transistor M3. In light emission stage Y3, the light-emitting element L is controlled to emit light.

[0186] It should be noted that by adjusting the timing of the clock signal and frame start signal (such as the signal received by the input signal terminal STV of the first-stage shift register) received by the shift register, the gate drive signal output by the gate drive signal output terminal can be adjusted, thereby enabling the gate drive signal output terminal of the shift register to be used as: the light emission control signal input terminal EM, the first reset signal input terminal Reset1, the second reset signal input terminal Reset2, the first scan signal input terminal Gate1, or the second scan signal input terminal Gate2.

[0187] This utility model embodiment also provides a display device, including the display panel provided in the above embodiment.

[0188] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0189] In the display panel provided in the above embodiment, the active layers of the second node control transistor T7, the third node control transistor T3, and the first node control transistor T6 are arranged along a first direction. The first conductive connection portion 31 includes at least a portion extending along the first direction, such that the second electrode of the second node control transistor T7 and the second electrode of the third node control transistor T3 are coupled together and coupled to the first end portion 31b of the first conductive connection portion 31, and the second end portion 31c of the first conductive connection portion 31 is coupled to the first electrode of the first node control transistor T6. This not only reduces the distance between the first conductive connection portion and the second electrode in the second direction intersecting the first direction, but also... The layout space occupied by the first conductive connection part 31, the first node control transistor T6, the second node control transistor T7, and the third node control transistor T3 is conducive to narrowing the width of the display panel bezel. It also simplifies the structure of the first conductive connection part 31, reduces the connection difficulty between the first conductive connection part 31 and each control transistor, and allows the first conductive connection part 31 to be located on one side of the control transistor it is coupled to, and adjacent to the control transistor it is coupled to, avoids the first conductive connection part 31 from overlapping with other functional structures, and better ensures the stability of the first conductive connection part 31 as the second output control node N3, thereby effectively improving the stability of the gate drive circuit output signal.

[0190] The display device provided in this embodiment of the present invention, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0191] like Figure 1 and Figure 8As shown, this utility model embodiment also provides a gate driving circuit, which is applied to the display panel provided in the above embodiment; the gate driving circuit includes: a plurality of cascaded shift registers, each shift register including a first output control node N2, a first gating output sub-circuit 10, a pull-down sub-circuit 11 and a gate driving signal output terminal OUT;

[0192] The first gating output sub-circuit 10 is coupled to the first output control node N2, the first first level signal input terminal VGL1 and the gate drive signal output terminal OUT respectively, and is used to control the conduction or disconnection of the electrical connection between the first first level signal input terminal VGL1 and the gate drive signal output terminal OUT under the control of the first output control node N2.

[0193] The pull-down sub-circuit 11 is coupled to the control signal input terminal K1 and the pull-down signal input terminal K2 respectively. The pull-down sub-circuit 11 is also coupled to the first output control node N2 or the gate drive signal output terminal OUT. It is used to control the potential of the first output control node N2 according to the pull-down signal input terminal K2 under the control of the control signal input terminal K1; or, according to the pull-down signal input terminal K2, control the potential of the gate drive signal output terminal OUT.

[0194] For example, the first level signal input to the first first level signal input terminal VGL1 can be a low level signal, but it is not limited to this. The first first level signal line VGL10 included in the display panel can serve as the first level signal input terminal.

[0195] For example, the control signal input terminal K1 can be a node included in the shift register, or it can be the gate drive signal output terminal OUT included in other stages of shift registers, but it is not limited to this.

[0196] For example, the pull-down signal input terminal K2 is used to input a pull-down signal, which acts on the first output control node N2 or the gate drive signal output terminal OUT to pull down the potential of the first output control node N2 or the gate drive signal output terminal OUT.

[0197] For example, the first gating output sub-circuit 10 includes a first gating output transistor T5, the gate of the first gating output transistor T5 is coupled to the first output control node N2, the first terminal of the first gating output transistor T5 is coupled to the first first level signal input terminal VGL1, and the second terminal of the first gating output transistor T5 is coupled to the gate drive signal output terminal OUT.

[0198] As can be seen from the specific structure of the gate driving circuit described above, in the gate driving circuit provided by this utility model embodiment, by setting the pull-down sub-circuit 11, the pull-down sub-circuit 11 can control the pull-down of the potential of the first output control node N2 to be low according to the pull-down signal input terminal K2; or, it can control the pull-down of the potential of the gate driving signal output terminal OUT to be low according to the pull-down signal input terminal K2; thereby stabilizing the potential of the first output control node N2 or the gate driving signal output terminal OUT, so that the gate driving signal output terminal OUT of the shift register can output a low potential signal stably for a long time.

[0199] like Figure 3 and Figure 10 As shown, in some embodiments, the pull-down sub-circuit 11 includes a first pull-down transistor T8, the gate of the first pull-down transistor T8 is coupled to the control signal input terminal K1, the first terminal of the first pull-down transistor T8 is coupled to the pull-down signal input terminal K2, and the second terminal of the first pull-down transistor T8 is coupled to the first output control node N2 or the gate drive signal output terminal OUT.

[0200] For example, the first pull-down transistor T8 includes a P-type transistor.

[0201] For example, the pull-down signal input terminal K2 includes a second first-level signal input terminal VGL2; the potential of the second first-level signal input terminal VGL2 may be the same as or different from the potential of the first-level signal input terminal VGL1. More specifically, the display panel may include a second first-level signal line VGL20, and the first-level signal line may serve as the second first-level signal input terminal VGL2, but is not limited thereto.

[0202] like Figures 1 to 3 As shown, in some embodiments, the shift register further includes an input sub-circuit 12 and an input node N1. The input sub-circuit 12 is coupled to the first clock signal input terminal CK, the input signal terminal STV, and the input node N1, respectively, and is used to control the electrical connection between the input signal terminal STV and the input node N1 to be turned on or off under the control of the first clock signal input terminal CK. When the pull-down sub-circuit 11 is coupled to the first output control node N2, the input node N1 or the first output control node N2 is multiplexed as the control signal input terminal K1.

[0203] For example, the input sub-circuit 12 includes an input transistor T1, the gate of which is coupled to a first clock signal input terminal CK, the first terminal of which is coupled to an input signal terminal STV, and the second terminal of which is coupled to the input node N1.

[0204] like Figure 4 As shown, the working process of the shift register will be described in detail below, taking the first output control node N2 multiplexed as the control signal input terminal K1 and the pull-down sub-circuit 11 including the first pull-down transistor T8 as an example.

[0205] At time P1, the input signal terminal STV provides a high-level signal. At this time, the first clock signal input terminal CK is high, and the input transistor T1 is turned off. The shift register remains in the state of the previous time step, with input node N1 and the first output control node N2 remaining low, and the second output control node N3 remaining high.

[0206] At time P2, the input signal terminal STV provides a high-level signal. At this time, the first clock signal input terminal CK is low, and the input transistor T1 is turned on. The high-level signal provided by the input signal terminal STV is written to the input node N1. At this time, the third node control transistor T3 is turned off. Since the gate of the transmission transistor T2 is connected to the first-level signal, the transmission transistor T2 is turned on, and the first output control node N2 is written with a high level. The first pull-down transistor T8 is turned off. At this time, the first gating output transistor T5 is turned off, and the first node control transistor T6 is turned on. The first-level signal is written to the second output control node N3 through the first node control transistor T6. At this time, the second gating output transistor T4 is turned on, and the second-level signal is output to the gate drive signal output terminal OUT through the turned-on second gating output transistor T4. That is, at this time, the gate drive signal output terminal OUT outputs a high level.

[0207] At time P3, the input signal terminal STV provides a low-level signal, while the first clock signal input terminal CK provides a high-level signal, and input transistor T1 is turned off. At this time, input node N1, first output control node N2, and second output control node N3 maintain the potential of the previous stage. Therefore, at time P3, transmission transistor T2, second gating output transistor T4, and first node control transistor T6 are turned on, while third node control transistor T3, first gating output transistor T5, and first pull-down transistor T8 are turned off. At this time, the gate drive signal output terminal OUT outputs a high level.

[0208] At time P4, the input signal terminal STV provides a low-level signal. At this time, the first clock signal input terminal CK provides a low-level signal, and input transistor T1 is turned on. At this time, input node N1 is written with a low-level signal, the third node control transistor T3 is turned on, and a second-level signal is written to the second output control node N3. At this time, the second gating output transistor T4 is turned off. Transmission transistor T2 remains on, and the first output control node N2 is also written with a low-level signal. At this time, the first node control transistor T6 is turned off, and the first gating output transistor T5 and the first pull-down transistor T8 are turned on. The gate drive signal output terminal OUT outputs a first-level signal via the turned-on first gating output transistor T5. At time P4, the first-level signal is written to the first output control node N2 via the turned-on first pull-down transistor T8. At this time, the potential of the first output control node N2 is further pulled down, and the first gating output transistor T5 can be fully turned on.

[0209] When the pull-down sub-circuit 11 is coupled to the first output control node N2, the input node N1 or the first output control node N2 is multiplexed as the control signal input terminal K1. This not only avoids the introduction of an independent control signal input terminal K1 and reduces the circuit complexity of the gate drive circuit, but also stabilizes the potential of the first output control node N2, enabling the gate drive signal output terminal OUT of the shift register to output a low potential signal stably for a long time.

[0210] like Figures 8 to 10 As shown, in some embodiments, the shift register further includes an input sub-circuit 12 and an input node N1. The input sub-circuit 12 is coupled to a first clock signal input terminal CK, an input signal terminal STV, and the input node N1, respectively, and is used to control the electrical connection between the input signal terminal STV and the input node N1 to be turned on or off under the control of the first clock signal input terminal CK. The shift register further includes a second gating output sub-circuit 13 and a second output control node N3. The second gating output sub-circuit 13 is coupled to the second output control node N3, the gate drive signal output terminal OUT, and the second electrical control node N1, respectively. The level signal input terminal is coupled to control the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal under the control of the second output control node N3; when the pull-down sub-circuit 11 is coupled to the gate drive signal output terminal OUT: the input node N1, the first output control node N2 or the second output control node N3 are multiplexed as the control signal input terminal K1; or, the gate drive signal output terminal OUT(n+1) of the adjacent next-stage shift register is multiplexed as the pull-down signal input terminal K2 coupled to the pull-down sub-circuit 11 in the current stage shift register.

[0211] For example, the second gating output sub-circuit 13 includes a second gating output transistor T4, the gate of the second gating output transistor T4 is coupled to the second output control node N3, the first terminal of the second gating output transistor T4 is coupled to the second level signal input terminal, and the second terminal of the second gating output transistor T4 is coupled to the gate drive signal output terminal OUT.

[0212] For example, when the pull-down sub-circuit 11 is coupled to the gate drive signal output terminal OUT, and the second output control node N3 is multiplexed as the control signal input terminal K1, the first pull-down transistor T8 includes an N-type transistor; this helps to reduce the threshold loss generated when the first pull-down transistor T8 transmits the first level signal.

[0213] For example, when the pull-down sub-circuit 11 is coupled to the gate drive signal output terminal OUT, and the gate drive signal output terminal OUT of the input node N1, the first output control node N2, or the adjacent next-level shift register is multiplexed as the pull-down signal input terminal K2 coupled to the pull-down sub-circuit 11 in the current-level shift register, the first pull-down transistor T8 includes a P-type transistor.

[0214] The above configuration not only avoids introducing a separate control signal input terminal K1 and reduces the circuit complexity of the gate drive circuit, but also achieves a stable potential of the gate drive signal output terminal OUT, enabling the shift register's gate drive signal output terminal OUT to output a low potential signal stably for a long period of time.

[0215] like Figures 5 to 7 As shown, in some embodiments, the pull-down sub-circuit 11 includes a second pull-down transistor T9 and a coupling capacitor C3. The gate of the second pull-down transistor T9 is coupled to the control signal input terminal K1, the first terminal of the second pull-down transistor T9 is coupled to the pull-down signal input terminal K2, the second terminal of the second pull-down transistor T9 is coupled to the first plate of the coupling capacitor C3, and the second plate of the coupling capacitor C3 is coupled to the first output control node N2.

[0216] For example, the control signal input terminal K1 includes the first output control node N2, and the pull-down signal input terminal K2 includes a second clock signal input terminal.

[0217] like Figure 7 As shown, when the pull-down sub-circuit 11 includes the second pull-down transistor T9 and the coupling capacitor C3, the specific operation process of the shift register is as follows:

[0218] At time P1, the input signal terminal STV provides a high-level signal. At this time, the first clock signal input terminal CK is high, and the second clock signal input terminal CB is changed from low to high. Input transistor T1 is turned off. The shift register circuit maintains the state of the previous time step, with input node N1 and the first output control node N2 remaining low, and the second output control node N3 remaining high.

[0219] At time P2, the input signal terminal STV provides a high-level signal. At this time, the first clock signal input terminal CK is low, and the second clock signal input terminal CB is high. Input transistor T1 is turned on, and the high-level signal provided by the input signal terminal STV is written to input node N1. At this time, the third node control transistor T3 is turned off. Since the gate of the transmission transistor T2 receives the first-level signal, the transmission transistor T2 is turned on, and the first output control node N2 is written with a high level. The first pull-down transistor T8 is turned off. At this time, the first gating output transistor T5 is turned off, and the first node control transistor T6 is turned on. The first-level signal is written to the second output control node N3 through the first node control transistor T6. At this time, the second gating output transistor T4 is turned on, and the second-level signal is output to the gate drive signal output terminal OUT through the turned-on second gating output transistor T4. That is, the gate drive signal output terminal OUT outputs a high level at this time.

[0220] At time P3, the input signal terminal STV provides a low-level signal, while the first clock signal input terminal CK provides a high-level signal, and the second clock signal input terminal CB is shifted from low to high. Input transistor T1 is turned off at this time. Input node N1, first output control node N2, and second output control node N3 maintain the potential from the previous stage. Therefore, at time P3, transmission transistor T2, second gating output transistor T4, and first node control transistor T6 are turned on, while third node control transistor T3, first gating output transistor T5, and first pull-down transistor T8 are turned off. At this time, the gate drive signal output terminal OUT outputs a high level.

[0221] At time P4, the input signal terminal STV provides a low-level signal. At this time, the first clock signal input terminal CK provides a low-level signal, and the second clock signal input terminal CB is high. Input transistor T1 is turned on. At this time, input node N1 is written with a low-level signal, the third node control transistor T3 is turned on, and a second-level signal is written to the second output control node N3. At this time, the second gating output transistor T4 is turned off. Transmission transistor T2 remains on, and the first output control node N2 is also written with a low-level signal. At this time, the first node control transistor T6 is turned off, and the first gating output transistor T5 and the first pull-down transistor T8 are turned on. The gate drive signal output terminal OUT outputs a first-level signal via the turned-on first gating output transistor T5. At time P4, the first pull-down transistor T8 is turned on, and the second clock signal input terminal CB provides a high-level signal. At this time, the high-level signal (e.g., +5V) provided by the second clock signal input terminal CB is written to the first plate of the coupling capacitor C3, i.e., node N4, through the conducting first pull-down transistor T8. Meanwhile, the other plate of the coupling capacitor C3 is electrically connected to the first output control node N2 (if the potential of the first output control node N2 is -5V at this time). The charge stored in the coupling capacitor C3 at this time is Q. C3 =+5V-(-5V)=10V.

[0222] At time P5, the input signal terminal STV and the second clock signal input terminal CB provide low-level signals, while the first clock signal input terminal CK provides a high-level signal. At this time, input transistor T1 is turned off. Input node N1 and the second output control node N3 maintain the potential from the previous stage. Since the first output control node N2 is a low-level signal (e.g., -5V), the potential of node N4 is +5V, the first pull-down transistor T8 is turned on, and the low-level signal provided by the second clock signal input terminal CB is written to the first plate of the capacitor (e.g., -5V). Due to the presence of coupling capacitor C3, the first output control node N2 is coupled to -15V, thus pulling its potential even lower. At time P5, the first output control node N2 is pulled down to -15V due to capacitive coupling. At this time, for the transmission transistor T2, the gate-source voltage Vgs = VGL - V N2 =-5V-(-15V)=10V>Vth, at this time, the transmission transistor T2 is turned off, where VGL represents the voltage value of the first level signal connected to the gate of the transmission transistor T2, V N2 Vth represents the voltage value of the first output control node N2, and Vth represents the threshold voltage of the transmission transistor T2.

[0223] At time P6, the first clock signal inputs at input signal terminal STV and first clock signal input terminal CK provide a low-level signal, while the second clock signal input terminal CB provides a high-level signal. At this time, input transistor T1 is on, input node N1 is low, third node control transistor T3 is on, second output control node N3 is high, and second gating output transistor T4 is off. At this time, first pull-down transistor T8 is on, and the high-level signal (e.g., +5V) provided by the second clock signal input terminal CB is written to node N4. Due to the presence of coupling capacitor C3, the first output control node N2 is coupled to -5V.

[0224] In the subsequent time intervals, the shift register will alternate between the P5 and P6 operating phases. At time P6, the first output control node N2 is pulled high. For the transfer transistor T2, its conduction condition is Vgs < Vth, and VGL - V N2 <Vth, with V N2 >VGL-Vth. That is, when the first output control node N2 exceeds VGL-Vth, the transmission transistor T2 is turned on. At this time, the voltage of the first output control node N2 will leak from the input transistor T1 and the transmission transistor T2 path to the input signal terminal STV. At time P5, when the second clock signal input terminal CB signal jumps to a low level, the level value of the first output control node N2 can be pulled more negative. This achieves the purpose of stabilizing the first gating output transistor T5, which is beneficial for long-term low frequency. Therefore, the larger the coupling capacitor C3 is at this time, the more stable the gate drive signal output terminal OUT will output the first level signal for a long time.

[0225] It should be noted that at time P4, the gate drive signal output terminal OUT outputs VGL. Due to the presence of the second capacitor C2, the voltage change at the gate drive signal output terminal OUT will cause the voltage of the first output control node N2 to be coupled down, pulling down the potential of the first output control node N2. At this time, one end of the coupling capacitor C3 is VGH (the voltage value of the second level signal), and the other end is the first output control node N2. The gate drive signal output terminal OUT is coupled down to the first output control node N2 through the second capacitor C2. At this time, the first output control node N2 can be regarded as a series node between VGH and the gate drive signal output terminal OUT, which causes the pull-down of the first output control node N2 to be affected by the coupling capacitor C3. The pull-down amplitude is determined by C2 / (C2+C3). Therefore, the smaller the coupling capacitor C3 and the larger the second capacitor C2, the better the pull-down effect of the first output control node N2.

[0226] Therefore, the values ​​of the second capacitor C2 and the coupling capacitor C3 are in a balanced relationship. The charge pump formed by the second pull-down transistor T9 and the coupling capacitor C3 can indeed periodically pull down the voltage of the first output control node N2, stabilizing the output of the first gating output transistor T5. At this time, the larger the coupling capacitor C3, the more stable the long-term output VGL will be. However, at the same time, to ensure that the first output control node N2 is fully coupled when the gate drive signal output terminal OUT outputs VGL, C2 / (C2+C3) needs to be as large as possible. It can be adjusted according to actual needs.

[0227] like Figure 3 , Figure 6 and Figure 10 As shown, in some embodiments, the shift register further includes: a second gating output sub-circuit 13 and a second output control node N3, wherein the second gating output sub-circuit 13 is coupled to the second output control node N3, the gate drive signal output terminal OUT, and the second level signal input terminal, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal under the control of the second output control node N3;

[0228] The shift register further includes a first node control sub-circuit 14, which is coupled to the second output control node N3, the second first level signal input terminal VGL2 and the first output control node N2 respectively, and is used to control the electrical connection between the second output control node N3 and the second first level signal input terminal VGL2 to be turned on or off under the control of the first output control node N2.

[0229] For example, the first node control sub-circuit 14 includes a first node control transistor T6, the gate of the first node control transistor T6 is coupled to the first output control node N2, the first terminal of the first node control transistor T6 is coupled to the second first level signal input terminal VGL2, and the second terminal of the first node control transistor T6 is coupled to the second output control node N3.

[0230] like Figure 11 As shown, in some embodiments, the shift register further includes: a second gating output sub-circuit 13 and a second output control node N3, wherein the second gating output sub-circuit 13 is coupled to the second output control node N3, the gate drive signal output terminal OUT, and the second level signal input terminal, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal under the control of the second output control node N3;

[0231] The shift register further includes an input sub-circuit 12 and an input node N1. The input sub-circuit 12 is coupled to the first clock signal input terminal CK, the input signal terminal STV and the input node N1 respectively, and is used to control the electrical connection between the input signal terminal STV and the input node N1 to be turned on or off under the control of the first clock signal input terminal CK.

[0232] The shift register further includes a first node control sub-circuit 14, which is coupled to the second output control node N3, the second first level signal input terminal VGL2 and the input node N1 respectively, and is used to control the electrical connection between the second output control node N3 and the second first level signal input terminal VGL2 under the control of the input node N1.

[0233] For example, the first node control sub-circuit 14 includes a first node control transistor T6, the gate of the first node control transistor T6 is coupled to the input node N1, the first terminal of the first node control transistor T6 is coupled to the second first level signal input terminal VGL2, and the second terminal of the first node control transistor T6 is coupled to the second output control node N3.

[0234] In the shift register provided in the above embodiments, the gate of the first node control sub-circuit 14 can be coupled to the input node N1 or the first output control node N2, so that the first node control sub-circuit 14 can control the potential of the second output control node N3 under the control of the input node N1 or the first output control node N2.

[0235] like Figure 12 As shown, in some embodiments, the shift register further includes a second gating output sub-circuit 13 and a second output control node N3. The second gating output sub-circuit 13 is coupled to the second output control node N3, the gate drive signal output terminal OUT, and the local brush control signal input terminal K1, respectively, and is used to control the electrical connection between the gate drive signal output terminal OUT and the local brush control signal input terminal K1 to be turned on or off under the control of the second output control node N3.

[0236] For example, the second gating output sub-circuit 13 includes a second gating output transistor T4, the gate of the second gating output transistor T4 is coupled to the second output control node N3, the first terminal of the second gating output transistor T4 is coupled to the local brush control signal input terminal MSK1, and the second terminal of the second gating output transistor T4 is coupled to the gate drive signal output terminal OUT.

[0237] like Figure 13As shown, during low-frequency refresh, the level of the local refresh control signal input at the MSK1 terminal is set low. At this time, the gate drive signal output terminal OUT outputs a low-level signal to the corresponding scan line of the display area, and the cascade signal output terminal SCAN outputs the cascade signal.

[0238] like Figure 14 As shown, during normal refresh, the level of the local refresh control signal input at the MSK1 terminal is set high. At this time, the gate drive signal output terminal OUT outputs the gate drive signal normally, and the cascade signal output terminal SCAN outputs the cascade signal.

[0239] The shift register provided in the above embodiments can realize the partial refresh function, while ensuring normal cascaded signal output, so that the gate drive circuit can adapt to the requirements of different refresh rates.

[0240] like Figure 12 As shown, in some embodiments, the shift register further includes a first cascaded output sub-circuit 15 and a second cascaded output sub-circuit 16;

[0241] The first cascaded output sub-circuit 15 is coupled to the first output control node N2, the first first level signal input terminal VGL1 and the cascaded signal output terminal SCAN respectively, and is used to control the electrical connection between the first first level signal input terminal VGL1 and the cascaded signal output terminal SCAN to be turned on or off under the control of the first output control node N2.

[0242] The second cascaded output sub-circuit 16 is coupled to the second output control node N3, the second level signal input terminal and the cascaded signal output terminal SCAN respectively, and is used to control the electrical connection between the second level signal input terminal and the cascaded signal output terminal SCAN to be turned on or off under the control of the second output control node N3.

[0243] For example, the first cascaded output sub-circuit 15 includes a first cascaded output transistor T10, the gate of the first cascaded output transistor T10 is coupled to the first output control node N2, the first terminal of the first cascaded output transistor T10 is coupled to the first first level signal input terminal VGL1, and the second terminal of the first cascaded output transistor T10 is coupled to the cascaded signal output terminal SCAN.

[0244] For example, the second cascaded output sub-circuit 16 includes a second cascaded output transistor T11, the gate of the second cascaded output transistor T11 is coupled to the second output control node N3, the first terminal of the second cascaded output transistor T11 is coupled to the second level signal input terminal, and the second terminal of the second cascaded output transistor T11 is coupled to the cascaded signal output terminal SCAN.

[0245] like Figures 2 to 12 As shown, in some embodiments, the shift register further includes:

[0246] The second node control sub-circuit 17 is coupled to the reset signal input terminal, the second first level signal input terminal VGL2, and the second output control node N3 respectively, and is used to control the electrical connection between the second first level signal input terminal VGL2 and the second output control node N3 to be turned on or off under the control of the reset signal input terminal.

[0247] The third node control sub-circuit 18 is coupled to the input node N1, the second level signal input terminal and the second output control node N3 respectively, and is used to control the electrical connection between the second level signal input terminal and the second output control node N3 to be turned on or off under the control of the input node N1.

[0248] The transmission sub-circuit 19 is coupled to the second first level signal input terminal VGL2, the input node N1 and the first output control node N2 respectively, and is used to control the electrical connection between the input node N1 and the first output control node N2 to be turned on or off under the control of the second first level signal input terminal VGL2.

[0249] For example, the second node control sub-circuit 17 includes a second node control transistor T7, the gate of which is coupled to the reset signal input terminal, the first terminal of which is coupled to the second first level signal input terminal VGL2, and the second terminal of which is coupled to the second output control node N3.

[0250] For example, the third node control sub-circuit 18 includes a third node control transistor T3, the gate of which is coupled to the input node N1, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the second output control node N3.

[0251] For example, the transmission sub-circuit 19 includes a transmission transistor T2, the gate of which is coupled to the second first level signal input terminal VGL2, the first terminal of which is coupled to the input node N1, and the second terminal of which is coupled to the first output control node N2.

[0252] It should be noted that in the embodiments of this utility model, "same layer" can refer to film layers on the same structural layer. Alternatively, for example, film layers on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0253] In the various method embodiments of this utility model, the sequence number of each step is not used to limit the order of each step. For those skilled in the art, changes in the order of each step are also within the protection scope of this utility model without creative effort.

[0254] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0255] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this utility model pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected," "coupled," or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0256] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0257] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0258] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A display panel, characterized in that, The device includes a substrate and a gate driving circuit disposed on the substrate. The gate driving circuit includes a cascaded multi-stage shift register, and the shift register includes a second output control node, a first node control transistor, a second node control transistor, and a third node control transistor. The active layer of the second node control transistor, the active layer of the third node control transistor, and the active layer of the first node control transistor are arranged along a first direction. The shift register further includes a first conductive connection portion, which serves as the second output control node. The first conductive connection portion includes at least a portion extending along a first direction. A first end of the first conductive connection portion is coupled to the second pole of the second node control transistor and the second pole of the third node control transistor. A second end of the first conductive connection portion is coupled to the first pole of the first node control transistor.

2. The display panel according to claim 1, characterized in that, The active layer of the second node control transistor extends along the first direction, and the active layer of the third node control transistor extends along the first direction. The portion of the active layer of the second node control transistor used to form the second electrode of the second node control transistor is coupled to the portion of the active layer of the third node control transistor used to form the second electrode of the third node control transistor, forming a first common connection terminal of an integral structure. The first end of the first conductive connection portion is coupled to the first common connection end.

3. The display panel according to claim 1, characterized in that, The active layer of the first node control transistor extends along a first direction, and the active layers of the first node control transistor and the third node control transistor are offset along a second direction, which intersects with the first direction. The portion of the active layer of the first node control transistor used to form the second electrode of the first node control transistor is closer to the active layer of the third node control transistor than the portion of the active layer of the first node control transistor used to form the first electrode of the first node control transistor. The second end of the first conductive connection portion is coupled to the portion in the active layer of the first node control transistor used to form the second electrode of the first node control transistor.

4. The display panel according to claim 1, characterized in that, The display panel further includes at least one second-level signal line; the shift register further includes a second gating output transistor and a first capacitor; the second plate of the first capacitor and the first plate of the second gating output transistor are coupled to the same second-level signal line, or the second plate of the first capacitor and the first plate of the second gating output transistor are coupled to different second-level signal lines; The second terminal of the second strobe output transistor is coupled to the gate drive signal output terminal; When the second plate of the first capacitor and the first plate of the second gate output transistor are coupled to the same second level signal line, the shift register further includes a first gate connection portion, and the first gate connection portion, the first plate of the first capacitor and the gate of the second gate output transistor are coupled sequentially along the second direction; the second end of the first conductive connection portion is also coupled to the first gate connection portion.

5. The display panel according to claim 4, characterized in that, The orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the second level signal line coupled to it on the substrate at least partially overlap.

6. The display panel according to claim 4, characterized in that, The first conductive connection portion further includes a connection body portion connected between the first end and the second end, the connection body portion extending along a first direction; at least a portion of the orthographic projection of the active layer of the third node control transistor on the substrate is located between the orthographic projection of the connection body portion on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate. Both the first end and the second end extend along the second direction, and at least a portion of the orthographic projection of the active layer of the third node control transistor onto the substrate is located between the orthographic projection of the first end onto the substrate and the orthographic projection of the second end onto the substrate.

7. The display panel according to claim 1, characterized in that, The display panel includes a first gate metal layer, a second gate metal layer, and a third gate metal layer sequentially stacked along a direction away from the substrate. The first node control transistor includes an oxide transistor, an oxide active layer, and at least one of a top gate layer and a bottom gate layer. The top gate layer is located on the side of the oxide active layer facing away from the substrate, and the bottom gate layer is located on the side of the oxide active layer facing the substrate. The bottom gate layer is disposed in the same layer and with the same material as the first gate metal layer or the second gate metal layer. The top gate layer is disposed in the same layer and with the same material as the second gate metal layer or the third gate metal layer.

8. The display panel according to claim 7, characterized in that, The bottom gate layer and the top gate layer are coupled together; or, the bottom gate layer and the top gate layer are independent of each other.

9. The display panel according to claim 7, characterized in that, The display panel further includes a first first level signal line; the shift register further includes a second capacitor and a first gating output transistor, the first plate of the second capacitor is coupled to the gate of the first gating output transistor, the second plate of the second capacitor is coupled to the gate drive signal output terminal, the first terminal of the first gating output transistor is coupled to the first first level signal line, and the second terminal of the first gating output transistor is coupled to the gate drive signal output terminal. The first electrode of the second capacitor is disposed in the same layer and made of the same material as the first gate metal layer, the second gate metal layer, or the third gate metal layer; the second electrode of the second capacitor is disposed in the same layer and made of the same material as the first gate metal layer, the second gate metal layer, or the third gate metal layer; the first electrode of the second capacitor and the second electrode of the second capacitor are disposed in different layers.

10. The display panel according to claim 9, characterized in that, The shift register further includes a second gate connection portion, and the second gate connection portion, the first plate of the second capacitor, and the gate of the first gate output transistor are sequentially coupled along the second direction; The shift register further includes a second conductive connection portion coupled to the second gate connection portion and coupled to at least one of the top gate layer and the bottom gate layer of the first node control transistor.

11. The display panel according to claim 7, characterized in that, The display panel further includes a first first level signal line; the shift register further includes a second capacitor and a first gating output transistor, the first plate of the second capacitor is coupled to the gate of the first gating output transistor, the second plate of the second capacitor is coupled to the gate drive signal output terminal, the first terminal of the first gating output transistor is coupled to the first first level signal line, and the second terminal of the first gating output transistor is coupled to the gate drive signal output terminal. The first electrode of the second capacitor includes a first sub-electrode and a second sub-electrode disposed opposite to each other. The first sub-electrode is disposed in the same layer and with the same material as the first gate metal layer, and the second sub-electrode is disposed in the same layer and with the same material as the third gate metal layer. The second electrode of the second capacitor is located between the first sub-electrode and the second sub-electrode, and the second electrode of the second capacitor is disposed in the same layer and with the same material as the second gate metal layer.

12. The display panel according to claim 11, characterized in that, The shift register further includes a second gate connection portion, and the gates of the second gate connection portion, the first sub-plate, and the first gate output transistor are sequentially coupled along the second direction; The shift register further includes a second conductive connection portion coupled to the second gate connection portion and coupled to at least one of the top gate layer and the bottom gate layer of the first node control transistor.

13. The display panel according to claim 7, characterized in that, The display panel further includes a first first level signal line; the shift register further includes a second capacitor and a first gating output transistor, the first plate of the second capacitor is coupled to the gate of the first gating output transistor, the second plate of the second capacitor is coupled to the gate drive signal output terminal, the first terminal of the first gating output transistor is coupled to the first first level signal line, and the second terminal of the first gating output transistor is coupled to the gate drive signal output terminal. The first electrode of the second capacitor includes a first sub-electrode and a second sub-electrode disposed opposite to each other. The second electrode of the second capacitor is located between the first sub-electrode and the second sub-electrode. The second sub-electrode or the second electrode of the second capacitor is disposed in the same layer and with the same material as the oxide active layer.

14. The display panel according to any one of claims 9 to 13, characterized in that, The shift register also includes a compensation capacitor, the first plate of which is coupled to the first plate of the second capacitor, the second plate of which is coupled to the second plate of the second capacitor, and the second plate of which is also coupled to the gate drive signal output terminal of the shift register. The orthographic projection of the active layer of the first gated output transistor on the substrate and the orthographic projection of the first plate of the compensation capacitor on the substrate are arranged along a first direction.

15. The display panel according to claim 14, characterized in that, The shift register further includes a fourth conductive connection portion, which is coupled to the second plate of the compensation capacitor; the fourth conductive connection portion also serves as an input signal terminal coupled to the input transistor in the adjacent N-stage shift register, where N is an integer greater than or equal to 1.

16. The display panel according to claim 15, characterized in that, The fourth conductive connection portion is disposed in the same layer and made of the same material as the second gate metal layer.

17. The display panel according to any one of claims 1 to 13, characterized in that, The display panel further includes at least two clock signal lines and a second first-level signal line; the shift register further includes an input transistor and a transmission transistor, the gate of the input transistor is coupled to the corresponding clock signal line, the first terminal of the input transistor is coupled to the input signal terminal, and the second terminal of the input transistor and the first terminal of the transmission transistor are both coupled to the input node in the shift register; the gate of the transmission transistor is coupled to the second first-level signal line, and the second terminal of the transmission transistor is coupled to the first output control node; The portion of the active layer of the input transistor used to form the second electrode of the input transistor is coupled to the portion of the active layer of the transmission transistor used to form the first electrode of the transmission transistor, forming a second common connection terminal of an integral structure. The shift register further includes a third conductive connection portion, which serves as the input node and is coupled to the second common connection terminal.

18. The display panel according to claim 17, characterized in that, The orthographic projection of the third conductive connection portion on the substrate and the orthographic projection of the active layer of the third node control transistor on the substrate are arranged along the second direction, and the third conductive connection portion is coupled to the gate of the third node control transistor.

19. The display panel according to claim 10 or 12, characterized in that, The display panel further includes a second first-level signal line; the shift register further includes a first pull-down transistor, the gate of the first pull-down transistor is coupled to the second gate connection portion, the first electrode of the first pull-down transistor is coupled to the second first-level signal line, and the second electrode of the first pull-down transistor is coupled to the second conductive connection portion.

20. The display panel according to any one of claims 1 to 13, characterized in that, The display panel further includes multiple sub-pixels, each sub-pixel including a sub-pixel driving circuit, which is coupled to a light emission control signal input terminal, a reset signal input terminal, and a scan signal input terminal, respectively; the gate driving signal output terminal of the shift register serves as the light emission control signal input terminal, the reset signal input terminal, or the scan signal input terminal.

21. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 20.

22. A gate driving circuit, characterized in that, The gate driving circuit is applied to a display panel as described in any one of claims 1 to 20; the gate driving circuit includes: a plurality of cascaded shift registers, each shift register including a first output control node, a first gating output sub-circuit, a pull-down sub-circuit, and a gate driving signal output terminal; The first gating output sub-circuit is coupled to the first output control node, the first first level signal input terminal and the gate drive signal output terminal respectively, and is used to control the electrical connection between the first first level signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the first output control node. The pull-down sub-circuit is coupled to both the control signal input terminal and the pull-down signal input terminal, and is also coupled to either the first output control node or the gate drive signal output terminal; it is used to control the potential of the first output control node according to the pull-down signal input terminal under the control of the control signal input terminal; or, according to the pull-down signal input terminal, control the potential of the gate drive signal output terminal.

23. The gate driving circuit according to claim 22, characterized in that, The pull-down sub-circuit includes a first pull-down transistor, the gate of which is coupled to the control signal input terminal, the first terminal of which is coupled to the pull-down signal input terminal, and the second terminal of which is coupled to the first output control node or the gate drive signal output terminal.

24. The gate driving circuit according to claim 23, characterized in that, The pull-down signal input terminal includes a second first-level signal input terminal; the potential of the second first-level signal input terminal may be the same as or different from that of the first first-level signal input terminal.

25. The gate driving circuit according to any one of claims 22 to 24, characterized in that, The shift register further includes an input sub-circuit and an input node. The input sub-circuit is coupled to a first clock signal input terminal, an input signal terminal, and the input node, respectively, and is used to control the electrical connection between the input signal terminal and the input node to be turned on or off under the control of the first clock signal input terminal. When the pull-down sub-circuit is coupled to the first output control node, the input node or the first output control node is multiplexed as the control signal input terminal.

26. The gate driving circuit according to any one of claims 22 to 24, characterized in that, The shift register further includes an input sub-circuit and an input node. The input sub-circuit is coupled to a first clock signal input terminal, an input signal terminal, and the input node, respectively, and is used to control the electrical connection between the input signal terminal and the input node to be turned on or off under the control of the first clock signal input terminal. The shift register further includes a second gating output sub-circuit and a second output control node. The second gating output sub-circuit is coupled to the second output control node, the gate drive signal output terminal, and the second level signal input terminal, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the second output control node. When the pull-down sub-circuit is coupled to the gate drive signal output terminal: the input node, the first output control node, or the second output control node is multiplexed as the control signal input terminal; or, the gate drive signal output terminal of the adjacent next-stage shift register is multiplexed as the pull-down signal input terminal coupled to the pull-down sub-circuit in the current-stage shift register.

27. The gate driving circuit according to claim 22, characterized in that, The pull-down sub-circuit includes a second pull-down transistor and a coupling capacitor. The gate of the second pull-down transistor is coupled to the control signal input terminal, the first terminal of the second pull-down transistor is coupled to the pull-down signal input terminal, the second terminal of the second pull-down transistor is coupled to the first plate of the coupling capacitor, and the second plate of the coupling capacitor is coupled to the first output control node.

28. The gate driving circuit according to claim 27, characterized in that, The control signal input terminal includes the first output control node, and the pull-down signal input terminal includes the second clock signal input terminal.

29. The gate driving circuit according to any one of claims 22-24, 27, and 28, characterized in that, The shift register further includes: a second gating output sub-circuit and a second output control node. The second gating output sub-circuit is coupled to the second output control node, the gate drive signal output terminal and the second level signal input terminal, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the second output control node. The shift register further includes a first node control sub-circuit, which is coupled to the second output control node, the second first level signal input terminal and the first output control node respectively, and is used to control the electrical connection between the second output control node and the second first level signal input terminal to be turned on or off under the control of the first output control node.

30. The gate driving circuit according to any one of claims 22-24, 27, and 28, characterized in that, The shift register further includes: a second gating output sub-circuit and a second output control node. The second gating output sub-circuit is coupled to the second output control node, the gate drive signal output terminal and the second level signal input terminal, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the second output control node. The shift register further includes an input sub-circuit and an input node. The input sub-circuit is coupled to a first clock signal input terminal, an input signal terminal, and the input node, respectively, and is used to control the electrical connection between the input signal terminal and the input node to be turned on or off under the control of the first clock signal input terminal. The shift register further includes a first node control sub-circuit, which is coupled to the second output control node, the second first level signal input terminal and the input node respectively, and is used to control the electrical connection between the second output control node and the second first level signal input terminal to be turned on or off under the control of the input node.

31. The gate driving circuit according to any one of claims 22-24, 27, and 28, characterized in that, The shift register further includes a second gating output sub-circuit and a second output control node. The second gating output sub-circuit is coupled to the second output control node, the gate drive signal output terminal, and the local brush control signal input terminal, respectively, and is used to control the electrical connection between the gate drive signal output terminal and the local brush control signal input terminal to be turned on or off under the control of the second output control node.

32. The gate driving circuit according to claim 31, characterized in that, The shift register also includes a first cascaded output sub-circuit and a second cascaded output sub-circuit; The first cascaded output sub-circuit is coupled to the first output control node, the first first level signal input terminal and the cascaded signal output terminal respectively, and is used to control the electrical connection between the first first level signal input terminal and the cascaded signal output terminal to be turned on or off under the control of the first output control node. The second cascaded output sub-circuit is coupled to the second output control node, the second level signal input terminal, and the cascaded signal output terminal, respectively, and is used to control the electrical connection between the second level signal input terminal and the cascaded signal output terminal to be turned on or off under the control of the second output control node.

33. The gate driving circuit according to any one of claims 22-24, 27, and 28, characterized in that, The shift register also includes: The second node control sub-circuit is coupled to the reset signal input terminal, the second first level signal input terminal, and the second output control node, respectively, and is used to control the electrical connection between the second first level signal input terminal and the second output control node to be turned on or off under the control of the reset signal input terminal. The third node control sub-circuit is coupled to the input node, the second level signal input terminal and the second output control node respectively, and is used to control the electrical connection between the second level signal input terminal and the second output control node to be turned on or off under the control of the input node. The transmission sub-circuit is coupled to the second first-level signal input terminal, the input node, and the first output control node, respectively, and is used to control the electrical connection between the input node and the first output control node to be turned on or off under the control of the second first-level signal input terminal.

Images