A current peak protection circuit

Abstract

This utility model belongs to the field of circuit technology and discloses a current peak protection circuit, including a sampling resistor RS1. One end of the sampling resistor RS1 is connected to one end of an inductor L1, and the other end of the inductor L1 is connected to one end of a resistor R1. The other end of the resistor R1 is connected to one end of a capacitor C1 and pin 2 of a chip U1. The other end of the sampling resistor RS1 is connected to one end of an inductor L2, and the other end of the inductor L2 is connected to one end of a resistor R2. The other end of the resistor R2 is connected to the other end of capacitor C1, one end of capacitor C2, one end of resistor R3, pin 4 of the chip U1, and port GND1. The beneficial effects of this utility model are: simple circuit, stable performance, and it can solve the problem of transistor damage due to excessive current in PFC circuits.

Description

Technical Field

[0001] This utility model relates to the field of circuit technology, and in particular to a current peak protection circuit. Background Technology

[0002] In a PFC circuit, the input current is a 50Hz alternating current. To prevent excessive current from damaging the transistor, a differential sampling circuit is usually used to convert the current into a small voltage signal and send it to the MCU. After conversion by an ADC, the protection reaches the corresponding maximum or minimum voltage value. The MCU immediately shuts down the drive to turn off the transistor. However, the processing and drive shutdown time of the chip generally takes tens to hundreds of milliseconds. If the chip processing time is too long, the current will continue to rise during this process, and the transistor will be damaged because the current exceeds the maximum allowable current.

[0003] Therefore, it is necessary to provide a current peak protection circuit to solve the problem of transistors in PFC circuits being damaged due to excessive current. Utility Model Content

[0004] This utility model discloses a current peak protection circuit, belonging to the field of power electronics, specifically relating to an AC current peak protection circuit, which can effectively solve the technical problems involved in the background art.

[0005] To achieve the above objectives, the technical solution of this utility model is as follows:

[0006] A current peak protection circuit includes a sampling resistor RS1, one end of which is connected to one end of an inductor L1, the other end of which is connected to one end of a resistor R1, the other end of which is connected to one end of a capacitor C1 and pin 2 of a chip U1, the other end of which is connected to one end of an inductor L2, the other end of which is connected to one end of a resistor R2, the other end of which is connected to the other end of capacitor C1, one end of capacitor C2, one end of resistor R3, pin 4 of the chip U1, and port GND1, pin 1 of the chip U1 is connected to one end of capacitor C3 and port VCC1, the other end of capacitor C3 is connected to port GND1, and pin 3 of the chip U1 is connected to the other end of capacitor C2 and the other end of resistor R3.

[0007] Pin 5 of chip U1 is connected to pin 7 of chip U1, port GND2 and one end of capacitor C5. Pin 6 of chip U1 is connected to the other end of capacitor C5, one end of resistor R4 and the negative end of diode D1. The positive end of diode D1 is connected to port OCP. Pin 8 of chip U1 is connected to one end of capacitor C6, the other end of resistor R4 and port VCC2. The other end of capacitor C6 is connected to port GND2.

[0008] As a preferred improvement of this utility model: one end of the sampling resistor RS1 is connected to port A1, the other end of the sampling resistor RS1 is connected to port A2, and port A1 and port A2 are connected in series to the sampling point of the AC circuit.

[0009] As a preferred improvement of this utility model: pin 1 of the chip U1 is connected to one end of capacitor C4, and the other end of capacitor C4 is connected to port GND1.

[0010] As a preferred improvement of this utility model, the port VCC1 is connected to a 5V power supply.

[0011] As a preferred improvement of this utility model, the port VCC2 is connected to a 5V power supply.

[0012] As a preferred improvement of this utility model, the port GND1 and the port GND2 are connected to different grounding terminals.

[0013] As a preferred improvement of this utility model, the chip U1 is model NSI22C12.

[0014] As a preferred improvement of this utility model: pin 8 of the chip U1 is connected to one end of capacitor C7, and the other end of capacitor C7 is connected to port GND2.

[0015] As a preferred improvement of this utility model: the sampling resistor RS1 is connected in series to the sampling point of the circuit to be controlled, the port OCP is connected to the controller MCU, and the controller MCU controls the switching transistor of the circuit to be controlled.

[0016] The beneficial effects of this utility model are as follows:

[0017] This protection circuit can shut down the transistor before the chip detects and processes the current, which is faster and reduces the risk of transistor damage due to excessive current. The circuit is simple and has stable performance, which can solve the problem of transistor damage due to excessive current in PFC circuits. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0019] Figure 1 This is a schematic diagram of a current peak protection circuit according to the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0022] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0023] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0024] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0025] Please see Figure 1As shown, this utility model provides a current peak protection circuit, including a sampling resistor RS1. The sampling resistor RS1 is connected in series to the sampling point of the circuit to be controlled. In this embodiment, one end of the sampling resistor RS1 is connected to port A1, and the other end of the sampling resistor RS1 is connected to port A2. Port A1 and port A2 are connected in series to the sampling point of the AC circuit. One end of the sampling resistor RS1 is connected to one end of the inductor L1, and the other end of the inductor L1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the capacitor C1 and pin 2 of the chip U1. The other end of the sampling resistor RS1 is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the other end of the capacitor C1, one end of the capacitor C2, one end of the resistor R3, pin 4 of the chip U1, and port GND1. Pin 1 of the chip U1 is connected to one end of the capacitor C3 and port VCC1. The other end of the capacitor C3 is connected to port GND1. Pin 3 of the chip U1 is connected to the other end of the capacitor C2 and the other end of the resistor R3. Pin 1 of the chip U1 is connected to one end of the capacitor C4, and the other end of the capacitor C4 is connected to port GND1. Port VCC1 is connected to a 5V power supply.

[0026] Pin 5 of chip U1 is connected to pin 7 of chip U1, port GND2, and one end of capacitor C5. Pin 6 of chip U1 is connected to the other end of capacitor C5, one end of resistor R4, and the negative terminal of diode D1. The positive terminal of diode D1 is connected to port OCP. Pin 8 of chip U1 is connected to one end of capacitor C6, the other end of resistor R4, and port VCC2. The other end of capacitor C6 is connected to port GND2. Port VCC2 is connected to a 5V power supply. Pin 8 of chip U1 is connected to one end of capacitor C7. The other end of capacitor C7 is connected to port GND2. Port OCP is connected to the controller MCU, which controls the switching transistor of the circuit under control. Ports GND1 and GND2 are connected to different ground terminals. The chip U1 is an NSI22C12.

[0027] Specifically, an AC current peak protection circuit includes a current conversion section, a chip sampling section, and a chip processing section.

[0028] Current conversion section: AC current passes through sampling resistor RS1 to form a continuous sinusoidal voltage signal UINP.

[0029] Chip sampling section: The primary input of chip U1 is powered by 5V-A (VCC1). Resistor R3 sets the reference value UREF, where UREF = 100uA * R3. For example, if RS1 is set to 0.0005Ω and the peak current is 120A to trigger protection, the resistance of R3 can be determined as 120 * 0.0005 / 100uA = 600Ω. When the sinusoidal voltage signal applied to the sampling resistor RS1 is filtered by L1, R1, C1, R2, and L2, it enters pin 2 "INP" of chip U1. If the absolute value of the maximum or minimum voltage of UINP is less than UREF, chip U1 does not perform any processing.

[0030] Chip processing section: The secondary power supply of chip U1 is provided by 5V-B (VCC2). Pin 6 "OUT1" is pulled up to a high level through resistor R4. When the absolute value of the maximum or minimum voltage of UINP is greater than UREF, chip U1 quickly pulls the internal voltage of pin 6 "OUT1" to a low level, that is, the "OCP" port is quickly pulled to a low level. The input port "OCP" of the MCU chip detects the low level and quickly turns off all transistors.

[0031] Although the embodiments of this utility model have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for this utility model. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, this utility model is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A current peak protection circuit, characterized in that: The circuit includes a sampling resistor RS1, one end of which is connected to one end of an inductor L1, the other end of which is connected to one end of a resistor R1, the other end of which is connected to one end of a capacitor C1 and pin 2 of a chip U1, the other end of which is connected to one end of an inductor L2, the other end of which is connected to one end of a resistor R2, the other end of which is connected to the other end of a capacitor C1, one end of a capacitor C2, one end of a resistor R3, pin 4 of a chip U1, and port GND1, pin 1 of a chip U1 is connected to one end of a capacitor C3 and port VCC1, the other end of a capacitor C3 is connected to port GND1, and pin 3 of a chip U1 is connected to the other end of a capacitor C2 and the other end of a resistor R3. Pin 5 of chip U1 is connected to pin 7 of chip U1, port GND2 and one end of capacitor C5. Pin 6 of chip U1 is connected to the other end of capacitor C5, one end of resistor R4 and the negative end of diode D1. The positive end of diode D1 is connected to port OCP. Pin 8 of chip U1 is connected to one end of capacitor C6, the other end of resistor R4 and port VCC2. The other end of capacitor C6 is connected to port GND2.

2. The current peak protection circuit according to claim 1, characterized in that: One end of the sampling resistor RS1 is connected to port A1, and the other end of the sampling resistor RS1 is connected to port A2. Port A1 and port A2 are connected in series to the sampling point of the AC circuit.

3. The current peak protection circuit according to claim 1, characterized in that: Pin 1 of the chip U1 is connected to one end of capacitor C4, and the other end of capacitor C4 is connected to port GND1.

4. The current peak protection circuit according to claim 1, characterized in that: The VCC1 port is connected to a 5V power supply.

5. A current peak protection circuit according to claim 1, characterized in that: The VCC2 port is connected to a 5V power supply.

6. A current peak protection circuit according to claim 1, characterized in that: Port GND1 and port GND2 are connected to different grounding terminals.

7. A current peak protection circuit according to claim 1, characterized in that: The chip U1 is model NSI22C12.

8. A current peak protection circuit according to claim 1, characterized in that: Pin 8 of the chip U1 is connected to one end of capacitor C7, and the other end of capacitor C7 is connected to port GND2.

9. A current peak protection circuit according to claim 1, characterized in that: The sampling resistor RS1 is connected in series to the sampling point of the circuit to be controlled, and the port OCP is connected to the controller MCU. The controller MCU controls the switching transistor of the circuit to be controlled.

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